JP2020047858A - Working condition selection method - Google Patents

Abstract

To provide a working condition selection method capable of easily selecting appropriate working conditions, by allowing to easily confirming whether or not a functional layer remains on the bottom of a processing groove.SOLUTION: A working condition selection method is a method of selecting the working conditions for removing the functional layer of a semiconductor wafer where the functional layer is laminated on the surface of a substrate. The working condition selection method includes a processing groove formation step ST1 of forming a processing groove by setting arbitrary working conditions and irradiating the functional layer with a laser light beam of such a wavelength as the functional layer has absorptivity, a plasma etching step ST2 of etching a processing groove with plasma reacting on the substrate but not reacting on the functional layer after execution of the processing groove formation step ST1, and a selection step ST3 of observing the processing groove after execution of the plasma etching step ST2, and selecting an arbitrary working conditions, where the functional layer is removed, as the appropriate working conditions.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a processing condition selection method for selecting a processing condition for removing a functional layer.

  A semiconductor wafer on which a functional layer such as a low-k film is laminated is formed by irradiating a laser to form two laser processing grooves from which the functional layer has been removed in a line to be divided, and cutting between the two laser processing grooves. A processing method of cutting into individual devices by cutting with a blade is employed (for example, see Patent Document 1).

JP 2003-320466 A

  By the way, the processing method disclosed in Patent Document 1 is designed to select a processing condition for dividing a semiconductor wafer on which a new device is formed, when selecting a laser output, a feed rate of a chuck table for holding the semiconductor wafer, a laser repetition frequency. Ablation processing is performed by changing various parameters such as processing conditions, and the processing results are observed, and appropriate processing conditions are adopted as processing conditions for processing an actual semiconductor wafer.

  After performing ablation processing by changing various parameters of the processing conditions described above, the operator observed the laser processing groove with a microscope to check whether the functional layer remained at the bottom of the laser processing groove. However, observation using a microscope has made it difficult and inaccurate to identify the functional layer when silicon and the like constituting the substrate below the functional layer were melted and adhered as debris.

  Further, in the processing method disclosed in Patent Document 1, when a laser oscillator of a laser processing apparatus for forming a laser processing groove is changed, even if the processing is performed under the same processing conditions as before the replacement, the individual difference of the laser oscillator itself is reduced. For this reason, it was necessary to check whether the functional layer remained, but it could not be checked accurately. Further, the processing method disclosed in Patent Literature 1 is not limited to the Low-k film, but has a similar problem when a metal component called, for example, a TEG (Test Element Group) is formed on a line to be divided. Was.

  The present invention has been made in view of such a problem, and an object of the present invention is to make it possible to easily confirm whether or not a functional layer remains at the bottom of a processing groove, and to set appropriate processing conditions. An object of the present invention is to provide a processing condition selection method that can be easily selected.

  In order to solve the above-described problems and achieve the object, a processing condition selection method according to the present invention provides a processing method for selecting a processing condition for removing a functional layer of a semiconductor wafer having a functional layer laminated on a surface of a substrate. A condition selecting method, wherein a processing groove is formed by setting arbitrary processing conditions and irradiating the functional layer with a laser beam having a wavelength at which the functional layer has absorptivity to form a processing groove; and A plasma etching step of etching the processing groove with plasma that reacts with the substrate but does not react with the functional layer after performing the processing groove; and observing the processing groove after performing the plasma etching step, the functional layer is removed. And selecting an arbitrary processing condition as an appropriate processing condition.

  In the processing condition selection method, two or more arbitrary processing conditions may be set, and an appropriate processing condition may be selected.

  In the processing condition selection method, the functional layer may be a low dielectric constant insulating film or TEG.

  In the processing condition selection method, the substrate may be silicon.

  The processing condition selection method of the present invention has an effect that it is possible to easily check whether or not the functional layer remains at the bottom of the laser processing groove, and it is possible to easily select appropriate processing conditions. .

FIG. 1 is a perspective view illustrating an example of a semiconductor wafer to be processed under processing conditions selected by the processing condition selection method according to the first embodiment. FIG. 2 is a flowchart illustrating the flow of the processing condition selection method according to the first embodiment. FIG. 3 is a perspective view showing a configuration example of a laser processing apparatus used in a processing groove forming step of the processing condition selecting method shown in FIG. FIG. 4 is a cross-sectional view schematically showing a state in which the laser processing apparatus performs alignment in a processing groove forming step of the processing condition selection method shown in FIG. FIG. 5 is a cross-sectional view schematically illustrating a state in which a laser processing apparatus forms a processing groove in a processing groove forming step of the processing condition selection method illustrated in FIG. FIG. 6 is a plan view of a semiconductor wafer on which processing grooves are formed under arbitrary processing conditions in the processing groove forming step of the processing condition selection method shown in FIG. FIG. 7 is a plan view of a semiconductor wafer on which processing grooves are formed under processing conditions different from those in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII in FIGS. 6 and 7. FIG. 9 is a sectional view taken along line IX-IX in FIG. FIG. 10 is a sectional view showing the configuration of an etching apparatus used in the plasma etching step of the processing condition selection method shown in FIG. FIG. 11 is a cross-sectional view showing a state where the semiconductor wafer shown in FIG. 8 is etched in the plasma etching step of the processing condition selection method shown in FIG. FIG. 12 is a cross-sectional view showing a state where the semiconductor wafer shown in FIG. 9 is etched in the plasma etching step of the processing condition selecting method shown in FIG. FIG. 13 is a plan view of the semiconductor wafer on which the processing grooves shown in FIG. 6 have been formed after the plasma etching step. FIG. 14 is a plan view of the semiconductor wafer on which the processing grooves shown in FIG. 7 have been formed after the plasma etching step. FIG. 15 is a cross-sectional view taken along line XV-XV in FIGS. 13 and 14. FIG. 16 is a sectional view taken along the line XVI-XVI in FIG. FIG. 17 is a diagram illustrating a binary image obtained by imaging a semiconductor wafer on which a processing groove is formed under arbitrary processing conditions in a selection step of the processing condition selection method according to the second embodiment. FIG. 18 is a diagram illustrating a binary image obtained by imaging a semiconductor wafer on which a processing groove is formed under processing conditions different from those in FIG. 17 in the selection step of the processing condition selection method according to the second embodiment. FIG. 19 is a perspective view showing an example of a semiconductor wafer to be processed under processing conditions selected by the processing condition selection method according to the modification of the first and second embodiments.

  An embodiment (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. The components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Further, the configurations described below can be appropriately combined. In addition, various omissions, substitutions, or changes in the configuration can be made without departing from the spirit of the present invention.

[Embodiment 1]
A processing condition selection method according to the first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a perspective view illustrating an example of a semiconductor wafer to be processed under processing conditions selected by the processing condition selection method according to the first embodiment. FIG. 2 is a flowchart illustrating the flow of the processing condition selection method according to the first embodiment.

The processing condition selection method according to the first embodiment is a method for selecting processing conditions when processing the semiconductor wafer 1 shown in FIG. In the first embodiment, the semiconductor wafer 1 is a disc-shaped semiconductor wafer having a substrate 2 made of silicon. However, in the present invention, the substrate 2 of the semiconductor wafer 1 is made of sapphire, SiC (silicon carbide), or the like. May be configured. As shown in FIG. 1, a semiconductor wafer 1 has a functional layer 4 laminated on a surface 3 of a substrate 2 and a plurality of devices 5 formed thereon. The functional layer 4 is a low dielectric constant insulator film (Low-k film) made of an inorganic film such as SiO ₂ , SiOF, BSG (SiOB) or an organic film such as a polyimide or parylene polymer film. It consists of. The functional layer 4 is laminated on the surface 3 of the substrate 2.

  The device 5 is formed in each area defined by a plurality of planned dividing lines 6 intersecting the surface 3. That is, the scheduled division line 6 divides the plurality of devices 5. The device is, for example, an integrated circuit such as an IC (Integrated Circuit) or an LSI (Large Scale Integration). The circuit constituting the device 5 is supported by the functional layer 4.

  In the first embodiment, after the functional layers 4 at both ends in the width direction of the respective dividing lines 6 are removed and the substrate 2 is exposed, the semiconductor wafer 1 is cut between the substrates 2 exposed at both ends in the width direction. It is cut by an apparatus or the like and divided into individual devices 5.

  The processing condition selection method according to the first embodiment is a method for selecting processing conditions for removing the functional layer 4 of the semiconductor wafer 1 from the surface 3 of the substrate 2 shown in FIG. As shown in FIG. 2, the processing condition selection method includes a processing groove forming step ST1, a plasma etching step ST2, and a selection step ST3.

(Processing groove forming step)
FIG. 3 is a perspective view showing a configuration example of a laser processing apparatus used in a processing groove forming step of the processing condition selecting method shown in FIG. FIG. 4 is a cross-sectional view schematically showing a state in which the laser processing apparatus performs alignment in a processing groove forming step of the processing condition selection method shown in FIG. FIG. 5 is a cross-sectional view schematically illustrating a state in which a laser processing apparatus forms a processing groove in a processing groove forming step of the processing condition selection method illustrated in FIG.

  The processing groove forming step ST1 is performed using the laser processing apparatus 10 shown in FIG. In the first embodiment, the laser processing apparatus 10 is configured to hold the back surface 7 of the semiconductor wafer 1 in which the adhesive tape 8 is attached to the back surface 7 of the substrate 2 and the annular frame 9 is attached to the outer peripheral edge of the adhesive tape 8 to a chuck table. This is a device for suction-holding on the holding surface 12 of 11. In addition, the laser processing apparatus 10 moves the chuck table 11 relative to the laser beam irradiation unit 13 along the planned dividing line 6 based on the set processing conditions, and the laser beam irradiation unit 13 moves the functional layer 4 from the laser beam irradiation unit 13. The apparatus also irradiates the functional layer 4 on the line 6 to be divided with a pulsed laser beam 14 having an absorptive wavelength to form a processing groove 100 on the line 6 to be divided. In the first embodiment, the semiconductor wafer 1 has the adhesive tape 8 attached to the back surface 7 of the substrate 2 and the annular frame 9 attached to the outer peripheral edge of the adhesive tape 8, but the present invention is not limited to this. .

  In the first embodiment, the processing conditions include the wavelength of the laser beam 14, the average output of the laser beam 14, the repetition frequency of the laser beam 14, the spot diameter of the focal point of the laser beam 14 on the functional layer 4, and the moving speed of the chuck table 11. At least one of them.

  The processing groove forming step ST1 sets an arbitrary processing condition, and the laser processing apparatus 10 irradiates the functional layer 4 with the laser beam 14 from the surface 3 side of the substrate 2 of the semiconductor wafer 1 along the planned dividing line 6, This is a step of forming a processing groove 100 on the dividing line 6. In the processing groove forming step ST1, the operator places the back surface 7 side of the semiconductor wafer 1 on the holding surface 12 of the chuck table 11 via the adhesive tape 8 on the outer edge portion, operates the input unit 15, and operates the control unit which is a computer. The processing conditions are set in 16 and the control unit 16 stores the set processing conditions. In the first embodiment, in the processing groove forming step ST1, the control unit 16 sets two or more different processing conditions.

  In the processing groove forming step ST1, the operator operates the input unit 15 to input an instruction to start forming the processing groove 100, and when the control unit 16 receives an instruction to start forming the processing groove 100, the laser processing apparatus 10 The back surface 7 side of the semiconductor wafer 1 is suction-held on the holding surface 12 of the chuck table 11 via the adhesive tape 8, and the annular frame 9 is clamped by the clamp 17. In the processing groove forming step ST1, the laser processing apparatus 10 positions the chuck table 11 below the imaging unit 20 with the X-axis moving unit 18, the Y-axis moving unit 19, and the like, and as shown in FIG. An image of the surface 3 of the wafer 1 is taken to detect the planned division line 6, and alignment for aligning the semiconductor wafer 1 with the laser beam irradiation unit 13 is performed.

  The imaging unit 20 includes, as shown in FIG. 4, a CCD (Charge Coupled Device) imaging device 21 for photographing the surface of the semiconductor wafer 1 held on the chuck table 11, an epi-illumination (also referred to as coaxial illumination) 22. , Oblique illumination 23. The CCD imaging device 21 images the surface 3 of the semiconductor wafer 1 held on the chuck table 11 through the condenser lens 24.

  The epi-illumination 22 illuminates the surface of the semiconductor wafer 1 held on the chuck table 11 with illumination light 25 through a condenser lens 24. The optical axis of the illumination light 25 is coaxial with the optical axis of the CCD image sensor 21. The oblique illumination 23 irradiates the surface of the semiconductor wafer 1 held on the chuck table 11 with illumination light 26 without passing through the condenser lens 24. The optical axis of the illumination light 26 crosses the optical axis of the CCD image sensor 21. The epi-illumination 22 and the oblique illumination 23 include, for example, a halogen light source and an LED (Light Emitting Diode), and the light amount is adjusted by the control unit 16. The light amounts of the epi-illumination 22 and the oblique illumination 23 are set by the control unit 16 to be light amounts capable of detecting the planned division line 6 when performing alignment.

  In the processing groove forming step ST1, the laser processing apparatus 10 relatively moves the chuck table 11 along the scheduled division line 6 with respect to the laser beam irradiation unit 13 according to the set processing conditions, as shown in FIG. The laser beam irradiation unit 13 irradiates the functional layer 4 with the laser beam 14 while setting the focal point of the laser beam 14 having a wavelength that is absorptive to the functional layer 4 on the functional layer 4 on the dividing line 6. In the processing groove forming step ST1, the laser processing apparatus 10 performs ablation processing on the functional layer 4 on the line to be divided 6 to form a concave processing groove 100 from the functional layer 4.

  In the first embodiment, in the processing groove forming step ST1, the laser processing apparatus 10 forms the processing groove 100 having a predetermined length at a different position for each set processing condition.

  FIG. 6 is a plan view of a semiconductor wafer on which processing grooves are formed under arbitrary processing conditions in the processing groove forming step of the processing condition selection method shown in FIG. FIG. 7 is a plan view of a semiconductor wafer on which processing grooves are formed under processing conditions different from those in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII in FIGS. 6 and 7. FIG. 9 is a sectional view taken along line IX-IX in FIG.

  In the processing groove forming step ST1, the processing groove 100 formed under arbitrary processing conditions is obtained by removing the functional layer 4 from the groove bottom 101 over the entire length of the processing groove 100, as shown in FIGS. And the substrate 2 is exposed. In the processing groove forming step ST1, a processing groove 100 formed under processing conditions different from arbitrary processing conditions has a function from a groove bottom 101 in a part of the processing groove 100, as shown in FIGS. The layer 4 is removed and the substrate 2 is exposed, and the functional layer 4 remains on the groove bottom 101 in the remaining portion, so that the functional layer 4 covers the substrate 2. Although the present specification shows only the processing groove 100 shown in FIGS. 6 and 7, the processing groove 100 formed by the present invention is not limited to those shown in FIGS.

  The processing condition setting method proceeds to the plasma etching step ST2 when the laser processing apparatus 10 forms all the processing grooves 100 according to all the set processing conditions.

(Plasma etching step)
FIG. 10 is a sectional view showing the configuration of an etching apparatus used in the plasma etching step of the processing condition selection method shown in FIG. FIG. 11 is a cross-sectional view showing a state where the semiconductor wafer shown in FIG. 8 is etched in the plasma etching step of the processing condition selection method shown in FIG. FIG. 12 is a cross-sectional view showing a state where the semiconductor wafer shown in FIG. 9 is etched in the plasma etching step of the processing condition selecting method shown in FIG.

  In the plasma etching step ST2, after performing the processing groove forming step ST1, using the etching apparatus 30 shown in FIG. 10, a plasma 31 that reacts with the substrate 2 but does not react with the functional layer 4 (see FIGS. 11 and 12). ) Is a step of etching the processing groove 100. The etching apparatus 30 shown in FIG. 10 used in the plasma etching step ST2 does not generate plasma from an etching gas or the like in a closed space containing the semiconductor wafer 1 in a vacuum chamber by applying high-frequency power to the electrodes. This is a remote plasma type plasma etching apparatus that introduces a plasma 31 generated outside the vacuum chamber 32 into a closed space 33 inside the vacuum chamber 32. In the first embodiment, the remote plasma type etching apparatus 30 is used in the plasma etching step ST2. However, the present invention may be applied to an etching apparatus that generates the plasma 31 in the closed space 33 in the vacuum chamber 32. good.

In the first embodiment, a fluorine-based gas such as SF ₆ , C ₄ F ₈ or CF ₄ is used as an etching gas in which the plasma 31 reacts with silicon constituting the substrate 2 and does not react with the functional layer 4. In the present invention, the etching gas is not limited to these.

  In the plasma etching step ST2, the etching apparatus 30 transports the semiconductor wafer 1 to the sealed space 33 in the vacuum chamber 32 and places the semiconductor wafer 1 on the chuck table 34 (electrostatic chuck, ESC: Electrostatic chuck) via the adhesive tape 8. 1 is held by suction on the back surface 7 side. In the plasma etching step ST2, the control unit 36, which is a computer of the etching apparatus 30, operates the gas exhaust unit 35 to evacuate the sealed space 33 in the vacuum chamber 32, and operates the inert gas supply unit (not shown) to perform piping. An inert gas is supplied into the closed space 33 through 37, the pressure in the closed space 33 is maintained at a predetermined pressure, and the coolant supply unit 38 is operated to be provided in the electrode 39 on which the chuck table 34 is installed. Helium gas as a refrigerant is circulated in the passage 40.

  In the plasma etching step ST2, the etching apparatus 30 operates the etching gas supply unit 41 to supply the etching gas into the supply pipe 42, and the etching gas is supplied from the high frequency power supply 44 to the electrode 43 attached to the supply pipe 42. And a high-frequency power for generating ions from the high-frequency power supply 44 to the lower electrode 28 is applied. Then, the plasma 31 is generated from the etching flowing in the supply pipe 42, and the plasma 31 is supplied to the closed space 33 through the supply pipe 42.

  In the plasma etching step ST2, since high-frequency power is applied to the electrodes 39 and 43, the plasma 31 is likely to be drawn into the surface of the semiconductor wafer 1 as shown in FIGS. However, in the first embodiment, since the etching gas is a fluorine-based gas and the substrate 2 is made of silicon, the plasma 31 is drawn into the substrate 2 exposed in the processing groove 100 and reacts with the substrate 2. It is not drawn into the functional layer 4 and does not react with the functional layer 4 (or hardly reacts with silicon constituting the substrate 2).

  In the plasma etching step ST2, the plasma 31 etches the substrate 2 exposed at the groove bottom 101 of the processing groove 100, and advances the processing groove 100 toward the back surface 7 at a position where the substrate 2 is exposed at the groove bottom 101. Form deeply. Further, in the plasma etching step ST2, the plasma 31 does not advance the processing groove 100 toward the back surface 7 at the position where the functional layer 4 remains on the groove bottom 101, and changes the state where the functional layer 4 remains on the groove bottom 101. maintain.

  In the plasma etching step ST2, when the etching apparatus 30 performs plasma etching on the semiconductor wafer 1 held on the chuck table 11 for a predetermined time, the process proceeds to the selection step ST3.

  FIG. 13 is a plan view of the semiconductor wafer on which the processing groove shown in FIG. 6 has been formed after the plasma etching step. FIG. 14 is a plan view of the semiconductor wafer on which the processing grooves shown in FIG. 7 have been formed after the plasma etching step. FIG. 15 is a cross-sectional view taken along line XV-XV in FIGS. 13 and 14. FIG. 16 is a sectional view taken along the line XVI-XVI in FIG.

  In the plasma etching step ST2, the processing groove 100 shown in FIGS. 13 and 14 of the semiconductor wafer 1 that has been plasma-etched for a predetermined period of time is located at a position where the substrate 2 was exposed at the groove bottom 101 before the plasma etching step ST2. As shown in FIG. 15, it is formed much deeper than before the plasma etching step ST2. In the plasma etching step ST2, the processing groove 100 shown in FIGS. 13 and 14 of the semiconductor wafer 1 which has been plasma-etched for a predetermined time is located at a position where the functional layer 4 remains on the groove bottom 101 before the plasma etching step ST2. Then, as shown in FIG. 16, the state where the functional layer 4 remains on the groove bottom 101 is maintained.

(Selection step)
The selection step ST3 is a step of observing the processing groove 100 after performing the plasma etching step ST2 and selecting an arbitrary processing condition from which the functional layer 4 has been removed as an appropriate processing condition. In the first embodiment, in the selection step ST3, the semiconductor wafer 1 after the plasma etching step ST2 is suction-held via the adhesive tape 8 on the holding surface 12 of the chuck table 11 of the laser processing apparatus 10 shown in FIG.

  In the selection step ST3, the operator operates the input unit 15 to cause the imaging unit 20 to sequentially image the processing grooves 100 formed at different positions for each processing condition, and display the images on the display unit 27 connected to the control unit 16. Then, the processing grooves 100 are observed in order. The processing groove 100 displayed on the display unit 27 is formed at a position where the substrate 2 is exposed at the groove bottom 101 in the plasma etching step ST2, and is formed much deeper than after the processing groove forming step ST1. At the position where the layer 4 remained, the state where the functional layer 4 remained at the groove bottom 101 was maintained, so that the position where the functional layer 4 remained at the groove bottom 101 and the substrate 2 were exposed. The contrast with the position (difference in color and density of the image) is made larger than before the plasma etching step ST2. In the first embodiment, the processing groove 100 is imaged by the imaging unit 20 in the selection step ST3, but in the present invention, the operator may observe each processing groove 100 with a microscope.

  In the selection step ST3, if the processing groove 100 in which the substrate 2 is exposed on the groove bottom 101 over the entire length of the processing groove 100 sequentially displayed on the display unit 27 exists, the operator The processing conditions for forming the processing groove 100 in which the substrate 2 is exposed at the groove bottom 101 are selected as appropriate processing conditions used for actual processing of the semiconductor wafer 1. In the selection step ST3, when there are a plurality of processing grooves 100 in which the substrate 2 is exposed at the groove bottom 101 over the entire length of the processing grooves 100 sequentially displayed on the display unit 27, the operator An arbitrary processing condition among a plurality of processing conditions for forming the processing groove 100 in which the substrate 2 is exposed at the groove bottom 101 is selected as an appropriate processing condition used for actual processing of the semiconductor wafer 1.

  In the selection step ST3, when the processing groove 100 in which the substrate 2 is exposed on the groove bottom 101 over the entire length of the processing grooves 100 sequentially displayed on the display unit 27 does not exist, the operator selects the groove bottom. The processing condition under which the processing groove 100 having the least functional layer 4 remaining in the substrate 101 is formed may be selected as an appropriate processing condition used in actual processing of the semiconductor wafer 1, and at least one or more processing conditions are set again. Then, the processing may be performed in order from the processing groove forming step ST1. The processing condition selection method according to the first embodiment ends when the selection step ST3 is performed.

  The semiconductor wafer 1 is formed with processing grooves 100 at both ends in the width direction of the respective dividing lines 6 by ablation processing of irradiating a laser beam according to the processing conditions selected in the selection step ST3. It is cut by a cutting device (not shown) or the like, and divided into individual devices 5.

  In the processing condition selection method according to the first embodiment, the plasma etching step ST2 is performed after the processing groove forming step ST1, and the plasma 31 that does not react with the functional layer 4 is used in the plasma etching step ST2. The difference in depth between the position where the functional layer 4 remains on the groove bottom 101 of the groove 100 and the position where the substrate 2 is exposed is increased. For this reason, the processing condition selection method uses a method in which when observing the processing groove 100 in the selection step ST3, the contrast between the position where the functional layer 4 remains on the groove bottom 101 and the position where the substrate 2 is exposed is reduced by plasma. It can be made larger than before the etching step ST2, and the height difference between the position where the substrate 2 is exposed at the groove bottom 101 and the position where the functional layer 4 remains at the groove bottom 101 becomes clear. As a result, the processing condition selection method can easily check whether or not the functional layer 4 remains at the groove bottom 101 of the processing groove 100, and can easily select appropriate processing conditions. It works.

[Embodiment 2]
A processing condition selection method according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 17 is a diagram illustrating a binary image obtained by imaging a semiconductor wafer on which a processing groove is formed under arbitrary processing conditions in a selection step of the processing condition selection method according to the second embodiment. FIG. 18 is a diagram illustrating a binary image obtained by imaging a semiconductor wafer on which a processing groove is formed under processing conditions different from those in FIG. 17 in the selection step of the processing condition selection method according to the second embodiment. 17 and 18, the same parts as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

  The processing condition selection method according to the second embodiment is the same as the first embodiment except that the selection step ST3 is different. In the selection step ST3 of the processing condition selection method according to the second embodiment, when the imaging unit 20 captures an image of each processing groove 100, the amount of light received when the CCD imaging device 21 captures an image of the functional layer 4 is predetermined. The illumination lights 25 and 26 of the epi-illumination 22 and the oblique illumination 23 so that the amount of light received when the CCD image sensor 21 images the substrate 2 exposed at the groove bottom 101 of the processing groove 100 is less than the threshold and is less than the threshold. Are set.

  In the second embodiment, in the selection step ST3, the control unit 16, which is a computer of the laser processing apparatus 10, performs binarization processing on an image obtained by imaging the processing groove 100 by the imaging unit 20 using the above-described threshold. Thus, the binary images 201 and 202 shown in FIGS. 17 and 18 are generated. Specifically, in the second embodiment, in the selection step ST3, the control unit 16 sets an area of the image captured by the CCD image sensor 21 where the amount of received light exceeds a predetermined threshold value to white (both binarization). 17 and FIG. 18, and the area below the threshold is black (also called zero of binarization, and is shown by dense parallel oblique lines in FIGS. 17 and 18). FIG. 17 is a binary image of the semiconductor wafer shown in FIG. 13, and FIG. 18 is a binary image of the semiconductor wafer shown in FIG.

  In the second embodiment, in the selection step ST3, the control unit 16 extracts the processing groove 100 from the generated binary images 201 and 202, and calculates the area of the functional layer 4 in the processing groove 100. In the second embodiment, in the selection step ST3, the control unit 16 displays the area of the functional layer 4 in each processing groove 100 on the display unit 27. In the second embodiment, in the selection step ST3, the operator subsequently selects appropriate processing conditions based on the area of the functional layer 4 in each processing groove 100 displayed on the display unit 27, as in the first embodiment. . Further, in the present invention, in the selection step ST3, the display unit 27 may display each of the binary images 201 and 202, and the control unit 16 determines that the processing condition where the area of the processing groove 100 is the largest is an appropriate processing condition. May be selected.

  In this case, the laser processing device 10 is a processing condition selection device that selects processing conditions for removing the functional layer 4 of the semiconductor wafer 1 from the surface 3 of the substrate 2, and the laser beam irradiation unit 13 processes the functional layer 4 The imaging unit 20 is an imaging unit that captures an image of the processing groove 100 formed in the semiconductor wafer 1. The control unit 16 is a processing groove forming unit that forms the groove 100. It is a selection means for selecting the processing conditions.

  In the processing condition selection method according to the second embodiment, as in the first embodiment, the plasma etching step ST2 is performed after the processing groove forming step ST1, and the plasma 31 that does not react with the functional layer 4 in the plasma etching step ST2 is used. The difference in depth between the position where the functional layer 4 remains on the groove bottom 101 of the processed groove 100 after the etching step ST2 and the position where the substrate 2 is exposed is increased. In the processing condition selection method according to the second embodiment, the control unit 16 calculates the area of the functional layer 4 on the groove bottom 101 of each processing groove 100. As a result, the processing condition selection method can easily check whether or not the functional layer 4 remains at the groove bottom 101 of the processing groove 100, and can easily select appropriate processing conditions. It works.

(Modification)
A processing condition selection method according to a modification of the first and second embodiments of the present invention will be described with reference to the drawings. FIG. 19 is a perspective view showing an example of a semiconductor wafer to be processed under processing conditions selected by the processing condition selection method according to the modification of the first and second embodiments. In FIG. 19, the same portions as those in the first and second embodiments are denoted by the same reference numerals, and description thereof will be omitted.

  In the semiconductor wafer 1 to be processed under the processing conditions selected by the processing condition selection method according to the modification, the functional layer 4 has a low dielectric constant insulator film (Low-k film) and a TEG (Test Element Group). ) And a dummy pattern for CMP (Chemical Mechanical Polishing). The TEG is a test pattern formed of a metal or the like and for finding out problems in designing and manufacturing the device 5. The dummy pattern for CMP is used to uniformly remove the semiconductor wafer 1 during the CMP polishing and to suppress a variation in the thickness of the semiconductor wafer 1.

  As in the first and second embodiments, the processing condition selection method according to the modified example performs the plasma etching step ST2 after the processing groove forming step ST1 and uses the plasma 31 that does not react with the functional layer 4 in the plasma etching step ST2. Therefore, the difference in depth between the position where the functional layer 4 remains on the groove bottom 101 of the processing groove 100 after the plasma etching step ST2 and the position where the substrate 2 is exposed is increased. As a result, the processing condition selection method according to the modified example can easily confirm whether or not the functional layer 4 remains at the groove bottom 101 of the processing groove 100 as in the first and second embodiments. As a result, it is possible to easily select appropriate processing conditions.

  Note that the present invention is not limited to the above embodiment and the like. That is, various modifications can be made without departing from the gist of the present invention. For example, in the present invention, the functional layer 4 of the semiconductor wafer 1 may be an oxide film or a nitride film formed on the surface of the semiconductor wafer 1. In short, in the present invention, it is sufficient that the functional layer 4 includes at least one of a low dielectric constant insulator film (Low-k film), a metal component 4-1, an oxide film, and a nitride film. In the first and second embodiments, the selection step ST3 is performed using the laser processing apparatus 10. However, in the selection step ST3, a unit requiring the same function as the imaging unit 20 and the control unit 16 is used in the selection step ST3. An apparatus different from the laser processing apparatus 10 including the above may be used.

DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 2 Substrate 3 Surface 4 Functional layer 4-1 Metal part (TEG)
14 Laser beam 31 Plasma 100 Processing groove ST1 Processing groove forming step ST2 Plasma etching step ST3 Selection step

Claims (4)

A processing condition selection method for selecting processing conditions for removing a functional layer of a semiconductor wafer having a functional layer laminated on a surface of a substrate,
A processing groove forming step of setting an arbitrary processing condition and irradiating the functional layer with a laser beam having a wavelength at which the functional layer has absorptivity to form a processing groove,
A plasma etching step of etching the processing groove by plasma that reacts with the substrate but does not react with the functional layer after performing the processing groove forming step;
A selection step of observing the processing groove after performing the plasma etching step and selecting any processing condition in which the functional layer is removed as an appropriate processing condition;
A method for selecting processing conditions, comprising: Set any two or more processing conditions,
The processing condition selection method according to claim 1, wherein an appropriate processing condition is selected.   The method according to claim 1, wherein the functional layer is a low dielectric constant insulating film or TEG.   The method according to any one of claims 1 to 3, wherein the substrate is silicon.

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