CN117594529A - Wafer processing method - Google Patents

Wafer processing method Download PDF

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Publication number
CN117594529A
CN117594529A CN202310974559.3A CN202310974559A CN117594529A CN 117594529 A CN117594529 A CN 117594529A CN 202310974559 A CN202310974559 A CN 202310974559A CN 117594529 A CN117594529 A CN 117594529A
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China
Prior art keywords
wafer
processing
processing groove
protective film
forming step
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Chinese (zh)
Inventor
小田中健太郎
胡恬钧
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Disco Corp
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Disco Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K10/00—Welding or cutting by means of a plasma
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/362—Laser etching
    • B23K26/364—Laser etching for making a groove or trench, e.g. for scribing a break initiation groove
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005—Apparatus not specifically provided for elsewhere
    • H01L21/67011—Apparatus for manufacture or treatment
    • H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00—Articles made by soldering, welding or cutting
    • B23K2101/36—Electric or electronic devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Mechanical Engineering (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

The invention provides a wafer processing method, which can improve processing quality in plasma etching. The wafer processing method comprises the following steps: a 1 st processing groove forming step of forming a 1 st processing groove on the functional layer by irradiating laser light from the front surface of the wafer along a dividing line; a mask protective film forming step of forming a protective film that covers the front surface of the wafer and fills the 1 st processing groove after the 1 st processing groove forming step is performed; a 2 nd processing groove forming step of forming a 2 nd processing groove having a smaller width than the 1 st processing groove by irradiating the 1 st processing groove with laser light after the mask protective film forming step is performed, and exposing the substrate along the 2 nd processing groove; and a plasma etching step of performing plasma etching along the 2 nd processing groove using the protective film as a mask after the 2 nd processing groove forming step is performed.

Description

Wafer processing method
Technical Field
The present invention relates to a wafer processing method.
Background
In the case of performing plasma dicing on a wafer having a functional layer laminated on a substrate, first, a pretreatment is performed (a protective film is formed on the front surface of the wafer, laser light is irradiated along a predetermined line for dividing, the protective film and the functional layer are removed to expose the substrate), and then, plasma dicing is performed using the protective film as a mask (for example, see patent document 1).
Patent document 1: japanese patent laid-open No. 2022-052821
However, due to the thermal influence of the laser beam, the side surface of the functional layer or the front surface of the exposed substrate melts, and a modified layer having irregularities, micro cracks, and being brittle than other regions is formed.
When plasma etching is performed in a state where such a region is exposed, the irregularities are etched so as to extend in the depth direction, and irregularities are formed on the side surfaces of the etched substrate, which deteriorates the processing quality.
Disclosure of Invention
Accordingly, an object of the present invention is to provide a wafer processing method capable of improving processing quality in plasma etching.
According to the present invention, there is provided a method of processing a wafer, in which a wafer having a plurality of devices formed by functional layers laminated on a front surface of a substrate is processed along a plurality of dividing lines dividing intersections of the plurality of devices, the method of processing the wafer including the steps of: a 1 st processing groove forming step of forming a 1 st processing groove on the functional layer by irradiating laser light from the front surface of the wafer along the dividing line; a mask protective film forming step of forming a mask protective film that covers the front surface of the wafer and fills the 1 st processing groove after the 1 st processing groove forming step is performed; a 2 nd processing groove forming step of forming a 2 nd processing groove having a narrower width than the 1 st processing groove by irradiating a laser beam along the 1 st processing groove after the mask protective film forming step is performed, and exposing the substrate along the 2 nd processing groove; and a plasma etching step of performing plasma etching along the 2 nd processing groove using the protective film for mask as a mask after the 2 nd processing groove forming step is performed.
Preferably, the output of the laser beam irradiated in the 2 nd processing groove forming step is smaller than that in the 1 st processing groove forming step.
Preferably, in the plasma etching step, the wafer is divided to manufacture a plurality of device chips.
The preferred wafer processing method further comprises the steps of: a 1 st protective film forming step of forming a 1 st protective film on the front surface of the wafer before performing the 1 st processing groove forming step; and a 1 st protective film removing step of cleaning and removing the 1 st protective film after the 1 st processing groove forming step is performed.
Preferably, the width of the 1 st processing groove is not all the same, and the width of the 2 nd processing groove is all the same.
Preferably, the 1 st processing groove has a width wider than the metal member laminated on the front surface of the line to divide.
The invention has the effect of improving the processing quality in plasma etching.
Drawings
Fig. 1 is a perspective view schematically showing a wafer to be processed, which is a processing method of a wafer according to embodiment 1.
Fig. 2 is a cross-sectional view schematically showing a main portion of the wafer shown in fig. 1.
Fig. 3 is a flowchart showing a flow of a wafer processing method according to embodiment 1.
Fig. 4 is a cross-sectional view schematically showing a main portion of the wafer after the 1 st protective film forming step of the processing method of the wafer shown in fig. 3.
Fig. 5 is a cross-sectional view schematically showing a main portion of a wafer after a groove forming step of the 1 st processing method of the wafer shown in fig. 3.
Fig. 6 is a cross-sectional view schematically showing a main portion of the wafer after the 1 st protective film removal step of the processing method of the wafer shown in fig. 3.
Fig. 7 is a cross-sectional view schematically showing a main portion of the wafer after a mask protective film forming step of the processing method of the wafer shown in fig. 3.
Fig. 8 is a cross-sectional view schematically showing a main portion of a wafer after a formation step of a 2 nd process groove of the processing method of the wafer shown in fig. 3.
Fig. 9 is a cross-sectional view schematically showing a main portion of a wafer in a plasma etching step of the processing method of the wafer shown in fig. 3.
Fig. 10 is a cross-sectional view schematically showing a main portion of the wafer after a mask protective film removal step of the processing method of the wafer shown in fig. 3.
Fig. 11 is a cross-sectional view schematically showing a main portion of a wafer after the 1 st protective film forming step in the wafer processing method according to the modification example of embodiment 1.
Fig. 12 is a cross-sectional view schematically showing a main portion of a wafer after a step of forming a 1 st processing groove in the processing method of the wafer according to the modification example of embodiment 1.
Fig. 13 is a cross-sectional view schematically showing a main portion of a wafer after the 1 st protective film removal step in the processing method of the wafer according to the modification example of embodiment 1.
Fig. 14 is a cross-sectional view schematically showing a main portion of a wafer after a mask protective film forming step in a wafer processing method according to a modification of embodiment 1.
Fig. 15 is a cross-sectional view schematically showing a main portion of a wafer after a step of forming a groove in a 2 nd processing groove in a method of processing a wafer according to a modification of embodiment 1.
Fig. 16 is a cross-sectional view schematically showing a main part of a wafer in a plasma etching step in a method for processing a wafer according to a modification example of embodiment 1.
Fig. 17 is a cross-sectional view schematically showing a main portion of a wafer after a mask protective film removal step in a wafer processing method according to a modification of embodiment 1.
Fig. 18 is a plan view schematically showing a main portion of a wafer to be processed, which is a processing method of the wafer according to embodiment 2.
Fig. 19 is a cross-sectional view taken along line XIX-XIX in fig. 18.
FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18.
Fig. 21 is a cross-sectional view schematically showing a cross section perpendicular to a 1 st division line of a main portion of a wafer after a 1 st protective film forming step in the wafer processing method of embodiment 2.
Fig. 22 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st protective film forming step of the wafer processing method of embodiment 2.
Fig. 23 is a cross-sectional view schematically showing a cross section perpendicular to a 1 st division line of a main portion of a wafer after a 1 st processing groove forming step in the processing method of the wafer according to embodiment 2.
Fig. 24 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 1 st processing groove forming step in the processing method of the 2 nd embodiment.
Fig. 25 is a cross-sectional view schematically showing a cross section perpendicular to a 1 st division line of a main portion of a wafer after a 1 st protective film removal step in the wafer processing method of embodiment 2.
Fig. 26 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st protective film removal step in the wafer processing method of embodiment 2.
Fig. 27 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the mask protective film forming step in the wafer processing method according to embodiment 2.
Fig. 28 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film forming step in the wafer processing method according to embodiment 2.
Fig. 29 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 2 nd processing groove forming step in the processing method of the 2 nd embodiment of the wafer.
Fig. 30 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 2 nd processing groove forming step in the processing method of the 2 nd embodiment of the wafer.
Fig. 31 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of a main portion of a wafer in a plasma etching step of the wafer processing method of embodiment 2.
Fig. 32 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of a main portion of a wafer in a plasma etching step of the processing method of the wafer of embodiment 2.
Fig. 33 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the mask protective film removal step in the wafer processing method according to embodiment 2.
Fig. 34 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film removal step in the wafer processing method according to embodiment 2.
Fig. 35 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 1 st protective film forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 36 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st protective film forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 37 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 1 st processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 38 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 39 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 1 st protective film removal step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 40 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 1 st protective film removal step in a method of processing a wafer according to a modification example of embodiment 2.
Fig. 41 is a cross-sectional view schematically showing a cross-section perpendicular to the 1 st division line of a main portion of the wafer after the mask protective film forming step in the wafer processing method according to the modification example of embodiment 2.
Fig. 42 is a cross-sectional view schematically showing a cross-section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film forming step in the wafer processing method according to the modification example of embodiment 2.
Fig. 43 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of a main portion of a wafer after a 2 nd processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 44 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 2 nd processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 45 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of a main portion of a wafer in a plasma etching step in a wafer processing method according to a modification example of embodiment 2.
Fig. 46 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of a main portion of a wafer in a plasma etching step in a wafer processing method according to a modification example of embodiment 2.
Fig. 47 is a cross-sectional view schematically showing a cross-section perpendicular to the 1 st division line of the main portion of the wafer after the mask protective film removal step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 48 is a cross-sectional view schematically showing a cross-section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film removal step in the wafer processing method according to the modification example of embodiment 2.
Description of the reference numerals
1: a wafer; 2: a substrate; 3: a front face; 4: dividing a predetermined line; 5: a device; 6: a functional layer; 7: 1 st division scheduled line (division scheduled line); 8: the 2 nd division scheduled line (division scheduled line); 9: a back surface; 10: a device chip; 13: a 1 st protective film; 14. 141, 142: a 1 st processing groove; 14-1, 141-1, 142-1: a width; 15: a protective film for a mask; 16: a 2 nd processing groove; 16-1: a width; 101: a 1 st protective film forming step; 102: a step 1 of forming a machining groove; 103: a 1 st protective film removing step; 104: a mask protective film forming step; 105: a 2 nd processing groove forming step; 106: a plasma etching step; 107: and a mask protective film removing step.
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The present invention is not limited to the following embodiments. The constituent elements described below include those that can be easily understood by those skilled in the art and those that are substantially the same. The structures described below may be appropriately combined. Various omissions, substitutions and changes in the structure may be made without departing from the spirit of the invention.
[ embodiment 1 ]
A method for processing a wafer according to embodiment 1 of the present invention will be described with reference to the accompanying drawings. Fig. 1 is a perspective view schematically showing a wafer to be processed, which is a processing method of a wafer according to embodiment 1. Fig. 2 is a cross-sectional view schematically showing a main portion of the wafer shown in fig. 1. Fig. 3 is a flowchart showing a flow of a wafer processing method according to embodiment 1.
(wafer)
The wafer processing method of embodiment 1 is the wafer processing method 1 shown in fig. 1. In embodiment 1, the wafer 1 is a wafer such as a disk-shaped semiconductor wafer having silicon, glass, siC, sapphire, gallium arsenide, or the like as the substrate 2. As shown in fig. 1, a device 5 is formed on a front surface 3 of a wafer 1 in a region divided in a lattice shape by a plurality of lines 4 for dividing formed in a lattice shape.
The device 5 is, for example, an integrated circuit such as an IC (Integrated Circuit: integrated circuit) or an LSI (Large Scale Integration: large scale integration), a CCD (Charge Coupled Device: inductive coupling element), a memory (semiconductor memory device), or the like.
In embodiment 1, as shown in fig. 1 and 2, a wafer 1 has a functional layer 6 laminated on the front surface of a substrate 2. The functional layer 6 has: a Low dielectric constant insulator film (hereinafter referred to as a Low-k film) composed of an inorganic film such as SiOF or BSG (SiOB), an organic film which is a polymer film such as polyimide film or parylene film, or a silicon oxide-containing film (SiOCH); and a circuit layer configured to include a conductive metal pattern or a metal film.
The Low-k film is laminated with the circuit layer to form the device 5. The circuit layer constitutes the circuit of the device 5. Therefore, the device 5 is composed of Low-k films laminated on each other and a circuit layer laminated between the Low-k films of the functional layers 6 laminated on the substrate 2. At the lines 4 to be divided, the functional layer 6 is composed of a Low-k film laminated on the substrate 2.
When the wafer 1 is cut from the front surface 3 side by a cutting tool, the functional layer 6 such as a Low-k film is easily peeled from the substrate 2. Thus, in embodiment 1, the wafer 1 forms the device 5 on the front surface 3 through the functional layer 6 laminated on the substrate 2.
In embodiment 1, the line 4 to be divided has a plurality of lines 7 to be divided 1 which are parallel to each other and a plurality of lines 8 to be divided 2 which are parallel to each other and intersect the lines 7 to be divided 1 (intersect in embodiment 1). In this way, the wafer 1 has the plurality of devices 5 and the lines 7 and 8 for dividing the plurality of devices 5 formed on the front surface 3. In embodiment 1, the width of the 1 st line 7 to be divided of the wafer 1 is equal to the width of the 2 nd line 8 to be divided.
(wafer processing method)
The wafer processing method according to embodiment 1 is a method of processing a wafer 1 having a plurality of devices 5 formed by a functional layer 6 laminated on the front surface of a substrate 2 along lines 7 and 8 for dividing the plurality of devices 5. In embodiment 1, the wafer processing method is also a method of dividing (corresponding to processing) the wafer 1 along the lines 7 and 8 to form the device chips 10 (shown in fig. 1). In addition, the device chip 10 includes a part of the substrate 2 and the devices 5.
As shown in fig. 3, the wafer processing method includes a 1 st protective film forming step 101, a 1 st processing groove forming step 102, a 1 st protective film removing step 103, a mask protective film forming step 104, a 2 nd processing groove forming step 105, a plasma etching step 106, and a mask protective film removing step 107. In embodiment 1, as shown in fig. 1, a wafer 1 is processed by a wafer processing method, a disk-shaped tape 11 having a larger diameter than the wafer 1 is attached to a back surface 9 on the back surface side of the front surface 3 of the wafer 1, and an annular frame 12 is attached to the outer edge portion of the tape 11 and supported by the frame 12.
(1 st protective film Forming step)
Fig. 4 is a cross-sectional view schematically showing a main portion of the wafer after the 1 st protective film forming step of the processing method of the wafer shown in fig. 3. The 1 st protective film forming step 101 is a step of forming a 1 st protective film 13 (shown in fig. 4) on the front surface 3 of the wafer 1 before performing the 1 st processing groove forming step 102.
In embodiment 1, in the 1 st protective film forming step 101, a resin coating device, not shown, sucks and holds the back surface 9 side of the wafer 1 on the holding surface of the rotary table via the belt 11, clamps the frame 12 by the clamp portion, rotates the rotary table around the axis, and drops the liquid water-soluble resin from the water-soluble resin supply nozzle to the center of the front surface 3 of the wafer 1. The water-soluble resin dropped flows from the center side toward the outer peripheral side on the front surface 3 of the wafer 1 by the centrifugal force generated by the rotation of the rotary table, and is applied to the entire front surface 3 of the wafer 1. In all the embodiments, the structure including the frame 12 is described, but the frame 12 may not be used.
The water-soluble resin includes, for example, a water-soluble resin such as polyvinyl alcohol (polyvinyl alcohol: PVA) or Polyvinylpyrrolidone (PVP). In the 1 st protective film forming step 101, the water-soluble resin applied to the entire front surface 3 of the wafer 1 is dried, whereby the entire front surface 3 of the wafer 1 is covered with the 1 st protective film 13 containing the water-soluble resin as shown in fig. 4. Thus, in embodiment 1, the 1 st protective film 13 is made of a water-soluble resin. The water-soluble resin constituting the 1 st protective film 13 has resistance, and when the water-soluble resin is dried, the etching rate by the plasma etching gas 18 (shown in fig. 9) used in the plasma etching step 106 is lower than that of the substrate 2.
(1 st processing groove formation step)
Fig. 5 is a cross-sectional view schematically showing a main portion of a wafer after a groove forming step of the 1 st processing method of the wafer shown in fig. 3. The 1 st processing groove forming step 102 is a step of forming a 1 st processing groove 14 (shown in fig. 5) on the functional layer 6 by irradiating a laser beam, not shown, from the front surface 3 of the wafer 1 along the lines 7 and 8.
In embodiment 1, in step 102 of forming the 1 st processing groove, a laser processing apparatus, not shown, sucks and holds the back surface 9 side of the wafer 1 on the holding surface of the holding table via the belt 11, and clamps the frame 12 with the clamp portion. In embodiment 1, in step 102 of forming the 1 st processing groove, the laser processing apparatus photographs the front surface 3 side of the wafer 1 by a photographing means, not shown, detects the lines 7 and 8 to align the laser beam irradiation means with the lines 7 and 8.
In embodiment 1, in the 1 st processing groove forming step 102, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines to divide 7 and 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines to divide 7 and 8. In embodiment 1, in step 102 of forming the 1 st processing groove, the laser processing apparatus sets the converging point of the laser beam on the front surface of the 1 st protective film 13 or the front surface of the substrate 2, and irradiates the wafer 1 with the laser beam along the lines 7 and 8.
In embodiment 1, in step 102 of forming the 1 st processing groove, the laser processing apparatus ablates the 1 st protective film 13, the functional layer 6, and the substrate 2 on the lines 7 and 8 to remove a part of them, and as shown in fig. 5, forms the 1 st processing groove 14 for cutting the functional layer 6 on the lines 7 and 8.
In embodiment 1, in step 102 of forming the 1 st processing groove, laser light is irradiated to both edges in the width direction of each planned cutting line 7, 8, ablation processing is performed on the 1 st protective film 13, the functional layer 6, and the substrate 2 on both edges in the width direction of each planned cutting line 4 to form the processing groove, and then laser light is irradiated between the processing grooves of each planned cutting line 7, 8, and ablation processing is performed on the 1 st protective film 13, the functional layer 6, and the substrate 2 between the processing grooves of each planned cutting line 4 to form the 1 st processing groove 14. In embodiment 1, in the process step 102 of forming the 1 st processing groove, a laser beam having a wavelength of 355nm (not limited to 355nm, preferably a wavelength in the ultraviolet region) and a repetition frequency of 200kHz to 2000kHz is irradiated.
In embodiment 1, in step 102 of forming the 1 st processing groove, two edge processing grooves are formed on both edges of the planned dividing lines 7 and 8 in the width direction, and when ablation processing is performed, the average output of the laser beam is set to 0.5W, the relative movement speed of the laser beam irradiation unit and the wafer (hereinafter referred to as processing feed speed) is set to 100 mm/sec to 400 mm/sec, and the spot of the converging point of the laser beam is set to a circular shape having a diameter of 5 μm. In embodiment 1, in the step 102 of forming the 1 st processing groove, when ablation processing is performed between the processing grooves on both edges of the lines to be divided 7, 8, the average output of the laser beam is set to 10.0W, the processing feed speed is set to 200 mm/sec to 1000 mm/sec, and the spot of the converging point of the laser beam is set to a rectangle having a width of 60 μm.
In embodiment 1, the widths 14-1 of all the 1 st processing grooves 14 are the same.
(1 st protective film removing step)
Fig. 6 is a cross-sectional view schematically showing a main portion of the wafer after the 1 st protective film removal step of the processing method of the wafer shown in fig. 3. The 1 st protective film removal step 103 is a step of cleaning and removing the 1 st protective film 13 after the 1 st processing groove formation step 102 is performed.
In embodiment 1, in the 1 st protective film removing step 103, a cleaning device, not shown, sucks and holds the rear surface 9 side of the wafer 1 on the holding surface of the spin base via the belt 11, clamps the frame 12 by the clamp portion, and supplies cleaning water composed of pure water from the cleaning water supply nozzle to the center of the front surface 3 of the wafer 1 in a state where the spin base is rotated around the axis. The cleaning water supplied to the front surface 3 of the wafer 1 flows from the center side toward the outer peripheral side on the front surface 3 of the wafer 1 by the centrifugal force generated by the rotation of the rotary table, and cleans the front surface 3 of the wafer 1, and as shown in fig. 6, the 1 st protective film 13 containing the water-soluble resin is removed from the front surface 3 of the wafer 1 together with foreign matter such as chips.
(protective film Forming step for mask)
Fig. 7 is a cross-sectional view schematically showing a main portion of the wafer after a mask protective film forming step of the processing method of the wafer shown in fig. 3. The mask protection film forming step 104 is a mask protection film forming step of forming a mask protection film 15 that covers the front surface 3 of the wafer 1 and fills the 1 st processing groove 14 after the 1 st processing groove forming step 102 is performed.
In embodiment 1, in the mask protective film forming step 104, a resin coating device, not shown, sucks and holds the back surface 9 side of the wafer 1 on the holding surface of the rotary table via the belt 11, clamps the frame 12 by the clamp portion, rotates the rotary table around the axis, and drops the liquid water-soluble resin from the water-soluble resin supply nozzle to the center of the front surface 3 of the wafer 1. The water-soluble resin dropped flows from the center side toward the outer peripheral side on the front surface 3 of the wafer 1 by the centrifugal force generated by the rotation of the rotary table, spreads over the entire front surface 3 of the wafer 1, and fills the 1 st processing tank 14.
The water-soluble resin includes, for example, a water-soluble resin such as polyvinyl alcohol (polyvinyl alcohol: PVA) or Polyvinylpyrrolidone (PVP). In the mask protective film forming step 104, the water-soluble resin applied to the entire front surface 3 of the wafer 1 is dried, whereby the entire front surface 3 of the wafer 1 is covered with the mask protective film 15 containing the water-soluble resin, and the mask protective film 15 is filled into the 1 st processing groove 14, as shown in fig. 7.
Thus, in embodiment 1, the mask protective film 15 is made of a water-soluble resin. The water-soluble resin constituting the mask protective film 15 has resistance, and when the water-soluble resin is dried, the etching rate by the plasma etching gas 18 used in the plasma etching step 106 is lower than that of the substrate 2. In embodiment 1, the material of the water-soluble resin constituting the mask protective film 15 is the same as the water-soluble resin constituting the 1 st protective film 13 formed in the 1 st protective film forming step 101, but in the present invention, the material may be different from the water-soluble resin constituting the 1 st protective film 13 formed in the 1 st protective film forming step 101 as long as the material is resistant to the etching gas 18.
(2 nd Process tank Forming step)
Fig. 8 is a cross-sectional view schematically showing a main portion of a wafer after a formation step of a 2 nd process groove of the processing method of the wafer shown in fig. 3. The 2 nd process groove forming step 105 is a step of forming a 2 nd process groove 16 (shown in fig. 8) having a width 16-1 smaller than the 1 st process groove 14 by irradiating the 1 st process groove 14 with laser light after the mask protective film forming step 104, and exposing the substrate 2 along the 2 nd process groove 16.
In embodiment 1, in the 2 nd processing groove forming step 105, a laser processing apparatus, not shown, sucks and holds the back surface 9 side of the wafer 1 on the holding surface of the holding table via the belt 11, and clamps the frame 12 with the clamp portion. In embodiment 1, in step 105 of forming the 2 nd processing groove, the laser processing apparatus detects the lines to divide 7 and 8 by photographing the front surface 3 side of the wafer 1 with a photographing means, not shown, and performs alignment for aligning the laser beam irradiation means with the lines to divide 7 and 8.
In embodiment 1, in step 105 of forming the 2 nd processing groove, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines to divide 7 and 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines to divide 7 and 8. In embodiment 1, in step 105 of forming the 2 nd processing groove, the laser processing apparatus sets the converging point of the laser beam on the front surface of the mask protection film 15 or the substrate 2, and irradiates the wafer 1 with the laser beam along the 1 st processing groove 14 formed in each of the lines 7 and 8.
In embodiment 1, in step 105 of forming the 2 nd processing groove, the laser processing apparatus ablates the mask protection film 15 and the substrate 2 formed on the bottom surface 17 of the 1 st processing groove 14 of each planned dividing line 7, 8 to remove a part of them, and forms the 2 nd processing groove 16 having a width 16-1 smaller than that of the 1 st processing groove 14 on the bottom surface 17 of the 1 st processing groove 14 where the functional layer 6 is divided on each planned dividing line 7, 8 as shown in fig. 7.
In embodiment 1, in step 105 of forming the 2 nd processing groove, laser light is irradiated to the center in the width direction of the 1 st processing groove 14 formed in each of the lines 7 and 8, and ablation processing is performed on the mask protection film 15 and the substrate 2 on the bottom surface 17 of the 1 st processing groove 14 to form the 2 nd processing groove 16. In embodiment 1, in the 2 nd processing groove forming step 105, a laser beam having a wavelength of 355nm (not limited to 355nm, preferably a wavelength in the ultraviolet region) and a repetition frequency of 200kHz to 1000kHz is irradiated.
In embodiment 1, in the 2 nd processing groove forming step 105, the average output of the laser beam is set to 1.0W, the processing feed speed is set to 200 mm/sec, and the spot of the converging point of the laser beam is set to a circular shape having a diameter of 25 μm to 40 μm. In embodiment 1, in the 2 nd processing groove forming step 105, the average output of the laser beam may be lower than the average output of the laser beam irradiated between the processing grooves in the 1 st processing groove forming step 102. In this way, in embodiment 1, the output of the laser beam irradiated in the 2 nd processing groove forming step 105 is smaller than that in the 1 st processing groove forming step 102. Alternatively, in embodiment 1, the energy density of 1 spot of the laser beam irradiated in the 2 nd processing groove forming step 105 is lower than the energy density of 1 spot of the laser beam irradiated in the 1 st processing groove forming step 102. In embodiment 1, the width 16-1 of all the 2 nd processing grooves 16 is the same.
(plasma etching step)
Fig. 9 is a cross-sectional view schematically showing a main portion of a wafer in a plasma etching step of the processing method of the wafer shown in fig. 3. The plasma etching step 106 is a step of performing plasma etching along the 2 nd processing groove 16 using the mask protection film 15 as a mask after the 2 nd processing groove forming step 105 is performed.
In embodiment 1, in the plasma etching step 106, a plasma etching apparatus, not shown, holds the back surface 9 side of the wafer 1 on the holding surface of the holding table via the belt 11. In embodiment 1, in the plasma etching step 106, the etching gas 18 is supplied to the front surface 3 side of the wafer 1 while high-frequency power for maintaining the production plasma is applied to the upper electrode and high-frequency power for attracting ions is applied to the holding table as the lower electrode.
Then, in embodiment 1, in the plasma etching step 106, the plasma etching apparatus plasmatizes the etching gas 18 that maintains the space between the stage and the upper electrode, attracts the plasmatized etching gas 18 to the wafer 1 side, and etches the substrate 2 of the wafer 1 exposed on the bottom surface of the 2 nd processing groove 16 formed in the mask, i.e., the mask protection film 15 (so-called plasma etching), so that the 2 nd processing groove 16 proceeds toward the back surface 9 of the wafer 1.
In embodiment 1, in the plasma etching step 106, the plasma etching apparatus performs plasma etching on the wafer 1 until the 2 nd processing groove 16 opens on the back surface 9 side to divide the wafer 1 into the device chips 10 as shown in fig. 9. In this way, in embodiment 1, in the plasma etching step 106, the wafer 1 is divided to manufacture a plurality of device chips 10.
(protective film removal step for mask)
Fig. 10 is a cross-sectional view schematically showing a main portion of the wafer after a mask protective film removal step of the processing method of the wafer shown in fig. 3. The mask protective film removal step 107 is a step of cleaning and removing the mask protective film 15 after the plasma etching step 106 is performed.
In embodiment 1, in the mask protective film removing step 107, a cleaning device, not shown, sucks and holds the back surface 9 side of the wafer 1 on the holding surface of the spin base via the belt 11, clamps the frame 12 by the clamp portion, and supplies cleaning water composed of pure water or pure water containing a surface active material from the cleaning water supply nozzle to the center of the front surface 3 of the wafer 1 in a state where the spin base is rotated around the axis. The cleaning water supplied to the front surface 3 of the wafer 1 flows from the center side toward the outer peripheral side on the front surface 3 of the wafer 1 by the centrifugal force generated by the rotation of the rotary table, and the front surface 3 of the wafer 1 is cleaned, and as shown in fig. 10, the mask protection film 15 including the water-soluble resin is removed from the front surface 3 of the wafer 1 together with foreign matter such as debris.
In the conventional processing method, when the substrate 2 on the bottom surface of the 1 st processing groove 14 is subjected to plasma etching, the 1 st protective film 13 and the functional layer 6 are removed to form the 1 st processing groove 14, and therefore irradiation of a laser beam having a large output is required, and heat damage to the functional layer 6 is also large, and irregularities are generated particularly in the functional layer 6 on the inner side surface of the 1 st processing groove 14. Therefore, in the conventional processing method, when plasma etching is performed on the substrate 2 on the bottom surface of the 1 st processing groove 14, the substrate 2 is etched along the irregularities of the inner surface of the 1 st processing groove 14, particularly the functional layer 6, and the irregularities are generated on the side surface of the device chip 10, thereby reducing the bending strength of the device chip 10.
In the processing method of the wafer according to embodiment 1 described above, compared with the conventional processing method, the mask protection film 15 is filled in the 1 st processing groove 14, the 2 nd processing groove 16 is formed by removing the mask protection film 15 in the 1 st processing groove 14, and the mask protection film 15 is processed with energy smaller than that of the functional layer 6, so that the output of the laser beam at the time of forming the 2 nd processing groove 16 can be suppressed to be smaller than the output of the laser beam at the time of forming the 1 st processing groove 14. Therefore, in the method for processing a wafer according to embodiment 1, the thermal damage to the mask protection film 15 when the 2 nd processing groove 16 is formed can be suppressed to be smaller than the thermal damage to the functional layer 6 when the 1 st processing groove 14 is formed, and the concave-convex of the inner surface of the 2 nd processing groove 16 formed in the mask protection film 15 can be suppressed as compared with the concave-convex of the inner surface of the 1 st processing groove 14 formed in the functional layer 6.
In the method for processing a wafer according to embodiment 1, since the mask protective film 15 is processed with energy smaller than that of the functional layer 6, the output of the laser beam in the 2 nd processing groove forming step 105 can be made smaller than the output of the laser beam in the 1 st processing groove forming step 102, the 2 nd processing groove 16 can be formed, and the irregularities generated on the inner surface of the 2 nd processing groove 16 can be reduced. While the side surface of the device chip 10 formed by plasma etching is transferred with the irregularities on the side surface of the processing groove as a mask, in the processing method of the wafer according to embodiment 1, the irregularities on the inner side surface of the processing groove 16 as a mask are small, and therefore the irregularities on the side surface of the device chip 10 can be reduced.
As a result, in the wafer processing method according to embodiment 1, since the substrate 2 on the bottom surface of the 2 nd processing groove 16 is etched along the 2 nd processing groove 16 in the plasma etching step 106, the processing quality can be improved in the plasma etching, and the uneven surface of the side surface of the device chip 10 can be suppressed, and the decrease in the bending strength of the device chip 10 can be suppressed.
Modification example
A method for processing a wafer according to a modification of embodiment 1 will be described with reference to the accompanying drawings. Fig. 11 is a cross-sectional view schematically showing a main portion of a wafer after the 1 st protective film forming step in the wafer processing method according to the modification example of embodiment 1. Fig. 12 is a cross-sectional view schematically showing a main portion of a wafer after a step of forming a 1 st processing groove in the processing method of the wafer according to the modification example of embodiment 1. Fig. 13 is a cross-sectional view schematically showing a main portion of a wafer after the 1 st protective film removal step in the processing method of the wafer according to the modification example of embodiment 1. Fig. 14 is a cross-sectional view schematically showing a main portion of a wafer after a mask protective film forming step in a wafer processing method according to a modification of embodiment 1. Fig. 15 is a cross-sectional view schematically showing a main portion of a wafer after a step of forming a groove in a 2 nd processing groove in a method of processing a wafer according to a modification of embodiment 1. Fig. 16 is a cross-sectional view schematically showing a main part of a wafer in a plasma etching step in a method for processing a wafer according to a modification example of embodiment 1. Fig. 17 is a cross-sectional view schematically showing a main portion of a wafer after a mask protective film removal step in a wafer processing method according to a modification of embodiment 1. In fig. 11, 12, 13, 14, 15, 16, and 17, the same parts as those in embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.
The method for processing the wafer according to the modification example of embodiment 1 is a method for dividing the wafer 1 into the device chips 10 along the lines 7 and 8, as in embodiment 1. The processing method of the wafer according to the modification example of embodiment 1 includes a 1 st protective film forming step 101, a 1 st processing groove forming step 102, a 1 st protective film removing step 103, a mask protective film forming step 104, a 2 nd processing groove forming step 105, a plasma etching step 106, and a mask protective film removing step 107, as in embodiment 1.
In the modification of embodiment 1, in the 1 st protective film forming step 101, as in embodiment 1, the entire front surface 3 of the wafer 1 is covered with the 1 st protective film 13 containing a water-soluble resin, as shown in fig. 11.
In the modification of embodiment 1, in the process groove forming step 102 of embodiment 1, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines 7 and 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines 7 and 8, as in embodiment 1.
In the modification of embodiment 1, in step 102 of forming the 1 st processing groove, the laser processing apparatus ablates the 1 st protective film 13 and the functional layer 6 on the lines 7 and 8 to remove a part of them, and as shown in fig. 12, the 1 st processing groove 14 recessed from the front surface of the functional layer 6 and not cutting the functional layer 6 is formed on the lines 7 and 8.
In the modification of embodiment 1, in the 1 st protective film removing step 103, as in embodiment 1, the front surface 3 of the wafer 1 is cleaned and the 1 st protective film 13 is removed from the front surface 3 of the wafer 1 as shown in fig. 13.
In the modification of embodiment 1, in the mask protective film forming step 104, as in embodiment 1, the entire front surface 3 of the wafer 1 is covered with the mask protective film 15 containing a water-soluble resin, and the mask protective film 15 is filled into the 1 st processing groove 14, as shown in fig. 14.
In the modification of embodiment 1, in the 2 nd processing groove forming step 105, as in embodiment 1, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines to divide 7, 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines to divide 7, 8.
In the modification of embodiment 1, in step 105 of forming the 2 nd processing groove, the laser processing apparatus ablates the mask protection film 15, the functional layer 6, and the substrate 2 formed on the bottom surface 17 of the 1 st processing groove 14 of each planned dividing line 7, 8 to remove a part of them, and as shown in fig. 15, forms the 2 nd processing groove 16 having a width 16-1 smaller than that of the 1 st processing groove 14 and breaking the functional layer 6 on the bottom surface 17 of the 1 st processing groove 14 of each planned dividing line 7, 8.
In the modification of embodiment 1, the output of the laser beam irradiated in the 2 nd processing groove forming step 105 is smaller than that in the 1 st processing groove forming step 102. Alternatively, in the modification of embodiment 1, the energy density of 1 spot of the laser beam irradiated in the 2 nd processing groove forming step 105 is lower than the energy density of 1 spot of the laser beam irradiated in the 1 st processing groove forming step 102. In the modification of embodiment 1, the widths 14-1 of all the 1 st processing grooves 14 are the same, and the widths 16-1 of all the 2 nd processing grooves 16 are the same.
In the modification of embodiment 1, in the plasma etching step 106, as in embodiment 1, as shown in fig. 16, the substrate 2 of the wafer 1 exposed on the bottom surface of the 2 nd processing groove 16 formed in the mask protective film 15, that is, the mask, is etched (so-called plasma etching), and the 2 nd processing groove 16 is advanced toward the back surface 9 of the wafer 1, and the wafer 1 is subjected to plasma etching until the wafer 1 is divided into the device chips 10.
In the modification of embodiment 1, in the mask protective film removal step 107, as in embodiment 1, the front surface 3 of the wafer 1 is cleaned, and the mask protective film 15 including the water-soluble resin is removed from the front surface 3 of the wafer 1 together with foreign matter such as debris, as shown in fig. 17.
In the processing method of the wafer according to the modification example of embodiment 1, as in embodiment 1, the mask protection film 15 is filled in the 1 st processing groove 14, and the 2 nd processing groove 16 is formed by removing the mask protection film 15 in the 1 st processing groove 14, so that the following effects are obtained: the irregularities on the inner side surface of the 2 nd processing groove 16 can be suppressed to be smaller than the irregularities on the inner side surface of the 1 st processing groove 14, and the irregularities on the side surface of the dividing groove formed by plasma etching can be reduced, so that the bending strength of the manufactured device chip 10 can be improved, and the processing quality can be improved. In the processing method of the wafer according to the modification example of embodiment 1, as compared with example 1 in which the 1 st processing groove 14 having a depth at which the functional layer 6 is to be broken is formed at one time in the 1 st processing groove forming step 102, the 1 st processing groove 14 having a depth at which the functional layer 6 is to be broken is formed by being divided into the 1 st processing groove forming step 102 and the 2 nd processing groove forming step 105, the following effects are obtained: the thermal influence generated between the functional layer 6 and the substrate 2 is reduced, and the flexural strength of the device chip 10 is improved. In the processing method of the wafer according to the modification example of embodiment 1, since the remaining functional layer 6 and the mask protective film 15 are removed in the 2 nd processing groove forming step 105 to expose the substrate 2, the output of the laser beam is increased as compared with the 2 nd processing groove forming step 105 of embodiment 1, but the roughness of the side surface of the 2 nd processing groove 16 is reduced as compared with the conventional technique in which the functional layer 6 is exposed on the entire inner side surface of the 2 nd processing groove 16 as a mask, and the processing quality at the time of plasma etching can be improved.
[ embodiment 2 ]
A method for processing a wafer according to embodiment 2 will be described with reference to the accompanying drawings. Fig. 18 is a plan view schematically showing a main portion of a wafer to be processed, which is a processing method of the wafer according to embodiment 2. Fig. 19 is a cross-sectional view taken along line XIX-XIX in fig. 18. FIG. 20 is a cross-sectional view taken along line XX-XX in FIG. 18. Fig. 21 is a cross-sectional view schematically showing a cross section perpendicular to a 1 st division line of a main portion of a wafer after a 1 st protective film forming step in the wafer processing method of embodiment 2. Fig. 22 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st protective film forming step of the wafer processing method of embodiment 2.
Fig. 23 is a cross-sectional view schematically showing a cross section perpendicular to a 1 st division line of a main portion of a wafer after a 1 st processing groove forming step in the processing method of the wafer according to embodiment 2. Fig. 24 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 1 st processing groove forming step in the processing method of the 2 nd embodiment. Fig. 25 is a cross-sectional view schematically showing a cross section perpendicular to a 1 st division line of a main portion of a wafer after a 1 st protective film removal step in the wafer processing method of embodiment 2. Fig. 26 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st protective film removal step in the wafer processing method of embodiment 2.
Fig. 27 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the mask protective film forming step in the wafer processing method according to embodiment 2. Fig. 28 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film forming step in the wafer processing method according to embodiment 2. Fig. 29 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 2 nd processing groove forming step in the processing method of the 2 nd embodiment of the wafer. Fig. 30 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 2 nd processing groove forming step in the processing method of the 2 nd embodiment of the wafer.
Fig. 31 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of a main portion of a wafer in a plasma etching step of the wafer processing method of embodiment 2. Fig. 32 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of a main portion of a wafer in a plasma etching step of the processing method of the wafer of embodiment 2. Fig. 33 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the mask protective film removal step in the wafer processing method according to embodiment 2. Fig. 34 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film removal step in the wafer processing method according to embodiment 2. In fig. 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33 and 34, the same parts as those in embodiment 1 are denoted by the same reference numerals, and description thereof is omitted.
As shown in fig. 18, in wafer 1, which is the object of the wafer processing method according to embodiment 2, the width of line 7 for dividing 1 is smaller than the width of line 8 for dividing 2. As shown in fig. 18 and 20, in wafer 1, which is the object of the wafer processing method according to embodiment 2, TEG (Test Elementary Group: test element group) 21, which is a metal member, is stacked on the front surface of line 8 for dividing 2. In embodiment 2, as shown in fig. 18 and 19, the wafer 1 is also laminated with the TEG 22 as a metal member on the front surface of the 1 st line 7, but in the present invention, the TEG 22 may not be laminated on the front surface of the 1 st line 7.
The TEGs 21 and 22 are elements for evaluation for finding problems in design and manufacture of the device 5. The TEG 21 of the wafer 1 to be processed, which is the processing method of the wafer according to embodiment 2, has a width slightly smaller than the width of the line 8 for dividing 2 and a width wider than the line 7 for dividing 1. In embodiment 2, the width of the TEG 22 is slightly smaller than the width of the 1 st line 7.
The wafer processing method of embodiment 2 is a method of dividing the wafer 1 into individual device chips 10 along the lines 7 and 8, as in embodiment 1. The wafer processing method of embodiment 2 includes, as in embodiment 1, a 1 st protective film forming step 101, a 1 st processing groove forming step 102, a 1 st protective film removing step 103, a mask protective film forming step 104, a 2 nd processing groove forming step 105, a plasma etching step 106, and a mask protective film removing step 107.
In embodiment 2, in the 1 st protective film forming step 101, as in embodiment 1, as shown in fig. 21 and 22, the entire front surface 3 of the wafer 1 is covered with the 1 st protective film 13 containing a water-soluble resin.
In embodiment 2, in the 1 st processing groove forming step 102, as in embodiment 1, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines to divide 7, 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines to divide 7, 8.
In order to suppress burrs from being generated in the TEGs 21 and 22 and to ensure the processing quality of the device chip 10, it is necessary to remove the entirety of the TEGs 21 and 22 stacked on the front surfaces of the lines to be divided 7 and 8 in the 1 st processing groove forming step 102. In the wafer 1 to be processed in the wafer processing method according to embodiment 2, the TEG 21 is slightly narrower than the width of the line 8 for dividing 2 and wider than the width of the line 7 for dividing 1.
Therefore, in the wafer processing method according to embodiment 2, in step 102 of forming the 1 st processing groove, the width 141-1 of the 1 st processing groove 14 (hereinafter referred to as 141 in fig. 23) formed in the 1 st line to divide 7 is made narrower than the width 142-1 of the 1 st processing groove 14 (hereinafter referred to as 142 in fig. 24) formed in the 2 nd line to divide 8. In the wafer processing method according to embodiment 2, the 1 st processing grooves 141 and 142 formed in the 1 st processing groove forming step 102 have widths 141-1 and 142-1 wider than the widths of the TEGs 22 and 21 as metal members. In this way, in the wafer processing method according to embodiment 2, the widths 141-1 and 142-1 of the 1 st processing grooves 141 and 142 formed in the 1 st processing groove forming step 102 are not all the same. In embodiment 2, the width 141-1 of the 1 st processing groove 141 is 60mm, and the width 142-1 of the 1 st processing groove 142 is 120mm.
In embodiment 2, in the 1 st processing groove forming step 102, the laser processing apparatus ablates the 1 st protective film 13, the TEGs 21, 22, the functional layer 6, and the substrate 2 on the lines 7, 8 to remove a part of the 1 st protective film 13, the functional layer 6, and the substrate 2, and the TEGs 21, 22 as a whole, and as shown in fig. 23 and 24, 1 st processing grooves 141, 142 for cutting the functional layer 6 are formed on the lines 7, 8.
In embodiment 2, in the 1 st protective film removing step 103, as in embodiment 1, the front surface 3 of the wafer 1 is cleaned and the 1 st protective film 13 is removed from the front surface 3 of the wafer 1 as shown in fig. 25 and 26.
In embodiment 2, in the mask protective film forming step 104, as in embodiment 1, as shown in fig. 27 and 28, the entire front surface 3 of the wafer 1 is covered with the mask protective film 15 containing a water-soluble resin, and the mask protective film 15 is filled into the 1 st processing grooves 141 and 142.
In embodiment 2, in the process step 105 of forming the 2 nd processing groove, as in embodiment 1, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines 7 and 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines 7 and 8.
In embodiment 2, in the 2 nd processing groove forming step 105, the laser processing apparatus performs ablation processing on the mask protection film 15 and the substrate 2 formed on the bottom surfaces 17 of the 1 st processing grooves 141, 142 of the lines to be divided 7, 8 to remove a part of them, and as shown in fig. 29 and 30, forms the 2 nd processing groove 16 having a width 16-1 smaller than the 1 st processing grooves 141, 142 on the bottom surfaces 17 of the 1 st processing grooves 141, 142 of the lines to be divided 7, 8.
In embodiment 2, the output of the laser beam irradiated in the 2 nd processing groove forming step 105 is smaller than that in the 1 st processing groove forming step 102. In embodiment 2, the width 16-1 of all the 2 nd processing grooves 16 is the same.
In embodiment 2, as in embodiment 1, in the plasma etching step 106, as shown in fig. 31 and 32, the substrate 2 of the wafer 1 exposed on the bottom surface of the 2 nd processing groove 16 formed in the mask protective film 15, that is, the mask, is etched (so-called plasma etching), and the 2 nd processing groove 16 is advanced toward the back surface 9 of the wafer 1, and the wafer 1 is subjected to plasma etching until the wafer 1 is divided into the device chips 10.
In embodiment 2, in the mask protective film removal step 107, as in embodiment 1, the front surface 3 of the wafer 1 is cleaned, and the mask protective film 15 containing a water-soluble resin is removed from the front surface 3 of the wafer 1 together with foreign matter such as debris, as shown in fig. 33 and 34.
In the wafer processing method according to embodiment 2, as in embodiment 1, the mask protection film 15 is filled in the 1 st processing grooves 141 and 142, and the 2 nd processing groove 16 is formed by removing the mask protection film 15 in the 1 st processing grooves 141 and 142, so that the following effects are obtained: the irregularities on the inner surface of the 2 nd processing groove 16 can be suppressed to be smaller than the irregularities on the inner surface of the 1 st processing groove 14, and the processing quality can be improved in plasma etching.
In order to suppress burrs from being generated in the TEGs 21, 22, when the TEGs 21, 22 are removed entirely in the 1 st processing groove forming step 102, the widths 141-1, 142-1 of the 1 st processing grooves 141, 142 are different. Therefore, when plasma etching is performed on the wafer 1 by the conventional processing method, a deviation occurs in the processing during plasma etching, and the processing cannot be performed uniformly. However, in the wafer processing method according to embodiment 2, the widths 141-1 and 142-1 of the 1 st processing grooves 141 and 142 are different, and the widths 16-1 of the 2 nd processing grooves 16 are the same, so that occurrence of variations in processing during plasma etching can be suppressed.
Modification example
A method for processing a wafer according to a modification of embodiment 2 will be described with reference to the accompanying drawings. Fig. 35 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 1 st protective film forming step in the processing method of the wafer according to the modification example of embodiment 2. Fig. 36 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st protective film forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 37 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 1 st processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2. Fig. 38 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of the main portion of the wafer after the 1 st processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2. Fig. 39 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of the main portion of the wafer after the 1 st protective film removal step in the processing method of the wafer according to the modification example of embodiment 2. Fig. 40 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 1 st protective film removal step in a method of processing a wafer according to a modification example of embodiment 2.
Fig. 41 is a cross-sectional view schematically showing a cross-section perpendicular to the 1 st division line of a main portion of the wafer after the mask protective film forming step in the wafer processing method according to the modification example of embodiment 2. Fig. 42 is a cross-sectional view schematically showing a cross-section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film forming step in the wafer processing method according to the modification example of embodiment 2. Fig. 43 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of a main portion of a wafer after a 2 nd processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2. Fig. 44 is a cross-sectional view schematically showing a cross section perpendicular to a 2 nd division line of a main portion of a wafer after a 2 nd processing groove forming step in the processing method of the wafer according to the modification example of embodiment 2.
Fig. 45 is a cross-sectional view schematically showing a cross section perpendicular to the 1 st division line of a main portion of a wafer in a plasma etching step in a wafer processing method according to a modification example of embodiment 2. Fig. 46 is a cross-sectional view schematically showing a cross section perpendicular to the 2 nd division line of a main portion of a wafer in a plasma etching step in a wafer processing method according to a modification example of embodiment 2. Fig. 47 is a cross-sectional view schematically showing a cross-section perpendicular to the 1 st division line of the main portion of the wafer after the mask protective film removal step in the processing method of the wafer according to the modification example of embodiment 2. Fig. 48 is a cross-sectional view schematically showing a cross-section perpendicular to the 2 nd division line of the main portion of the wafer after the mask protective film removal step in the wafer processing method according to the modification example of embodiment 2. In fig. 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47 and 48, the same parts as those in embodiment 1 and embodiment 2 are denoted by the same reference numerals, and description thereof is omitted.
In the wafer 1 to be processed, which is the processing method of the wafer according to the modification of embodiment 2, similarly to embodiment 2, the width of the 1 st line to divide 7 is smaller than the width of the 2 nd line to divide 8, and the TEG 21, which is a metal member, is laminated on the front surface of the 2 nd line to divide 8. In the modification of embodiment 2, the TEG 22 that is a metal member is also laminated on the front surface of the 1 st line of intended division 7 in the wafer 1 as in embodiment 2, but in the present invention, the TEG 22 may not be laminated on the front surface of the 1 st line of intended division 7. In addition, in wafer 1, which is the object of the processing method of the wafer according to the modification of embodiment 2, the width of TEG 21 is narrower than the width of line 8 to divide 2 and wider than the width of line 7 to divide 1.
The method for processing the wafer according to the modification example of embodiment 2 is a method for dividing the wafer 1 into the device chips 10 along the lines 7 and 8, similarly to the embodiments 1 and 2. The method for processing a wafer according to the modification example of embodiment 2 includes a 1 st protective film forming step 101, a 1 st processing groove forming step 102, a 1 st protective film removing step 103, a mask protective film forming step 104, a 2 nd processing groove forming step 105, a plasma etching step 106, and a mask protective film removing step 107, as in embodiment 1 and embodiment 2.
In the modification of embodiment 2, in the 1 st protective film forming step 101, as in embodiment 1, the entire front surface 3 of the wafer 1 is covered with the 1 st protective film 13 containing a water-soluble resin, as shown in fig. 35 and 36.
In the modification of embodiment 2, in the 1 st processing groove forming step 102, as in embodiments 1 and 2, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines 7 and 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines 7 and 8.
In the processing method of the wafer according to the modification example of embodiment 2, in the 1 st processing groove forming step 102, the width 141-1 of the 1 st processing groove 141 formed in the 1 st line to divide 7 is made narrower than the width 142-1 of the 1 st processing groove 142 formed in the 2 nd line to divide 8, as in embodiment 2. In this way, in the processing method of the wafer according to the modification of embodiment 2, the widths 141-1 and 142-1 of the 1 st processing grooves 141 and 142 formed in the 1 st processing groove forming step 102 are not all the same.
In the modification of embodiment 2, in the 1 st processing groove forming step 102, the laser processing apparatus ablates the 1 st protective film 13, TEGs 21, 22 and the functional layer 6 on the respective lines 7, 8 to remove a part of the 1 st protective film 13 and the functional layer 6 and the TEGs 21, 22 as a whole, and as shown in fig. 37 and 38, 1 st processing grooves 141, 142 recessed from the front surface of the functional layer 6 and not cutting the functional layer 6 are formed on the respective lines 7, 8.
In the modification of embodiment 2, in the 1 st protective film removing step 103, the front surface 3 of the wafer 1 is cleaned and the 1 st protective film 13 is removed from the front surface 3 of the wafer 1 as shown in fig. 47 and 48, similarly to the 1 st and 2 nd embodiments.
In the modification of embodiment 2, in the mask protective film forming step 104, as in embodiments 1 and 2, as shown in fig. 41 and 42, the entire front surface 3 of the wafer 1 is covered with the mask protective film 15 containing a water-soluble resin, and the mask protective film 15 is filled into the 1 st processing grooves 141 and 142.
In the modification of embodiment 2, in the 2 nd processing groove forming step 105, as in embodiments 1 and 2, the laser processing apparatus irradiates the wafer 1 with laser light having a wavelength that is absorptive to the wafer 1 along the lines 7 and 8 from the laser light irradiation means while relatively moving the wafer 1 and the laser light irradiation means along the lines 7 and 8.
In the modification of embodiment 2, in the 2 nd processing groove forming step 105, the laser processing apparatus performs ablation processing on the mask protection film 15, the functional layer 6, and the substrate 2 formed on the bottom surfaces 17 of the 1 st processing grooves 141 and 142 of the lines to be divided 7 and 8, and removes a part of them, and as shown in fig. 43 and 44, forms the 2 nd processing groove 16 having a width 16-1 smaller than the 1 st processing grooves 141 and 142 and breaking the functional layer 6 on the bottom surfaces 17 of the 1 st processing grooves 141 and 142 of the lines to be divided 7 and 8.
In the modification of embodiment 2, the output of the laser beam irradiated in the 2 nd processing groove forming step 105 is smaller than that in the 1 st processing groove forming step 102. Alternatively, in the modification of embodiment 2, the energy density of 1 spot of the laser beam irradiated in the 2 nd processing groove forming step 105 is lower than the energy density of 1 spot of the laser beam irradiated in the 1 st processing groove forming step 102. In the modification of embodiment 2, the widths 16-1 of all the 2 nd processing grooves 16 are the same.
In the modification of embodiment 2, in the plasma etching step 106, as in embodiment 1 and embodiment 2, as shown in fig. 45 and 46, the substrate 2 of the wafer 1 exposed on the bottom surface of the 2 nd processing groove 16 formed in the mask, i.e., the mask protection film 15 is etched (so-called plasma etching), the 2 nd processing groove 16 is advanced toward the back surface 9 of the wafer 1, and the wafer 1 is subjected to plasma etching until the wafer 1 is divided into the device chips 10.
In the modification of embodiment 2, in the mask protective film removal step 107, as in embodiment 1, the front surface 3 of the wafer 1 is cleaned, and the mask protective film 15 including the water-soluble resin is removed from the front surface 3 of the wafer 1 together with foreign matter such as debris, as shown in fig. 33 and 34.
In the processing method of the wafer according to the modification of embodiment 2, as in embodiments 1 and 2, the mask protection film 15 is filled in the 1 st processing grooves 141 and 142, and the 2 nd processing groove 16 is formed by removing the mask protection film 15 in the 1 st processing grooves 141 and 142, so that the following effects are obtained: the irregularities on the inner surface of the 2 nd processing groove 16 can be suppressed to be smaller than the irregularities on the inner surface of the 1 st processing groove 14, and the processing quality can be improved in plasma etching.
In the processing method of the wafer according to the modification example of embodiment 2, as in embodiment 2, the widths 141-1 and 142-1 of the 1 st processing grooves 141 and 142 are different, and the width 16-1 of the 2 nd processing groove 16 is the same, so that occurrence of variations in processing during plasma etching can be suppressed.
The present invention is not limited to the above embodiment. That is, various modifications may be made and implemented within a range not departing from the gist of the present invention. For example, in the present invention, the 1 st protective film forming step 101 and the 1 st protective film removing step 103 may not be performed. In the present invention, the wafer 1 may not be divided into the device chips 10 in the plasma etching step 106.

Claims (6)

1. A wafer processing method for processing a wafer having a plurality of devices formed by a functional layer laminated on the front surface of a substrate along a plurality of dividing lines dividing intersections of the plurality of devices, wherein,
the wafer processing method comprises the following steps:
a 1 st processing groove forming step of forming a 1 st processing groove on the functional layer by irradiating laser light from the front surface of the wafer along the dividing line;
a mask protective film forming step of forming a mask protective film that covers the front surface of the wafer and fills the 1 st processing groove after the 1 st processing groove forming step is performed;
a 2 nd processing groove forming step of forming a 2 nd processing groove having a narrower width than the 1 st processing groove by irradiating a laser beam along the 1 st processing groove after the mask protective film forming step is performed, and exposing the substrate along the 2 nd processing groove; and
and a plasma etching step of performing plasma etching along the 2 nd processing groove using the protective film for mask as a mask after the 2 nd processing groove forming step is performed.
2. The method for processing a wafer according to claim 1, wherein,
the output of the laser beam irradiated in the 2 nd processing groove forming step is small compared to that in the 1 st processing groove forming step.
3. The method for processing a wafer according to claim 1, wherein,
in the plasma etching step, the wafer is divided to manufacture a plurality of device chips.
4. The method for processing a wafer according to claim 1, wherein,
the wafer processing method also comprises the following steps:
a 1 st protective film forming step of forming a 1 st protective film on the front surface of the wafer before performing the 1 st processing groove forming step; and
and a 1 st protective film removing step of cleaning and removing the 1 st protective film after the 1 st processing groove forming step is performed.
5. The method for processing a wafer according to claim 1, wherein,
the widths of the 1 st processing groove are not all the same, and the widths of the 2 nd processing groove are all the same.
6. The method for processing a wafer as set forth in claim 5, wherein,
the 1 st processing groove has a width wider than the metal member laminated on the front surface of the line to divide.
CN202310974559.3A 2022-08-15 2023-08-03 Wafer processing method Pending CN117594529A (en)

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JP2022-129400 2022-08-15

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