JP2020043196A - Silicon carbide semiconductor device - Google Patents

Abstract

To provide a silicon carbide semiconductor device with low channel resistance of a channel layer and high gate threshold voltage.SOLUTION: A silicon carbide semiconductor device is a vertical transistor, and comprises: a first layer 21 of a silicon carbide semiconductor of a first conductivity type; a second layer 22 of a silicon carbide semiconductor of a second conductivity type on the first layer 21; a third layer 23 of the silicon carbide semiconductor of the first conductivity type on the second layer 22; a groove 30, an insulation film 40 provided inside the groove 30; and a gate electrode 51 provided on the insulation film 40. Concentration of an impurity element of a second conductivity type in an interface between the second layer 22 and the third layer 23 exceeds a half value of a concentration peak value of an impurity element of the second conductivity type in the second layer 22. Concentration of an impurity element of the second conductivity type in an interface between the first layer 21 and the second layer 22 is less than a half value of a concentration peak value of an impurity element of the second conductivity type in the second layer 22 and higher than or equal to 1/20.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a silicon carbide semiconductor device.

  Silicon carbide has a wider band gap than silicon which has been widely used in conventional semiconductor devices, and is therefore used in high breakdown voltage semiconductor devices and the like. In a semiconductor device using such silicon carbide, there is a so-called vertical transistor having a structure in which a source electrode is formed on a first surface and a drain electrode is formed on a second surface, from the viewpoint of withstand voltage and the like. In such a vertical transistor, a groove is formed on one surface of the substrate, and a gate electrode is formed by filling the inside of the groove.

JP 2009-259896 A JP 2017-139441 A

  In a silicon carbide semiconductor device such as a vertical transistor as described above, the channel resistance of the channel layer is reduced in order to reduce the on-resistance, and the gate threshold voltage is increased in order to prevent malfunction due to noise and the like. Both are required.

  According to one aspect of the present embodiment, a silicon carbide semiconductor device includes a first layer of a first conductivity type silicon carbide semiconductor and a second conductivity type silicon carbide on the first layer that is different from the first conductivity type. A second layer of a semiconductor, a third layer of a silicon carbide semiconductor of the first conductivity type on the second layer, a third layer, the second layer, a groove having a side surface in a part of the first layer, The vertical transistor includes an insulating film provided inside the groove and a gate electrode provided on the insulating film inside the groove. Further, the concentration of the impurity element of the second conductivity type at the interface between the second layer and the third layer exceeds half the peak value of the concentration of the impurity element of the second conductivity type in the second layer. The concentration of the impurity element of the second conductivity type at the interface between the first layer and the second layer is less than half the value of the peak value of the concentration of the impurity element of the second conductivity type in the second layer. That is all.

  According to the present disclosure, in the silicon carbide semiconductor device, it is possible to lower the channel resistance of the channel layer and increase the gate threshold voltage.

FIG. 1 is a structural diagram of a silicon carbide semiconductor device. FIG. 2 is an explanatory diagram of the impurity concentration of the silicon carbide semiconductor device according to the embodiment of the present disclosure. FIG. 3 is a process diagram (1) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 4 is a process diagram (2) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 5 is a process diagram (3) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 6 is a process diagram (4) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 7 is a process diagram (5) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 8 is a process diagram (6) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 9 is a process diagram (7) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 10 is a process diagram (8) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 11 is a process diagram (9) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 12 is a process diagram (10) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 13 is a process diagram (11) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 14 is a process diagram (12) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 15 is a process diagram (13) of the method for manufacturing the silicon carbide semiconductor device according to the first embodiment of the present disclosure. FIG. 16 is a structural diagram of the silicon carbide semiconductor device according to the second embodiment of the present disclosure.

  An embodiment for carrying out the invention will be described below.

[Description of Embodiment of the Present Disclosure]
First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements have the same reference characters allotted, and the same description will not be repeated. In the crystallographic description of this specification, [] indicates an individual direction, <> indicates a collective direction, () indicates an individual plane, and indicates a collective plane with ｛｝. Here, a negative crystallographic index is usually expressed by adding a "-" (bar) over a number, but in this specification, a negative sign is added before the number. It represents a negative index in crystallography. Further, the epitaxial growth of the present disclosure is homoepitaxial growth.

  [1] A semiconductor device according to an embodiment of the present disclosure includes a first layer of a first conductivity type silicon carbide semiconductor and a second conductivity type silicon carbide on the first layer, the second conductivity type being different from the first conductivity type. A second layer of a semiconductor, a third layer of the first conductivity type silicon carbide semiconductor on the second layer, and side surfaces of the third layer, the second layer, and a part of the first layer A vertical transistor having a trench, an insulating film provided inside the trench, and a gate electrode provided on the insulating film inside the trench, wherein the second layer and the third The concentration of the impurity element of the second conductivity type at the interface with the layer exceeds half the value of the peak value of the concentration of the impurity element of the second conductivity type in the second layer. The concentration of the impurity element of the second conductivity type at the interface with the second layer is the same as that of the second conductivity type in the second layer. Less than half the value of the peak value of the concentration of pure object elements it is 1/20 or more.

  In silicon carbide semiconductor devices such as vertical transistors, it is required to lower both the channel resistance of the channel layer in order to reduce the on-resistance and to increase the gate threshold voltage in order to prevent malfunction due to noise. ing. However, there is a strong trade-off between reducing the channel resistance of the channel layer and increasing the gate threshold voltage, and it is not easy to improve both of them.

  Therefore, the inventor of the present application focused on the range and concentration of doping with an n-type impurity element and a p-type impurity element, and made intensive studies on obtaining a thin channel layer with a high impurity concentration. As a result, the concentration of the p-type impurity element at the interface between the channel layer and the contact layer exceeds half the peak value of the concentration of the p-type impurity element in the channel layer. In addition, the concentration of the p-type impurity element at the interface between the drift layer and the channel layer is less than half the value of the peak value of the concentration of the p-type impurity element in the channel layer, and 1/20 or more. As described above, it has been found that by doping the p-type impurity element and the n-type impurity element, both the reduction of the channel resistance of the channel layer and the increase of the gate threshold voltage can be achieved. Was. The present application is based on the findings thus found.

  [2] The first layer includes a first conductivity type impurity element and a second conductivity type impurity element, and 1 <(concentration of the first conductivity type impurity element) / (second conductivity type impurity element). Of impurity element) ≦ 2.

  [3] The first layer is formed on a first surface of the silicon carbide single crystal substrate, and includes a source electrode in contact with the third layer, and a first surface of the silicon carbide single crystal substrate. And a drain electrode provided on the second surface opposite to the second surface.

  [4] The polytype of the silicon carbide single crystal substrate is 4H, the surface of the third layer is a Si surface, and the side surface of the groove is perpendicular to the surface of the third layer.

  [5] The polytype of the silicon carbide single crystal substrate is 4H, the surface of the third layer is a C plane, and the side surface of the groove is at least 50 ° and at most 60 ° with respect to the surface of the third layer. It is.

[6] The peak value of the effective doping concentration in the second layer is 5.0 × 10 ¹⁷ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less.

[Details of Embodiment of the Present Disclosure]
Hereinafter, an embodiment of the present disclosure (hereinafter, referred to as “the present embodiment”) will be described in detail, but the present embodiment is not limited thereto.

[First Embodiment]
First, a vertical transistor which is a silicon carbide semiconductor device will be described with reference to FIG. In the following drawings of the structure of the silicon carbide semiconductor device, for convenience, the thickness, width, and the like of each layer forming the silicon carbide semiconductor device are different from actual ones.

  A silicon carbide semiconductor device serving as a vertical transistor shown in FIG. 1 includes a first n-type layer 21, a p-type layer 22, and a second n-type layer on first surface 10 a of silicon carbide single crystal substrate 10. Layers 23 are sequentially formed. Further, the groove 30 is formed by removing the second n-type layer 23, the p-type layer 22, and the first n-type layer 21. The groove 30 is formed so that the side surface 30 a is perpendicular to the surface of the second n-type layer 23, and the side surface 30 a of the groove 30 is formed on the second n-type layer 23, the p-type layer 22, One n-type layer 21 is formed. A gate insulating film 40 is formed on the side surface 30 a and the bottom surface 30 b inside the groove 30 and on the second n-type layer 23 near the groove 30, and on the gate insulating film 40 inside the groove 30. Has a gate electrode 51 formed thereon.

  A high concentration p-type region 24 having a high impurity concentration is formed in a region apart from the trench 30 where the gate insulating film 40 is not formed by ion-implanting a p-type impurity element. On the gate electrode 51, an interlayer insulating film 61 is formed so as to cover the entire gate electrode 51, and a barrier metal layer 62 that covers the interlayer insulating film 61 is formed.

  Further, a Ni film is formed on a part of the second n-type layer 23 and the high-concentration p-type region 24, and heat treatment is performed so that Ni and the second n-type layer 23 and the high-concentration p-type 24 is alloyed with Si (silicon) contained therein, and the ohmic contact layer 52a is formed of NiSi. By forming the ohmic contact layer 52a in this manner, the contact resistance can be reduced. On the ohmic contact layer 52a and the barrier metal layer 62, a source electrode 52 is formed of Al or the like, and on the source electrode 52, a passivation film 63 is formed. An ohmic contact layer 53a is formed on a second surface 10b of the silicon carbide single crystal substrate 10 opposite to the first surface 10a by forming a Ni film and performing heat treatment. The drain electrode 53 is formed on the layer 53a.

  The first n-type layer 21 is an n-type drift layer, in which an n-type impurity element is doped at a relatively low concentration. The p-type layer 22 is a p-type channel layer, and is a layer doped with an impurity element that becomes p. The second n-type layer 23 is a high-concentration n-type contact layer, and has a higher concentration of the n-type impurity element than the first n-type layer 21. The high-concentration p-type region 24 is a high-concentration p-type contact region, and has a higher concentration of the p-type impurity element than the p-type layer 22. In the present application, the first n-type layer 21 may be referred to as a first layer, the p-type layer 22 may be referred to as a second layer, and the second n-type layer 23 may be referred to as a third layer.

  In the vertical silicon carbide semiconductor device shown in FIG. 1, when a predetermined voltage is applied to gate electrode 51, a channel is formed in a region of p-type layer 22 near gate insulating film 40, and the first n The conduction between the mold layer 21 and the second n-type layer 23 is established. Thereby, a current flows between source electrode 52 and drain electrode 53, and the silicon carbide semiconductor device is turned on. Note that when a predetermined voltage is not applied to the gate electrode 51, no channel is formed in the p-type layer 22 and no current flows between the source electrode 52 and the drain electrode 53. The semiconductor device is turned off.

  The vertical silicon carbide semiconductor device shown in FIG. 1 uses a silicon carbide epitaxial substrate in which a silicon carbide epitaxial layer is formed on first surface 10 a of silicon carbide single crystal substrate 10. The silicon carbide epitaxial layer is doped with an n-type impurity element. A p-type layer 22 is formed from the surface of the silicon carbide epitaxial layer by ion-implanting Al (aluminum) as a p-type impurity element, and P (phosphorus) is ion-implanted as an n-type impurity element. As a result, a second n-type layer 23 is formed. In the ion implantation of the silicon carbide epitaxial layer, the depth at which the ions of the impurity element are implanted can be changed by changing the acceleration voltage or the like of the ions of the impurity element to be implanted. In this manner, second n-type layer 23 is formed on the surface side of the silicon carbide epitaxial layer, and p-type layer 22 is formed in a region deeper than second n-type layer 23. In the silicon carbide epitaxial layer, a region excluding the p-type layer 22 and the second n-type layer 23 into which the impurity element has been ion-implanted becomes the first n-type layer 21. High-concentration p-type region 24 is formed by ion-implanting Al as a p-type impurity element from the surface of the silicon carbide epitaxial layer.

  In the vertical silicon carbide semiconductor device, the channel resistance of p-type layer 22 serving as a channel layer is reduced, the gate threshold voltage of gate voltage applied to gate electrode 51 is increased, and source electrode 52 and drain It is required to increase the breakdown voltage between the electrode 53 and the electrode 53. By reducing the channel resistance of p-type layer 22 serving as a channel layer, the on-resistance of the silicon carbide semiconductor device can be reduced. In addition, if the gate threshold voltage of gate electrode 51 is low, the silicon carbide semiconductor device is likely to be erroneously turned on due to the influence of noise or the like. Therefore, it is preferable that the gate threshold voltage be high. By increasing the breakdown voltage between source electrode 52 and drain electrode 53, the silicon carbide semiconductor device can have a higher breakdown voltage.

  In a vertical silicon carbide semiconductor device, lowering the channel resistance in the p-type layer 22 and increasing the gate threshold voltage are in a trade-off relationship, and it is easy to satisfy both requirements. is not.

(Silicon carbide semiconductor device)
Next, the silicon carbide semiconductor device according to the first embodiment will be described. The polytype of silicon carbide in silicon carbide single crystal substrate 10 is 4H. This is because 4H polytype silicon carbide is superior to other polytypes in electron mobility, breakdown electric field strength, and the like. The silicon carbide semiconductor device according to the present embodiment is different from the vertical silicon carbide semiconductor device shown in FIG. 1 in that the impurity concentration of p-type layer 22 is increased in order to increase the gate threshold voltage, The film thickness is reduced. R _ch channel resistance, the thickness of the p-type layer 22 serving as the channel layer L, and the mobility of carriers in the p-type layer 22 and mu _n, if the proportional constant was k, these are the number 1 below It has the relationship of the formula shown.

According to the equation shown in Equation 1, when the mobility mu _n of the carrier is lowered, the channel resistance R _ch is increased, if the film thickness L of the p-type layer 22 is made thinner channel resistance R _ch is lower.

The higher the impurity concentration of the p-type layer 22 in order to increase the gate threshold voltage, mobility mu _n carrier is reduced in the p-type layer 22, the channel resistance R _ch is increased. Therefore, by making the film thickness L of the p-type layer 22 as thin as possible, the increase in the channel resistance R _ch is suppressed, and the channel resistance R _ch is further reduced. As a result, both increasing the gate threshold voltage and decreasing the channel resistance _Rch are achieved.

  The silicon carbide semiconductor device according to the present embodiment has an impurity element concentration distribution profile as shown in FIG. FIG. 2 shows, in the silicon carbide semiconductor device shown in FIG. 1, the interface between second n-type layer 23 and gate insulating film 40 and ohmic contact layer 52 a of source electrode 52 in the depth direction of the silicon carbide semiconductor layer. 2 shows a concentration distribution of an impurity element. In FIG. 2, the P concentration (Nd) of an n-type impurity element serving as a donor, the Al concentration (Na) of a p-type impurity element serving as an acceptor, the concentration of the n-type impurity element and the p-type impurity element Is the effective doping concentration (| Na-Nd |), which is the difference in the concentration of GaAs.

  Note that the concentration of the n-type impurity element and the concentration of the p-type impurity element can be measured by SIMS (Secondary Ion Mass Spectrometry). The effective donor concentration (Nd-Na) is a value obtained by subtracting the concentration (Na) of a p-type impurity element serving as an acceptor from the concentration (Nd) of an n-type impurity element serving as a donor. The effective acceptor concentration (Na-Nd) is a value obtained by subtracting the concentration (Nd) of an n-type impurity element serving as a donor from the concentration (Na) of a p-type impurity element serving as an acceptor. In the present application, the effective donor concentration (Nd-Na) and the effective acceptor concentration (Na-Nd) may be described as an effective doping concentration (| Na-Nd |).

In the silicon carbide semiconductor device of the present embodiment, the concentration (Nd) of the n-type impurity element in the region up to about 0.27 μm in the depth direction from the surface of the second n-type layer 23 is the p-type impurity element. Is higher than the concentration (Na), and this region becomes the second n-type layer 23. Therefore, the thickness of the second n-type layer 23 is about 0.27 μm, and the peak value of the effective donor concentration (Nd—Na) in the second n-type layer 23 is about 2 × 10 ¹⁹ cm ^{− 3} .

Next, in the region from about 0.27 μm to about 0.57 μm in the depth direction from the surface of the second n-type layer 23, the concentration (Na) of the p-type impurity element is changed to the concentration of the n-type impurity element (Na). Nd) is more p-type, and this region becomes the p-type layer 22. Accordingly, the thickness of the p-type layer 22 is about 0.30 μm, and the peak value of the concentration (Na) of Al, which is a p-type impurity element, in the p-type layer 22 is about 2 × 10 ¹⁸ cm ⁻³ . is there. In addition, the peak value of the effective acceptor concentration (Na-Nd) in the p-type layer 22 is preferably 5.0 × 10 ¹⁷ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less, and FIG. In, the value of this peak is about 1.5 × 10 ¹⁸ cm ⁻³ .

Next, in a region deeper than about 0.57 μm in the depth direction from the surface of the second n-type layer 23, the concentration (Nd) of the n-type impurity element is higher than the concentration (Na) of the p-type impurity element. Many are n-type, and this region becomes the first n-type layer 21. In the first n-type layer 21, the value of the effective donor concentration (Nd-Na) is substantially constant at 2 × 10 ^{16 to} 3 × 10 ¹⁶ cm ⁻³ except for the vicinity of the interface with the p-type layer 22. .

Accordingly, an interface between the second n-type layer 23 and the p-type layer 22 is formed at a depth of about 0.27 μm from the surface of the second n-type layer 23, and the n-type interface is formed at this interface. The concentration (Nd) of the impurity element and the concentration (Na) of the p-type impurity element are substantially equal, and are about 1.5 × 10 ¹⁸ cm ⁻³ . This value is larger than about 1 × 10 ¹⁸ cm ^−3, which is half the peak value of the concentration (Na) of the p-type impurity element in the p-type layer 22.

Further, an interface between the p-type layer 22 and the first n-type layer 21 is formed at a position at a depth of about 0.57 μm from the surface of the second n-type layer 23. The concentration (Nd) of the impurity element and the concentration (Na) of the p-type impurity element are substantially equal, and are about 1.5 × 10 ¹⁷ cm ⁻³ . This value is smaller than about 1 × 10 ¹⁸ cm ^−3, which is half the peak value of the concentration (Na) of the p-type impurity element in the p-type layer 22, and is about 1/20, which is 1/20. × 10 ¹⁷ cm ⁻³ or more. Note that the value of the concentration (Nd) of the n-type impurity element at the interface between the p-type layer 22 and the first n-type layer 21 is the peak of the concentration (Na) of the concentration of the p-type impurity element in the p-type layer 22. When the value is more than half of the value, the p-type layer 22 having an effective thickness is not formed. Further, the concentration (Nd) of the n-type impurity element at the interface between the p-type layer 22 and the first n-type layer 21 is set to one of the peak value of the concentration (Na) of the p-type impurity element in the p-type layer 22. By setting / 20 or more, the p-type layer 22 can be thinned.

  Therefore, in the present embodiment, in the first n-type layer 21, the p-type layer 22, and the second n-type layer 23 formed by ion implantation of the impurity element, the n-type impurity at the interface of the p-type layer 22 is formed. By increasing the element concentration (Nd), the thickness of the p-type layer 22 is reduced. That is, when the p-type layer 22 is formed by ion implantation, it is difficult to accurately implant the impurity element to a desired depth, resulting in a concentration distribution as shown in FIG. Therefore, at the interface between the first n-type layer 21 and the p-type layer 22 and the interface between the p-type layer 22 and the second n-type layer 23, the concentration (Nd) of the n-type impurity element is increased. And these interfaces are formed in regions where the concentration of the p-type impurity element is relatively high. Thereby, the impurity concentration in the p-type layer 22 sandwiched between the two interfaces can be increased, the thickness of the p-type layer 22 can be reduced, the channel resistance in the p-type layer 22 can be reduced, and the p-type layer 22 can be gated. The threshold voltage can be increased.

  Furthermore, in the present embodiment, in order to improve the breakdown voltage between the source electrode 52 and the drain electrode 53, the value of the effective donor concentration (Nd-Na) in the first n-type layer 21 is set to be substantially constant. Is formed. Specifically, the relationship between the concentration (Nd) of the n-type impurity element and the concentration (Na) of the p-type impurity element is formed so as to satisfy the following equation (2). The equation shown in the following Expression 2 can be expressed as 1 <(concentration of impurity element of first conductivity type) / (concentration of impurity element of second conductivity type) ≦ 2.

  The concentration ratio (Nd / Na) is larger than 1 because the first n-type layer 21 is n-type. By setting the concentration ratio (Nd / Na) to 2 or less, the first n-type layer 21 is formed. The value of the effective donor concentration (Nd-Na) in the layer 21 can be made substantially constant.

  In the silicon carbide semiconductor device according to the present embodiment, side surface 30 a of trench 30 is formed so as to be perpendicular to the surface of second n-type layer 23, and the surface of second n-type layer 23 has a Si surface. It has become. In the present application, the above-mentioned vertical does not mean vertical in a strict sense, but is a range considered to be vertical and means having a width in a range where the effects of the present embodiment are exhibited. .

(Method of Manufacturing Silicon Carbide Semiconductor Device)
Next, a method for manufacturing the silicon carbide semiconductor device according to the present embodiment will be described with reference to FIGS.

  First, as shown in FIG. 3, silicon carbide epitaxial layer 11 is formed on first surface 10a of silicon carbide single crystal substrate 10. Silicon carbide epitaxial layer 11 is formed by epitaxial growth of silicon carbide to which P is added as an n-type impurity element.

Next, as shown in FIG. 4, p-type layer 22 is formed by ion-implanting Al as a p-type impurity element from surface 11 a of silicon carbide epitaxial layer 11. P type layer 22 has a peak Al concentration at 0.30 μm to 0.37 μm from surface 11 a of silicon carbide epitaxial layer 11, and the Al concentration at this peak is about 2.0 × 10 ¹⁸ cm ^−3. Is formed by ion implantation. The p-type layer 22 is p-type because the concentration of the p-type impurity element is higher than that of the n-type impurity element by ion implantation of Al.

Next, as shown in FIG. 5, P is ion-implanted from surface 11a of silicon carbide epitaxial layer 11 as an n-type impurity element to form second n-type layer 23. Second n-type layer 23 is ion-implanted such that the concentration of P near the surface 11a of silicon carbide epitaxial layer 11 has a peak, and the concentration of P at this peak is about 2.0 × 10 ¹⁹ cm ^−3. It forms by doing. The second n-type layer 23 becomes n-type because the concentration of the n-type impurity element becomes higher than the concentration of the p-type impurity element by ion implantation of P. At this time, it is formed by ion implantation so that the concentration of P at 0.50 μm to 0.60 μm from surface 11 a of silicon carbide epitaxial layer 11 is 1.0 × 10 ¹⁷ cm ⁻³ or more. Thus, a thin p-type layer 22 having a thickness of about 0.3 μm is formed. As described above, by forming p-type layer 22 and second n-type layer 23 by ion implantation, in silicon carbide epitaxial layer 11, a region excluding second n-type layer 23 and p-type layer 22 is formed. Becomes the first n-type layer 21.

  Next, as shown in FIG. 6, from the surface 11 a of the silicon carbide epitaxial layer 11, the second n-type layer 23, the p-type layer 22, and a part of the first n-type layer 21 have a p-type impurity element. To form a high concentration p-type region 24 by ion implantation of Al. The high-concentration p-type region 24 becomes p-type by ion-implanting Al so that the concentration of the p-type impurity element becomes higher than the concentration of the n-type impurity element. Specifically, a hard mask (not shown) having an opening in a region where a high-concentration p-type region 24 is formed is formed on the second n-type layer 23 serving as the surface 11a of the silicon carbide epitaxial layer 11 by using silicon oxide. And ion implantation is performed. Thereby, ions can be implanted into silicon carbide epitaxial layer 11 in the opening of the hard mask, and high-concentration p-type region 24 is formed by such ion implantation.

  Next, as shown in FIG. 7, a groove 30 is formed by partially removing the silicon carbide epitaxial layer from the surface of the second n-type layer 23, and a second n-type The layer 23, the p-type layer 22, and a part of the first n-type layer 21 are exposed. Specifically, a photoresist is applied to the surface of the second n-type layer 23, and is exposed and developed by an exposure device to form a resist pattern (not shown) having an opening in a region where the groove 30 is formed. I do. Thereafter, in the opening of the resist pattern, a part of the second n-type layer 23, the p-type layer 22, and the first n-type layer 21 is removed by RIE (Reactive Ion Etching). Thereby, the groove 30 is formed. The first n-type layer 21 is exposed on the bottom surface 30b of the groove 30. Thereafter, the resist pattern (not shown) is removed with an organic solvent or the like.

  Next, as shown in FIG. 8, a gate insulating film 40 is formed on the side surface 30a and the bottom surface 30b of the groove 30, the second n-type layer 23, and the like.

  Next, as shown in FIG. 9, a gate electrode 51 is formed by depositing polysilicon on the gate insulating film 40 inside the trench 30.

  Next, as shown in FIG. 10, an interlayer insulating film 61 is formed on the gate insulating film 40 and the gate electrode 51.

  Next, as shown in FIG. 11, by removing the interlayer insulating film 61 and the gate insulating film 40 except for the gate electrode 51 and the periphery of the gate electrode 51, the high-concentration p-type region 24 and the second n-type layer 23 are removed. Expose part of

  Next, as shown in FIG. 12, a barrier metal layer 62 covering the interlayer insulating film 61 and the gate insulating film 40 is formed by forming a titanium nitride film. Specifically, after a titanium nitride film is formed on the interlayer insulating film 61, the high-concentration p-type region 24, and the second n-type layer 23, and a photoresist is applied on the titanium nitride film, Exposure and development are performed by an exposure device to form a resist pattern (not shown). The resist pattern has an opening in the region where the source electrode 52 is formed on the second n-type layer 23, and thereafter, the titanium nitride film in the region where the resist pattern is not formed is removed by RIE or the like. It is removed by dry etching to expose the second n-type layer 23 and the like. Thereby, the barrier metal layer 62 is formed by the remaining titanium nitride film.

  Next, as shown in FIG. 13, an ohmic contact layer 52a is formed on the exposed second n-type layer 23 and the high concentration p-type region 24, and the second An ohmic contact layer 53a is formed on the surface 10b. The ohmic contact layer 52a and the ohmic contact layer 53a are formed by forming a Ni film by sputtering or the like and performing a heat treatment to alloy Si and the Ni film of silicon carbide to form a NiSi alloy layer.

  Next, as shown in FIG. 14, a source electrode 52 is formed on the ohmic contact layer 52a and the barrier metal layer 62, and a drain electrode 53 is formed on the ohmic contact layer 53a. The source electrode 52 and the drain electrode 53 are formed of a metal film such as Al.

  Next, as shown in FIG. 15, a passivation film 63 is formed on the source electrode 52.

  Through the above steps, the silicon carbide semiconductor device according to the present embodiment can be manufactured.

[Second embodiment]
Next, a second embodiment will be described. The silicon carbide semiconductor device serving as a vertical transistor according to the present embodiment has a structure in which a V-shaped groove 130 is formed as shown in FIG. Therefore, the surface of the second n-type layer 23 is a C (carbon) plane. Specifically, the V-shaped groove 130 is formed by removing the second n-type layer 23, the p-type layer 22, and the first n-type layer 21. In the V-shaped groove 130, the side surface 130a is inclined at 55 ° ± 5 °, that is, in the range of 50 ° or more and 60 ° or less with respect to the surface of the second n-type layer 23. The side surface 130a of the groove 130 is formed by the second n-type layer 23, the p-type layer 22, and a part of the first n-type layer 21. A gate insulating film 140 is formed on the side surface 130a and the bottom surface 130b inside the V-shaped groove 130 and on the second n-type layer 23 near the V-shaped groove 130, and the V-shaped groove 130 is formed. A gate electrode 151 is formed on the gate insulating film 140 inside the trench 130.

  In the silicon carbide semiconductor device according to the present embodiment, by forming the V-shaped groove 130, even if the concentration of the impurity element in p-type layer 22 is increased, the mobility of carriers when a channel is formed is reduced. Can be prevented. The V-shaped groove 130 can be formed by thermal etching. Specifically, the V-shaped groove 130 whose side surface 130a is a {0-33-8} surface is formed by thermal etching, and the second n-type layer 23 is formed on the side surface 130a of the V-shaped groove 130. , The p-type layer 22 and part of the first n-type layer 21 are exposed. Thereafter, a gate insulating film 140 is formed on the side surface 130 a and the bottom surface 130 b of the V-shaped groove 130, the second n-type layer 23, and the like, and further, the gate insulating film 140 inside the V-shaped groove 130 is formed. A gate electrode 151 is formed by forming a polysilicon film on the substrate.

  The contents other than those described above are the same as in the first embodiment.

  The embodiment has been described in detail above, but is not limited to a specific embodiment, and various modifications and changes are possible within the scope described in the claims.

Reference Signs List 10 silicon carbide single crystal substrate 10a first surface 10b second surface 11 silicon carbide epitaxial layer 11a surface 21 first n-type layer 22 p-type layer 23 second n-type layer 24 high-concentration p-type region 30 groove 30a Side surface 30b Bottom surface 40 Gate insulating film 51 Gate electrode 52 Source electrode 52a Ohmic contact layer 53 Drain electrode 53a Ohmic contact layer 61 Interlayer insulating film 62 Barrier metal layer 63 Passivation film 130 V-shaped groove 130a Side surface 130b Bottom surface 140 Gate insulating film 151 Gate electrode

Claims (6)

A first layer of a silicon carbide semiconductor of a first conductivity type;
A second layer of a silicon carbide semiconductor of a second conductivity type different from the first conductivity type on the first layer;
A third layer of the first conductivity type silicon carbide semiconductor on the second layer;
A groove having a side surface in a part of the third layer, the second layer, and the first layer;
An insulating film provided inside the groove,
A gate electrode provided on the insulating film inside the groove,
A vertical transistor having
The concentration of the impurity element of the second conductivity type at the interface between the second layer and the third layer exceeds half the peak value of the concentration of the impurity element of the second conductivity type in the second layer. And
A concentration of the impurity element of the second conductivity type at an interface between the first layer and the second layer is less than half a value of a peak value of a concentration of the impurity element of the second conductivity type in the second layer; A silicon carbide semiconductor device that is 1/20 or more. The first layer includes the first conductivity type impurity element and the second conductivity type impurity element,
1 <(concentration of impurity element of first conductivity type) / (concentration of impurity element of second conductivity type) ≦ 2
The silicon carbide semiconductor device according to claim 1, wherein The first layer is formed on a first surface of a silicon carbide single crystal substrate,
A source electrode in contact with the third layer;
A drain electrode provided on a second surface of the silicon carbide single crystal substrate opposite to the first surface;
3. The silicon carbide semiconductor device according to claim 1, comprising: The polytype of the silicon carbide single crystal substrate is 4H,
The surface of the third layer is a Si surface,
The silicon carbide semiconductor device according to claim 3, wherein a side surface of the groove is perpendicular to a surface of the third layer. The polytype of the silicon carbide single crystal substrate is 4H,
The surface of the third layer is a C-plane,
The silicon carbide semiconductor device according to claim 3, wherein a side surface of the groove is at least 50 ° and at most 60 ° with respect to a surface of the third layer. The peak value of the effective doping concentration in the second layer is 5.0 × 10 ¹⁷ cm ⁻³ or more and 3.0 × 10 ¹⁸ cm ⁻³ or less, according to any one of claims 1 to 5. The silicon carbide semiconductor device according to the above.

Images