JP2020035833A - Semiconductor storage device and method of manufacturing the same - Google Patents

Abstract

To provide a staircase structure that has lead-out wiring with increased thickness.SOLUTION: A semiconductor storage device according to an embodiment has on a substrate: a laminate that has a staircase structure in which a plurality of wiring layers and a plurality of interlayer insulating layers laminated alternately are set to one step; and a memory cell arranged three-dimensionally on the laminate. The staircase structure comprises: a plurality of terrace parts configured by the interlayer insulating layers and having different heights; a plurality of step parts that connect the respective terrace parts in a height direction; an insulating layer covering the step parts; and lead-out wiring that leads out the undermost wiring layer in a first step onto the terrace part in a second step lower than the first step.SELECTED DRAWING: Figure 3

Description

  Embodiments described herein relate generally to a semiconductor storage device and a method of manufacturing the semiconductor storage device.

  In recent years, miniaturization of a semiconductor storage device has been advanced, and a three-dimensional nonvolatile memory having a memory cell having a stacked structure has been proposed. In a three-dimensional nonvolatile memory, a step-like structure may be adopted in order to draw out word lines in each layer of memory cells arranged in a height direction.

JP 2010-027870 A

  However, obtaining such a structure requires precise process control, and it is difficult to obtain a sufficient process margin.

  An object of one embodiment is to provide a semiconductor memory device and a method of manufacturing a semiconductor memory device that can easily form a staircase structure having a thicker lead wire.

  The semiconductor memory device according to the embodiment has a stacked body having a stepped structure in which a plurality of wiring layers and interlayer insulating layers are alternately stacked on a substrate, and a memory three-dimensionally arranged in the stacked body. A semiconductor memory device having a cell, wherein the staircase structure is formed of the interlayer insulating layer, and has a plurality of terrace portions having different heights, and a plurality of step portions connecting each of the terrace portions in a height direction. An insulating layer covering the step portion; and a lead-out line for drawing out the lowermost wiring layer of the first stage onto the terrace portion of the second stage which is the lower stage of the first stage.

FIG. 1 is a diagram schematically illustrating an example of a configuration of a nonvolatile memory according to an embodiment. FIG. 2 is a diagram schematically illustrating an example of a configuration of a staircase structure of the nonvolatile memory according to the embodiment. FIG. 3 is a cross-sectional view illustrating an example of a configuration of a staircase structure of the nonvolatile memory according to the embodiment. FIG. 4 is a flowchart illustrating an example of a procedure of a manufacturing process of the nonvolatile memory according to the embodiment. FIG. 5 is a flowchart illustrating an example of a procedure of a manufacturing process of the nonvolatile memory according to the embodiment. FIG. 6 is a flowchart illustrating an example of a procedure of a manufacturing process of the nonvolatile memory according to the embodiment. FIG. 7 is a flowchart illustrating an example of a procedure of a manufacturing process of the nonvolatile memory according to the embodiment. FIG. 8 is a diagram illustrating a staircase structure of a nonvolatile memory according to a comparative example.

  Hereinafter, the present invention will be described in detail with reference to the drawings. The present invention is not limited by the following embodiments. The components in the following embodiments include those that can be easily assumed by those skilled in the art or those that are substantially the same.

(Configuration example of nonvolatile memory)
FIG. 1 is a diagram schematically illustrating an example of the configuration of the nonvolatile memory 10 according to the embodiment. In FIG. 1, two directions parallel to the main surface of the substrate Sub and orthogonal to each other are defined as an X direction and a Y direction. A direction orthogonal to both the X direction and the Y direction is defined as a Z direction (stacking direction). In FIG. 1, an interlayer insulating layer and the like are omitted.

  As shown in FIG. 1, a source line SL made of a conductive layer is provided on a substrate Sub of a nonvolatile memory 10 as a semiconductor storage device. The source line SL is provided with a plurality of pillars P made of silicon oxide or the like extending in the Z direction. Each pillar P has on its side surface a channel layer made of polysilicon or the like and a memory layer in which a plurality of insulating layers are stacked. On the source line SL, a stacked body LB in which a plurality of conductive layers made of tungsten or the like and insulating layers made of silicon oxide or the like are alternately stacked via an interlayer insulating layer (not shown) is provided. Each pillar P penetrates through the stacked body LB.

  The lowermost conductive layer in the stacked body LB functions as a source-side select gate line SGS, and the uppermost conductive layer functions as a drain-side select gate line SGD. The selection gate line SGD is divided for each pillar P arranged in the X direction. A plurality of conductive layers sandwiched between the select gate lines SGS and SGD function as a plurality of word lines WL. The number of stacked word lines WL shown in FIG. 1 is an example. The insulating layer between the select gate lines SGS, SGD and the plurality of word lines WL functions as an interlayer insulating layer (not shown).

  Each pillar P is connected to a bit line BL on the stacked body LB. Each bit line BL is connected to a plurality of pillars P arranged in the Y direction.

  As described above, the memory cells MC arranged in the height direction of the pillars P are arranged at the connection portions between the respective pillars P and the word lines WL of the respective layers. A source-side select transistor STS and a drain-side select transistor STD are arranged at the connection between each pillar P and select gate lines SGS and SGD. The memory string MS is composed of the select transistor STS, the plurality of memory cells MC, and the select transistor STD arranged in the height direction of one pillar P. The memory cells MC arranged in a three-dimensional matrix form a memory cell array MA.

  The select gate lines SGS, SGD and the plurality of word lines WL are drawn out of the memory cell array MA in the X direction to form a step-like structure.

(Configuration example of staircase structure)
Next, a step-like structure provided in the nonvolatile memory 10 will be described with reference to FIG. FIG. 2 is a diagram schematically illustrating an example of the configuration of the staircase structures LBa and LBb of the nonvolatile memory 10 according to the embodiment. In FIG. 2, the substrate Sub and the like below the stacked body LB are omitted. Hereinafter, the word lines WL and the selection gate lines SGS, SGD may be referred to as word lines WL without distinction.

  As shown in FIG. 2, outside the above-described memory cell array MA, the stacked body LB has staircase structures LBa and LBb. The staircase structures LBa, LBb are mirror images of each other with their structures inverted, and are separated by slits ST.

  The staircase structures LBa, LBb have a staircase structure in which the word lines WL and the interlayer insulating layers ID, which are alternately stacked by three layers in the X direction, have one step. Further, the staircase structures LBa and LBb have a staircase structure in which the word line WL and the interlayer insulating layer ID which are stacked one by one in the Y direction have one step. The terrace portion LBtr, which is a flat portion of each step of the staircase structures LBa and LBb, is formed of an interlayer insulating layer ID.

  On the terrace portion LBtr of each stage, for example, a lead wiring LL made of the same material as the conductive layer forming the word line WL is provided. Each lead line LL is connected in the X direction and the Y direction to a lowermost word line WL included in an upper stage to which the terrace portion LBtr provided with the lead line LL belongs, and serves as a conductor of the word line WL. Function. For example, the lead wiring LL1 is connected to the first-layer word line WL1 and functions as a conductive line of the word line WL1. The lead wiring LL5 is connected to the fifth-layer word line WL5, and functions as a conductor for the word line WL5.

  The lead wiring LL has a predetermined thickness, and thus has an upper surface higher than the upper surface of the word line WL to which the lead wiring LL is connected. For example, the height of the upper surface of the lead wiring LL1 is higher than the upper surface of the word line WL1. The height of the upper surface of the lead wiring LL5 is higher than the upper surface of the word line WL5.

  Each lead-out wiring LL is provided with a contact CT for connecting a wiring in an upper layer of the staircase structures LBa, LBb and the lead-out wiring LL. For example, the contact CT1 is connected to the lead line LL1, and the contact CT1 is electrically connected to the word line WL1 via the lead line LL1. The contact CT5 is connected to the lead wiring LL5, and the contact CT5 is electrically connected to the word line WL5 via the lead wiring LL5.

  In the X direction, a spacer (not shown) made of an insulating layer such as silicon oxide is provided on the step portion LBst, which is a side surface of each step, connecting the terrace portions LBtr of each step in the height direction. . The function of the spacer will be described with reference to FIG.

  FIG. 3 is a cross-sectional view illustrating an example of the configuration of the staircase structures LBa and LBb of the nonvolatile memory 10 according to the embodiment. 3A is a cross-sectional view along the X direction in FIG. 1, and FIG. 3B is a cross-sectional view along the Y direction in FIG. The film covering the entire step structures LBa and LBb is an insulating film IDL.

  As shown in FIG. 3A, the lowermost interlayer insulating layer ID1 of the staircase structures LBa and LBb forms a terrace portion LBtr having no step portion LBst.

  The first stage of the staircase structures LBa and LBb is composed of word lines WL1 to WL3 and interlayer insulating layers ID2 to LD4, and the terrace LBtr is composed of interlayer insulating layers ID4. In the step portion LBst, the word line WL1 and the interlayer insulating layer ID2 slightly protrude from the other word lines WL2 and WL3 and the interlayer insulating layers ID3 and ID4.

  Spacers SP are provided on the protruding portions of the word lines WL1 and the interlayer insulating layers ID2 so as to cover the word lines WL2 and WL3 and the step portions LBst of the interlayer insulating layers ID3 and ID4. Although the height of the lead-out wiring LL1 for drawing out the word line WL1 is generally lower than the upper surface of the interlayer insulating layer ID2, a part of the lead-out wiring LL1 that is in contact with the first-stage step portion LBst is partially lower than the word line WL2. Has reached. However, since the spacer SP covers the word line WL2, the extraction wiring LL1 and the word line WL2 are insulated.

  The second stage of the staircase structures LBa and LBb is composed of word lines WL4 to WL6 and interlayer insulating layers ID5 to LD7, and the terrace LBtr is composed of interlayer insulating layers ID7. In the step portion LBst, the word line WL4 and the interlayer insulating layer ID5 slightly protrude from the other word lines WL5, WL6 and the interlayer insulating layers ID6, ID7.

  Spacers SP are provided on the protruding portions of the word lines WL4 and the interlayer insulating layers ID5 so as to cover the word lines WL5 and WL6 and the step portions LBst of the interlayer insulating layers ID6 and ID7. The height of the lead-out line LL4 for leading out the word line WL4 is generally lower than the upper surface of the interlayer insulating layer ID5, but a part of the lead-out line LL4 in contact with the second-step portion LBst is partially lower than the word line WL5. Has reached. However, since the spacer SP covers the word line WL5, the extraction wiring LL4 and the word line WL5 are insulated.

  As shown in FIG. 3B, the lowermost interlayer insulating layer ID1 of the staircase structures LBa and LBb forms a terrace portion LBtr having no step portion LBst. The first stage of the staircase structures LBa and LBb is configured by the word line WL1 and the interlayer insulating layer ID2, and the terrace LBtr is configured by the interlayer insulating layer ID2. The height of the lead wiring LL1 is generally lower than the height of the upper surface of the interlayer insulating layer ID2. The second stage of the staircase structures LBa and LBb is configured by the word line WL2 and the interlayer insulating layer ID3, and the terrace LBtr is configured by the interlayer insulating layer ID3. The height of the lead wiring LL2 is generally lower than the height of the upper surface of the interlayer insulating layer ID3. The staircase structures LBa and LBb have no spacer in the step portion LBst in the Y direction.

(Example of manufacturing process of nonvolatile memory)
Next, an example of a manufacturing process of the staircase structures LBa and LBb will be described as an example of a manufacturing process of the nonvolatile memory 10 with reference to FIGS. 4 to 7 are flowcharts illustrating an example of a procedure of a manufacturing process of the nonvolatile memory 10 according to the embodiment. 4 to 7 are cross-sectional views of the staircase structures LBa and LBb along the X direction in the manufacturing process. 4 to 7 are cross-sectional views of the staircase structures LBa and LBb in the Y direction in the manufacturing process.

  First, an example of the manufacturing process in the X direction will be described.

  As shown in the left diagram of FIG. 4A, a stacked body LB in which a plurality of sacrificial layers SC and interlayer insulating layers ID are alternately stacked is formed on a substrate Sub (see FIG. 1). The stacked body LB includes, for example, seven sacrificial layers SC1 to SC7 and eight interlayer insulating layers ID1 to ID8. The sacrificial layers SC1 to SC7 are formed of insulating layers of a type different from the insulating layers forming the interlayer insulating layers ID1 to ID8, and are layers that can be replaced with conductive layers that later become the word lines WL1 to WL7. More specifically, the insulating layers forming the interlayer insulating layers ID1 to ID8 are, for example, silicon oxide, and the insulating layers forming the sacrificial layers SC1 to SC7 are, for example, silicon nitride.

  As shown in the left diagram of FIG. 4B, the staircase structures LBa and LBb are formed. However, at this point, no slit ST (see FIG. 2) is formed in the staircase structures LBa and LBb, and the staircase structures LBa and LBb are not separated from each other.

  The staircase structures LBa and LBb include, for example, two steps. The second stage from the bottom is composed of the sacrificial layers SC5 to SC7 and the interlayer insulating layers ID6 to ID8, and the terrace LBtr of the second stage is composed of the interlayer insulating layer ID8. The first stage from the bottom includes the sacrificial layers SC2 to SC4 and the interlayer insulating layers ID3 to ID5, and the terrace LBtr of the first stage includes the interlayer insulating layer ID5. Under the first stage, only the terrace portion LBtr having no step portion LBst is formed. The configuration of only the terrace portion LBtr is set to the 0th stage for convenience. The terrace portion LBtr of the 0th stage is composed of the interlayer insulating layer ID2.

  An insulating layer SPb is formed to cover each of the terrace portions LBtr and the step portions LBst of the staircase structures LBa and LBb. The insulating layer SPb is made of, for example, silicon oxide or the like, and later becomes the spacer SP of the step portion LBst.

  As shown in the left diagram of FIG. 4C, the staircase structures LBa and LBb are etched back, and the insulating layer SPb, the interlayer insulating layer ID, and the sacrificial layer SC are formed one by one from each of the terraces LBtr. Remove. At this time, it is preferable that these layers be removed by dry etching, chemical dry etching, wet etching, or the like using highly anisotropic etching conditions.

  Thereby, each step of the staircase structures LBa and LBb is configured by a combination of a new sacrificial layer SC and an interlayer insulating layer ID. The second stage includes the sacrificial layers SC4 to SC6 and the interlayer insulating layers ID5 to ID7, and the newly exposed interlayer insulating layer ID7 forms the second terrace portion LBtr. The first stage includes the sacrificial layers SC1 to SC3 and the interlayer insulating layers ID2 to ID4, and the newly exposed interlayer insulating layer ID4 forms the first terrace portion LBtr. The newly exposed interlayer insulating layer ID1 constitutes the terrace portion LBtr of the 0th stage.

  Further, the spacer SP is formed by the insulating layer SPb remaining without being removed in the step portion LBst of each stage. The second-stage spacer SP covers the sacrificial layers SC5 and SC6 and the interlayer insulating layers ID6 and ID7, and the sacrificial layer SC4 and the interlayer insulating layer ID5 newly belonging to the second-stage are exposed in the step portion LBst. . The first-stage spacer SP covers the sacrifice layers SC2 and SC3 and the interlayer insulation layers ID3 and ID4, and the sacrifice layer SC1 and the interlayer insulation layer ID2 that newly belong to the first-stage are exposed in the step portion LBst. .

  As shown in the left diagram of FIG. 5A, a sacrifice layer LLb is formed to cover each of the terrace portions LBtr and the step portions LBst of the newly formed staircase structures LBa and LBb. The sacrifice layer LLb is formed of the same type of insulation layer as the insulation layers constituting the sacrifice layers SC1 to SC6, and is a layer that can be replaced with a conductive layer that will later become the lead wiring LL.

  At this time, it is preferable to form the sacrificial layer LLb such that the sacrificial layer LLb of the terrace portion LBtr is thicker than the sacrificial layer LLb of the step portion LBst. More specifically, it is preferable to form the sacrificial layer LLb such that the sacrificial layer LLb of the terrace portion LBtr is about twice as thick as the sacrificial layer LLb of the step portion LBst. Such a sacrificial layer LLb can be formed by using high-density plasma CVD (Chemical Vapor Deposition), plasma CVD, or the like, using a condition in which the growth rate in the stacking direction is higher than the growth rate in the direction parallel to the substrate Sub. it can.

  As shown in the left diagram of FIG. 5B, the staircase structures LBa and LBb are etched back to remove the sacrificial layer LLb from each step portion LBst. At this time, it is preferable to remove the sacrificial layer LLb by dry etching, chemical dry etching, wet etching, or the like, using isotropic etching conditions.

  Thereby, the sacrifice layer LLb formed in each terrace LBtr is separated from the sacrifice layer LLb formed in the other terrace LBtr, and the lowermost sacrifice layer SC in the upper stage of the terrace LBtr in which the sacrifice layer LBtr is formed. Is connected to the sacrifice layer LLp.

  At this time, the sacrificial layer LLb is etched back to reduce the thickness of the sacrificial layer LLp to a predetermined thickness. Here, for example, the height of the upper surface of the sacrifice layer LLp is generally lower than the height of the lower surface of the upper sacrifice layer SC from the lowermost layer in the upper stage in accordance with the later-described manufacturing process in the Y direction. However, a part of the sacrifice layer LLp may remain in the step part LBst, and therefore, a part of the sacrifice layer LLp may be higher than the lower surface of the upper sacrifice layer SC. Even in this case, the sacrifice layer LLp and the upper sacrifice layer SC are separated by the spacer SP.

  As shown in the left diagram of FIG. 5C, unnecessary portions of the sacrificial layer LLp are removed. Unnecessary portions of the sacrificial layer LLp can be removed by etching using a photolithography technique.

  As shown in the left diagram of FIG. 6A, an interlayer insulating film IDL is formed so as to cover the entirety of the staircase structures LBa and LBb. Further, a slit ST (see FIG. 2) for separating the staircase structures LBa and LBb is formed.

  As shown in the left drawing of FIG. 6B, the sacrificial layers SC1 to SC6 and LLp are removed through the slit ST shown in FIG. As a result, voids are created in the places where the sacrificial layers SC1 to SC6 and LLp existed.

  As shown in the left diagram of FIG. 6 (c), a void formed in the place where the sacrificial layers SC1 to SC6 and LLp existed is filled with a conductor such as tungsten through the slit ST shown in FIG. . Thus, the word lines WL1 to WL6 and the lead wirings LL1, LL4, LL7 are formed.

  As shown in the left diagram of FIG. 7A, through holes TH1, TH4, and TH7 that reach the lead wirings LL1, LL4, and LL7 are formed in the interlayer insulating film IDL on the lead wirings LL1, LL4, and LL7. These through holes TH1, TH4, and TH7 are collectively formed by etching using a photolithography technique. Therefore, in order to form the through-hole TH1 reaching the lead-out wiring LL1, excessive over-etching is applied to the through-holes TH4 and TH7. However, since the lead wirings LL1, LL4, and LL7 are made thick, it is possible to prevent the lead wirings LL4, LL7 from penetrating (punch through).

  As shown in the left diagram of FIG. 7B, a conductor such as tungsten is buried in the through holes TH1, TH4, and TH7 to form contacts CT1, CT4, and CT7. Thereafter, an upper layer wiring and the like connected to CT1, CT4 and CT7 are formed above the contacts CT1, CT4 and CT7, and the upper layer wiring is connected to a row decoder and the like for controlling each word line WL.

  The manufacturing process in the Y direction is also sequentially performed in parallel with the manufacturing process in the X direction.

  As shown in the right diagram of FIG. 4A, a stacked body LB in which sacrifice layers SC1 to SC7 and interlayer insulating layers ID1 to ID8 are alternately stacked is formed on a substrate Sub.

  As shown in the right diagram of FIG. 4B, for example, staircase structures LBa and LBb having two steps are formed. The second stage from the bottom includes the sacrificial layer SC3 and the interlayer insulating layer ID4. The first stage from the bottom includes the sacrificial layer SC2 and the interlayer insulating layer ID3. The terrace portion LBtr of the 0th stage is composed of the interlayer insulating layer ID2. An insulating layer SPb is formed to cover each of the terrace portions LBtr and the step portions LBst of the staircase structures LBa and LBb.

  As shown in the right diagram of FIG. 4C, the staircase structures LBa and LBb are etched back, and the insulating layer SPb, the interlayer insulating layer ID, and the sacrifice layer SC are formed one by one from each of the terraces LBtr. Remove. At this time, the insulating layer SPb is also removed from each step portion LBst, and the insulating layer SPb disappears.

  Thus, the second stage is composed of the sacrificial layer SC2 and the interlayer insulating layer ID3, and the newly exposed interlayer insulating layer ID3 constitutes the terrace portion LBtr of the second stage. The first stage includes the sacrificial layer SC1 and the interlayer insulating layer ID2, and the newly exposed interlayer insulating layer ID2 forms the terrace portion LBtr of the first stage. The newly exposed interlayer insulating layer ID1 constitutes the terrace portion LBtr of the 0th stage.

  As shown in the right diagram of FIG. 5A, a sacrificial layer LLb is formed to cover each terrace portion LBtr and step portion LBst of the newly formed staircase structures LBa and LBb.

  As shown in the right diagram of FIG. 5B, the staircase structures LBa and LBb are etched back to remove the sacrificial layer LLb from each of the step portions LBst. At this time, the thickness of the sacrificial layer LLp is reduced until the upper surface of each sacrificial layer LLp becomes lower than the height of the lower surface of the upper sacrificial layer LLp.

  Thereby, the sacrifice layer LLb formed in each terrace portion LBtr is separated from the sacrifice layer LLb formed in the other terrace portion LBtr, and is connected to the upper sacrifice layer SC of the terrace portion LBtr in which the sacrifice layer LBtr is formed. It becomes the sacrificial layer LLp.

  As shown in the right diagram of FIG. 5C, unnecessary portions of the sacrificial layer LLp are removed.

  As shown in the right diagram of FIG. 6A, an interlayer insulating film IDL is formed so as to cover the entire staircase structures LBa and LBb. Further, a slit ST (see FIG. 2) for separating the staircase structures LBa and LBb is formed.

  As shown in the right figure of FIG. 6B, the sacrificial layers SC1 to SC3 and LLp are removed through the slit ST shown in FIG.

  As shown in the right figure of FIG. 6 (c), a conductor is filled in the gap formed at the place where the sacrificial layers SC1 to SC3 and LLp existed through the slit ST shown in FIG. To WL3 and the lead wirings LL1 to LL3.

  As shown in the right diagram of FIG. 7A, through holes TH1 to TH3 reaching the lead wires LL1 to LL3 are formed in the interlayer insulating film IDL on the lead wires LL1 to LL3.

  As shown in the right diagram of FIG. 7B, a conductor is buried in the through holes TH1 to TH3 to form contacts CT to CT3. The contacts CT1 to CT3 are connected to a row decoder or the like via an upper wiring or the like.

(Comparative example)
Next, a staircase structure according to a comparative example will be described with reference to FIG. FIG. 8 is a diagram illustrating a staircase structure of a nonvolatile memory according to a comparative example. As a simple structure for drawing a word line out of the memory cell array, it is conceivable to configure the terrace portion with a word line.

  That is, as shown in FIG. 8A, each terrace portion LBtr ′ forms a staircase structure including the sacrificial layers SC3 ′ and SC6 ′, and as shown in FIG. 8B1, the word line WL3 ', WL6'. However, as shown in FIG. 8 (c1), when the through holes TH1 ', TH3', TH6 'are formed so that the through hole TH1' reaches the word line WL1 ', for example, in the through holes TH3', TH6 ', There is a possibility that the word lines WL3 'and WL6' may penetrate (punch through PT) due to the addition of the overetch. In the example of FIG. 8C1, the through hole TH6 'has reached the word line WL5', and if the contact is buried as it is, the word lines WL5 'and WL6' conduct. Further, the through hole TH3 'reaches the interlayer insulating layer ID3', the withstand voltage of the thin interlayer insulating layer ID3 'is not sufficient, and a leak current flows from the word line WL3' to the word line WL2 '. There is a risk that it will. Therefore, it is conceivable to increase the thickness of the drawn word lines WL3 'and WL6'.

  That is, as shown in FIG. 8 (b2), a sacrificial layer LLb ′ covering the terrace portion LBtr ′ and the step portion LBst ′ of the staircase structure is formed, and as shown in FIG. 8 (c2), each of the terrace portions LBtr is formed. The 'sacrificial layer LLb' is separated to form a sacrificial layer LLp '. However, at this time, the sacrifice layer LLp 'must also be separated from the step portion LBst' so as not to contact the upper sacrifice layer SC '. It is very difficult to remove the sacrificial layer LLb 'only from the step portion LBst' while maintaining a sufficient layer thickness on the terrace portion LBtr ', and precise process control without a margin is required.

  The staircase structures LBa and LBb included in the nonvolatile memory 10 according to the embodiment include the spacer SP that covers the word line WL in the upper layer of the step portion LBst. Thus, even if the lead wiring LL provided on the lower terrace portion LBtr is made thicker, it can be electrically connected to the uppermost word line WL of the upper stage without being electrically connected to the upper word line WL of the upper stage.

  The spacer SP of the staircase structures LBa and LBb included in the nonvolatile memory 10 of the embodiment can be easily formed by, for example, etch back using anisotropic etching. Accordingly, the thickness of the lead wiring LL can be increased without requiring precise process control without a margin.

  The height of the upper surface of the lead-out line LL of the staircase structures LBa and LBb included in the nonvolatile memory 10 of the embodiment is substantially equal to the height of the upper word line WL in the upper direction in the X direction in accordance with the manufacturing process in the Y direction. , But is not limited to this. In the configuration in the X direction, each lead line LL is not restricted in increasing the film thickness as long as each lead line LL is separated from the other lead lines LL. More specifically, the thickness of the lead-out line LL in the configuration in the X direction is preferably 130% or more of the connected word line, and more preferably 150% or more of the connected word line. That's it.

  Although several embodiments of the present invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, replacements, and changes can be made without departing from the spirit of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

  10 nonvolatile memory, ID interlayer insulating layer, LB laminated body, LBa, LBb stair structure, LBst step part, LBtr terrace part, LL lead wiring, MC memory cell, P pillar, SC ... Sacrificial layer, SP ... Spacer, WL ... Word line.

Claims (5)

A stacked body having a stepped structure in which a plurality of wiring layers and interlayer insulating layers are alternately stacked on a substrate for one step, and a semiconductor memory device having memory cells arranged three-dimensionally in the stacked body. hand,
The staircase structure,
A plurality of terraces composed of the interlayer insulating layer and having different heights,
A plurality of step portions connecting each of the terrace portions in the height direction,
An insulating layer covering the step portion;
A lead-out line that draws out the lowermost wiring layer of the first stage onto the terrace portion of the second stage that is the lower stage of the first stage.
Semiconductor storage device. The lead wiring has a predetermined thickness, and the height of the upper surface of the lead wiring on the second stage is higher than the height of the upper surface of the lowermost wiring layer of the first stage.
The semiconductor memory device according to claim 1. The lead wiring on the second stage and the wiring layer above the first stage are insulated by the insulating layer covering the step portion of the first stage.
The semiconductor memory device according to claim 1. A contact connected to a wiring arranged in an upper layer of the staircase structure is connected to the extraction wiring,
The semiconductor memory device according to claim 1. On a substrate, a plurality of terrace portions having different heights and a plurality of step portions connecting each of the terrace portions in the height direction are provided. Forming a staircase structure as a step,
Forming a third layer covering the terrace portion and the step portion;
The third layer, the second layer, and the first layer are removed from the terrace, and the first layer immediately above the terrace composed of the newly exposed second layer is removed. A step of exposing the step portion on the upper stage of the newly exposed terrace portion,
Forming a fourth layer connected to the first layer exposed on the upper step portion on the newly exposed terrace portion,
A method for manufacturing a semiconductor storage device.

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