JP2020035509A - Semiconductor device - Google Patents

Abstract

To provide a driving circuit for a display device which is constituted by a TFT of one conductivity type and which can normally obtain the amplitude of an output signal.SOLUTION: In a pulse output circuit, a pulse is inputted to TFTs 101, 104 to be turned on, and when the potential becomes VDD - VthN after a potential of a node α rises, the TFT becomes a floating state. Therefore, as a TFT 105 is turned on and a clock signal becomes Hi, the potential of an output node rises. On the other hand, the potential of the gate electrode of the TFT 105 further rises due to a function of a capacitor 107 as the potential of the output node rises, and becomes higher than VDD + VthN. Thereby, the potential of the output node rises to VDD without voltage drop due to a threshold value of the TFT 105. After a next stage output is inputted to TFTs 102, 103 to be turned on, and the potential of the node α drops and the TFT 105 is turned off. At the same time, a TFT 106 is turned on, and the potential of the output node becomes Lo.SELECTED DRAWING: Figure 1

Description

The present invention relates to a pulse output circuit, a shift register, and a display device. Note that in this specification, a display device includes a liquid crystal display device including a liquid crystal element in a pixel and a self-luminous display device including self-luminous elements such as an electroluminescence (EL) element. A driving circuit of a display device refers to a circuit which inputs a video signal to a pixel provided in the display device and performs processing for displaying a video, a shift register, a pulse output circuit including an inverter, and the like, It includes an amplifier circuit such as an amplifier.

In recent years, display devices in which a semiconductor thin film is formed over an insulator, particularly a glass substrate, particularly active matrix display devices using thin film transistors (hereinafter, referred to as TFTs) have been widely used. An active matrix display device using TFTs has hundreds of thousands to millions of pixels arranged in a matrix, and displays an image by controlling the charge of each pixel by the TFT arranged in each pixel. It is carried out.

As a more recent technology, in addition to a pixel TFT constituting a pixel, a TF is provided around a pixel portion.
Technology relating to polysilicon TFTs in which drive circuits are simultaneously formed using T has been developed, and has greatly contributed to miniaturization and low power consumption of devices. Display devices have become indispensable devices for display units and the like.

Generally, a CMOS circuit in which an N-channel TFT and a P-channel TFT are combined is generally used as a circuit constituting a driving circuit of a display device.
Here, a shift register will be described as an example of a CMOS circuit generally used conventionally. FIG. 11A illustrates an example of a shift register that has been conventionally used. A portion surrounded by a dotted frame 1100 is a circuit that outputs one stage of pulses. FIG. 11A shows three stages extracted. The circuits for one stage include clocked inverters 1101, 1103,
And an inverter 1102. FIG. 11B shows a detailed circuit structure. In FIG. 11B, a clocked inverter 1101 is formed by TFTs 1104 to 1107, an inverter 1102 is formed by TFTs 1108 and 1109, and a clocked inverter 1103 is formed by TFTs 1110 to 1113.

The TFT constituting the circuit has three electrodes: a gate electrode, a source electrode, and a drain electrode.
In general, in a CMOS circuit, an N-channel TFT uses a lower potential as a source electrode and a higher potential as a drain electrode. In a P-channel TFT, a higher potential uses a source electrode and a lower potential. Is often used as a drain electrode.
In describing the connection, one of the source electrode and the drain electrode is described as an input electrode and the other is described as an output electrode in order to avoid confusion.

The operation of the circuit will be described. Regarding the operation of the TFT, a potential is applied to the gate electrode, a channel is formed between the impurity regions, and a conductive state is ON, and a state where the channel of the impurity region is lost and becomes non-conductive is OFF. write.

Reference is made to the timing charts shown in FIGS. 11A and 11B and FIG. 11C. TF
A clock signal (hereinafter referred to as CK) and a clock inversion signal (hereinafter referred to as CKB) are input to T1107 and T1107, respectively. A start pulse (hereinafter referred to as SP) is input to the TFTs 1105 and 1106. When CK is at Hi potential, CKB is at Lo potential, and SP is at Hi potential, the TFTs 1106 and 1107 are turned ON, and the Lo potential is output, and the TFTs 1108 and 110 are output.
9 and is inverted and output to the output node (SRout1).
The potential is output. Thereafter, when CK becomes Lo potential and CKB becomes Hi potential while SP is at Hi potential, the holding operation is performed in a loop constituted by the inverter 1102 and the clocked inverter 1103. Therefore, the Hi potential is continuously output to the output node.
Next, when CK becomes Hi potential and CKB becomes Lo potential, the clocked inverter 1101 again performs a write operation. At this time, since SP has already been at the Lo potential, the Lo potential is output to the output node. Thereafter, when CK becomes Lo potential and CKB becomes Hi potential, the holding operation is performed again. At this time, the Lo potential of the output node is held in the loop constituted by the inverter 1102 and the clocked inverter 1103.

The above is the operation for one stage. In the next stage, the connections of CK and CKB are reversed, and the same operation is performed in a state where the polarity of the clock signal is opposite to that described above. This is repeated alternately, and thereafter, similarly, sampling pulses are sequentially output as shown in FIG.

As a feature of the CMOS circuit, a current flows only at the moment when the logic changes (from Hi potential to Lo potential or from Lo potential to Hi potential), and no current flows while a certain logic is held (actually, a minute current). (There is a leakage current.) Therefore, the current consumption of the entire circuit can be suppressed low.

By the way, the demand for display devices using liquid crystal or self-luminous elements is due to the miniaturization of mobile electronic devices,
Although the demand is rapidly increasing with the reduction in weight, it is difficult to keep the manufacturing cost sufficiently low in terms of yield and the like. It is easily anticipated that demand in the future will increase more rapidly, and it is therefore desired to be able to supply display devices at lower cost.

As a method for manufacturing a driver circuit over an insulator, using a plurality of photomasks, an active layer,
In general, exposure and etching are used to create patterns such as wiring, but the large number of steps directly affects the manufacturing cost. Ideally. Therefore, if a driving circuit conventionally formed by a CMOS circuit can be formed by using a TFT of only one of the N-channel type and the P-channel type, a part of the ion doping step is omitted. In addition, the number of photomasks can be reduced.

(Problems of the technology before the present invention)
FIG. 9A shows an example of a conventional CMOS inverter (I) and inverters (II) and (III) configured using TFTs having only one polarity. (II) is TFT
The load type inverter, (III) is a resistance load type inverter. Hereinafter, each operation will be described.

FIG. 9B shows a waveform of a signal input to the inverter. Here, the input signal amplitude is between VDD and VSS (VSS <VDD). Here, it is assumed that VSS = 0 [V].

The circuit operation will be described. In addition, in order to make the description clear and simple, N
The threshold voltage of the type TFT is uniform (VthN) assuming that there is no variation. The same applies to the P-type TFT (VthP).

When a signal as shown in FIG. 9B is input to the CMOS inverter, the potential of the input signal becomes Hi.
At the time of the potential, the P-type TFT 901 is turned off and the N-type TFT 902 is turned on, so that the potential of the output node becomes Lo potential. Conversely, when the potential of the input signal is Lo potential, the P-type TFT
When the 901 is turned on and the N-type TFT 902 is turned off, the potential of the output node becomes Hi potential (FIG. 9C).

Next, the operation of the TFT load type inverter (II) will be described. Consider a case where a signal as shown in FIG. 9B is input. First, when the input signal is at the Lo potential, the N-type TF
T904 is turned off. On the other hand, since the load TFT 903 is always performing a saturation operation, the potential of the output node is raised in the Hi potential direction. On the other hand, when the input signal is at the Hi potential, the N-type TFT 904 is turned on. Here, the current capability of the load TFT 903 is larger than that of the N-type TFT 90.
By making the current capability of 4 sufficiently high, the potential of the output node is lowered in the Lo potential direction.

Similarly, for the resistance load type inverter (III), the ON resistance value of the N-type TFT 906 is calculated as follows.
By setting the resistance sufficiently lower than the resistance value of the load resistor 905, when the input signal is at the Hi potential, the N-type TFT 906 is turned on, so that the output node is pulled down to the Lo potential direction. When the input signal is at the Lo potential, the N-type TFT 906 is turned off, and the output node is pulled up to the Hi potential direction.

However, when using a TFT load type inverter or a resistance load type inverter, there are the following problems. FIG. 9D shows an output waveform of the TFT load type inverter.
When the output is at the Hi potential, the potential is lower than VDD by the amount indicated by 907. Load TFT
In 903, if the terminal on the output node side is a source and the terminal on the power supply VDD side is a drain, the gate electrode and the drain region are connected, and the potential of the gate electrode at this time is VD
D. Further, the condition that the load TFT is ON is (voltage between gate and source of TFT 903> VthN), and therefore, the potential of the output node is (VDD−Vt) at the maximum.
hN). That is, 907 is equal to VthN. Furthermore, load TFT 9
03 and the current capability of the N-type TFT 904, when the output potential is Lo potential, 908
The potential becomes higher than VSS by the amount indicated by. In order to make this sufficiently close to VSS, it is necessary to sufficiently increase the current capability of the N-type TFT 904 with respect to the load TFT 903. Similarly, FIG. 9E shows the output waveform of the resistive load type inverter.
Depending on the ratio of the resistance of the TFT 05 to the ON resistance of the N-type TFT 906, the potential is increased by the amount indicated by 909. In other words, when an inverter configured using a TFT having only one polarity as shown here is used, the amplitude of the output signal is attenuated with respect to the amplitude of the input signal.

In the case of a circuit such as a shift register in which the output pulse of the previous stage is input to the next stage, the amplitude is determined by the threshold value of the TFT every time the stage is overlapped from the mth stage → m + 1st stage → m + 2nd stage. , And does not function as a circuit.

The present invention has been made in view of the above problems, and can be manufactured at low cost by reducing the number of manufacturing steps using TFTs of only one polarity, and can produce an output without amplitude attenuation. It is an object to provide a pulse output circuit and a shift register which can be obtained.

In the TFT load type inverter shown in (II) of FIG. 9A, conditions for the output signal amplitude to be normally VDD-VSS will be considered. First, in the circuit as shown in FIG. 10A, when the potential of the output signal becomes Lo potential, in order to sufficiently bring the potential close to VSS, the resistance value between the power supply VDD and the output node must be increased. It is sufficient that the resistance value between the power supply VSS and the output node is sufficiently low. That is, while the N-type TFT 1002 is ON, N
It is sufficient that the type TFT 1001 is off. Second, when the potential of the output signal becomes the Hi potential, the absolute value of the gate-source voltage of the N-type TFT 1001 only needs to always exceed VthN so that the potential becomes equal to VDD. That is, the Hi potential of the output node becomes VDD.
In order to satisfy the condition, the potential of the gate electrode of the N-type TFT 101 is (VDD + VthN)
Need to be higher. Since only two types of power are supplied to the circuit, VDD and VSS, the conventional method cannot satisfy this condition unless there is a third power having a higher potential than VDD.

Therefore, the present invention takes the following measures. As shown in FIG.
A capacitor 1003 is provided between the gate and the source of T1001. When the potential of the output node is raised when the gate electrode of the N-type TFT 1001 is in a floating state with a certain potential, the capacity coupling of the capacitor 1003 causes the N-type TFT 1010 to increase in accordance with the potential rise of the output node.
The potential of the gate electrode 01 is also raised.
By utilizing this effect, the potential of the gate electrode of the N-type TFT 1001 can be higher than VDD (more precisely, higher than VDD + VthN). Therefore, it is possible to sufficiently raise the potential of the output node to VDD.

As the capacitor 1003 shown in FIG. 10B, a parasitic capacitance between the gate and the source of the TFT 1001 may be used, or a capacitor portion may be actually manufactured. In the case where the capacitance portion is formed independently, it is easy and preferable to form the structure in which an insulating layer is interposed between any two of the active layer, the gate material, and the wiring material. It may be manufactured using another material.

According to the present invention, a driver circuit and a pixel portion of a display device can be formed using only one-conductivity-type TFTs.
This contributes to an improvement in yield, and enables supply of a display device at lower cost.

FIG. 4 illustrates one embodiment of a pulse output circuit of the present invention. FIG. 2 is a diagram showing a timing chart for driving the pulse output circuit shown in FIG. 1. FIG. 3 is a diagram showing a shift register to which a scanning direction switching function is added, which is one embodiment of the pulse output circuit of the present invention. FIG. 4 is a diagram illustrating a configuration example of a source signal line driver circuit in a display device provided by the present invention. FIG. 3 is a detailed diagram of a circuit configuration of a level shifter in the display device provided by the present invention. FIG. 2 is a detailed diagram of a circuit configuration of a buffer and a sampling switch in the display device provided by the present invention. FIG. 2 is a diagram illustrating a shift register with a simplified configuration according to an embodiment of the present invention. FIG. 13 illustrates an example of an electronic device to which the present invention can be applied. The figure which shows the structure of a conventional CMOS inverter and a load type inverter, and the waveform of each input / output signal. FIG. 4 illustrates an operation principle of a pulse output circuit of the present invention. FIG. 4 is a diagram showing a circuit configuration and a timing chart of a conventional shift register. FIG. 1 is a diagram showing an entire appearance of a display device provided by the present invention. FIG. 4 is a diagram illustrating an operation of the shift register described in the embodiment of the present invention depending on a difference in pulse width of a clock signal. FIG. 13 is a diagram illustrating a shift register to which an input of a reset signal is added. FIG. 13 is a diagram illustrating a shift register to which an input of a reset signal is added. FIG. 4 is a diagram illustrating a circuit configuration using transistors of a conductivity type different from that of the embodiment. FIG. 17 illustrates a timing chart for driving the shift register illustrated in FIG. 16.

FIG. 1 shows a shift register to which a bootstrap method is applied, which is one mode of a pulse output circuit of the present invention. In the block diagram illustrated in FIG. 1A, a block denoted by 100 is a pulse output circuit that outputs a sampling pulse for one stage, and the shift register in FIG. 1A includes n stages of pulse output circuits. Have been. Clock signal (hereinafter referred to as CK), clock inverted signal (hereinafter referred to as CKB)
, A start pulse (hereinafter referred to as SP) is input. FIG. 1B shows a detailed circuit configuration of the block 100. In FIG. 1B, a block 110 is a first amplitude compensation circuit, and a block 120 is a second amplitude compensation circuit. FIG. 1C shows a further detailed diagram. FIG. 1 (C
), The TFT 101 connected to the power supply VDD and the TFT 1 connected to the power supply VSS.
02 constitutes a first amplitude compensation circuit, and the TFT 103 connected to the power supply VDD and the TFT 104 connected to the power supply VSS constitute a second amplitude compensation circuit.

The operation of the circuit will be described with reference to the circuit diagram illustrated in FIG. 1 and the timing chart illustrated in FIG. In a certain m-th stage (1 <m ≦ n) pulse output circuit, the TFTs 101, 10
The output pulse of the (m-1) -th stage is input to the gate electrode of No. 4 (m = 1, that is, in the case of the first stage, SP is input), and the TFT 101 and 104 are turned ON (FIG. 2). 2
01). As a result, the potential of the node α is raised to the VDD side (see FIG. 220), and when the potential becomes VDD−VthN, the TFT 101 is turned off to be in a floating state. Therefore, the TFT 105 is turned on. On the other hand, no pulse is input to the gate electrodes of the TFTs 102 and 103 at this time, and the TFTs 102 and 103 remain at the Lo potential, and thus are turned off. Therefore, the potential of the gate electrode of the TFT 106 is Lo potential and is OFF, so that the TFT 1
As one end of the impurity region 05, that is, CK input from the first input signal line (1) becomes Hi potential, the potential of the output node is raised to the VDD side (see 203 in FIG. 220).
.

Here, a capacitor 107 is provided between the gate of the TFT 105 and the output node, and the node α, that is, the gate electrode of the TFT 105 is in a floating state. The potential of the gate electrode of the TFT 105 is further raised from VDD−VthN by the strap. Thus, the potential of the gate electrode of the TFT 105 takes a higher potential than VDD + VthN (see 202 in FIG. 220). Therefore, the potential of the output node rises completely to VDD without lowering the potential due to the threshold value of the TFT 105 (see 203 in FIG. 220).

Similarly, in the (m + 1) -th stage, a pulse is output in accordance with the CKB (204 in FIG. 2).
reference). The output pulse of the (m + 1) th stage is fed back to the mth stage and is input to the gate electrodes of the TFTs 102 and 103. When the gate electrodes of the TFTs 102 and 103 become Hi potential and are turned on, the potential of the node α is reduced to the VSS side and the TFT 105 is turned off. At the same time
The potential of the gate electrode of the FT 106 becomes Hi potential and turns ON, and the potential of the m-th output node becomes Lo potential.

Thereafter, pulses having an amplitude between VDD and VSS are sequentially output by the same operation until the last stage. In the final stage, since there is no next-stage output pulse to be input from the third input signal line in FIG. 1C, CK is continuously output. Therefore, since the output of the last stage cannot be used as a sampling pulse, if the number of output stages of the actually required sampling pulse is n, the number of shift register stages is set to be larger than n and the extra The stage may be treated as a dummy stage. However, the output of the last stage needs to be stopped by some method until the next horizontal period. However, in the circuit shown in FIG. 1, the start pulse input to the first stage is changed to the third stage. Is also used as a feedback pulse by inputting to the input signal line, and the output of the last-stage pulse is stopped immediately before the next horizontal period.

Note that the configuration of the amplitude compensation circuit described in the present embodiment is an example, and other configurations may be used.

As another method, as shown in FIGS. 14A and 14B, a reset signal is prepared and input to the third input signal line 1401 at the final stage during the retrace period, whereby pulse output is performed. 15A or as shown in FIGS. 15A and 15B, the reset TFTs 1508, 1
When a reset signal is input using the switch 509, the potential of the gate electrode of the TFT 1505 is turned off as the Lo potential, and the gate electrode potential of the TFT 1506 is turned on as the Hi potential.
By doing so, there is a method of fixing the outputs of all the stages to the Lo potential. At this time, the input timing of the reset signal may be the same as the timing chart shown in FIG. In FIG. 15A, the third pulse output circuit indicated by * in the last stage is shown.
Are connected to the power supply potential on the VSS side, and the TFTs 1502 and 1503 are always turned off.
It is desirable to make it F.

Although not particularly shown, in the case of the circuit shown in FIG. 15, the reset signal is input first before the circuit starts outputting the sampling pulse, that is, immediately after the power is turned on, so that the output at all stages is obtained. The potential of the node is determined (in the case of the circuit of FIG. 15, the output nodes of all stages are Lo
Potential). In the case of a dynamic circuit, such an operation is effective for stably operating the circuit.

With the above operation, even in a circuit configured using only one conductivity type TFT,
An output signal having a normal amplitude with respect to the input signal can be obtained without causing amplitude attenuation due to the influence of the threshold value of the TFT connected to the power supply on the high potential side. Further, it can be said that the circuit shown in the present embodiment has a great advantage that it does not have a complicated configuration as compared with a conventional CMOS circuit.

  Hereinafter, embodiments of the present invention will be described.

FIG. 3 shows an example in which a scan direction inversion function is added to the shift register shown in the embodiment of the present invention. 3A, a scanning direction switching signal (LR) and a scanning direction switching inversion signal (LRB) are added as compared with the circuit shown in FIG. 1A.

FIG. 3B shows in detail the structure of the pulse output circuit for one stage shown by the block 300 in FIG. The pulse output circuit main body composed of the TFTs 301 to 306 and the capacitor 307 is the same as that shown in FIG. 1B, but the second input signal line (
A scanning direction switching circuit indicated by a dotted frame 350 is provided between 2) and the third input signal line (3) and the pulse output circuit main body. The scanning direction switching circuit shown in this embodiment is a TFT 3
08 to 311 and functions as an analog switch.

The gate electrodes of the TFT 301 and the TFT 304 are connected to the TFT 3 as shown in FIG.
08, it is connected to the second input signal line (2), and the TFT 310 is connected to the third input signal line (3). The gate electrodes of TFT302 and TFT303 are TFT3
09 is connected to the second input signal line (2) via the TFT 311 and is connected to the third input signal line (3) via the TFT 311. The LR signal is input to the gate electrodes of the TFT 308 and the TFT 310, and the LRB signal is input to the gate electrodes of the TFT 309 and the TFT 311. LR and LRB exclusively take the Hi potential or the Lo potential, and therefore, the scanning direction switching circuit of the present embodiment takes the following two states.

First, when LR is at the Hi potential and LRB is at the Lo potential, the TFT 308 and the TFT 310 are turned ON, the second input signal line (2) and the gate electrodes of the TFT 301 and the TFT 304 conduct, and the third input signal line is turned on. In (3), the gate electrodes of the TFT 302 and the TFT 303 conduct. Second, when LR is at Lo potential and LRB is at Hi potential, TFT 309 and TFT 3
11 turns ON, the second input signal line (2) and the gate electrodes of the TFT 302 and the TFT 303 conduct, and the third input signal line (3) and the gate electrodes of the TFT 301 and the TFT 304 conduct.

That is, when a signal is input to the LR and the potential becomes Hi potential, and when the LRB is Lo potential, the output of the sampling pulse is in the order of the first stage to the second stage...
When a signal is input to the LRB and becomes a Hi potential, the output of the sampling pulse is output from the final stage to
・ ・ The order is from the second stage to the first stage. In the present invention, these functions can be easily added by adding a simple circuit. In this embodiment, the circuit is configured using an N-channel TFT. When the circuit is configured using a P-channel TFT, a state in which a signal is input to LR corresponds to a state in which the signal has a Lo potential. In the case of Hi potential, no signal is input.

Note that the scanning direction switching circuit shown in this embodiment is an example, and a similar function may be added by another configuration.

In this embodiment, an example in which a display device is manufactured using a TFT having only one polarity will be described.

FIG. 12 is a schematic diagram of a display device. A source signal line driving circuit 120 is provided on a substrate 1200.
1. The gate signal line drive circuit 1202 and the pixel portion 1203 are integrally formed.
In the pixel portion, a portion surrounded by a dotted frame 1210 is one pixel. In the example of FIG. 12, a pixel of a liquid crystal display device is shown, and electric charge applied to one electrode of a liquid crystal element is controlled by one TFT (hereinafter, referred to as a pixel TFT). Source signal line drive circuit 120
1. The signal input to the gate signal line drive circuit 1202 is a flexible printed circuit board (Flexib
le Print Circuit (FPC) 1204, and is supplied from outside.

FIG. 4 is a diagram showing an entire configuration of the source signal line driving circuit 1201 in the display device shown in FIG. The source signal line driving circuit includes a clock signal level shifter 401, a start pulse level shifter 402, a scanning direction switching shift register 403, and a buffer 4.
04, a sampling switch 405, and a signal input from the outside includes a clock signal (CK) and a clock inversion signal (CKB).
, Start pulse (SP), scanning direction switching signal (LR, LRB), analog video signal (V
video1 to Video12). Among them, CK, CKB, and SP are subjected to amplitude conversion by a level shifter immediately after being externally input as low-voltage amplitude signals, and input to the drive circuit as high-voltage amplitude signals. The sampling pulse output from the one-stage shift register drives the sampling switch 405 to simultaneously sample the analog video signals for 12 columns of the source signal lines.

FIG. 5A shows the (LS1) configuration of the clock signal level shifter.
This is achieved by arranging a one-input type level shifter circuit in parallel (Stage 1) and providing a buffer stage (St)
Age2 to Stage4) are configured to alternately input their respective outputs.

The operation of the circuit will be described. The power supply potentials used in the figures are VDD1, VDD
2, three potentials of VSS and VSS <VDD1 <VDD2. In this embodiment, VSS =
0 [V], VDD1 = 5 [V], and VDD2 = 16 [V]. Also, in the figure, 501, 503,
The TFTs 506 and 508 have a W gate structure, but these TFTs may have a single gate or a multi-gate structure having three or more gate electrodes. The other TFTs are not limited by the number of gate electrodes.

CK having an amplitude of VDD1−VSS is input from the signal input unit 1 (1). When CK is at the Hi potential, the TFTs 502 and 504 are turned ON, and the potential of the gate electrode of the TFT 503 becomes L.
It is turned off at the potential o. Therefore, Lo potential is output to output node α. CK is Lo
At the time of the potential, the TFTs 502 and 504 are turned off. Therefore, the TFT 50 operating in saturation is
1, the gate electrode potential of the TFT 503 is raised to the VDD2 side, and the potential is
When DD2−VthN, the TFT 501 is turned off, and the gate electrode of the TFT 503 is in a floating state. As a result, the TFT 503 is turned on, and the potential of the output node α is raised to the VDD2 side. Here, due to the function of the capacitor 505, the potential of the gate electrode of the TFT 503 in a floating state is also raised with the rise of the potential of the output node α, and the potential becomes VD.
By taking a potential higher than D2 and the potential exceeding VDD + VthN, the Hi potential of the output node α becomes equal to VDD2. Therefore, the Lo potential of the output signal is VSS, Hi
The potential becomes VDD2, and the amplitude conversion is completed.

On the other hand, from the signal input unit 2 (2), CKB having the same VDD1-VSS amplitude as CK is input.
Is input, the amplitude is converted by a level shifter including the TFTs 506 to 509 and the capacitor 510, and a signal having an amplitude of VDD2 to VSS is output to the output node β. Note that the signals output to the nodes α and β have opposite polarities with respect to the input CK and CKB.

The level shifter used in the display device of the present embodiment is provided with a buffer stage in consideration of the load on the pulse after the amplitude conversion (Stage 2 to Stage 4). The inverter circuit constituting this buffer stage is of a two-input type and requires an input signal and its inverted signal. FIG.
In the buffer circuit shown in Stage 2, a signal input to the gate electrode of the TFT 511 and a signal input to the gate electrode of the TFT 512 require a signal whose polarity is inverted. The same applies to the TFTs 516 and 517. Therefore, here, since CK and CKB are the polarity inversion signals of each other, the above-described output of the level shifter is used as the inversion input of each signal.

The operation of the inverter circuit forming the buffer stage will be described. Here, the TFT
Only the operation in the inverter circuit constituted by 511 to 514 and the capacitor 515 will be described in detail, but the operation is the same for other inverter circuits.

When the signal input to the gate electrode of the TFT 511 is at the Hi potential, the TFT 511 turns on,
The potential of the gate electrode of the TFT 513 is raised to the VDD2 side, and the potential becomes VDD2-V.
When it becomes thN, the TFT 511 is turned off, and the gate electrode of the TFT 513 is in a floating state. On the other hand, the Lo potential is input to the gate electrodes of the TFTs 512 and 514, and the TFTs are turned off. Subsequently, the TFT 513 is turned on, and the potential of the output node γ is raised to the VDD2 side. Here, similarly to the above-described shift register and level shifter, the potential of the gate electrode of the TFT 513 in a floating state is raised by the function of the capacitor 515, and VDD2 + VthN
Take a higher potential. Therefore, the Hi potential of the output node γ becomes equal to VDD2.

On the other hand, when the signal input to the gate electrode of the TFT 511 is at the Lo potential, the TFT 511
The flip-flop is turned on when the Hi potential is input to the gate electrodes of the TFTs 512 and 514. Therefore, the potential of the gate electrode of the TFT 513 becomes Lo potential, and the potential of the output node γ becomes Lo potential.

The inverter circuit constituted by the TFTs 516 to 519 and the capacitor 520 operates similarly to the above, and outputs a pulse to the output node δ. The output node δ outputs a pulse whose polarity is inverted to that of the signal output to the output node γ.

Thereafter, pulses are finally output from the signal output unit 3 (3) and the signal output unit 4 (4) in Stage3 and Stage4 by the same operation. In FIG. 5A, when the output of Stage2 is input to Stage3, the output from Stage1 is changed to Stage3.
Contrary to the case of 2, the input is performed so that the logic is not inverted. However, it is sufficient that the connection is finally made in accordance with the pulse logic required by the user. In particular, the connection between Stages is limited. Absent.

FIG. 5B shows how the amplitude of the clock signal (CK) is converted.
The amplitude of the input signal is 0 to 5 [V], and the amplitude of the output signal is 0 to 16 [V].

FIG. 5C shows a level shifter (LS2) for a start pulse. In the case of a start pulse, since it does not have its inverted signal, a one-input type level shifter circuit (Stag)
Using e1), a one-input type inverter circuit (Stage 2) and a two-input type inverter circuit (Stage 3) were used. The circuit operation is the same as that described in the section of the level shifter for the clock signal, and the description is omitted here.

FIG. 5D shows how the amplitude of the start pulse (SP) is converted. The amplitude of the input signal is 5 [V], and the amplitude of the output signal is 16 [V].

FIG. 6A shows the configuration of the buffer (Buf.), And the one-input type inverter circuit (Sf.
(stage1) and three-stage two-input inverter circuits (Stage2 to Stage4). The operation of the one-input inverter circuit is the same as that of the level shifter circuit except that the amplitude of the input pulse is VDD2 to VSS and there is no amplitude conversion between input and output pulses.

In the operation of the two-input type inverter circuit, an output signal from the preceding stage is input to the TFT 607 as an input signal, and an input signal to the preceding inverter is used as the inverted signal of the input signal to the TFT 606. When the TFTs 606 and 607 operate exclusively, the TF
The potential of the gate electrode at T608 is controlled in the same manner as in the above-described level shifter circuit. In the subsequent inverter circuits, the input signal operates using the output signal from the preceding stage, and the inverted signal of the input signal operates using the input signal to the preceding stage.

FIG. 6B illustrates a configuration of the sampling switch. A sampling pulse is input from the signal input unit 25 (25), and the twelve TFTs 621 arranged in parallel are simultaneously controlled. An analog video signal is input from the signal input units 1 (1) to 12 (12), and the function of writing the potential of the video signal at that time to a source signal line by input of a sampling pulse.

Among the circuits constituting the drive circuit shown in the present embodiment, the inverter circuit and the level shifter circuit are the same as those described in the invention filed by the present inventors in Japanese Patent Application No. 2001-133431. Is used.

In the display device described in this embodiment, a driver circuit which forms the entire display device including a pixel portion is manufactured using only a single-polarity TFT (for example, an N-type TFT) having the same polarity as the pixel TFT. I have. This makes it possible to omit the ion doping step of giving a P-type to the semiconductor layer, which can contribute to reduction in manufacturing cost, improvement in yield, and the like.

Although the polarity of the TFT constituting the display device of this embodiment is N-type, it is of course possible by the present invention to configure the drive circuit and the pixel TFT using only the P-type TFT. In this case, note that the omitted ion doping step is a step of giving an N-type to the semiconductor layer. Further, the present invention can be applied not only to a liquid crystal display device but also to any device which is manufactured by integrally forming a drive circuit on an insulator.

In this embodiment, an example in which the configuration of the pulse output circuit illustrated in FIG. 1 is simplified in the embodiment will be described.

FIG. 7 shows a shift register according to the present embodiment. In FIG. 7A, a block 700 is a pulse output circuit that outputs a pulse for one stage, and the shift register in FIG. 7A includes an n-stage pulse output circuit. FIG. 7B shows a detailed circuit configuration. FIG.
The block diagram of the shift register illustrated in FIG. 7A is similar to that of the shift register in FIG. 7A, and the input signal is also similar. This embodiment is different from the first embodiment in that the pulse output circuit in FIG. 7B includes four TFTs 701 to 704 and a capacitor 705. In FIG. 7B, a block 710 is an amplitude compensation circuit. FIG. 7C shows a further detailed diagram. In FIG. 7C, the TFT 701 connected to the power supply VDD and the power supply VS
An amplitude compensation circuit is configured by using the TFT 702 connected to S.

The operation of the circuit will be described. In the m-th stage (1 <m ≦ n), the pulse output from the (m−1) -th stage is input to the gate electrode of the TFT 701 (when m = 1, that is, SP is input in the first stage). ), The potential of the gate electrode of the TFT 701 becomes Hi potential,
N. As a result, the potential of the node α is raised to the VDD side, and the potential becomes VDD−V
When the current reaches thN, the TFT 701 is turned off, and the node α is in a floating state.
03 turns ON. On the other hand, no pulse is input to the gate electrodes of the TFTs 702 and 704 at this point, and the TFTs remain at the Lo potential. Accordingly, as CK input from one end of the impurity region of the TFT 703, that is, the first input signal line (1) becomes Hi potential, the potential of the output node is raised to the VDD side.

Here, a capacitor 705 is provided between the gate of the TFT 703 and the output node, and the node α, that is, the gate electrode of the TFT 703 is in a floating state. The potential of the gate electrode of the TFT 703 is further raised from VDD−VthN by the strap. Thus, the potential of the gate electrode of the TFT 703 takes a higher potential than VDD + VthN. Therefore, the potential of the output node is
With the threshold value of 03, the potential completely rises to VDD without lowering the potential.

Similarly, in the (m + 1) th stage, a pulse is output according to the CKB. The output pulse of the (m + 1) th stage is fed back to the mth stage and is input to the gate electrodes of the TFTs 702 and 704. TF
When the gate electrodes of T702 and 704 become Hi potential and are turned on, the potential of the node α is pulled down to the VSS side, the TFT 703 is turned off, and the potential of the output node becomes Lo potential.

Thereafter, pulses having an amplitude between VDD and VSS are sequentially output by the same operation until the last stage. In the final stage, since there is no next stage output pulse to be input from the third input signal line (3) in FIG. 7B, CK continues to be output as it is. If there is no problem. In the present embodiment shown in FIG. 7, the start pulse is input to the third input signal line of the last stage, so that the output pulse of the last stage is stopped immediately before the next horizontal period. As another method, a reset signal is prepared as described in the section of the embodiment, and the reset signal is input to the third input signal line of the final stage during the flyback period.
There are a method of stopping the pulse output, a method of inputting a reset signal so as to fix the output nodes of all stages to the Lo potential during the retrace period (the same as in FIG. 15), and the like.

The pulse output circuit shown in this embodiment has a smaller number of elements than the pulse output circuit shown in the embodiment, and has many portions which are in a floating state during a period in which there is no input and output of a sampling pulse. Therefore, it can be said that this is particularly suitable for a portion where the driving frequency is high. Therefore, in a display device, it is desirable to use it for a source signal line driver circuit or the like.

Please refer to FIG. In the shift register described in the embodiment mode, the first embodiment, the third embodiment, and the like of the present invention, as shown in FIG. 13A, CK has the same length as the Hi potential period 1301 and the Lo potential period 1302; CKB whose polarity is inverted is input. At this time,
Since the pulse width of the sampling pulse is equal to the pulse width of CK and CKB, the output is as shown at 1303 to 1307 in FIG. Reference numeral 1303 denotes a first-stage sampling pulse, 1304 denotes a second-stage sampling pulse, and hereafter, third to fifth-stage sampling pulses.

Here, the CK and other input / output signals have a rise time when the potential changes from the Lo potential to the Hi potential and a fall time when the potential changes from the Hi potential to the Lo potential. In some cases, overlapping pulses that should not appear ideally may occur. FIG. 13 (
In (A), the sampling pulses 1303 to 1307 show that the rising period and the falling period overlap between adjacent pulses.

In particular, in the case of a display device which performs video display by sampling an analog video signal, sampling of a video signal may be performed at an improper timing due to such overlap of adjacent sampling pulses, which causes deterioration in display quality. Will be.

Therefore, in order to avoid such overlapping of sampling pulses, FIG.
As shown in (1), a difference is given to the pulse width of CK. In this case, the period 1308 of the Hi potential is L
This is slightly shorter than the period 1309 of the o potential. Similarly, the CKB has a Hi potential period of L
The period is slightly shorter than the period of the o potential. This eliminates the overlap between the rising period of CK and the falling period of CKB, or the overlapping of the falling period of CK and the rising period of CKB. , The overlapping of the rising period and the falling period can be eliminated.

Here, FIG. 1 is referred to again. The operation of the pulse output circuit shown in FIG.
When CK or CKB is output to the output node during a period when the switch 05 is ON, a sampling pulse is output. That is, CK or CKB is output as it is from when the potential of the node α starts to rise until the potential is lowered to the Lo potential by the next sampling pulse. Therefore, if the rising period of CK and the falling period of CKB or the falling period of CK and the rising period of CKB overlap, an incorrect pulse may be output before and after the sampling pulse.

In FIG. 13A, a sampling pulse 1304 at a previous stage is input to a shift register from which a sampling pulse 1305 is output, and CK or CKB (
At the stage where the sampling pulse 1305 is output, since CK) appears at the output node as it is, at the timing indicated by 1315, that is, at the timing when the sampling pulse 1304 of the preceding stage starts to rise, if CK has not completely dropped to Lo potential, FIG. 13 (B)
As shown in (1), an illegal pulse 1316 appears before the sampling pulse 1305 originally output. Therefore, as shown in this embodiment, by modulating the pulse widths of CK and CKB, these malfunctions can be avoided.

In the embodiment and the examples described above, the example in which the circuit is configured using only the N-channel TFT is described. However, the same applies to the case where only the P-channel TFT is used by replacing the level of the power supply potential. A circuit can be configured.

FIGS. 15A and 15B illustrate an example of a shift register including only P-channel TFTs. Regarding the block diagram shown in FIG. 16A, the N-channel type T shown in FIG.
The configuration is the same as that of the shift register configured using only the FT.
This is a pulse output circuit that outputs sampling pulses for the stages. The difference from the shift register constituted by the N-channel TFT is that the level of the power supply potential is reversed as shown in FIG.

FIG. 17 shows a timing chart and output pulses. Since the operation of each unit has been described in the embodiment with reference to FIGS. 1 and 2, detailed description is omitted here. The configuration shown in FIG. 2 has a form in which the Hi potential and the Lo potential are reversed.

The present invention can be applied to manufacture of a display device used for various electronic devices. Such electronic devices include a portable information terminal (electronic notebook, mobile computer, mobile phone, etc.), a video camera, a digital camera, a personal computer, a television, a mobile phone, and the like. FIG. 8 shows an example of them.

FIG. 8A illustrates a liquid crystal display (LCD), which includes a housing 3001, a support 3002, a display portion 3003, and the like. The present invention can be applied to the display portion 3003.

FIG. 8B illustrates a video camera, which includes a main body 3011, a display unit 3012, and a voice input unit 301.
3, an operation switch 3014, a battery 3015, an image receiving unit 3016, and the like. The present invention can be applied to the display portion 3012.

FIG. 8C illustrates a laptop personal computer, which includes a main body 3021 and a housing 3022.
, A display unit 3023, a keyboard 3024, and the like. The present invention relates to the display unit 30.
23 is applicable.

FIG. 8D illustrates a portable information terminal, which includes a main body 3031, a stylus 3032, and a display portion 303.
3, an operation button 3034, an external interface 3035, and the like. The present invention can be applied to the display portion 3033.

FIG. 8E illustrates a sound reproducing device, specifically, an audio device for a vehicle.
, A display unit 3042, operation switches 3043, 3044, and the like. The present invention can be applied to the display portion 3042. In this embodiment, the in-vehicle audio device is described as an example. However, the present invention may be applied to a portable or home audio device.

FIG. 8F illustrates a digital camera, which includes a main body 3051, a display unit (A) 3052, and an eyepiece unit 3.
053, an operation switch 3054, a display portion (B) 3055, a battery 3056, and the like. The present invention can be applied to the display portion (A) 3052 and the display portion (B) 3055.

FIG. 8G illustrates a mobile phone, which includes a main body 3061, an audio output unit 3062, and an audio input unit 306.
3, a display unit 3064, operation switches 3065, an antenna 3066, and the like. The present invention can be applied to the display portion 3064.

It should be noted that the example shown in this embodiment is merely an example, and the present invention is not limited to these applications.

Claims (1)

A first transistor, a second transistor, a first circuit, and a second circuit;
The conductivity type of each of the first transistor and the second transistor is the same,
In the first transistor, a gate is electrically connected to the first circuit, one of a source and a drain is electrically connected to the first wiring, and the other of the source and the drain is electrically connected to one of a source and a drain of the second transistor. And
The semiconductor device, wherein the second transistor has a gate electrically connected to the second circuit and the other of the source and the drain connected to a second wiring.

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