JP2020031442A - Lock-in amplifier - Google Patents

Abstract

To provide a lock-in amplifier that does not cause a measurement error even when a low-pass filter having a small time constant or order is used.SOLUTION: A lock-in amplifier (22) includes first phase detection means (phase detector 24-1), second phase detection means (phase detector 24-2), a low-pass filter (30), and at least one filter excluding the low-pass filter (band rejection filter 28). The first phase detection means converts a signal to be measured input to the first phase detection means into a plurality of frequency components, removes at least one of the plurality of converted frequency components by the filter, and converts the remaining frequency components into a direct current by the second phase detection means.SELECTED DRAWING: Figure 4

Description

The present invention relates to a lock-in amplifier that detects a minute repetitive signal buried in noise.

  An outline of the most basic operation of the lock-in amplifier 102 shown in FIG. 9A will be described. The signal under measurement having the frequency f output from the device under test 112 is supplied to the lock-in amplifier 102 as an input signal of the lock-in amplifier 102. The signal to be measured having the frequency f passes through an amplifier, a filter, and the like as necessary, and is provided to the phase detector 104. On the other hand, the reference signal generator 106 also generates a reference signal having the same frequency f as the signal under measurement, and supplies the reference signal to the phase detector 104. The phase detector 104 performs frequency conversion of the signal under measurement using the reference signal, and outputs AC and DC (frequency = 0) having a frequency of f ± f, that is, a frequency of 2f. This output attenuates an alternating current having a frequency of 2f by passing through a low-pass filter (LPF: Low Pass Filter) 110, and becomes an output of only a direct current. Since the DC output is proportional to the amplitude of the signal under test, the magnitude of the signal under test can be known from the voltage of the DC output.

  The operation of the lock-in amplifier 102 will be described in detail with reference to FIG. The phase detector 104 (synchronous detection) basically multiplies two input signals, and includes a type using a square wave, a type using a pseudo sine wave, and a type using a sine wave for the input on the reference signal side. . Here, description will be made using a sine wave.

  Assuming that the input of the phase detector 104 on the signal under test includes only a single frequency, the input of the phase detector 104 ((1) in FIG. 9A) can be written as Acos (ωt + α). . Here, A is amplitude, ω = 2πf, t is time, and α is phase. This input can be represented as shown in FIG. On the other hand, if the frequency of the input of the phase detector 104 on the reference signal side is the same as that of the input on the signal under test side and the amplitude is 2 for convenience, it can be written as 2 cos (ωt).

  According to the product-sum formula of the trigonometric functions, the output of the phase detector 104 ((2) in FIG. 9A) is represented by the following equation (1). This output can be represented as shown in FIG.

Output of phase detector 104 = Acos (ωt + α) × 2cos (ωt)
= Acos (2ωt + α) + Acos (α) (1)

  The first term of Equation (1) is a frequency component of 2f, and the second term is a DC component that does not change with time. Both are proportional to the input amplitude of the phase detector 104 on the signal under test.

This output passes through a low-pass filter 110 (this low-pass filter 110 has, for example, a transmittance characteristic indicated by an LPF in FIG. 10B), whereby the 2f frequency component is attenuated, and The output of the bandpass filter 110 ((3) in FIG. 9A) is an output including only DC, as shown in FIG. According to such a lock-in amplifier 102, a signal having the same frequency as the reference signal in the signal under measurement can be detected as a DC output,
Since this DC output is proportional to the amplitude of the input signal of the phase detector 104 on the signal under test side, the magnitude of the signal under test can be known from the voltage of the DC output.

  Almost the same contents as those described above are shown in FIG. 2 and paragraphs 0006 to 0008 of Patent Document 1.

  As shown in the latter part of Expression (1), the voltage of the DC output changes depending on the phase of the signal under measurement with respect to the reference signal, so that the phase of the signal under measurement and the phase of the reference signal need to be synchronized. Note that phase synchronization can be achieved using a phase synchronization function unit such as a commonly used phase locked loop (PLL: Phase Locked Loop), and a description of a means for achieving phase synchronization will be omitted.

  FIGS. 9B to 9D show an example of phase synchronization. FIG. 9B is an example in which the reference signal is phase-synchronized based on the signal under measurement. FIG. 9C is an example in which a synchronization signal is received from the device under test 112 and the reference signal is phase-synchronized. FIG. 9D illustrates an example in which a reference signal is supplied to the device under test 112 and a signal obtained from the device under test 112 is measured. Note that the phase synchronization function unit 114 is not shown in drawings other than FIGS. 9B to 9D, but any of them can be provided with such a phase synchronization function unit 114. 9 (C) is shown in FIG. 2 of Patent Document 2, and the same content as FIG. 9 (D) is shown in FIG. 1 of Patent Document 2.

  As shown in the latter part of equation (1), the absolute value of the DC output is maximum when the signal under measurement and the reference signal are in phase or opposite phase, and the DC output is zero when the signal is ± 90 °. By adjusting the phase of the reference signal as a reference, the phase of the signal under measurement can be known.

  To more easily know the phase of an input signal, a two-phase lock-in amplifier is known. The two-phase lock-in amplifier 122 shown in FIG. 11 uses two reference signals whose phases are shifted by 90 ° and two corresponding phase detectors 104-1 and 104-2.

  The inputs of the two phase detectors 104-1 and 104-2 on the signal-under-measurement side are commonly connected, and both are Acos (ωt + α) as described above. The input of the phase detector 104-1 on the reference signal side is 2 cos (ωt) as described above, and the input of the phase detector 104-2 is −2 sin (ωt). In this case, the output of the phase detector 104-1 is as shown in the above equation (1), and the output of the phase detector 104-2 is as shown in the following equation (2).

Output of phase detector 104-2 = Acos (ωt + α) × {−2 sin (ωt)}
= −Asin (2ωt + α) + Asin (α) (2)

  The low-pass filters 110-1 and 110-2 provided at the outputs of the phase detectors attenuate the preceding term (2f frequency component) in Equations (1) and (2), resulting in the phase detector 104- The first DC output (X output) on the 1 side has a DC voltage proportional to the cos component of the signal under test, and the second DC output (Y output) on the phase detector 104-2 has the DC voltage of the signal under test. A DC voltage proportional to the sin component appears.

  Almost the same contents as those described above are also shown in FIG. 3 of Patent Document 1 and paragraphs 0008 to 0010.

  Note that the amplitude A and the phase α of the signal under measurement can be obtained from the latter part of each of the equations (1) and (2) as shown in FIG.

  The basic configuration and operating principle of the lock-in amplifier have been described above without distinction between analog and digital. Each component of the lock-in amplifier can be realized by an analog circuit, but in recent years, each component has been replaced by a digital circuit, a CPU (Central Processing Unit), a DSP (Digital Signal Processor), and an FPGA (Field Programmable Gate Array). Digital lock-in amplifiers realized by digital arithmetic means such as those described above have also become widespread. In a digital lock-in amplifier, for example, an input to be measured is converted into a digital signal by an AD converter, and the necessary components such as a phase detector and a filter are realized by a digital circuit or digital arithmetic means. (If necessary, the analog circuit may be partially used together.)

  An example of a one-phase digital lock-in amplifier is shown in FIG. 4 and paragraphs 0010 to 0011 of Patent Document 1. Examples of a two-phase digital lock-in amplifier are shown in FIG. 5 and paragraphs 0018 to 0019 of Patent Document 1 and in FIG. 1 of Patent Document 3.

JP 2007-003458 A JP-T-2007-536519 JP-A-01-093914

  In the related art, since the low-pass filter 110 needs to sufficiently attenuate the frequency component of 2f, it is necessary to increase the time constant, that is, to lower the cutoff frequency. However, when the magnitude of the signal to be measured changes, there is a problem that if the time constant of the low-pass filter 110 is large, the change in the DC output becomes slow, that is, the measurement response becomes slow.

  In particular, when the low-pass filter 110 having a small order is used with emphasis on the phase characteristics and the like of the filter, the time constant has to be increased accordingly, and the effect of this problem is further increased.

  Further, in the case where the spectrum width is wide such as when the signal under measurement is modulated, as shown in FIG. 13, the following contradictory conditions shown in (1), (2) and (3) occur. Problems arise.

  (1) When a low-pass filter having a large time constant is used, a flat frequency characteristic cannot be obtained within a spectrum width, and a measurement error occurs.

  (2) If a low-pass filter having a large order is used to reduce the time constant, the phase characteristics of the filter are sacrificed.

  (3) If a low-pass filter with a small time constant is used, a frequency component near 2f cannot be sufficiently attenuated, and a measurement error occurs.

Therefore, an object of the present invention is to provide a lock-in amplifier in which a measurement error does not occur even when a low-pass filter having a small time constant or order is used.

  To achieve the above object, according to one aspect of the present invention, a lock-in amplifier includes a phase detection unit, a low-pass filter, and at least one filter excluding a low-pass filter. The phase detector includes a first phase detector and a second phase detector. The first phase detector converts the signal to be measured input to the first phase detector into a plurality of frequency components, and removes at least one of the plurality of converted frequency components by the filter. Then, the remaining frequency components are converted to direct current by the second phase detector.

  In the lock-in amplifier, the filter may be any one of a band elimination filter, a band-pass filter, and a high-pass filter.

  The lock-in amplifier detects a frequency of the signal under test inputted to the first phase detection means, and adjusts the first phase detection means and the second phase detection signal in accordance with the detected frequency of the signal under test. And a frequency detection / setting unit for controlling the frequency of the reference signal provided to each of the phase detection means.

  In the lock-in amplifier, a digital circuit or a digital operation means may be used for the phase detection means, the low-pass filter, and a part or all of the filter.

  In the lock-in amplifier, the phase detection means may convert part or all of the frequency by a digital circuit or a digital operation means using a CORDIC method.

  According to the present invention, the following effects can be obtained.

  (1) According to the lock-in amplifier of the present invention, an unnecessary frequency such as 2f is attenuated by at least one filter excluding the low-pass filter. Therefore, the time constant of the low-pass filter is increased, that is, the cutoff frequency is reduced. Need not be lowered. For this reason, even when the magnitude of the signal under measurement changes, the DC output quickly follows the change in the signal under measurement, so that the measurement response can be made faster.

  (2) It is possible to use a low-pass filter having a small order with emphasis on the phase characteristics and the like of the filter.

(3) Further, even when the signal to be measured is modulated and the spectrum width is wide, the degree of freedom in selecting the low-pass filter can be increased.

FIG. 2 is a diagram illustrating a configuration of a lock-in amplifier according to the first embodiment. FIG. 5 is a diagram illustrating an example of an operation of the lock-in amplifier according to the first embodiment. FIG. 2 is a diagram illustrating a configuration of a two-phase lock-in amplifier according to the first embodiment. FIG. 9 is a diagram illustrating a configuration of a lock-in amplifier according to a second embodiment. FIG. 14 is a diagram illustrating an example of an operation of the lock-in amplifier according to the second embodiment. FIG. 14 is a diagram illustrating a configuration of a lock-in amplifier according to a third embodiment. FIG. 14 is a diagram illustrating an example of an operation of the lock-in amplifier according to the third embodiment. FIG. 14 is a diagram illustrating a configuration of a lock-in amplifier according to a fourth embodiment. FIG. 11 is a diagram illustrating a configuration of a lock-in amplifier according to the related art. FIG. 11 is a diagram illustrating an example of the operation of the lock-in amplifier according to the related art. FIG. 9 is a diagram illustrating a configuration of a two-phase lock-in amplifier according to the related art. FIG. 9 is a diagram illustrating an example of a relationship between an output of a two-phase lock-in amplifier and an amplitude / phase according to the related art. FIG. 9 is a diagram illustrating a problem of the lock-in amplifier according to the related art.

  Hereinafter, embodiments of the present invention will be described in detail.

  [First Embodiment]

  In the first embodiment, an AC component included in the output of the phase detector, that is, the preceding term (the frequency component of 2f) of the above-described equations (1) and (2) is removed using a band elimination filter. Indicates a lock-in amplifier that reduces the time constant of the low-pass filter.

  FIG. 1 shows a basic configuration of the lock-in amplifier 2 according to the first embodiment, and FIG. 2 shows an example of a basic operation of such a lock-in amplifier 2. FIG. 3 shows a basic configuration when a two-phase lock-in amplifier is configured by the lock-in amplifier 2 according to the first embodiment.

  In FIG. 1, a phase detector 4 is an example of a phase detector that converts a signal to be measured input to the phase detector 4 into a plurality of frequency components. The measured signal output from the device under test 12 and the reference signal output from the reference signal generator 6 are input to the phase detector 4. A signal to be measured having a frequency f shown in FIG. 2A is given to the input unit on the signal input side of the phase detector 4 ((1) in FIG. 1), and the input unit on the reference signal side of the phase detector 4 is supplied to the input unit on the reference signal side. As a result of the provision of the reference signal having the frequency f, the output of the phase detector 4 ((2) in FIG. 1) is given by the above-mentioned equation (1) as Acos (2ωt + α) + Acos (α). The output of the phase detector 4 includes two frequency components of a frequency 0 and a frequency 2f, as shown in FIG. The output mode of the phase detector 4 is the same as that of the lock-in amplifier described in the background art of FIG. 9A.

  In the first embodiment, the 2f frequency component of the output of the phase detector 4 is removed by a band elimination filter (BEF) 8. That is, as shown in FIG. 2C, the output of the band elimination filter 8 ((3) in FIG. 1) is only the DC component in the latter term of the equation (1). As the band elimination filter 8, a filter circuit designed to attenuate some frequency components and allow other frequency components to pass can be used. The band elimination filter 8 has, for example, a transmittance characteristic indicated by BEF in FIG. 2B, and includes the aforementioned AC component (frequency component of 2f) included in the output of the phase detector 4, that is, the signal under measurement. It is designed to attenuate twice the frequency.

  According to the lock-in amplifier 102 described in the background art, the low-pass filter 110 shown in FIG. 9A removes the 2f frequency component as shown by the LPF in FIG. have. However, according to the first embodiment, since the band elimination filter 8 removes the frequency component of 2f, the low-pass filter 10 can be set to remove the frequency component higher than 2f. Therefore, the low-pass filter 10 does not need to have a large time constant that can sufficiently remove the 2f frequency component, but can set a small time constant that allows the 2f frequency component to pass. For example, as shown in the LPF of FIG. 2C, the time constant can be reduced as necessary. That is, even if the time constant of the low-pass filter 10 is reduced as necessary, the output ((4) in FIG. 1) of the low-pass filter 10 is reduced by only the DC component as shown in FIG. Can be

  If the time constant of the low-pass filter 10 is small, the DC output can quickly follow the change in the signal under measurement even when the signal under measurement changes, so that the measurement response can be made fast. Further, since it is not necessary to remove the frequency component of 2f by the low-pass filter 10, the low-pass filter 10 having a small order can be used with emphasis on the phase characteristics and the like of the filter. Further, when the spectrum of the signal to be measured is wide because the signal to be measured is modulated, the degree of freedom in selecting the low-pass filter 10 can be increased (see FIG. 13).

  In the first embodiment, the lock-in amplifier 2 includes the band elimination filter 8 and the low-pass filter 10 having different frequency components to be attenuated, and each filter shares the attenuation of the frequency component that needs to be attenuated. , Attenuate all frequency components that need to be attenuated throughout the filter.

  FIG. 1 shows an example in which the band elimination filter 8 is provided before the low-pass filter 10, but the band elimination filter 8 can be provided after the low-pass filter 10.

  Further, when the signal to be measured includes noise (for example, 50 Hz or 60 Hz of an AC power supply) or an interfering wave (for example, an AM radio wave), it is also possible to further add a band elimination filter for removing these. (The same applies to the second embodiment, the third embodiment, and the fourth embodiment described below).

  The lock-in amplifier 2 can be realized as a two-phase lock-in amplifier 2 by expanding the lock-in amplifier 2 as shown in FIG. The phase detector 4-1, the band elimination filter 8-1, and the low-pass filter 10-1 of the two-phase lock-in amplifier 2 are the phase detector 4, the band elimination filter 8 of the one-phase lock-in amplifier 2, respectively. , Low-pass filter 10. The phase detector 4-2, the band elimination filter 8-2, and the low-pass filter 10-2 of the two-phase lock-in amplifier 2 are respectively the phase detector 4, the band elimination filter 8 of the one-phase lock-in amplifier 2. , Low-pass filter 10.

  In the two-phase lock-in amplifier 2, one of two reference signals whose phases are shifted by 90 °, for example, a reference signal of 2 cos (ωt) is input to an input unit on the reference signal side of the phase detector 4-1. Then, the other reference signal, for example, −2 sin (ωt), is input to the input unit on the reference signal side of the phase detector 4-2. In such a two-phase lock-in amplifier 2, like the two-phase lock-in amplifier 122, the first DC output (X output) on the phase detector 4-1 side is proportional to the cos component of the signal under measurement. As a result, a DC voltage proportional to the sin component of the signal under measurement appears at the second DC output (Y output) on the phase detector 4-2 side. Since the band elimination filters 8-1 and 8-2 remove the frequency component of 2f similarly to the band elimination filter 8, the low-pass filters 10-1 and 10-2 remove the frequency components higher than 2f. Can be set to do.

  Also in the first embodiment, similarly to the lock-in amplifier described in the background art, it is freely determined whether each of the components of the lock-in amplifier is realized by an analog circuit, a digital circuit, or a digital operation unit. Can be selected.

  The band elimination filter 8 and the band elimination filters 8-1 and 8-2 can be realized by various band elimination realizing means including a CR filter such as an LC filter and a twin T-type notch filter, and various active filters using an analog circuit. Can be. The band elimination means includes a digital filter such as a comb filter, a SINC filter, and a cascaded integration comb (CIC) filter. FIG. 2B illustrates a band elimination filter that eliminates only a single frequency, but a function of eliminating a predetermined frequency even with a filter that eliminates a plurality of frequencies such as a comb filter. Is common to the other band elimination filters, and is included in the band elimination filter in this application. (The same applies to the second to fourth embodiments described below.)

  It should be noted that a filter that removes a plurality of frequencies, such as a comb filter, may be more preferable because some frequencies in various types of noise can be removed in addition to a predetermined frequency.

  The low-pass filter 10 and the low-pass filters 10-1 and 10-2 are realized by various low-pass realizing means including an LC filter, a CR filter, various active filters using analog circuits, and various digital filters. be able to. (The same applies to the second to fourth embodiments described below.)

  Further, in the first embodiment, by using the band elimination filter 8 or the band elimination filters 8-1, 8-2, the low-pass filters 10, 10-1, 10-2 can be omitted. . (The same applies to the third embodiment and the fourth embodiment described below.)

  In the first embodiment, the band elimination filter 8 that can remove twice the frequency of the signal under measurement is used. For this reason, when the frequency of the signal under measurement changes, the frequency characteristic of the band elimination filter 8 may be changed according to the change in the frequency of the signal under measurement, or a plurality of filters may be provided to switch the filters.

  If the frequency characteristic of the band elimination filter 8 is changed, or if a large number of filters are provided, the band elimination filter 8 becomes complicated and the band elimination filter 8 needs to be controlled. This is applied when the frequency of the signal under measurement is stable. For example, when the phase synchronization method as shown in FIG. 9D is used, the first embodiment can be suitably used by keeping the frequency of the reference signal constant.

[Second embodiment]

  The second embodiment is a lock-in amplifier including two phase detectors, and the two phase detectors use the lock-in amplifier regardless of whether the frequency of the signal under measurement changes. Can be.

  FIG. 4 shows an example of the lock-in amplifier 22 according to the second embodiment, and FIG. 5 shows an example of a basic operation of such a lock-in amplifier.

  In FIG. 4, a phase detector 24-1 is an example of a phase detector that converts a signal under measurement input to the phase detector 24-1 into a plurality of frequency components. A signal to be measured having a frequency f shown in FIG. 5A is supplied to an input unit on the signal input side of the phase detector 24-1 ((1) in FIG. 4), and the reference signal generator 26-1 outputs the signal to be measured. The reference signal having the frequency f ′ is supplied to an input unit on the reference signal side of the phase detector 24-1. The input on the signal input side of the phase detector 24-1 is Acos (ωt + α), and the input on the reference signal generator 26-1 side of the phase detector 24-1 is 2 cos (ω′t), as described above. . (Here, ω ′ = 2πf ′.) As a result, the output ((2) in FIG. 4) of the phase detector 24-1 is as shown in the following equation (3).

Output of phase detector 24-1 = Acos (ωt + α) × 2cos (ω′t)
= Acos ｛(ω + ω ') t + α｝ + Acos ｛(ω-ω') t + α｝ (3)

  The first term of Equation (3) is a frequency component of f + f ', and the second term is a frequency component of f-f'. Accordingly, the output of the phase detector 24-1 is an alternating current including a frequency component of f ± f 'as shown in FIG.

  The output of the phase detector 24-1 is input to a band elimination filter 28 (the band elimination filter 28 has, for example, a transmittance characteristic indicated by BEF in FIG. 5B). As shown in FIG. 5B, the band elimination filter 28 removes the ff ′ frequency component from the f ± f ′ frequency components. As a result, as shown in FIG. 5C, f + f ′. Only the frequency component of remains.

  In order to remove the frequency component of ff ′ and leave only the frequency component of f + f ′, in addition to the band elimination filter 28, a band-pass filter (BPF) or a high-pass filter (HPF: High-frequency filter). Other filters besides a low-pass filter, such as a Pass Filter, can also be used. Such a band-pass filter has, for example, a transmittance characteristic such as a BPF portion indicated by a dotted line in FIG. 5B, and passes a frequency component of f + f ′ and a frequency component near f + f ′. In addition, such a high-pass filter has, for example, a transmittance characteristic such as an HPF portion shown by a dashed line in FIG. 5B, and is capable of removing a frequency component of f + f ′ and a frequency component higher than f + f ′. Let it pass. Even when a filter such as a band-pass filter or a high-pass filter other than the low-pass filter is used, the frequency component of f−f ′ can be removed and the frequency component of f + f ′ can be left. When the low-pass filter is used, the response of the measurement of the lock-in amplifier may be slow. However, when a filter other than the low-pass filter is used, a configuration in which the response of the measurement is fast can be realized.

  The phase detector 24-2 is an example of a phase detector that converts the output of the band elimination filter 28 input to the phase detector 24-2 into a plurality of frequency components. The output of the band elimination filter 28 including the frequency component of f + f ′ ((3) in FIG. 4) is given to the input unit on the signal input side of the phase detector 24-2, and the reference signal side of the phase detector 24-2. Is supplied with a reference signal of frequency f + f ′ output from the reference signal generator 26-2. The input on the signal input side of the phase detector 24-2 is Acos {(ω + ω ′) t + α) in the preceding term of the equation (3), and the input on the reference signal side of the phase detector 24-2 is the phase detector 24. −2 cos {(ω + ω ′) t} where the frequency is the same as that of the input on the signal input side of −2, and the amplitude is 2. As a result, the output ((4) in FIG. 4) of the phase detector 24-2 is as shown in the following equation (4).

Output of phase detector 24-2 = Acos {(ω + ω ′) t + α} × 2 cos {(ω + ω ′) t}
= Acos ｛2 (ω + ω ') t + α｝ + Acos (α) (4)

  The first term of Equation (4) is a frequency component of 2 (f + f '), and the second term is a DC component that does not change with time. Therefore, the output of the phase detector 24-2 includes a frequency component of 2 (f + f ') and a DC component as shown in FIG.

  This output passes through a low-pass filter 30 (for example, the low-pass filter 30 has a transmittance characteristic indicated by an LPF in FIG. 5D), so that the frequency of 2 (f + f ′) is attenuated. Then, the output of the low-pass filter 30 ((5) in FIG. 4) is an output including only DC as shown in FIG. 5 (E). The low-pass filter 30 can have a smaller time constant than a low-pass filter that attenuates the frequency component of 2f as shown by the dotted line in FIG. Therefore, the response of the measurement can be made faster, a low-pass filter having a small order can be used with emphasis on the phase characteristics of the filter, and the spectrum width is increased when the signal under measurement is modulated. Even in a wide case, the degree of freedom in selecting a low-pass filter can be increased.

  In the first embodiment, when the frequency of the signal under measurement changes, it is necessary to change the frequency characteristic of the band elimination filter 8 so as to follow the change in frequency. However, in the second embodiment, the reference signal of the frequency f ′ generated by the reference signal generation unit 26-1 and the reference signal of the frequency f + f ′ generated by the reference signal generation unit 26-2 are changed to the frequency change of the signal under measurement. It is possible to follow the change in the frequency of the signal under measurement only by changing the following, and the frequency characteristic of the band elimination filter 28 can be kept constant.

  For changing the reference signal, for example, the frequency detection / setting unit 32 shown in FIG. 4 is used. The frequency detection / setting unit 32 detects the frequency f of the signal under measurement, and adjusts the frequency f 'so that the band elimination filter 28 removes the frequency component of f-f'. Further, the frequency detection / setting unit 32 sets the reference signal generation unit 26-1 so that the reference signal generation unit 26-1 outputs a signal of the frequency f ′, and the reference signal generation unit 26-2 sets the frequency f + f ′. The frequency detection / setting unit 32 sets the reference signal generation unit 26-2 to output a signal. Thus, the band elimination filter 28 for removing the frequency component of f-f 'has a constant frequency characteristic and does not need to be changed.

  Since the frequency of the reference signal generators 26-1 and 26-2 can be easily changed, the frequency f 'of the reference signal generator 26-1 and the frequency f + f' of the reference signal generator 26-2 can be easily set. Can follow the change of the frequency f of the signal under measurement.

  In the second embodiment, a case where f> f ′ is illustrated as shown in FIGS. 5B and 5C, but f <f ′ may be set. .

  In the first embodiment, the lock-in amplifier 2 having the basic configuration of FIG. 1 is expanded as shown in FIG. 3 to realize a two-phase lock-in amplifier. A phase lock-in amplifier can be realized.

  Also, in the second embodiment, similarly to the lock-in amplifier according to the first embodiment and the lock-in amplifier described in the background art, each of the components of the lock-in amplifier includes an analog circuit, a digital circuit, and a digital circuit. Which of the arithmetic means is realized can be freely selected.

  In the second embodiment, in order to reduce the time constant of the low-pass filter 30, the band elimination filter 28 removes a frequency lower than the frequency (f) of the signal under measurement.

[Third Embodiment]

  The third embodiment is a two-phase lock-in amplifier including six phase detectors. The six phase detectors enable the two-phase lock-in amplifier regardless of whether the frequency of the signal under measurement changes. An amplifier can be used, and a frequency that can be removed by the band elimination filter can be selected higher than the frequency of the signal under measurement.

  FIG. 6 shows an example of a lock-in amplifier according to the third embodiment, and FIG. 7 shows an example of a basic operation of such a lock-in amplifier.

  In FIG. 6, the phase detectors 44-1 and 44-2 are an example of a first phase detector that converts a signal under measurement into a plurality of frequency components. A signal to be measured having a frequency f shown in FIG. 7A is supplied to both input sections on the signal input side of the phase detector 44-1 and the phase detector 44-2 ((1) in FIG. 6). Further, reference signals having a frequency f 'and a phase difference of 90 [deg.] From each other are given to the input parts on the reference signal side of the phase detector 44-1 and the phase detector 44-2. This out-of-phase reference signal is output from reference signal generation section 46-1.

  The input on the signal input side of the phase detector 44-1 and the phase detector 44-2 is Acos (ωt + α) as described above. The input of the phase detector 44-1 on the reference signal side is 2 cos (ω′t), and the input of the phase detector 44-2 on the reference signal side is −2 sin (ω′t). (Here, ω ′ = 2πf ′.) As a result, the output of the phase detector 44-1 is as shown in the following equation (5), and the output of the phase detector 44-2 is as shown in the following equation (6). )become that way.

Output of phase detector 44-1 = Acos (ωt + α) × 2cos (ω′t)
= Acos ｛(ω + ω ') t + α)｝ + Acos ｛(ω-ω') t + α｝ (5)
Output of phase detector 44-2 = Acos (ωt + α) × {−2 sin (ω′t)}
= -Asin {(ω + ω ') t + α)｝ + Asin {(ω-ω') t + α}
... (6)

  The first term of each of the equations (5) and (6) is a frequency component of f + f ', and the second term is a frequency component of f-f'. Accordingly, the outputs of the phase detectors 44-1 and 44-2 ((2) in FIG. 6) are both alternating currents including frequency components of f ± f 'as shown in FIG. 7B.

  Here, as shown in FIG. 7B, the frequency components of f + f ′ are converted into band elimination filters 48-1 and 48-2 (the band elimination filters 48-1 and 48-2 are, for example, shown in FIG. 7B). As a result, as shown in FIG. 7C, only the frequency component of ff ′, that is, only the latter term of each of Expressions (5) and (6) is obtained. Will remain.

  The phase detectors 44-3, 44-4, 44-5, 44-6, the inverter 54, and the adders 56-1, 56-2 convert the ff 'frequency component into a direct current. It is an example of the means. The frequency component of ff ′ on the side of the phase detector 44-1 (the latter term of the equation (5)) is given to the input unit on the signal input side of the phase detectors 44-4 and 44-6, and is output from the phase detector. The frequency component of ff ′ on the 44-2 side (the latter term of the equation (6)) is given to the input section on the signal input side of the phase detectors 44-3 and 44-5. The inputs ((3) in FIG. 6) of the phase detectors 44-3, 44-4, 44-5, and 44-6 are all represented as shown in FIG. 7C.

  The reference signal generator 46-2 outputs the cosine signal (cosine signal) of the frequency ff ′ to the phase detectors 44-3 and 44-4, and outputs the −sin signal (minus sine signal) to the phase detector 44-. 5, 44-6. The input on the reference signal side of the phase detectors 44-3 and 44-4 is 2 cos {(ω-ω ') t}, and the input on the reference signal side of the phase detectors 44-5 and 44-6 is -2 sin. {(Ω−ω ′) t}.

  As a result, the output of the phase detector 44-3 is the following equation (7), the output of the phase detector 44-4 is the following equation (8), and the output of the phase detector 44-5 is the following equation (9). The output of the phase detector 44-6 is as shown in the following equation (10).

Output of phase detector 44-3 = A sin {(ω−ω ′) t + α} × 2 cos {(ω−ω ′) t}
= Asin ｛2 (ω-ω ') t + α｝ + Asin (α) (7)
Output of phase detector 44-4 = Acos {(ω-ω ′) t + α} × 2 cos {(ω−ω ′) t}
= Acos ｛2 (ω-ω ') t + α｝ + Acos (α) (8)
Output of phase detector 44-5 = A sin {(ω−ω ′) t + α} × [−2 sin {(ω−ω ′) t}]
= Acos ｛2 (ω-ω ') t + α｝ -Acos (α) (9)
Output of phase detector 44-6 = Acos {(ω-ω ′) t + α} × [−2 sin {(ω−ω ′) t}]
= −Asin ｛2 (ω−ω ′) t + α｝ + Asin (α) (10)

  The output of the phase detector 44-5 (the equation (9)) is inverted by the inverter 54.

  The adder 56-1 adds the inverted signal of the output of the phase detector 44-4 (formula (8)) and the output of the phase detector 44-5 (formula (9)). As a result of the expression (8) and the inverted preceding expression (9) canceling out each other, the output of the adder 56-1 is 2Acos (α).

  The adder 56-2 adds the output of the phase detector 44-3 (the above equation (7)) and the output of the phase detector 44-6 (the above equation (10)). As a result of the previous terms of Expressions (7) and (10) canceling each other, the output of the adder 56-2 is 2 Asin (α).

  In Equations (7) to (10), the preceding term is a frequency component of 2 (ff−f ′), and the latter term is a DC component that does not change with time. As a result of the inverter 54 and the adders 56-1 and 56-2 canceling each other out, the outputs of the adders 56-1 and 56-2 ((4) in FIG. 6) are as shown in FIG. As shown, the frequency component of 2 (ff ') does not appear, and only the DC component of the latter term remains.

  For this reason, the output of the low-pass filters 50-1 and 50-2 (the low-pass filters 50-1 and 50-2 have, for example, the transmittance characteristic indicated by the LPF in FIG. 7D) ( 6 (5)), only the DC component can be used as shown in FIG. 7 (E), and the low-pass filters 50-1 and 50-2 can freely set the desired optimum time constant and order. Can be selected.

  Since the time constant of the low-pass filter can be reduced, the DC output can quickly follow the change in the signal under test even when the signal under test changes in size. it can. Further, since it is not necessary to remove the frequency component of f + f 'by a low-pass filter, a low-order filter having a small order can be used with emphasis on the phase characteristics and the like of the filter. Further, even when the signal to be measured is modulated and the spectrum width is wide, the degree of freedom in selecting the low-pass filter can be increased.

  As in the second embodiment, the third embodiment also includes the frequency detection / setting unit 32, which controls the frequency of the reference signal in accordance with the frequency of the signal under measurement. The frequencies to be removed by -1, 48-2 can be kept constant.

  Note that FIG. 7 illustrates the case where f> f ′, but f <f ′ is also possible. (The same applies to the fourth embodiment described below.)

  When the frequency to be retained is higher than the frequency to be removed, other filters other than the low-pass filter such as a band-pass filter and a high-pass filter may be used instead of the band-elimination filters 48-1 and 48-2. Can be used. (The same applies to the fourth embodiment described below.)

  Further, also in the third embodiment, the lock-in amplifier according to the first embodiment, the lock-in amplifier according to the second embodiment, and the lock-in amplifier described in the background art. It is possible to freely select whether each of the above components is realized by an analog circuit, a digital circuit, or a digital operation means.

[Fourth Embodiment]

  In the fourth embodiment, the four phase detectors 44-3, 44-4, 44-5, 44-6, the inverter 54, and the two adders 56-1, 56 in the third embodiment are used. 2 shows a two-phase lock-in amplifier including a digital operation unit 64 instead of -2. The digital operation unit 64 is an example of a second phase detector, and includes four phase detectors 44-3, 44-4, 44-5, 44-6, an inverter 54, and two adders 56-1. , 56-2, that is, the function of converting the frequency component of ff ′ into the DC component without generating the frequency component of 2 (ff ′) by digital operation.

  FIG. 8 shows an example of the lock-in amplifier according to the fourth embodiment. 8, the same parts as those in FIG. 6 are denoted by the same reference numerals.

  Until the signal input passes through the phase detectors 44-1 and 44-2 to generate the ff 'frequency component in the output of the band elimination filters 48-1 and 48-2, the third embodiment shown in FIG. And the description is omitted. (1) to (5) in FIG. 8 correspond to (1) to (5) in FIG. 6 and FIGS. 7 (A) to 7 (E), respectively. 7 is the same as the operation shown in FIG.

  The input signal of the digital operation unit 64 on the band elimination filter 48-1 side is X, and the input signal of the digital operation unit 64 on the band elimination filter 48-2 side is Y.

  Here, the inputs to the digital operation unit 64, X and Y, are all digital signals of the frequency f-f '. When the signal under measurement is given as an analog signal, an A / D converter is provided between the signal input and the input of the digital operation unit 64, and the A / D converter may convert the analog signal into a digital signal. .

  The input signal P of the digital operation unit 64 on the reference signal side is a digital signal indicating the phase of the frequency f-f ', and has a range of, for example, ± 180 degrees. (Other ranges, such as 0 to 360 degrees, may be taken.)

  Both outputs of the digital operation unit 64 are digital signals. When the output of the lock-in amplifier 62 is an analog signal, a D / A converter is provided between the output of the digital operation unit 64 and the DC output (first DC output and second DC output). A digital signal may be converted into an analog signal by the D / A converter.

  Assuming that the phase of the frequency component of f-f 'at time t is ([omega]-[omega]') t, a signal corresponding to this phase is given to the input signal P of the digital operation unit 64 on the reference signal side. Here, (ω−ω ′) = 2π (ff−f ′).

  In order to convert the inputs X and Y of the digital operation unit 64 of the frequency f-f 'into DC components, the phase at the time t is rotated by-(?-?') T. (By giving − (ω−ω ′) t as the input signal P, positive / negative sign conversion can be omitted.)

  In the fourth embodiment, a CORDIC (Coordinate Rotary Digital Computer) method will be described below as a preferred example of the digital operation unit 64 that performs this phase rotation.

  In this method, the following Expressions (11) to (13) are regenerated so that the phase φ based on the input signals X and Y of the digital operation unit 64 at a certain time t approaches − (ω−ω ′) t. The frequency component of ff ′ is converted into a DC component by rotating the phase of the frequency component of ff ′ using the equation.

X _{i + 1} = X _i [− / +] (2 ⁻ⁱ × Y _i ) (11)
Y _{i + 1} = (2− ⁱ × X _i ) [+/−] Y _i (12)
φ _{i + 1} = φ _i [+/-] tan ^-1 (2- ⁱ ) (13)

  In Expressions (11) to (13), i is the number of repetitions (the number of iterations). When N operations are repeated, the expression (11) is changed while changing i from 0 to (N−1). -Repeat the calculation of Expression (13).

Here, depending on the relationship between φ _i and − (ω−ω ′) t at a certain i, Xi _{+ 1} , Yi _{+ 1} , and φi _{+ 1} in Equations (11) to (13) when Equation (13) are obtained. +/-] and [-/ +] are handled as follows.

When φ _i ≧ − (ω−ω ′) t, [+/−] is “+” and [− / +] is “−”.

When φ _i <− (ω−ω ′) t, [+/−] is “−” and [− / +] is “+”.

  When Expressions (11) to (13) are repeated under this rule, the phase φ approaches − (ω−ω ′) t.

Input signal X of the digital arithmetic unit 64 at a certain time t, and Y, respectively X _0, Y _0, When ^{_{φ 0 = tan -1 (Y 0}} / X 0), the initial equations (11) to Equation (13) The value (i = 0) is as shown in the following equations (11 ′) to (13 ′).

X ₁ = X ₀ [− / +] Y ₀ (11 ′)
Y ₁ = X ₀ [+/-] Y ₀ (12 ′)
φ ₁ = φ ₀ [+/-] tan ^-1 (1) (13 ′)
(In the equation (13 ′), tan ⁻¹ (1) is 45 degrees.)

Here, [+/−] and [− / +] in Expressions (11 ′) to (13 ′) are handled as follows according to the relationship between φ ₀ and − (ω−ω ′) t.

When φ ₀ ≧ − (ω−ω ′) t, [+/−] is “+” and [− / +] is “−”.

When φ ₀ <− (ω−ω ′) t, [+/−] is “−” and [− / +] is “+”.

When the formulas (11 ′) to (13 ′) are set as initial values (i = 0), and the formulas (11) to (13) are repeated from 1 to (N−1), X _N is finally obtained. Y _N is obtained. This is set as an output signal ((4) in FIG. 8) of the digital operation unit 64 at time t, and the next sample of the input digital signal (X, Y, P) of the digital operation unit 64 is waited.

X _N is a via a low-pass filter 50-1, the first DC output (X Output). Y _N becomes the second DC output (Y output) via the low-pass filter 50-2.

  The number of operations N is determined based on the sampling time of the input digital signal supplied to the digital operation unit 64, the operation speed, and the required operation accuracy.

  First, considering how many times Equations (11) to (13) can be repeated between the time when the digital signal at time t is given and the next time t ′ after one sampling time, Decide N. As an example, if the sampling time of the digital signal is 2 [microseconds] and it takes 100 [nanoseconds] for each operation of Expressions (11) to (13), N is theoretically 20 at the maximum. Actually, N is set to 19 or less in consideration of the pre-processing and post-processing of the calculation.

If N = 6, tan ^-1 (2 ^-6 ) ≒ 0.895 degrees, so that an accuracy of ± 1 degree or more can be obtained, and if N = 10, tan ^-1 (2 ^-10 ) ≒ Since it is 0.0560 degrees, an accuracy of ± 0.1 degrees or more can be obtained. If N = 13, tan ⁻¹ (2 ⁻¹³ ) ≒ 0.00699 degrees, and therefore ± 0.01 degrees The above accuracy can be obtained, and if N = 16, tan ⁻¹ (2 ⁻¹⁶ ) ≒ 0.0000874 degrees, so that an accuracy of ± 0.001 degrees or more can be obtained. The number of operations N is set in consideration of the required accuracy. If the required calculation accuracy cannot be obtained within the sampling time, a higher-speed digital circuit or digital calculation means may be used. Alternatively, by increasing the sampling time, N may be increased to increase the accuracy.

  In the equations (11) to (13) based on the CORDIC method, the rotatable phase is up to ± 90 degrees. Therefore, when − (ω−ω ′) t at a certain time t exceeds the range of ± 90 degrees, the following conversion processing of ± 90 degrees or 180 degrees is used in combination with the CORDIC method.

  (Conversion process of +90 degrees) In order to convert the phase by +90 degrees, (X, Y) = (− Y, X). That is, -Y before conversion is set to X after conversion, and X before conversion is set to Y after conversion.

  (-90 degree conversion process) In order to convert the phase by -90 degrees, (X, Y) = (Y, -X). That is, Y before conversion is set to X after conversion, and -X before conversion is set to Y after conversion.

  (180 degree conversion process) In order to convert the phase by 180 degrees, the positive and negative signs of each of X and Y are inverted.

  As an example, when − (ω−ω ′) t at a certain time t is 120 degrees, that is, when it is necessary to rotate the phase by 120 degrees, for example, conversion of ± 90 degrees or 180 degrees is performed as described below. The processing can be realized in combination.

  1. After subtracting 90 degrees from the required phase of 120 degrees to obtain +30 degrees, the phase is rotated by +30 degrees by the CORDIC method, and then the phase is further converted by +90 degrees.

  2. By subtracting 90 degrees from the required phase of 120 degrees to obtain +30 degrees, the phase is converted by +90 degrees in advance, and the phase is further rotated by +30 degrees by the CORDIC method.

  3. After subtracting 180 degrees from the required phase of 120 degrees, -60 degrees are obtained. After the phase is rotated by -60 degrees by the CORDIC method, the phase is further converted by 180 degrees.

  4. By subtracting 180 degrees from the required phase of 120 degrees to obtain -60 degrees, the phase is converted 180 degrees in advance, and the phase is further rotated by -60 degrees by the CORDIC method.

In Equations (11) to (13), the process of multiplying by 2- ⁱ can be realized by bit shifting in digital arithmetic of a fixed point. According to the process of multiplying 2- ⁱ by bit shift, the amount of calculation can be reduced. In the floating-point digital operation, when the exponent is expressed by the factorial of 2, a process of multiplying by 2- ⁱ by addition and subtraction of the exponent can be realized. The amount of calculation can be reduced by performing the process of multiplying 2- ⁱ by addition and subtraction of the exponent part.

In the operation of tan ^-1 (2- ⁱ ), for example, each value of tan ^-1 (2- ⁱ ) for i = 0 to N-1 is stored in the storage unit as a constant, and the stored value By referring to. By performing such a calculation, the amount of calculation can be reduced. The storage unit may be provided inside or outside the digital operation unit 64.

  In the CORDIC method, the amount of calculation can be reduced in this way to reduce the frequency conversion processing time. Therefore, even if a digital circuit or digital calculation means with a low speed calculation is used, high-precision frequency conversion can be performed. Can be performed.

  Also, in the fourth embodiment, similarly to the lock-in amplifiers according to the first to third embodiments and the lock-in amplifier described in the background art, each of the components other than the digital operation unit is replaced by an analog circuit. , Digital circuit, or digital operation means can be freely selected.

As described above, the embodiments of the present invention have been described. However, the present invention is not limited to the above description, and is based on the gist of the invention described in the claims or disclosed in the specification. It goes without saying that various modifications and changes can be made by those skilled in the art, and such modifications and changes are included in the scope of the present invention.

2, 22, 42, 62 Lock-in amplifiers 4, 4-1, 4-2, 24-1, 24-2, 44-1, 44-2, 44-3, 44-4, 44-5, 44- 6 phase detector 6, 26-1, 26-2, 46-1, 46-2 reference signal generator 8, 8-1, 8-2, 28, 48-1, 48-2 band elimination filter 10, 10 -1, 10-2, 30, 50-1, 50-2 Low-pass filter 32 Frequency detection / setting unit 54 Inverter 56-1, 56-2 Adder 64 Digital operation unit

Claims (5)

A lock-in amplifier including a phase detection unit and a low-pass filter,
Excluding a low-pass filter, further comprising at least one filter,
The phase detecting means includes a first phase detecting means and a second phase detecting means,
The first phase detector converts the signal under test input to the first phase detector into a plurality of frequency components,
A lock-in amplifier, wherein at least one of the plurality of converted frequency components is removed by the filter, and the remaining frequency components are converted to direct current by the second phase detection means.   The lock-in amplifier according to claim 1, wherein the filter is one of a band elimination filter, a band-pass filter, and a high-pass filter.   Further, a frequency of the signal under test inputted to the first phase detection means is detected, and the first phase detection means and the second phase detection means are adjusted in accordance with the detected frequency of the signal under measurement. The lock-in amplifier according to claim 1, further comprising a frequency detection / setting unit configured to control a frequency of a reference signal provided to each of the lock-in amplifiers.   The lock according to any one of claims 1 to 3, wherein a digital circuit or a digital operation means is used for a part or all of the phase detection means, the low-pass filter, and the filter. In amp. 5. The lock-in amplifier according to claim 3, wherein the phase detector converts part or all of the frequency by a digital circuit or a digital operation unit using a CORDIC method.

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