JP2020027825A - Semiconductor device and manufacture method of the semiconductor device - Google Patents

Abstract

To provide a semiconductor device having a large ON-current and an excellent reliability.SOLUTION: In a semiconductor device, a transistor 200 includes: an oxidation 230b on an insulation 224; oxidations 243a and 243b on the oxidation 230b; a conductor 242a on the oxidation 243a; a conductor 242b on the oxidation 243b; an oxidation 230c on the oxidation 230b; an insulation 250 on the oxidation 230c; a conductor 260 on the insulation 250; an insulation 272 on the conductor 260; and an insulator 273 on the insulation 272. The oxidation 230c contacts with an upper surface of the oxidation 230b, each side surface of the conductors 242a and 242b; and each side surface of the oxidations 243a and 243b, respectively. The oxidation 230b includes In, an element M, and Zn, and the oxidation 230c includes at least one of a construction element held by the oxidation 230b. Each of the oxidations 243a and 243b has an element M, and has a region of which a concentration of the element M is higher than that of the oxidation 230b.SELECTED DRAWING: Figure 1

Description

  One embodiment of the present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Alternatively, one embodiment of the present invention relates to a semiconductor wafer, a module, and an electronic device.

  Note that a semiconductor device in this specification and the like refers to any device that can function by utilizing semiconductor characteristics. A semiconductor device such as a transistor, a semiconductor circuit, an arithmetic device, and a storage device are one embodiment of a semiconductor device. A display device (a liquid crystal display device, a light-emitting display device, or the like), a projection device, a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like sometimes includes a semiconductor device. .

  Note that one embodiment of the present invention is not limited to the above technical field. One embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacturer, or a composition (composition of matter).

  As a semiconductor thin film applicable to a transistor, a silicon-based semiconductor material is widely known, but an oxide semiconductor is attracting attention as another material. As an oxide semiconductor, for example, not only a single metal oxide such as indium oxide and zinc oxide but also a multimetal oxide is known. Among oxides of multi-component metals, research on In-Ga-Zn oxide (hereinafter, also referred to as IGZO) has been actively conducted.

  Through research on IGZO, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline) structure that are neither single crystal nor amorphous in an oxide semiconductor have been found (see Non-Patent Documents 1 to 3). ). Non-Patent Documents 1 and 2 also disclose a technique for manufacturing a transistor using an oxide semiconductor having a CAAC structure. Further, Non-Patent Documents 4 and 5 show that even an oxide semiconductor having lower crystallinity than the CAAC structure and the nc structure has minute crystals.

  Further, a transistor using IGZO as an active layer has an extremely low off-state current (see Non-Patent Document 6), and an LSI and a display utilizing the characteristics have been reported (see Non-Patent Documents 7 and 8). .

S. Yamazaki et al. , "SID Symposium Digest of Technical Papers", 2012, volume 43, issue 1, p. 183-186 S. Yamazaki et al. , "Japanese Journal of Applied Physics", 2014, volume 53, Number 4S, p. 04ED18-1-04ED18-10 S. Ito et al. , “The Proceedings of AM-FPD'13 Digest of Technical Papers”, 2013, p. 151-154 S. Yamazaki et al. , "ECS Journal of Solid State Science and Technology", 2014, volume 3, issue 9, p. Q3012-Q3022 S. Yamazaki, "ECS Transactions", 2014, volume 64, issue 10, p. 155-164 K. Kato et al. , “Japanese Journal of Applied Physics”, 2012, volume 51, p. 021201-1-021201-7 S. Matsuda et al. , “2015 Symposium on VLSI Technology Digest of Technical Papers”, 2015, p. T216-T217 S. Amano et al. , "SID Symposium Digest of Technical Papers", 2010, volume 41, issue 1, p. 626-629

  An object of one embodiment of the present invention is to provide a highly reliable semiconductor device. Another object of one embodiment of the present invention is to provide a semiconductor device with high on-state current. Another object of one embodiment of the present invention is to provide a semiconductor device having high frequency characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device which can be miniaturized or highly integrated. Another object of one embodiment of the present invention is to provide a semiconductor device having favorable electric characteristics. Another object of one embodiment of the present invention is to provide a semiconductor device with high productivity.

  An object of one embodiment of the present invention is to provide a semiconductor device which can hold data for a long time. An object of one embodiment of the present invention is to provide a semiconductor device with high data writing speed. An object of one embodiment of the present invention is to provide a semiconductor device with high design flexibility. An object of one embodiment of the present invention is to provide a semiconductor device that can reduce power consumption. An object of one embodiment of the present invention is to provide a novel semiconductor device.

  Note that the description of these objects does not disturb the existence of other objects. Note that one embodiment of the present invention does not need to solve all of these problems. It should be noted that issues other than these are naturally evident from the description of the specification, drawings, claims, etc., and that other issues can be extracted from the description of the specifications, drawings, claims, etc. It is.

  According to one embodiment of the present invention, a first insulator is formed over a substrate, and a first oxide film, a second oxide film, and a first conductive film are sequentially formed over the first insulator. Processing the first oxide film, the second oxide film, and the first conductive film to form a first oxide, an oxide layer, and a conductor layer; A first insulating film and a second insulating film are sequentially formed to cover the conductor layer, and the first oxide is exposed to the oxide layer, the conductor layer, the first insulating film, and the second insulating film. Forming an opening to form a second oxide, a third oxide, a first conductor, a second conductor, a second insulator, and a third insulator; A third oxide film, a third insulating film, and a second conductive film are formed by forming a film, a third insulating film, and a second conductive film in this order, and performing a planarization process. Part of is exposed To form a fourth oxide, a fourth insulator, and a third conductor, perform a first heat treatment, perform a second heat treatment, and perform a fourth heat treatment on the third conductor. This is a method for manufacturing a semiconductor device in which an insulating film is formed.

  The first heat treatment is preferably performed in a nitrogen atmosphere at a temperature of higher than or equal to 300 ° C and lower than or equal to 450 ° C.

  It is preferable that the first heat treatment be performed for one hour or more.

  Further, the second heat treatment and the formation of the fourth insulating film are preferably performed sequentially under reduced pressure.

  Further, the fourth insulator preferably contains any one of aluminum oxide and silicon nitride.

  Further, the fourth insulator includes a first material and a second material, and the first material is located below the second material and is in contact with a lower surface of the second material. preferable.

  Further, it is preferable that the first material include aluminum oxide, the second material includes silicon nitride, and the second material be different from the first material.

  Further, the first to fourth oxides preferably contain In, an element M (M is Al, Ga, Y, or Sn), and Zn.

  Further, one embodiment of the present invention includes a first insulator, a first oxide over the first insulator, a second oxide and a third oxide over the first oxide, A first conductor on the second oxide, a second conductor on the third oxide, a fourth oxide on the first oxide, and a fourth conductor on the fourth oxide. A second insulator, a third conductor on the second insulator, a third insulator on the third conductor, and a fourth insulator on the third insulator. And the fourth oxide includes a top surface of the first oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the second oxide, and a side surface of the third oxide; Each of the first oxides has In, the element M (M is Al, Ga, Y, or Sn) and Zn, and the first oxide has a fourth oxide. A second oxide having at least one of the constituent elements, and a third oxide Products each have an element M, the second oxide and the third oxide, the concentration of the element M than the first oxide is a semiconductor device having a high region.

  Further, the third insulator preferably contains oxygen and aluminum, and the fourth insulator preferably contains nitrogen and silicon.

  According to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  Alternatively, a semiconductor device capable of holding data for a long period can be provided. Alternatively, a semiconductor device with high data writing speed can be provided. Alternatively, a semiconductor device with high design flexibility can be provided. Alternatively, a semiconductor device that can reduce power consumption can be provided. Alternatively, a novel semiconductor device can be provided.

  Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention does not need to have all of these effects. It should be noted that effects other than these are obvious from the description of the specification, drawings, claims, etc., and other effects can be extracted from the description of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 4A and 4B are a top view and a cross-sectional view of a semiconductor device according to one embodiment of the present invention. FIG. 3 is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 7A to 7C are a top view and cross-sectional views illustrating a method for manufacturing a semiconductor device according to one embodiment of the present invention. 4A and 4B illustrate an energy band structure of an oxide semiconductor. FIG. 4 is a schematic view illustrating oxidation of a conductor provided over an oxide semiconductor. FIG. 4 is a schematic view illustrating oxidation of a conductor provided over an oxide semiconductor. FIG. 4 is a schematic view illustrating oxidation of a conductor provided over an oxide semiconductor. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 13 is a cross-sectional view illustrating a structure of a memory device according to one embodiment of the present invention. FIG. 3 is a block diagram illustrating a configuration example of a storage device according to one embodiment of the present invention. FIG. 3 is a circuit diagram illustrating a configuration example of a memory device according to one embodiment of the present invention. FIG. 3 is a schematic view of a semiconductor device according to one embodiment of the present invention. FIG. 13 is a schematic diagram of a storage device according to one embodiment of the present invention. FIG. 13 illustrates an electronic device according to one embodiment of the present invention. 9 is a graph showing the carrier concentration of the oxide of the example. 9 is a graph showing the hydrogen concentration of the oxide of the example. FIG. 4 is a diagram illustrating a model in an initial state and a model in a final state. The figure explaining the change of energy.

  Hereinafter, embodiments will be described with reference to the drawings. However, it is easily understood by those skilled in the art that the embodiment can be implemented in many different modes, and that the mode and details can be variously changed without departing from the spirit and scope. You. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

  In the drawings, the size, the layer thickness, or the region is exaggerated for clarity in some cases. Therefore, it is not necessarily limited to the scale. The drawings schematically show ideal examples, and are not limited to the shapes and values shown in the drawings. For example, in an actual manufacturing process, a layer or a resist mask may be unintentionally reduced due to processing such as etching, but may not be reflected in the drawings for easy understanding. In the drawings, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description of such portions is not repeated in some cases. Further, when referring to the same function, the hatch pattern is the same, and there is a case where no particular reference numeral is given.

  In addition, in some cases, particularly in a top view (also referred to as a “plan view”) or a perspective view, description of some components is omitted in order to facilitate understanding of the invention. In addition, some hidden lines and the like may be omitted.

  In this specification and the like, ordinal numbers given as first, second, and the like are used for convenience, and do not indicate the order of steps or the order of lamination. Therefore, for example, the description can be made by appropriately replacing “first” with “second” or “third”. In addition, ordinal numbers described in this specification and the like do not always coincide with ordinal numbers used for specifying one embodiment of the present invention.

  Further, in this specification and the like, words indicating an arrangement such as "over" and "under" are used for convenience in describing the positional relationship between components with reference to drawings. Further, the positional relationship between the components changes as appropriate according to the direction in which each component is described. Therefore, the present invention is not limited to the words and phrases described in the specification, and can be appropriately paraphrased according to the situation.

  For example, in this specification and the like, when it is explicitly described that X and Y are connected, the case where X and Y are electrically connected, and the case where X and Y function It is assumed that a case in which X and Y are directly connected and a case in which X and Y are directly connected are disclosed in this specification and the like. Therefore, the connection relation is not limited to the predetermined connection relation, for example, the connection relation shown in the figure or the text, and it is assumed that anything other than the connection relation shown in the figure or the text is also described in the figure or the text.

  Here, X and Y are objects (for example, an apparatus, an element, a circuit, a wiring, an electrode, a terminal, a conductive film, a layer, and the like).

  In addition, the functions of the source and the drain may be switched when transistors with different polarities are used or when the direction of current changes in circuit operation. For this reason, in this specification and the like, the terms of source and drain may be used interchangeably.

  Note that in this specification and the like, depending on the structure of a transistor, a channel width in a region where a channel is actually formed (a channel formation region) (hereinafter, also referred to as an “effective channel width”) may be different from a top view of the transistor. The indicated channel width (hereinafter, also referred to as “apparent channel width”) may be different. For example, when the gate covers the side surface of the semiconductor, the effective channel width becomes larger than the apparent channel width, and the effect may not be negligible. For example, in a transistor which is minute and covers a side surface of a semiconductor, the proportion of a channel formation region formed on the side surface of the semiconductor may be large. In that case, the effective channel width is larger than the apparent channel width.

  In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known. Therefore, when the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

  In this specification, a simple term "channel width" may refer to an apparent channel width. Alternatively, in this specification, a simple term "channel width" may refer to an effective channel width. The values of the channel length, the channel width, the effective channel width, the apparent channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

  Note that a semiconductor impurity refers to, for example, elements other than the main components of the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be regarded as an impurity. When the impurity is contained, for example, the DOS (Density of States) of the semiconductor may be increased, or the crystallinity may be reduced. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. And transition metals other than the main components such as hydrogen, lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, water may function as an impurity in some cases. In the case of an oxide semiconductor, oxygen vacancies may be formed by entry of impurities, for example. In the case where the semiconductor is silicon, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, and a Group 15 element other than oxygen and hydrogen.

  Note that in this specification and the like, silicon oxynitride has a higher oxygen content than nitrogen as its composition. In addition, silicon nitride oxide has a higher nitrogen content than oxygen as its composition.

  In this specification and the like, the term "insulator" can be referred to as an insulating film or an insulating layer. Further, the term “conductor” can be referred to as a conductive film or a conductive layer. Further, the term “semiconductor” can be referred to as a semiconductor film or a semiconductor layer.

  In this specification and the like, “parallel” refers to a state where two straight lines are arranged at an angle of −10 degrees or more and 10 degrees or less. Therefore, a case where the angle is −5 degrees or more and 5 degrees or less is also included. The term “substantially parallel” refers to a state in which two straight lines are arranged at an angle of −30 degrees or more and 30 degrees or less. “Vertical” means a state in which two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, a case where the angle is 85 degrees or more and 95 degrees or less is also included. Further, “substantially perpendicular” refers to a state in which two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

  Note that in this specification, a barrier film refers to a film having a function of suppressing transmission of impurities such as water and hydrogen and oxygen, and when the barrier film has conductivity, the barrier film is referred to as a conductive barrier film. May be called.

  In this specification and the like, a metal oxide is a metal oxide in a broad sense. Metal oxide is classified into an oxide insulator, an oxide conductor (including a transparent oxide conductor), an oxide semiconductor (also referred to as an oxide semiconductor, or simply OS), and the like. For example, in the case where a metal oxide is used for a semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor in some cases. That is, the term “OS FET” or “OS transistor” can be referred to as a transistor including an oxide or an oxide semiconductor.

In this specification and the like, normally-off means that when a potential is not applied to a gate or a ground potential is applied to a gate, a current per 1 μm of a channel width flowing through a transistor is 1 × 10 ⁻²⁰ at room temperature. A or lower, 1 × 10 ⁻¹⁸ A or lower at 85 ° C., or 1 × 10 ⁻¹⁶ A or lower at 125 ° C.

(Embodiment 1)
Hereinafter, an example of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described. Note that in one embodiment of the present invention, a semiconductor device with favorable reliability can be provided by performing heat treatment under a specific condition or a specific range in a transistor manufacturing process. Note that the heat treatment in the transistor manufacturing process will be described in detail in a method for manufacturing a semiconductor device described later.

<Configuration example of semiconductor device>
FIGS. 1A, 1B, and 1C are a top view and a cross-sectional view of a transistor 200 according to one embodiment of the present invention and the periphery of the transistor 200. FIG.

  FIG. 1A is a top view of a semiconductor device including the transistor 200. FIGS. 1B and 1C are cross-sectional views of the semiconductor device. Here, FIG. 1B is a cross-sectional view of a portion indicated by a dashed line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in a channel length direction. FIG. 1C is a cross-sectional view of a portion indicated by a dashed-dotted line A3-A4 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that in the top view of FIG. 1A, some components are not illustrated for clarity.

  The semiconductor device of one embodiment of the present invention includes the insulator 212 over the substrate (not illustrated), the insulator 214 over the insulator 212, the transistor 200 over the insulator 214, and the insulator 280 over the transistor 200. , An insulator 282 on the insulator 280, an insulator 283 on the insulator 282, an insulator 274 on the insulator 283, and an insulator 281 on the insulator 274. The insulator 212, the insulator 214, the insulator 280, the insulator 282, the insulator 283, the insulator 274, and the insulator 281 function as an interlayer film. Further, the semiconductor device includes a conductor 240 (a conductor 240a and a conductor 240b) which is electrically connected to the transistor 200 and functions as a plug. Note that the insulator 241 (the insulator 241a and the insulator 241b) is provided in contact with a side surface of the conductor 240 functioning as a plug. In addition, a conductor 246 (a conductor 246a and a conductor 246b) which is electrically connected to the conductor 240 and functions as a wiring is provided over the insulator 281 and the conductor 240.

  Further, an insulator 241a is provided in contact with the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 283, the insulator 274, and the inner wall of the opening of the insulator 281. A first conductor of the body 240a is provided, and a second conductor of the conductor 240a is provided further inside. An insulator 241b is provided in contact with the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 283, the insulator 274, and the inner wall of the opening of the insulator 281. A first conductor of the body 240b is provided, and a second conductor of the conductor 240b is further provided inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be approximately equal. Note that although the transistor 200 has a structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked, the present invention is not limited to this. For example, a structure in which the conductor 240 is provided as a single layer or a stacked structure of three or more layers may be employed. When the structure has a laminated structure, ordinal numbers may be given in the order of formation to distinguish them.

[Transistor 200]
As illustrated in FIG. 1, the transistor 200 includes an insulator 216 over an insulator 214, a conductor 205 (a conductor 205 a and a conductor 205 b) which is embedded in the insulator 216, An insulator 222 on the conductor 205, an insulator 224 on the insulator 222, an oxide 230a on the insulator 224, an oxide 230b on the oxide 230a, and an oxide on the oxide 230b 243a and an oxide 243b; a conductor 242a on the oxide 243a; a conductor 242b on the oxide 243b; an oxide 230c on the oxide 230b; an insulator 250 on the oxide 230c; A conductor 260 (the conductor 260a and the conductor 260b) which is located above and overlaps with the oxide 230c; a part of the top surface of the insulator 224; An insulator 272 in contact with the side surface, the side surface of the oxide 230b, the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, the upper surface of the conductor 242a, the side surface of the conductor 242b, and the upper surface of the conductor 242b; , An insulator 273 on the insulator 272. The oxide 230c is in contact with the side surface of the oxide 243a, the side surface of the oxide 243b, the side surface of the conductor 242a, and the side surface of the conductor 242b. The conductor 260 has a conductor 260a and a conductor 260b, and the conductor 260a is arranged so as to cover the bottom and side surfaces of the conductor 260b. Here, as shown in FIG. 1B, the upper surface of the conductor 260 is disposed so as to substantially coincide with the upper surface of the insulator 250 and the upper surface of the oxide 230c. In addition, the insulator 282 is in contact with the top surfaces of the conductor 260, the oxide 230c, the insulator 250, and the insulator 280.

  Further, the insulator 222, the insulator 272, the insulator 273, the insulator 282, and the insulator 283 preferably have a function of suppressing at least one diffusion of hydrogen (eg, a hydrogen atom or a hydrogen molecule). Further, the insulator 222, the insulator 272, the insulator 273, and the insulator 282 preferably have a function of suppressing diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules). For example, the insulator 222, the insulator 272, the insulator 273, and the insulator 282 each preferably have lower permeability to one or both of oxygen and hydrogen than the insulator 224. The insulator 222, the insulator 272, the insulator 273, the insulator 282, and the insulator 283 each preferably have lower permeability to one or both of oxygen and hydrogen than the insulator 250. Each of the insulator 222, the insulator 272, the insulator 273, the insulator 282, and the insulator 283 preferably has lower permeability to one or both of oxygen and hydrogen than the insulator 280.

  As illustrated in FIG. 1B, the insulator 272 includes an upper surface and a side surface of the conductor 242a, an upper surface and a side surface of the conductor 242b, a side surface of the oxide 243a, a side surface of the oxide 243b, a side surface of the oxide 230a, and an oxide. It is preferable to contact the side surface of the object 230b and the upper surface of the insulator 224. It is preferable that the insulator 273 be provided in contact with the insulator 272. Thus, the insulator 280 is separated from the insulator 224 and the oxide 230 by the insulator 272 and the insulator 273.

  The oxide 230 includes an oxide 230a over the insulator 224, an oxide 230b over the oxide 230a, and an oxide 230c which is provided over the oxide 230b and at least part of which is in contact with the top surface of the oxide 230b. Is preferable.

  Note that in the transistor 200, a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 230c are stacked in and around the channel formation region is shown; however, the present invention is not limited to this. . For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230b and the oxide 230a, a two-layer structure of the oxide 230b and the oxide 230c, or a stacked structure of four or more layers may be provided. In the transistor 200, the conductor 260 is illustrated as having a two-layer structure, but the present invention is not limited to this. For example, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

  Here, the conductor 260 functions as a gate of the transistor, and the conductor 242a and the conductor 242b each function as a source electrode or a drain electrode. In the transistor 200, the conductor 260 functioning as a gate is formed in a self-aligned manner so as to fill an opening formed by the insulator 280 and the like. By forming the conductor 260 in this manner, the conductor 260 can be reliably disposed in a region between the conductor 242a and the conductor 242b without alignment.

  In the transistor 200, a metal oxide serving as an oxide semiconductor (hereinafter, also referred to as an oxide semiconductor) is used for the oxide 230 including the channel formation region (the oxide 230a, the oxide 230b, and the oxide 230c). Is preferred.

  The transistor 200 including an oxide semiconductor in a channel formation region has extremely low leakage current (off current) in a non-conduction state; thus, a semiconductor device with low power consumption can be provided. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for the transistor 200 included in a highly integrated semiconductor device.

  For example, as the oxide 230, an In-M-Zn oxide (element M is aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium , Neodymium, hafnium, tantalum, tungsten, or magnesium, or a plurality thereof). In particular, as the element M, aluminum, gallium, yttrium, or tin is preferably used. Further, as the oxide 230, an In—Ga oxide or an In—Zn oxide may be used.

  The oxide 230 includes an oxide 230a, an oxide 230b over the oxide 230a, and an oxide 230c over the oxide 230b. When the oxide 230a is provided below the oxide 230b, diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b can be suppressed. In addition, when the oxide 230c is provided over the oxide 230b, diffusion of impurities into the oxide 230b from a structure formed above the oxide 230c can be suppressed.

  Note that the oxide 230 preferably has a stacked structure of oxides having different atomic ratios of metal atoms. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is larger than that in the metal oxide used for the oxide 230b. Is preferred. Further, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than that in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than that in the metal oxide used for the oxide 230a. As the oxide 230c, a metal oxide that can be used for the oxide 230a or the oxide 230b can be used.

  Further, the oxide 230b preferably has crystallinity. For example, it is preferable to use a CAAC-OS (c-axis aligned crystal oxide semiconductor) described later. An oxide having crystallinity, such as a CAAC-OS, has a high density of impurities and defects (such as oxygen vacancies), high crystallinity, and a dense structure. Thus, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. Thus, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable at a high temperature (a so-called thermal budget) in a manufacturing process.

  Further, it is preferable that the energy at the bottom of the conduction band of the oxide 230a and the oxide 230c be higher than the energy of the bottom of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c be smaller than the electron affinity of the oxide 230b.

  Here, at the junction of the oxide 230a, the oxide 230b, and the oxide 230c, the energy level at the bottom of the conduction band gradually changes. In other words, it can be said that the energy level at the bottom of the conduction band at the junction of the oxide 230a, the oxide 230b, and the oxide 230c changes continuously or forms a continuous junction. In order to achieve this, the defect state density of a mixed layer formed at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c may be reduced.

  Specifically, a metal oxide of In: Ga: Zn = 1: 3: 4 [atomic ratio] or 1: 1: 0.5 [atomic ratio] may be used as the oxide 230a. As the oxide 230b, a metal oxide of In: Ga: Zn = 4: 2: 3 [atomic ratio] or 1: 1: 1 [atomic ratio] may be used. Further, as the oxide 230c, In: Ga: Zn = 1: 3: 4 [atomic ratio], Ga: Zn = 2: 1 [atomic ratio], or Ga: Zn = 2: 5 [atomic ratio] May be used. As a specific example in the case where the oxide 230c has a stacked structure, In: Ga: Zn = 4: 2: 3 [atomic ratio] and In: Ga: Zn = 1: 3: 4 [atomic ratio] , Ga: Zn = 2: 1 [atomic ratio] and In: Ga: Zn = 4: 2: 3 [atomic ratio], Ga: Zn = 2: 5 [atomic] Number ratio] and a stacked structure of In: Ga: Zn = 4: 2: 3 [atomic ratio] and a stacked structure of gallium oxide and In: Ga: Zn = 4: 2: 3 [atomic ratio]. And the like.

  At this time, the main path of the carriers is the oxide 230b. With the above structure of the oxides 230a and 230c, the density of defect states at the interface between the oxide 230a and the oxide 230b and the interface between the oxide 230b and the oxide 230c can be reduced. Therefore, the influence of carrier scattering due to interface scattering is small, and the transistor 200 can have high on-state current and high frequency characteristics.

  As the oxide 230, a metal oxide functioning as an oxide semiconductor is preferably used. For example, it is preferable to use one having an energy gap of 2 eV or more, preferably 2.5 eV or more. By using a metal oxide with a large energy gap as described above, the off-state current of the transistor can be reduced. With the use of such a transistor, a semiconductor device with low power consumption can be provided.

  As shown in FIG. 13, the electron affinity or the energy level Ec at the bottom of the conduction band can be obtained from the ionization potential Ip, which is the difference between the vacuum level and the energy Ev at the top of the valence band, and the energy gap Eg. The ionization potential Ip can be measured, for example, using an ultraviolet photoelectron spectroscopy (UPS) device. The energy gap Eg can be measured using, for example, a spectroscopic ellipsometer.

  Further, in a transistor including an oxide semiconductor, when impurities and oxygen vacancies are present in a channel formation region in the oxide semiconductor, electric characteristics are likely to be changed and reliability may be deteriorated in some cases. Further, when oxygen vacancies are contained in a channel formation region in an oxide semiconductor, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that oxygen vacancies in the channel formation region be reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the insulator 250 or the like to compensate for oxygen vacancies. Accordingly, it is possible to provide a transistor in which fluctuation in electric characteristics is suppressed, stable electric characteristics are improved, and reliability is improved.

  Further, in the case where the conductor arranged in the vicinity of the oxide semiconductor is made of a metal or an alloy, the conductor may be oxidized by oxygen atoms included in the oxide semiconductor. When the conductivity of the conductor decreases due to oxidation, the probability of causing a variation in electrical characteristics of the semiconductor device and a decrease in reliability is high.

  Here, an oxidation reaction of a metal or an alloy in contact with the oxide semiconductor by an oxygen atom included in the oxide semiconductor is described with reference to FIGS. Hereinafter, an oxidation reaction in the case where an In-Ga-Zn oxide is used as an oxide semiconductor and tantalum nitride is used as a conductor will be specifically described.

  FIG. 14A illustrates a region near an interface in a cross section of a stacked body of the oxide semiconductor 10 including In-Ga-Zn oxide and the conductor 20 including tantalum nitride. Note that, in the drawing, black circles shown in each structure indicate oxygen atoms. White circles shown in the oxide semiconductor 10 indicate oxygen vacancies generated in the oxide semiconductor.

  FIG. 14B shows an initial process of an oxidation reaction of the conductor 20. Note that, in the conductor 20, a region where oxygen forms a solid solution at a low concentration is shown as an oxygen solid solution region 22. FIG. 14C shows a growth process of the oxide 30 generated by the oxidation reaction of the conductor 20.

  First, an initial process of the oxidation reaction of the conductor 20 will be described with reference to FIG. The arrows in the figure indicate the moving direction of oxygen atoms. In the initial stage of the oxidation reaction of the conductor 20, it is assumed that tantalum metal atoms at the interface of the conductor 20 and oxygen ions at the interface of the oxide semiconductor 10 interact.

  As shown in FIG. 15A, when oxygen ions indicated by black circles in the figure reach the interface between the oxide semiconductor 10 and the conductor 20, the oxygen ions are adsorbed on tantalum metal atoms at the interface of the conductor 20.

  As shown in FIG. 15B, when heat treatment is performed in a state where oxygen ions are adsorbed on metal atomic tantalum, the oxygen ions diffuse into the conductor 20 and form oxygen solid solution inside the tantalum nitride. A region 22 is formed (see FIG. 15B). When the oxygen solid solution region 22 is formed, the oxidation reaction has not yet occurred, and the oxygen ions are in a solid solution state inside the conductor 20 as impurities. In addition, diffusion of oxygen ions into the conductor 20 may temporarily cause oxygen vacancies at the interface of the oxide semiconductor 10.

  It is assumed that the capacity of the conductor 20 to dissolve oxygen in a solid solution depends on the crystallinity or the density of the conductor 20. Oxygen ions at the interface of the oxide semiconductor 10 are dissolved in the conductor 20 so that oxygen vacancies generated at the interface of the oxide semiconductor 10 are filled with oxygen atoms inside the oxide semiconductor 10. (See FIG. 15C).

  By repeating the processes shown in FIGS. 15A to 15C, the oxygen concentration in the oxygen-solid solution region 22 increases. Here, when the solid solution of oxygen in the oxygen solid solution region 22 is saturated, the oxidation of tantalum metal atoms in the oxygen solid solution region 22 starts. Therefore, as illustrated in FIG. 15D, the oxide 30 containing tantalum oxide is formed between the oxide semiconductor 10 and the conductor 20.

  It is known that nucleation of an oxide generally occurs in the initial stage of a metal oxidation reaction. On the other hand, since the heat history in the manufacturing process of the semiconductor device using an oxide semiconductor is relatively low, an amorphous oxide thin film is formed at the interface between the oxide semiconductor 10 and the conductor 20. It is supposed to be.

  Subsequently, a growth process of the oxide 30 generated between the oxide semiconductor 10 and the conductor 20 will be described with reference to FIGS. When the oxide 30 is generated, the interface between the oxide 30 and the oxide semiconductor 10 is depleted of oxygen, so that the concentration of oxygen vacancies is high. That is, it is considered that a concentration gradient of oxygen deficiency occurs in the oxide semiconductor 10.

  Therefore, as illustrated in FIGS. 16A to 16C, in the oxide semiconductor 10, oxygen ions in the oxide semiconductor 10 diffuse in order to make the concentration of oxygen vacancies uniform. It is considered that the oxygen ions reach the interface with the oxide 30 (see FIG. 16A). Further, the reached oxygen ions are used for a growth reaction of tantalum oxide included in the oxide 30, and the oxide 30 is increased in film thickness (see FIGS. 16B and 16C).

  In the oxide 30 having tantalum oxide, the oxidation reaction generally depends on the diffusion rates of metal and oxygen ions in the thin film of the oxide 30 when the influence of interface defects is not considered.

  Therefore, a diffusion of oxygen concentration occurs inside the oxide semiconductor 10 and the oxide 30 due to diffusion of oxygen ions. In that case, it can be estimated that the diffusion rate of oxygen ions in the oxide 30 is a factor that determines the growth rate of tantalum oxide in the oxide 30. In the case where the diffusion species is oxygen ions, the diffusion species diffuses in the tantalum oxide of the oxide 30 and reaches the interface between the oxide 30 and the conductor 20, thereby generating new tantalum oxide and increasing the amount of the oxide 30. It is believed that a film occurs. In the growth process of this oxidation reaction, it is considered that the oxygen-solid-solution region 22 of the conductor 20 expands into the conductor 20.

  In order to suppress the above-described oxidation reaction of the conductor, the transistor 200 of one embodiment of the present invention includes an oxide 230b and a conductor which functions as a source electrode or a drain electrode as illustrated in FIG. An oxide 243 (an oxide 243a and an oxide 243b) is provided between the gate electrode 242 and the conductor 242a and the conductor 242b. Since the conductor 242 is not in contact with the oxide 230, the conductor 242 can suppress absorption of oxygen of the oxide 230. That is, by preventing the conductor 242 from being oxidized, a decrease in the conductivity of the conductor 242 can be suppressed. Therefore, the oxide 243 preferably has a function of suppressing oxidation of the conductor 242.

  Therefore, the oxide 243 preferably has a function of suppressing transmission of oxygen. By disposing the oxide 243 having a function of suppressing oxygen permeation between the conductor 242 functioning as a source electrode and a drain electrode and the oxide 230b, the electric potential between the conductor 242 and the oxide 230b can be increased. This is preferable because the resistance is reduced. With such a structure, electric characteristics of the transistor 200 and reliability of the transistor 200 can be improved.

  As the oxide 243, a metal oxide containing the element M may be used. In particular, as the element M, aluminum, gallium, yttrium, or tin is preferably used. The oxide 243 preferably has a higher concentration of the element M than the oxide 230b. Gallium oxide may be used as the oxide 243. Further, as the oxide 243, a metal oxide such as an In-M-Zn oxide may be used. Specifically, in the metal oxide used for the oxide 243, the atomic ratio of the element M to In is preferably larger than that in the metal oxide used for the oxide 230b. The thickness of the oxide 243 is preferably from 0.5 nm to 5 nm, more preferably from 1 nm to 3 nm. Further, the oxide 243 preferably has crystallinity. When the oxide 243 has crystallinity, release of oxygen in the oxide 230 can be favorably suppressed. For example, in the case where the oxide 243 has a crystal structure such as a hexagonal structure, release of oxygen in the oxide 230 can be suppressed in some cases.

  As shown in FIGS. 1B and 1C, the transistor 200 of one embodiment of the present invention has a structure in which the insulator 282 and the insulator 250 are in direct contact with each other. With such a structure, oxygen contained in the insulator 280 is less likely to be absorbed by the conductor 260. Accordingly, oxygen contained in the insulator 280 can be efficiently injected into the oxide 230a and the oxide 230b through the oxide 230c; thus, oxygen vacancies in the oxide 230a and the oxide 230b can be reduced. In addition, electric characteristics and reliability of the transistor 200 can be improved. Further, entry of impurities such as hydrogen contained in the insulator 280 into the insulator 250 can be suppressed; thus, adverse effects on electrical characteristics and reliability of the transistor 200 can be suppressed. As the insulator 282, silicon nitride, silicon nitride oxide, aluminum oxide, or hafnium oxide can be used.

  It is preferable that the insulator 272 and the insulator 273 have a function of suppressing transmission of impurities such as hydrogen and water and oxygen.

  FIG. 3A is an enlarged view of a cross section taken along a dashed-dotted line A5-A6 in FIG. 1A, and is also a cross-sectional view of the source or drain region of the transistor 200 in the channel width direction. As shown in FIG. 3A, the top surface of the conductor 242b, the side surface of the conductor 242b, the side surface of the oxide 230a, and the side surface of the oxide 230b are covered with an insulator 272 and an insulator 273. Accordingly, diffusion of impurities such as hydrogen and water and oxygen from the side surface of the conductor 242b and the top surface of the conductor 242b to the conductor 242b can be suppressed. Further, the lower surface of the conductor 242b is in contact with the oxide 243b, and oxygen in the oxide 230b is blocked by the oxide 243b, so that diffusion of the oxygen to the conductor 242b is suppressed. Accordingly, diffusion of oxygen from the periphery of the conductor 242b to the conductor 242b can be suppressed, so that oxidation of the conductor 242b can be suppressed. Note that the conductor 242a has a similar effect. In addition, diffusion of impurities such as hydrogen and water from the side surfaces of the oxide 230a and the oxide 230b to the oxide 230a and the oxide 230b can be suppressed. As the insulator 272, for example, aluminum oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, a silicon oxide film, a silicon nitride film, or a silicon nitride oxide film can be used. As the insulator 273, for example, aluminum oxide or hafnium oxide can be used.

  FIG. 3B is an enlarged view of the right half of the transistor 200 in FIG. An oxide 230c is in contact with the left side surface of the conductor 240b (a portion surrounded by a dotted line in FIG. 3B), and impurities such as hydrogen and water and oxygen from the insulator 250 diffuse into the conductor 240b. Can be suppressed. The insulator 272 is in contact with the right side surface of the conductor 240b, so that diffusion of impurities such as hydrogen and water and oxygen from the insulator 280 to the conductor 240b can be suppressed. Note that the conductor 240a has a similar effect.

  As described above, the periphery of the conductor 240 is surrounded by the insulator 272, the oxide 230c, and the oxide 243b each having a function of suppressing transmission of impurities such as hydrogen and water and oxygen, so that the conductor 240 Oxidation can be suppressed, so that the electrical characteristics of the transistor 200 and the reliability of the transistor 200 can be improved.

  1C, the height of the bottom surface of the conductor 260 in a region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap with each other with reference to the bottom surface of the insulator 224 is: It is preferable to be arranged at a position lower than the height of the bottom surface of the oxide 230b. The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in a region where the oxide 230b and the conductor 260 do not overlap with each other is 0 nm to 100 nm, preferably 3 nm to 50 nm. Or less, more preferably 5 nm or more and 20 nm or less.

  In this manner, the conductor 260 functioning as a gate covers the side surface and the upper surface of the oxide 230b in the channel formation region with the oxide 230c and the insulator 250 interposed therebetween, so that the electric field of the conductor 260 It becomes easy to act on the whole oxide 230b in the region. Thus, the on-state current of the transistor 200 can be increased and frequency characteristics can be improved.

  As described above, a semiconductor device including a transistor with high on-state current can be provided. Alternatively, a semiconductor device including a transistor having high frequency characteristics can be provided. Alternatively, it is possible to provide a semiconductor device in which fluctuations in electric characteristics are suppressed, stable electric characteristics are improved, and reliability is improved. Alternatively, a semiconductor device including a transistor with low off-state current can be provided.

  Hereinafter, a detailed structure of a semiconductor device including the transistor 200 according to one embodiment of the present invention will be described.

  The conductor 205 is provided so as to overlap with the oxide 230 and the conductor 260. It is preferable that the conductor 205 be provided so as to be embedded in the insulator 214 and the insulator 216.

  Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode in some cases. In some cases, the conductor 205 functions as a second gate (also referred to as a bottom gate) electrode. In that case, Vth of the transistor 200 can be controlled by changing the potential applied to the conductor 205 independently of the potential applied to the conductor 260 without changing the potential. In particular, by applying a negative potential to the conductor 205, Vth of the transistor 200 can be made higher than 0 V and off-state current can be reduced. Therefore, when a negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0 V can be smaller than when no negative potential is applied.

  Note that the conductor 205 is preferably provided to be larger than a region of the oxide 230 which does not overlap with the conductors 242a and 242b as illustrated in FIG. In particular, as illustrated in FIG. 1C, the conductor 205 preferably extends in a region outside an end portion of the oxide 230 intersecting with the channel width direction. That is, it is preferable that the conductor 205 and the conductor 260 overlap with each other with the insulator interposed outside the side surface of the oxide 230 in the channel width direction. Alternatively, when the conductor 205 is provided to be large, local charging (called charge-up) may be moderated in a process using plasma in a manufacturing process after the conductor 205 is formed. Note that one embodiment of the present invention is not limited to this. The conductor 205 may overlap with at least the oxide 230 located between the conductor 242a and the conductor 242b.

  With the above structure, the channel formation region can be electrically surrounded by an electric field of the conductor 260 having a function as the first gate and an electric field of the conductor 205 having a function of the second gate. . In this specification, a structure of a transistor which electrically surrounds a channel formation region by an electric field of a first gate and a second gate is referred to as a surrounded channel (S-channel) structure.

  Further, the conductor 205a is preferably a conductor which suppresses transmission of impurities such as water or hydrogen and oxygen. For example, titanium, titanium nitride, tantalum, or tantalum nitride can be used. It is preferable that the conductor 205b be formed using a conductive material mainly containing tungsten, copper, or aluminum. Although the conductor 205 is illustrated as having two layers, the conductor 205 may have a multilayer structure of three or more layers.

  FIG. 2 shows an example in which the conductor 205 has five layers. In the conductor 205, a conductor 205c is formed in contact with the inner wall of the opening of the insulator 216, and a conductor 205d is formed further inside. The conductor 205e is formed inside the conductor 205d. Further, a conductor 205f is formed so as to be in contact with the inner wall of the conductor 205d and the upper surface of the conductor 205e, and a conductor 205g is formed inside the conductor 205f. Here, the height of the upper surface of the conductor 205c, the conductor 205d, the conductor 205d, and the conductor 205f can be approximately equal to the height of the upper surface of the insulator 216. The conductor 205c is preferably formed using a material similar to that of the conductor 205a, and the conductor 205e and the conductor 205g are preferably formed using a material similar to that of the conductor 205b.

  Here, the oxide semiconductor, the insulator or the conductor located in the lower layer of the oxide semiconductor, and the insulator or the conductor located in the upper layer of the oxide semiconductor are formed in different films without opening to the air. It is preferable that the seeds be continuously formed because a substantially high-purity intrinsic oxide semiconductor film in which the concentration of impurities (in particular, hydrogen and water) is reduced can be formed.

  For example, with the use of a deposition apparatus having six treatment chambers, the insulator 222, the insulating film which is to be the insulator 224, the oxide film which is to be the oxide 230a, the oxide film which is to be provided over the insulator 216 and the conductor 205. An oxide film to be the object 230b, an oxide film to be the oxide 243, and a conductive film to be the conductor 242 may be sequentially formed.

The insulator 212, the insulator 214, the insulator 272, the insulator 282, the insulator 283, and the insulator 281 prevent impurities such as water or hydrogen from entering the transistor 200 from the substrate side or from above. It preferably functions as a barrier insulating film. Therefore, the insulator 212, the insulator 214, the insulator 272, the insulator 282, the insulator 283, and the insulator 281 each include a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (N ₂ O, It is preferable to use an insulating material having a function of suppressing diffusion of impurities such as NO and NO ₂ and copper atoms (the impurities are hardly transmitted). Alternatively, it is preferable to use an insulating material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the above-described oxygen is not easily transmitted).

  For example, it is preferable that silicon nitride or the like be used for the insulator 212, the insulator 283, and the insulator 281 and aluminum oxide or the like be used for the insulator 214, the insulator 272, and the insulator 283. Thus, diffusion of impurities such as water or hydrogen from the substrate side to the transistor 200 side through the insulator 212 and the insulator 214 can be suppressed. Alternatively, diffusion of oxygen contained in the insulator 224 or the like to the substrate via the insulator 212 and the insulator 214 can be suppressed. In addition, diffusion of impurities such as water or hydrogen from the insulator 280, the conductor 246, or the like which is provided above the insulator 272 to the transistor 200 side via the insulator 272 can be suppressed. As described above, it is preferable that the transistor 200 be surrounded by the insulator 212, the insulator 214, the insulator 282, and the insulator 283 each having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen.

In some cases, it is preferable to reduce the resistivity of the insulator 212, the insulator 283, and the insulator 281. For example, the resistivity of the insulator 212, the insulator 283, and the insulator 281 is approximately 1 × 10 ¹³ Ωcm, so that the insulator 212, the insulator 283, In some cases, the insulator 281 can reduce charge-up of the conductor 205, the conductor 242, or the conductor 260. Insulator 212, the resistivity of the insulator 283, and the insulator 281 is preferably a 1 × ^{10 15} Ωcm or less 1 × ^{10 10} Ωcm or more.

  In addition, the insulator 216, the insulator 280, and the insulator 274 preferably have a lower dielectric constant than the insulator 214. By using a material having a low dielectric constant as an interlayer film, parasitic capacitance generated between wirings can be reduced. For example, as the insulator 216, the insulator 280, and the insulator 274, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, carbon, and nitrogen are added. Silicon oxide, silicon oxide having holes, or the like may be used as appropriate.

  The insulator 222 and the insulator 224 have a function as a gate insulator.

  Here, the insulator 224 in contact with the oxide 230 preferably releases oxygen by heating. In this specification, oxygen released by heating may be referred to as excess oxygen. For example, the insulator 224 may be formed using silicon oxide or silicon oxynitride as appropriate. By providing an insulator containing oxygen in contact with the oxide 230, oxygen vacancies in the oxide 230 can be reduced and the reliability of the transistor 200 can be improved.

Specifically, it is preferable to use an oxide material from which part of oxygen is released by heating as the insulator 224. An oxide from which oxygen is released by heating means that the amount of released oxygen molecules is 1.0 × 10 ¹⁸ molecules / cm ³ or more in thermal desorption spectroscopy (TDS (Thermal Desorption Spectroscopy) analysis). Is an oxide film having a molecular weight of 1.0 × 10 ¹⁹ molecules / cm ³ or more, more preferably 2.0 × 10 ¹⁹ molecules / cm ³ or more, or 3.0 × 10 ²⁰ molecules / cm ³ or more. Note that the surface temperature of the film at the time of the TDS analysis is preferably in the range of 100 ° C to 700 ° C, or 100 ° C to 400 ° C.

  The insulator 222 preferably functions as a barrier insulating film for preventing impurities such as water or hydrogen from entering the transistor 200 from the substrate side. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By surrounding the insulator 224, the oxide 230, and the like with the insulator 222 and the insulator 272, entry of impurities such as water or hydrogen into the transistor 200 from the outside can be suppressed.

  Further, the insulator 222 preferably has a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule) (the oxygen is hardly transmitted). For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. It is preferable that the insulator 222 have a function of suppressing diffusion of oxygen and impurities because diffusion of oxygen included in the oxide 230 to a lower side than the insulator 222 can be reduced. In addition, the conductor 205 can be prevented from reacting with oxygen included in the insulator 224 and the oxide 230.

  As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials, may be used. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium. In the case where the insulator 222 is formed using such a material, the insulator 222 suppresses release of oxygen from the oxide 230 and entry of impurities such as hydrogen from the periphery of the transistor 200 into the oxide 230. Functions as a layer.

  Alternatively, to these insulators, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added. Alternatively, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be stacked over the above insulator.

The insulator 222 is formed of, for example, aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO ₃ ), or (Ba, Sr) TiO ₃ (BST). An insulator including a so-called high-k material may be used in a single layer or a stacked layer. When a transistor is miniaturized and highly integrated, a problem such as a leak current may occur due to thinning of a gate insulator. With the use of a high-k material for an insulator functioning as a gate insulator, reduction in gate potential at the time of transistor operation can be performed while the physical thickness is maintained.

  Note that the insulator 222 and the insulator 224 may have a stacked structure of two or more layers. In that case, the structure is not limited to a laminated structure made of the same material, and may be a laminated structure made of different materials.

  An oxide 243 is provided over the oxide 230b, and a conductor 242 (a conductor 242a and a conductor 242b) which functions as a source electrode and a drain electrode is provided over the oxide 243. The thickness of the conductor 242 may be, for example, from 1 nm to 50 nm, preferably from 2 nm to 25 nm.

  As the conductor 242, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, It is preferable to use a metal element selected from lanthanum, an alloy containing the above-described metal element as a component, an alloy in which the above-described metal elements are combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are not easily oxidized. A conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable.

  The insulator 250 functions as a gate insulator. The insulator 250 is preferably provided in contact with the upper surface of the oxide 230c. For the insulator 250, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes is used. be able to. In particular, silicon oxide and silicon oxynitride are preferable because they are stable against heat.

  Similarly to the insulator 224, the insulator 250 is preferably formed using an insulator from which oxygen is released by heating. When an insulator from which oxygen is released by heating is provided as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to a channel formation region of the oxide 230b. Further, similarly to the insulator 224, the concentration of impurities such as water or hydrogen in the insulator 250 is preferably reduced. The thickness of the insulator 250 is preferably greater than or equal to 1 nm and less than or equal to 20 nm.

  Further, a metal oxide may be provided between the insulator 250 and the conductor 260. It is preferable that the metal oxide suppress oxygen diffusion from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses diffusion of oxygen, diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, a decrease in the amount of oxygen supplied to the oxide 230 can be suppressed. Further, oxidation of the conductor 260 due to oxygen of the insulator 250 can be suppressed.

  Further, the metal oxide may function as part of a gate insulator. Therefore, in the case where silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable that the metal oxide be a high-k material having a high relative dielectric constant. When the gate insulator has a stacked structure of the insulator 250 and the metal oxide, a stacked structure which is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during the operation of the transistor while maintaining the physical thickness of the gate insulator. Further, the equivalent oxide thickness (EOT) of the insulator functioning as a gate insulator can be reduced.

  Specifically, one selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, or magnesium, or a metal oxide containing two or more kinds may be used. it can. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both oxides of aluminum and hafnium.

  Alternatively, the metal oxide may function as part of a gate in some cases. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

  In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as a conductor functioning as a gate. Further, a conductive material containing the above-described metal element and nitrogen may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed may be captured in some cases. Alternatively, in some cases, hydrogen mixed in from an outer insulator or the like can be captured.

  Although the conductor 260 is illustrated in FIG. 1 as having a two-layer structure, the conductor 260 may have a single-layer structure or a stacked structure of three or more layers.

The conductor 260a has a function of suppressing diffusion of impurities such as a hydrogen atom, a hydrogen molecule, a water molecule, a nitrogen atom, a nitrogen molecule, a nitrogen oxide molecule (eg, N ₂ O, NO, and NO ₂ ), and a copper atom. It is preferable to use a material. Alternatively, it is preferable to use a conductive material having a function of suppressing diffusion of oxygen (for example, at least one of an oxygen atom and an oxygen molecule).

  In addition, since the conductor 260a has a function of suppressing diffusion of oxygen, it is possible to suppress a decrease in conductivity due to oxidation of the conductor 260b due to oxygen contained in the insulator 250. As the conductive material having a function of suppressing diffusion of oxygen, for example, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like is preferably used.

  It is preferable that the conductor 260b be formed using a conductive material mainly containing tungsten, copper, or aluminum. Further, since the conductor 260 also functions as a wiring, a conductor having high conductivity is preferably used. For example, a conductive material containing tungsten, copper, or aluminum as a main component can be used. The conductor 260b may have a stacked structure, for example, a stacked structure of titanium, titanium nitride, and the above conductive material.

  The insulator 280 includes, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or vacancies as the insulator 280. It is preferable to have silicon oxide or the like. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, a material such as silicon oxide, silicon oxynitride, or silicon oxide having a hole is preferable because a region containing oxygen which is released by heating can be easily formed.

  It is preferable that the concentration of impurities such as water or hydrogen in the insulator 280 be reduced. Further, the upper surface of the insulator 280 may be planarized.

  The insulator 282 preferably functions as a barrier insulating film that prevents impurities such as water or hydrogen from entering the insulator 280 from above. As the insulator 282, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example.

  It is preferable that the insulator 274 function as an interlayer film be provided over the insulator 282. It is preferable that the insulator 274 have a reduced concentration of impurities such as water or hydrogen in the film, similarly to the insulator 224 and the like.

  It is preferable that the conductor 240a and the conductor 240b be formed using a conductive material containing tungsten, copper, or aluminum as a main component. Further, the conductor 240a and the conductor 240b may have a stacked structure.

  In the case where the conductor 240 has a stacked-layer structure, the insulator 281, the insulator 274, the insulator 282, the insulator 280, the insulator 273, and the conductor which is in contact with the insulator 272 include impurities such as water or hydrogen. It is preferable to use a conductive material having a function of suppressing transmission. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Further, a conductive material having a function of suppressing transmission of impurities such as water or hydrogen may be used in a single layer or a stacked layer. With the use of the conductive material, oxygen added to the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b. Further, entry of impurities such as water or hydrogen from above the insulator 281 into the oxide 230 through the conductor 240a and the conductor 240b can be suppressed.

  As the insulators 241a and 241b, an insulator such as aluminum oxide, silicon nitride, or silicon nitride oxide may be used, for example. Since the insulator 241a and the insulator 241b are provided in contact with the insulator 272 and the insulator 273, impurities such as water or hydrogen from the insulator 280 or the like are mixed into the oxide 230 through the conductors 240a and 240b. Can be suppressed. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b.

  Further, the conductor 246 (the conductor 246a and the conductor 246b) which functions as a wiring may be provided in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. The conductor 246 is preferably formed using a conductive material mainly containing tungsten, copper, or aluminum. Further, the conductor may have a stacked structure, for example, a stacked structure of titanium or titanium nitride and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in the insulator.

<Structural materials for semiconductor devices>
Hereinafter, constituent materials that can be used for a semiconductor device will be described.

<Substrate>
As a substrate over which the transistor 200 is formed, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. Examples of the insulator substrate include a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (such as a yttria-stabilized zirconia substrate), and a resin substrate. Examples of the semiconductor substrate include a semiconductor substrate of silicon, germanium, or the like, or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, or gallium oxide. Further, there is a semiconductor substrate having an insulator region inside the above-described semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Alternatively, a substrate including a metal nitride, a substrate including a metal oxide, and the like are given. Further, there are a substrate provided with a conductor or a semiconductor on an insulator substrate, a substrate provided with a conductor or an insulator on a semiconductor substrate, a substrate provided with a semiconductor or an insulator on a conductor substrate, and the like. Alternatively, a substrate in which an element is provided may be used. Elements provided on the substrate include a capacitor, a resistor, a switch, a light-emitting element, a storage element, and the like.

<Insulator>
Examples of the insulator include oxides, nitrides, oxynitrides, nitrided oxides, metal oxides, metal oxynitrides, and metal nitrided oxides having insulating properties.

  For example, when transistors are miniaturized and highly integrated, problems such as leakage current may occur due to thinning of a gate insulator. When a high-k material is used for an insulator functioning as a gate insulator, a voltage can be reduced during operation of a transistor while a physical thickness is maintained. On the other hand, by using a material having a low relative dielectric constant for an insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.

  Examples of the insulator having a high relative dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, and silicon and hafnium. Oxynitride or nitride containing silicon and hafnium.

  The insulator having a low relative dielectric constant includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and holes. Silicon oxide, resin, or the like is given.

  In addition, a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen. Examples of the insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. , Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, Alternatively, a metal oxide such as tantalum oxide, or a metal nitride such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon nitride oxide, or silicon nitride can be used.

  The insulator functioning as a gate insulator is preferably an insulator having a region containing oxygen which is released by heating. For example, with a structure in which silicon oxide or silicon oxynitride having a region containing oxygen released by heating is in contact with the oxide 230, oxygen vacancies in the oxide 230 can be compensated.

<Conductor>
Aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum It is preferable to use a metal element selected from the above, an alloy containing the above-described metal element as a component, an alloy in which the above-described metal elements are combined, or the like. For example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, an oxide containing lanthanum and nickel, and the like are used. Is preferred. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are not easily oxidized. A conductive material or a material that maintains conductivity even when oxygen is absorbed is preferable. Alternatively, a semiconductor having high electric conductivity, represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

  Alternatively, a plurality of conductive layers formed using the above materials may be stacked. For example, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined may be employed. Further, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined may be employed. Further, a stacked structure of a combination of the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

  Note that in the case where an oxide is used for a channel formation region of a transistor, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are used for a conductor functioning as a gate may be used. preferable. In this case, a conductive material containing oxygen is preferably provided on the channel formation region side. By providing a conductive material containing oxygen on the channel formation region side, oxygen released from the conductive material is easily supplied to the channel formation region.

  In particular, a conductive material containing oxygen and a metal element contained in a metal oxide in which a channel is formed is preferably used as a conductor functioning as a gate. Further, a conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. In addition, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and silicon were added. Indium tin oxide may be used. Alternatively, indium gallium zinc oxide containing nitrogen may be used. By using such a material, hydrogen contained in a metal oxide in which a channel is formed may be captured in some cases. Alternatively, in some cases, hydrogen mixed in from an outer insulator or the like can be captured.

<Metal oxide>
As the oxide 230, a metal oxide that functions as an oxide semiconductor is preferably used. Hereinafter, metal oxides applicable to the oxide 230 according to the present invention will be described.

  The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it is preferable that aluminum, gallium, yttrium, tin, or the like be contained in addition thereto. In addition, one or more kinds selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like may be included.

  Here, the case where the metal oxide is an In-M-Zn oxide including indium, the element M, and zinc is considered. Note that the element M is aluminum, gallium, yttrium, tin, or the like. Other elements applicable to the element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, in some cases, a combination of a plurality of the aforementioned elements may be used as the element M.

  Note that in this specification and the like, a metal oxide containing nitrogen may be collectively referred to as a metal oxide. Further, a metal oxide containing nitrogen may be referred to as metal oxynitride.

[Structure of metal oxide]
An oxide semiconductor (metal oxide) is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of the non-single-crystal oxide semiconductor include a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS, a pseudo-amorphous oxide semiconductor (a-like OS), and an amorphous oxide semiconductor. Semiconductors.

  The CAAC-OS has a c-axis orientation and a crystal structure in which a plurality of nanocrystals are connected in an ab plane direction and has a strain. Note that the strain refers to a region where the orientation of the lattice arrangement changes between a region where the lattice arrangement is uniform and a region where another lattice arrangement is uniform in a region where a plurality of nanocrystals are connected.

  The nanocrystal is basically a hexagon, but is not limited to a regular hexagon and may be a non-regular hexagon. In addition, distortion may have a lattice arrangement such as a pentagon and a heptagon. Note that in the CAAC-OS, it is difficult to confirm a clear crystal grain boundary (also referred to as a grain boundary) even in the vicinity of distortion. That is, it can be seen that the formation of crystal grain boundaries is suppressed by the distortion of the lattice arrangement. This is because the CAAC-OS can tolerate distortion because the arrangement of oxygen atoms is not dense in the ab plane direction, or the bonding distance between atoms changes by substitution with a metal element. That's why.

  The CAAC-OS is a layered crystal in which a layer containing indium and oxygen (hereinafter, an In layer) and a layer containing elements M, zinc, and oxygen (hereinafter, a (M, Zn) layer) are stacked. It tends to have a structure (also called a layered structure). Note that indium and the element M can be replaced with each other, and when the element M in the (M, Zn) layer is replaced with indium, it can also be referred to as an (In, M, Zn) layer. In addition, when indium in the In layer is replaced with the element M, it can be referred to as an (In, M) layer.

CAAC-OS is a metal oxide with high crystallinity. On the other hand, in the CAAC-OS, it is difficult to confirm a clear crystal grain boundary; thus, it can be said that electron mobility due to the crystal grain boundary is not easily reduced. Moreover, since the crystallinity of the metal oxide that may be reduced by such generation of contamination and defects impurities, CAAC-OS impurities and defects (oxygen deficiency _(V O: also referred to as oxygen vacancy), etc.) with little metal oxide It can be called a thing. Therefore, a metal oxide having a CAAC-OS has stable physical properties. Therefore, the metal oxide including the CAAC-OS is resistant to heat and has high reliability.

  The nc-OS has a periodic atomic arrangement in a minute region (for example, a region with a thickness of 1 nm to 10 nm, particularly, a region with a size of 1 nm to 3 nm). In the nc-OS, there is no regularity in crystal orientation between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method.

  Note that indium-gallium-zinc oxide (hereinafter, referred to as IGZO), which is a kind of metal oxide including indium, gallium, and zinc, may have a stable structure by being formed using the above-described nanocrystal. is there. In particular, since IGZO tends to be difficult to grow in the air, it is preferable to use a smaller crystal (for example, the above-described nanocrystal) than a large crystal (here, a crystal of several mm or a crystal of several cm). However, it may be structurally stable.

  The a-like OS is a metal oxide having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has a void or a low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and the CAAC-OS.

  Oxide semiconductors (metal oxides) have various structures and each have different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS.

  Note that in the semiconductor device of one embodiment of the present invention, the structure of the oxide semiconductor (metal oxide) is not particularly limited, but preferably has crystallinity. For example, the oxide 230 can have a CAAC-OS structure and the oxide 243 can have a hexagonal crystal structure. When the oxide 230 and the oxide 243 have the above crystal structure, a highly reliable semiconductor device can be obtained. Further, the oxide 230a, the oxide 230c, and the oxide 243 can have substantially the same composition.

[impurities]
Here, the influence of each impurity in the metal oxide will be described.

In addition, when an alkali metal or an alkaline earth metal is contained in a metal oxide, a defect level may be formed and carriers may be generated in some cases. Therefore, a transistor in which a metal oxide containing an alkali metal or an alkaline earth metal is used for a channel formation region is likely to have normally-on characteristics. Therefore, it is preferable to reduce the concentration of the alkali metal or alkaline earth metal in the metal oxide. Specifically, the concentration of an alkali metal or an alkaline earth metal in a metal oxide obtained by SIMS (the concentration obtained by Secondary Ion Mass Spectrometry (SIMS)) is set to 1 × 10 ¹⁸ atoms. / Cm ³ or less, preferably 2 × 10 ¹⁶ atoms / cm ³ or less.

  In addition, hydrogen contained in a metal oxide reacts with oxygen bonded to a metal atom to become water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers are generated in some cases. Further, part of hydrogen may bond with oxygen which is bonded to a metal atom to generate an electron serving as a carrier. Therefore, a transistor including a metal oxide containing hydrogen is likely to have normally-on characteristics.

Therefore, it is preferable that hydrogen in the metal oxide is reduced as much as possible. Specifically, in the metal oxide, the hydrogen concentration obtained by SIMS is less than 1 × 10 ²⁰ atoms / cm ³ , preferably less than 1 × 10 ¹⁹ atoms / cm ³ , more preferably 5 × 10 ¹⁸ atoms / cm 3. ^{It is set to} less than ³ , more preferably less than 1 × 10 ¹⁸ atoms / cm ³ . When a metal oxide with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electric characteristics can be provided.

  It is preferable to use a thin film with high crystallinity as the metal oxide used for the semiconductor of the transistor. With the use of the thin film, stability or reliability of the transistor can be improved. Examples of the thin film include a single crystal metal oxide thin film and a polycrystalline metal oxide thin film. However, forming a thin film of a single crystal metal oxide or a thin film of a polycrystalline metal oxide on a substrate requires a high-temperature or laser heating step. Therefore, the cost of the manufacturing process increases, and the throughput also decreases.

  It was reported in Non-Patent Documents 1 and 2 that an In-Ga-Zn oxide having a CAAC structure (referred to as CAAC-IGZO) was discovered in 2009. Here, it is reported that CAAC-IGZO has c-axis orientation, crystal grain boundaries are not clearly observed, and can be formed on a substrate at a low temperature. Further, it is reported that a transistor using CAAC-IGZO has excellent electric characteristics and reliability.

  In 2013, an In-Ga-Zn oxide having an nc structure (referred to as nc-IGZO) was discovered (see Non-Patent Document 3). Here, it has been reported that nc-IGZO has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 3 nm or less), and that there is no regularity in the crystal orientation between different regions. I have.

  Non-Patent Documents 4 and 5 show changes in the average crystal size due to the irradiation of electron beams to the thin films of the above-described CAAC-IGZO, nc-IGZO, and IGZO with low crystallinity. In an IGZO thin film having low crystallinity, crystalline IGZO of about 1 nm has been observed even before irradiation with an electron beam. Therefore, it is reported here that the existence of a completely amorphous structure in IGZO could not be confirmed. Furthermore, it is shown that the CAAC-IGZO thin film and the nc-IGZO thin film have higher stability to electron beam irradiation than the IGZO thin film having low crystallinity. Therefore, it is preferable to use a thin film of CAAC-IGZO or a thin film of nc-IGZO as a semiconductor of the transistor.

A transistor including a metal oxide has extremely low leakage current in a non-conducting state. Specifically, an off-state current per 1 μm of channel width of the transistor is in the order of yA / μm (10 ⁻²⁴ A / μm). Is shown in Non-Patent Document 6. For example, a low-power-consumption CPU utilizing the characteristic of low leakage current of a transistor including a metal oxide is disclosed (see Non-Patent Document 7).

  In addition, application of a transistor using a metal oxide to a display device utilizing the characteristic of low leakage current has been reported (see Non-Patent Document 8). In the display device, the displayed image switches several tens of times per second. The number of times the image is switched per second is called a refresh rate. Also, the refresh rate may be called a drive frequency. Such high-speed switching of the screen, which is difficult for the human eyes to perceive, is considered as a cause of eye fatigue. Therefore, it has been proposed to decrease the refresh rate of the display device to reduce the number of times of rewriting of the image. Further, power consumption of the display device can be reduced by driving with a reduced refresh rate. Such a driving method is called idling stop driving.

  The discovery of the CAAC structure and the nc structure contributes to improvement in electrical characteristics and reliability of a transistor including a metal oxide having a CAAC structure or an nc structure, reduction in manufacturing process cost, and improvement in throughput. In addition, research on application of the transistor to a display device and an LSI utilizing the characteristic of the transistor having a low leakage current has been advanced.

<Method for Manufacturing Semiconductor Device>
Next, a manufacturing method of the semiconductor device including the transistor 200 according to the present invention illustrated in FIG. 1 will be described with reference to FIGS. 4A to 12, (A) in each drawing is a top view. FIG. 2B is a cross-sectional view corresponding to a portion indicated by a dashed-dotted line A1-A2 in FIG. 1A, and is also a cross-sectional view of the transistor 200 in the channel length direction. Further, (C) of each drawing is a cross-sectional view corresponding to a portion indicated by a dashed line A3-A4 in (A), and is also a cross-sectional view of the transistor 200 in the channel width direction. Note that some components are not illustrated in the top view of FIG.

  First, a substrate (not shown) is prepared, and an insulator 212 is formed over the substrate. The insulator 212 is formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or a pulsed laser deposition (PLD) method. (Atomic Layer Deposition) method or the like.

  Note that the CVD method can be classified into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, an optical CVD (Photo CVD) method using light, and the like. . Further, the method can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to a source gas used.

  In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. Further, the thermal CVD method is a film formation method capable of reducing plasma damage to an object to be processed because plasma is not used. For example, a wiring, an electrode, an element (eg, a transistor or a capacitor) included in a semiconductor device may be charged up by receiving charge from plasma. At this time, the accumulated charges may destroy wirings, electrodes, elements, and the like included in the semiconductor device. On the other hand, in the case of a thermal CVD method that does not use plasma, such plasma damage does not occur, so that the yield of semiconductor devices can be increased. Further, in the thermal CVD method, a plasma film having few defects can be obtained because plasma damage does not occur during film formation.

  In addition, the ALD method utilizes the self-controlling property of atoms and can deposit atoms one by one, so that an extremely thin film can be formed, a film can be formed on a structure having a high aspect ratio, There are effects such as film formation with few defects such as holes, film formation with excellent coverage, and film formation at a low temperature. The ALD method also includes a plasma enhanced ALD (Plasma Enhanced ALD) method using plasma. Utilization of plasma makes it possible to form a film at a lower temperature, which is preferable in some cases. Some precursors used in the ALD method contain impurities such as carbon. Therefore, a film formed by an ALD method may contain more impurities such as carbon than a film formed by another film formation method. Note that the determination of impurities can be performed using X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy).

  The CVD method and the ALD method are different from a film formation method in which particles emitted from a target or the like are deposited, and are a film formation method in which a film is formed by a reaction on a surface of an object to be processed. Therefore, the film formation method is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use the ALD method in combination with another film formation method such as a CVD method with a high film formation rate.

  In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow ratio of the source gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on a flow rate ratio of a source gas. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow ratio of the source gas while forming the film. When film formation is performed while changing the flow ratio of the source gas, the time required for film formation is shortened because the time required for transport and pressure adjustment is not required as compared with the case where film formation is performed using a plurality of film formation chambers. can do. Therefore, the productivity of the semiconductor device may be improved in some cases.

  In this embodiment, silicon nitride is formed as the insulator 212 by a CVD method. In this manner, by using an insulator such as silicon nitride which does not easily transmit copper as the insulator 212, even when a metal such as copper which is easily diffused is used as a conductor in a layer (not illustrated) below the insulator 212, Diffusion of the metal into an upper layer through the insulator 212 can be suppressed. In addition, by using an insulator which does not easily transmit impurities such as water or hydrogen, such as silicon nitride, diffusion of impurities such as water or hydrogen from a layer below the insulator 212 can be suppressed.

  Next, the insulator 214 is formed over the insulator 212. The insulator 214 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, aluminum oxide is used for the insulator 214.

  Next, the insulator 216 is formed over the insulator 214. The insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, an opening reaching the insulator 214 is formed in the insulator 216. The opening includes, for example, a groove and a slit. In some cases, a region where an opening is formed is referred to as an opening. The opening may be formed by wet etching, but dry etching is more preferable for fine processing. Further, as the insulator 214, an insulator which functions as an etching stopper film when the insulator 216 is etched to form a groove is preferably selected. For example, when a silicon oxide film is used for the insulator 216 that forms the groove, the insulator 214 may be a silicon nitride film, an aluminum oxide film, or a hafnium oxide film.

  After the formation of the opening, a conductive film to be the conductor 205 is formed. The conductive film preferably includes a conductor having a function of suppressing transmission of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, or the like can be used. Alternatively, a stacked film of tantalum, tungsten, titanium, molybdenum, aluminum, copper, and a molybdenum tungsten alloy can be used. The conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  In this embodiment, the conductive film serving as the conductor 205 has a multilayer structure. First, tantalum nitride is formed by a sputtering method, and titanium nitride is stacked on the tantalum nitride. By using such a metal nitride for a lower layer of a conductive film to be the conductor 205, even if a metal such as copper which is easily diffused is used as an upper conductive film of the conductive film to be described later, Can be prevented from diffusing out of the conductor 205.

  Next, a conductive film over the conductive film to be the conductor 205 is formed. The conductive film can be formed by a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, a low-resistance conductive material such as copper is formed as a conductive film over the conductive film to be the conductor 205.

  Next, by performing a CMP process (Chemical Mechanical Polishing), an upper layer of the conductive film to be the conductor 205 and part of a lower layer of the conductive film to be the conductor 205 are removed, so that the insulator 216 is exposed. As a result, the conductive film serving as the conductor 205 remains only in the opening. Thus, the conductor 205 having a flat top surface can be formed. Note that part of the insulator 216 may be removed by the CMP treatment (see FIG. 4).

  Hereinafter, a method for forming the conductor 205 which is different from the above will be described below.

  A conductive film to be the conductor 205 is formed over the insulator 214. The conductive film to be the conductor 205 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. The conductive film serving as the conductor 205 can be a multilayer film. In this embodiment, tungsten is formed as a conductive film to be the conductor 205.

  Next, the conductive film serving as the conductor 205 is processed by lithography to form the conductor 205.

  In the lithography method, first, a resist is exposed through a mask. Next, a resist mask is formed by removing or leaving the exposed region using a developing solution. Next, by performing an etching treatment through the resist mask, a conductor, a semiconductor, an insulator, or the like can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, or the like. Further, a liquid immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens to perform exposure. Further, an electron beam or an ion beam may be used instead of the above-described light. When an electron beam or an ion beam is used, a mask is not required. Note that the resist mask can be removed by dry etching such as ashing, wet etching, wet etching after dry etching, or dry etching after wet etching.

  Further, a hard mask made of an insulator or a conductor may be used instead of the resist mask. In the case of using a hard mask, an insulating film or a conductive film serving as a hard mask material is formed over the conductive film serving as the conductor 205, a resist mask is formed thereover, and the hard mask material is etched to have a desired shape. A hard mask can be formed. The etching of the conductive film to be the conductor 205 may be performed after removing the resist mask, or may be performed with the resist mask left. In the latter case, the resist mask may disappear during the etching. After etching the conductive film to be the conductor 205, the hard mask may be removed by etching. On the other hand, if the material of the hard mask does not affect the post-process or can be used in the post-process, it is not always necessary to remove the hard mask.

  As the dry etching apparatus, a capacitively coupled plasma (CCP) etching apparatus having parallel plate electrodes can be used. The capacitively coupled plasma etching apparatus having the parallel plate type electrode may be configured to apply a high frequency power to one of the parallel plate type electrodes. Alternatively, a configuration in which a plurality of different high-frequency power sources are applied to one of the parallel plate electrodes may be employed. Alternatively, a configuration in which a high-frequency power source having the same frequency is applied to each of the parallel plate electrodes may be employed. Alternatively, a configuration may be employed in which high-frequency power sources having different frequencies are applied to the respective parallel plate electrodes. Alternatively, a dry etching apparatus having a high-density plasma source can be used. As a dry etching apparatus having a high-density plasma source, for example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

  Next, an insulating film to be the insulator 216 is formed over the insulator 214 and the conductor 205. The insulator to be the insulator 216 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In this embodiment, as the insulating film to be the insulator 216, silicon oxide is formed by a CVD method.

  Here, the thickness of the insulating film to be the insulator 216 is preferably greater than or equal to the thickness of the conductor 205. For example, when the thickness of the conductor 205 is 1, the thickness of the insulating film to be the insulator 216 is 1 or more and 3 or less. In this embodiment, the thickness of the conductor 205 is 150 nm, and the thickness of the insulating film serving as the insulator 216 is 350 nm.

  Next, CMP treatment is performed on the insulating film to be the insulator 216, so that part of the insulating film to be the insulator 216 is removed and the surface of the conductor 205 is exposed. As a result, the conductor 205 and the insulator 216 having a flat top surface can be formed. The above is a different method for forming the conductor 205.

  Next, the insulator 222 is formed over the insulator 216 and the conductor 205. As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium may be formed. Note that it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), or the like as the insulator containing one or both oxides of aluminum and hafnium. An insulator including an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. Since the insulator 222 has a barrier property to hydrogen and water, diffusion of hydrogen and water contained in a structure provided around the transistor 200 through the insulator 222 to the inside of the transistor 200 is suppressed. In addition, generation of oxygen vacancies in the oxide 230 can be suppressed.

  The insulator 222 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, an insulating film 224A is formed over the insulator 222. The insulating film 224A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Subsequently, heat treatment is preferably performed. The heat treatment may be performed at a temperature of 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C, more preferably 320 ° C to 450 ° C. Note that the heat treatment is performed in a nitrogen or inert gas atmosphere or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. The heat treatment may be performed in a reduced pressure state. Alternatively, in the heat treatment, heat treatment is performed in a nitrogen or inert gas atmosphere, and then heat treatment is performed in an atmosphere including an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to supplement desorbed oxygen. Good.

  In this embodiment mode, after the treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere, the treatment is continuously performed at 400 ° C. for one hour in an oxygen atmosphere. By the heat treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed.

  The heat treatment may be performed after the insulator 222 is formed. For the heat treatment, the above-described heat treatment conditions can be used.

  Here, in order to form an excess oxygen region in the insulating film 224A, plasma treatment including oxygen may be performed under reduced pressure. For the plasma treatment containing oxygen, it is preferable to use an apparatus having a power supply for generating high-density plasma using microwaves, for example. Alternatively, a power supply for applying RF (Radio Frequency) may be provided on the substrate side. With the use of high-density plasma, high-density oxygen radicals can be generated. By applying RF to the substrate side, oxygen radicals generated by high-density plasma can be efficiently guided into the insulating film 224A. it can. Alternatively, after performing plasma treatment including an inert gas using this apparatus, plasma treatment including oxygen may be performed to supplement desorbed oxygen. Note that by appropriately selecting the conditions of the plasma treatment, impurities such as water and hydrogen contained in the insulating film 224A can be removed. In that case, the heat treatment may not be performed.

  Here, aluminum oxide may be formed over the insulating film 224A by, for example, a sputtering method, and CMP may be performed until the aluminum oxide reaches the insulating film 224A. By performing the CMP, planarization of the surface of the insulating film 224A and planarization of the surface of the insulating film 224A can be performed. By arranging the aluminum oxide on the insulating film 224A and performing the CMP, the end point of the CMP can be easily detected. In addition, the insulating film 224A may be partially polished by CMP to reduce the thickness of the insulating film 224A; however, the thickness may be adjusted when the insulating film 224A is formed. By planarizing and smoothing the surface of the insulating film 224A, deterioration of the coverage of an oxide film to be formed later can be prevented, and reduction in the yield of a semiconductor device can be prevented in some cases. It is preferable that aluminum oxide be formed over the insulating film 224A by a sputtering method because oxygen can be added to the insulating film 224A.

  Next, an oxide film 230A and an oxide film 230B are sequentially formed on the insulating film 224A (see FIG. 4). Note that the oxide film is preferably formed continuously without exposure to the air environment. When the oxide film 230A and the oxide film 230B are formed without being exposed to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from being attached to the oxide films 230A and 230B, and the vicinity of the interface between the oxide films 230A and 230B can be reduced. Can be kept clean.

  The oxide films 230A and 230B can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  For example, in the case where the oxide films 230A and 230B are formed by a sputtering method, oxygen or a mixed gas of oxygen and a rare gas is used as a sputtering gas. By increasing the proportion of oxygen contained in the sputtering gas, excess oxygen in the oxide film to be formed can be increased. In the case where the above oxide film is formed by a sputtering method, the above In-M-Zn oxide target can be used.

  In particular, when the oxide film 230A is formed, part of oxygen contained in the sputtering gas may be supplied to the insulating film 224A. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230A may be 70% or more, preferably 80% or more, and more preferably 100%.

  In the case where the oxide film 230B is formed by a sputtering method, the proportion of oxygen contained in a sputtering gas is greater than or equal to 1% and less than or equal to 30%, preferably greater than or equal to 5% and less than or equal to 20%. It is formed. A transistor using an oxygen-deficient oxide semiconductor for a channel formation region can have relatively high field-effect mobility.

  In this embodiment mode, In: Ga: Zn = 1: 1: 0.5 [atomic ratio] (2: 2: 1 [atomic ratio]) or 1: 3 as the oxide film 230A by a sputtering method. : 4 [atomic ratio] is formed using a target. The oxide film 230B is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio] or 1: 1: 1 [atomic ratio]. Note that each oxide film may be formed in accordance with characteristics required for the oxide 230 by appropriately selecting a deposition condition and an atomic ratio.

  Next, heat treatment may be performed. For the heat treatment, the above-described heat treatment conditions can be used. By the heat treatment, impurities such as water and hydrogen in the oxide films 230A and 230B can be removed. In this embodiment mode, after the treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere, the treatment is continuously performed at 400 ° C. for one hour in an oxygen atmosphere.

  Next, an oxide film 243A is formed on the oxide film 230B. The oxide film 243A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the oxide film 243A, the atomic ratio of Ga to In is preferably larger than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 243A is formed by a sputtering method with a target of In: Ga: Zn = 1: 3: 4 [atomic ratio]. Next, a conductive film 242A is formed over the oxide film 243A. The conductive film 242A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 4).

  Next, the oxide film 230A, the oxide film 230B, the oxide film 243A, and the conductive film 242A are processed into an island shape to form an oxide 230a, an oxide 230b, an oxide layer 243B, and a conductor layer 242B (FIG. 5). Although not illustrated, in this step, the thickness of a region of the insulating film 224A which does not overlap with the oxide 230a may be reduced.

  Here, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B are formed so that at least a part thereof overlaps with the conductor 205. In addition, the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B are preferably substantially perpendicular to the top surface of the insulator 222. When the side surfaces of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B are substantially perpendicular to the top surface of the insulator 222, the area can be reduced when the plurality of transistors 200 is provided. Higher densities are possible. Alternatively, the angle formed between the oxide 230a, the oxide 230b, the oxide layer 243B, and the top surface of the conductor layer 242B and the insulator 222 may be low. In that case, the angle formed between the side surface of the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B and the upper surface of the insulator 222 is preferably greater than or equal to 60 ° and less than 70 °. By adopting such a shape, coverage with the insulator 272 and the like can be improved in a process after this, and defects such as voids can be reduced.

  In addition, a curved surface is provided between a side surface of the conductor layer 242B and an upper surface of the conductor layer 242B. That is, the end of the side surface and the end of the upper surface are preferably curved (hereinafter also referred to as a round shape). The curved surface has, for example, a radius of curvature of 3 nm or more and 10 nm or less, preferably 5 nm or more and 6 nm or less at an end of the conductive layer 242B. By not having a corner at the end, coverage of the film in the subsequent film forming process is improved.

  Note that the oxide film and the conductive film may be processed by a lithography method. In addition, the processing can use a dry etching method or a wet etching method. Processing by dry etching is suitable for fine processing.

  Next, an insulating film 272A is formed over the insulating film 224A, the oxide 230a, the oxide 230b, the oxide layer 243B, and the conductor layer 242B (see FIG. 6).

  The insulating film 272A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film 272A, an insulating film having a function of suppressing transmission of oxygen is preferably used. For example, aluminum oxide, silicon nitride, silicon oxide, or gallium oxide may be formed by a sputtering method or an ALD method.

  Next, an insulating film 273A is formed over the insulating film 272A. The insulating film 273A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to form an aluminum oxide film by an ALD method. In this embodiment mode, an aluminum oxide film is formed by an ALD method (see FIG. 6). Note that a structure in which the insulating film 273A is not formed may be employed.

  Next, an insulating film to be the insulator 280 is formed over the insulating film 273A. The insulating film to be the insulator 280 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Next, CMP treatment is performed on the insulating film to be the insulator 280, so that the insulator 280 having a flat top surface is formed (see FIG. 7).

  Next, part of the insulator 280, part of the insulating film 273A, part of the insulating film 272A, part of the oxide layer 243B, and part of the conductor layer 242B are processed to form openings reaching the oxide 230b. I do. The opening is preferably formed so as to overlap with the conductor 205. Through the formation of the opening, the oxide 243a, the oxide 243b, the conductor 242a, the conductor 242b, the insulator 272, the insulator 273, and the insulator 224 are formed (see FIG. 7).

  Processing of part of the insulator 280, part of the insulating film 273A, part of the insulating film 272A, part of the oxide layer 243B, and part of the conductor layer 242B may be performed under different conditions. For example, part of the insulator 280 is processed by a dry etching method, part of the insulating film 273A is processed by a wet etching method, part of the insulating film 272A, part of the oxide layer 243B, and part of the conductor layer 242B. May be processed by a dry etching method.

  By performing a conventional process such as dry etching, impurities due to an etching gas or the like may be attached or diffused to the surface or inside of the oxide 230a and the oxide 230b. Examples of the impurities include fluorine and chlorine.

  Cleaning is performed to remove the above impurities and the like. Examples of the cleaning method include wet cleaning using a cleaning liquid, plasma treatment using plasma, cleaning by heat treatment, and the like, and the above cleaning may be appropriately combined.

  As the wet cleaning, a cleaning treatment may be performed using an aqueous solution in which oxalic acid, phosphoric acid, ammonia water, hydrofluoric acid, or the like is diluted with carbonated water or pure water. Alternatively, ultrasonic cleaning using pure water or carbonated water may be performed.

  Next, first heat treatment may be performed. It is preferable that the first heat treatment be performed in an atmosphere containing oxygen. Alternatively, the first heat treatment may be performed under reduced pressure and the oxide film 230C may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide 230b and the like can be removed, and the moisture concentration and the hydrogen concentration in the oxide 230a and the oxide 230b can be further reduced. . The temperature of the first heat treatment is preferably from 100 ° C to 400 ° C, more preferably from 150 ° C to 350 ° C. In this embodiment, the temperature of the first heat treatment is set to 200 ° C. and the pressure is reduced under reduced pressure (see FIG. 8).

  Here, at least part of the side surface of the oxide 230a, part of the side surface and part of the top surface of the oxide 230b, part of the side surface of the oxide 243, part of the side surface of the conductor 242, It is preferable to be provided so as to be in contact with the side surface of the insulator 272, the side surface of the insulator 273, and the side surface of the insulator 280. Since the conductor 242 is surrounded by the oxide 243, the insulator 272, and the oxide film 230C, a decrease in conductivity due to oxidation of the conductor 242 in subsequent steps can be suppressed.

  The oxide film 230C can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the oxide film 230C, the atomic ratio of Ga to In is preferably larger than the atomic ratio of Ga to In in the oxide film 230B. In this embodiment, the oxide film 230C is formed by a sputtering method with the use of a target of In: Ga: Zn = 1: 3: 4 [atomic ratio].

  Note that the oxide film 230C may be stacked. For example, a film is formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio], and successively, In: Ga: Zn = 1: 3: 4 [atom]. [Numerical ratio].

  In particular, when the oxide film 230C is formed, part of oxygen contained in the sputtering gas may be supplied to the oxide 230a and the oxide 230b. Alternatively, part of oxygen contained in a sputtering gas may be supplied to the insulator 280 when the oxide film 230C is formed. Therefore, the proportion of oxygen contained in the sputtering gas of the oxide film 230C may be 70% or more, preferably 80% or more, and more preferably 100%.

  Next, a second heat treatment may be performed. The second heat treatment may be performed under reduced pressure, and the insulating film 250A may be formed continuously without exposure to the air. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the oxide film 230C and the like are removed, and the moisture concentration and the hydrogen concentration in the oxide 230a, the oxide 230b, and the oxide film 230C are further reduced. Can be done. The temperature of the second heat treatment is preferably from 100 ° C to 400 ° C. In this embodiment, the temperature of the second heat treatment is set to 200 ° C. (see FIG. 9).

  The insulating film 250A can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. It is preferable that silicon oxynitride be formed by a CVD method as the insulating film 250A. Note that the temperature at which the insulating film 250A is formed is preferably higher than or equal to 250 ° C. and lower than 450 ° C., and particularly preferably about 350 ° C. By forming the insulating film 250A at 350 ° C., an insulator with few impurities can be formed.

  Next, a conductive film 260Aa and a conductive film 260Ab are formed. The conductive films 260Aa and 260Ab can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. For example, it is preferable to use a CVD method. In this embodiment, the conductive film 260Aa is formed by an ALD method, and the conductive film 260Ab is formed by a CVD method (see FIG. 10).

  Next, by polishing the oxide film 230C, the insulating film 250A, the conductive film 260Aa, and the conductive film 260Ab by CMP until the insulator 280 is exposed, the oxide 230c, the insulator 250, and the conductor 260 (the conductor 260a And a conductor 260b) (see FIG. 11).

  Here, since the conductor 242 is provided so as to be surrounded by the oxide 243, the insulator 272, and the oxide 230c, a decrease in conductivity due to oxidation of the conductor 242 can be suppressed.

  Next, a third heat treatment is performed. In one embodiment of the present invention, by performing the third heat treatment, impurities (typically, water, hydrogen, or the like) contained in the oxide film 230C and the insulator 280 can be preferably removed. . For example, by performing the third heat treatment, water, hydrogen, and the like contained in the oxide film 230C are removed (dehydration / dehydrogenation), so that the oxide film 230C can be made to have a high purity. Further, by performing the third heat treatment, water, hydrogen, and the like contained in the insulator 280 are removed (dehydrated and dehydrogenated), so that water, hydrogen, and the like that can diffuse into the oxide film 230C are removed from the transistor. It can be removed during the fabrication process (see FIG. 11).

Note that the third heat treatment can be performed in a nitrogen atmosphere or an atmosphere containing oxygen. It is preferable that the third heat treatment be performed in an atmosphere containing nitrogen and oxygen. When the treatment is performed in an atmosphere containing nitrogen and oxygen, the proportion of oxygen is preferably 5% or more and 20% or less of the total of nitrogen and oxygen. Further, the temperature of the third heat treatment is preferably from 300 ° C to 450 ° C, more preferably from 300 ° C to 400 ° C. Typically, a temperature of 350 ° C. or near it is suitable. The heat treatment time is 100 hours or less, preferably 1 hour to 48 hours. Typically, a processing time of 24 hours or a time in the vicinity thereof is preferable. By performing the heat treatment, the moisture concentration and the hydrogen concentration in the oxide 230, the insulator 250, and the insulator 280 can be reduced, and the carrier density of the oxide 230 in a channel formation region can be reduced. In this embodiment, heat treatment is performed at 350 ° C. for 24 hours in a nitrogen atmosphere. Note that the heat treatment is preferably performed under such a condition that the conductor 260 is not oxidized by the third heat treatment.

  Alternatively, RTA (Rapid thermal anneal) processing may be performed using an RTA apparatus. The RTA treatment is to perform a high-temperature heat treatment in a short time. For example, heat treatment can be performed at a temperature of 400 to 700 ° C. for 60 seconds to 120 seconds in a nitrogen atmosphere. Note that a lamp method can be used as a light source for the RTA apparatus. By using the RTA apparatus of the lamp system, the processing tact can be increased and the productivity can be improved.

  Next, a fourth heat treatment may be performed. The fourth heat treatment is performed under reduced pressure and becomes an insulator 282 over the conductor 260, the oxide 230c, the insulator 250, and the insulator 280 without exposure to the air. It is preferable to form an insulating film and an insulating film to be the insulator 283 in that order. By performing such a treatment, moisture and hydrogen adsorbed on the surface of the conductor 260, the surface of the oxide 230c, the surface of the insulator 250, the surface of the insulator 280, and the like can be removed, which is preferable. The insulating film to be the insulator 282 and the insulating film to be the insulator 283 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As an insulating film to be the insulator 282, for example, aluminum oxide is preferably formed by a sputtering method. As the insulating film to be the insulator 283, for example, silicon nitride is preferably formed by a sputtering method. By arranging the insulator 282 and the insulator 283 in this manner, diffusion of impurities such as water or hydrogen from the outside to the transistor 200 through the insulator 282 and the insulator 283 can be suppressed. Further, by forming the insulator 282 in contact with the upper surface of the conductor 260, oxygen in the insulator 280 can be prevented from being absorbed by the conductor 260 in a heat treatment performed later, which is preferable. (See FIG. 12).

  As described above, in one embodiment of the present invention, by performing the third heat treatment, a highly reliable semiconductor device can be provided.

  Next, a fifth heat treatment may be performed. In this embodiment mode, treatment is performed at 400 ° C. for one hour in a nitrogen atmosphere. By the heat treatment, oxygen added by the formation of the insulator 282 can be injected into the insulator 280. The oxygen can be injected into the oxide 230a and the oxide 230b through the oxide 230c.

  Next, an insulator to be the insulator 274 may be formed over the insulator 283. The insulating film to be the insulator 274 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like (see FIG. 12).

  Next, an insulator to be the insulator 281 may be formed over the insulator 274. The insulating film to be the insulator 281 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As an insulating film to be the insulator 281, for example, silicon nitride is preferably formed by a sputtering method. (See FIG. 12).

  Next, openings which reach the conductors 242a and 242b are formed in the insulator 272, the insulator 273, the insulator 280, the insulator 282, the insulator 283, the insulator 274, and the insulator 281. The formation of the opening may be performed using a lithography method.

  Next, an insulating film to be the insulator 241 is formed, and the insulator 241 is formed by anisotropic etching of the insulating film. The conductive film can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. As the insulating film to be the insulator 241, an insulating film having a function of suppressing transmission of oxygen is preferably used. For example, aluminum oxide or silicon nitride is preferably formed by an ALD method. The anisotropic etching may be performed by, for example, a dry etching method. With such a structure of the side wall of the opening, permeation of oxygen from the outside can be suppressed, and oxidation of the conductor 240a and the conductor 240b to be formed next can be prevented. In addition, diffusion of impurities such as water and hydrogen from the conductor 240a and the conductor 240b to the outside can be prevented.

  Next, a conductive film to be the conductor 240a and the conductor 240b is formed. It is preferable that the conductive film to be the conductor 240a and the conductor 240b have a stacked structure including a conductor having a function of suppressing transmission of impurities such as water and hydrogen. For example, a stack of tantalum nitride, titanium nitride, or the like and tungsten, molybdenum, copper, or the like can be used. The conductive film to be the conductor 240 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, by performing CMP treatment, part of the conductive film to be the conductor 240a and the conductor 240b is removed, so that the insulator 281 is exposed. As a result, the conductive film remains only in the opening, so that the conductor 240a and the conductor 240b having a flat top surface can be formed (see FIG. 1). Note that part of the insulator 281 may be removed by the CMP treatment.

  Next, a conductive film to be the conductor 246 is formed. The conductive film to be the conductor 246 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like.

  Next, the conductive film serving as the conductor 246 is processed by lithography to form the conductor 246a in contact with the upper surface of the conductor 240a and the conductor 246b in contact with the upper surface of the conductor 240b (see FIG. 1).

  Through the above, a semiconductor device including the transistor 200 illustrated in FIG. 1 can be manufactured. As illustrated in FIGS. 4 to 12, the transistor 200 can be manufactured by using the method for manufacturing a semiconductor device described in this embodiment.

  According to one embodiment of the present invention, a semiconductor device with high on-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having high frequency characteristics can be provided. Alternatively, according to one embodiment of the present invention, a highly reliable semiconductor device can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device which can be miniaturized or highly integrated can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device having favorable electric characteristics can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with low off-state current can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with reduced power consumption can be provided. Alternatively, according to one embodiment of the present invention, a semiconductor device with high productivity can be provided.

  As described above, the structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 2)
In this embodiment, one embodiment of a semiconductor device is described with reference to FIGS.

[Storage device 1]
FIG. 17 illustrates an example of a semiconductor device (memory device) using the capacitor which is one embodiment of the present invention. In the semiconductor device of one embodiment of the present invention, the transistor 200 is provided above the transistor 300, and the capacitor 100 is provided above the transistor 300 and the transistor 200. Note that as the transistor 200, the transistor 200 described in the above embodiment can be used.

  The transistor 200 is a transistor in which a channel is formed in a semiconductor layer including an oxide semiconductor. Since the off-state current of the transistor 200 is small, stored data can be held for a long time by using the transistor 200 in a memory device. That is, since the refresh operation is not required or the frequency of the refresh operation is extremely low, the power consumption of the storage device can be sufficiently reduced.

  In the semiconductor device illustrated in FIG. 17, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. Further, the wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the first gate of the transistor 200, and the wiring 1006 is electrically connected to the second gate of the transistor 200. It is connected to the. Further, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. .

  The memory devices illustrated in FIG. 17 can be arranged in a matrix, so that a memory cell array can be formed.

<Transistor 300>
The transistor 300 is provided over a substrate 311 and has a conductor 316 functioning as a gate, an insulator 315 functioning as a gate insulator, a semiconductor region 313 which is part of the substrate 311, and a low-voltage transistor functioning as a source or drain region. It has a resistance region 314a and a low resistance region 314b. The transistor 300 may be either a p-channel transistor or an n-channel transistor.

  Here, in the transistor 300 illustrated in FIG. 17, a semiconductor region 313 (a part of the substrate 311) in which a channel is formed has a convex shape. The conductor 316 is provided so as to cover the side surface and the top surface of the semiconductor region 313 with the insulator 315 interposed therebetween. Note that the conductor 316 may be formed using a material whose work function is adjusted. Such a transistor 300 is also called a FIN transistor because it utilizes a projection of a semiconductor substrate. Note that an insulator may be provided in contact with an upper portion of the projection and functioning as a mask for forming the projection. Although a case where a part of a semiconductor substrate is processed to form a convex portion is described here, a semiconductor film having a convex shape may be formed by processing an SOI substrate.

  Note that the transistor 300 illustrated in FIG. 17 is an example, and there is no limitation on the structure, and an appropriate transistor may be used depending on a circuit configuration and a driving method.

<Capacitance element 100>
The capacitor 100 is provided above the transistor 200. The capacitor 100 includes a conductor 110 functioning as a first electrode, a conductor 120 functioning as a second electrode, and an insulator 130 functioning as a dielectric.

  Further, for example, the conductor 112 provided over the conductor 246 and the conductor 110 can be formed at the same time. Note that the conductor 112 functions as a plug or a wiring which is electrically connected to the capacitor 100, the transistor 200, or the transistor 300.

  In FIG. 17, the conductor 112 and the conductor 110 have a single-layer structure; however, this embodiment is not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having a barrier property and a conductor having high adhesion to a conductor having a high conductivity may be formed between a conductor having a barrier property and a conductor having a high conductivity.

  The insulator 130 is formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, or hafnium nitride. Or the like may be used, and they can be provided in a stacked or single layer.

  For example, it is preferable that the insulator 130 have a stacked structure of a material with high dielectric strength, such as silicon oxynitride, and a high dielectric constant (high-k) material. With this structure, the capacitor 100 has an insulator with a high dielectric constant (high-k), so that sufficient capacitance can be secured. Since the capacitor 100 has an insulator with a large dielectric strength, the dielectric strength is improved, and the capacitance is improved. Electrostatic breakdown of the element 100 can be suppressed.

  Gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium are given as insulators of a high dielectric constant (high-k) material (a material having a high relative dielectric constant). , An oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium.

  On the other hand, materials having high dielectric strength (materials having a low dielectric constant) include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, carbon and nitrogen. There is silicon oxide added, silicon oxide having pores, or a resin.

<Wiring layer>
A wiring layer provided with an interlayer film, a wiring, a plug, and the like may be provided between the structures. Further, a plurality of wiring layers can be provided depending on the design. Here, a conductor having a function as a plug or a wiring may be given the same reference numeral by combining a plurality of structures. Further, in this specification and the like, a wiring and a plug that is electrically connected to the wiring may be integrated. That is, a part of the conductor functions as a wiring and a part of the conductor functions as a plug in some cases.

  For example, over the transistor 300, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films. In the insulator 320, the insulator 322, the insulator 324, and the insulator 326, a conductor 328 that is electrically connected to the capacitor 100 or the transistor 200, a conductor 330, or the like is embedded. Note that the conductor 328 and the conductor 330 function as plugs or wirings.

  Further, the insulator functioning as an interlayer film may function as a flattening film that covers the uneven shape below the insulator. For example, the upper surface of the insulator 322 may be planarized by a planarization process using a chemical mechanical polishing (CMP) method or the like to improve planarity.

  A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 17, an insulator 350, an insulator 352, and an insulator 354 are sequentially stacked. Further, a conductor 356 is formed over the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or a wiring.

  Similarly, the conductor 218, the conductor (the conductor 205) included in the transistor 200, and the like are embedded in the insulator 210, the insulator 212, the insulator 214, and the insulator 216. Note that the conductor 218 functions as a plug or a wiring which is electrically connected to the capacitor 100 or the transistor 300. Further, an insulator 150 is provided over the conductor 120 and the insulator 130.

  Examples of an insulator that can be used as the interlayer film include an oxide, a nitride, an oxynitride, a nitrided oxide, a metal oxide, a metal oxynitride, and a metal nitride oxide having an insulating property.

  For example, by using a material having a low relative dielectric constant for an insulator functioning as an interlayer film, parasitic capacitance generated between wirings can be reduced. Therefore, a material may be selected according to the function of the insulator.

  For example, the insulator 150, the insulator 210, the insulator 352, the insulator 354, or the like preferably includes an insulator having a low relative dielectric constant. For example, the insulator may include silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide or resin having holes, or the like. preferable. Alternatively, the insulator is silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having holes. And a resin. Since silicon oxide and silicon oxynitride are thermally stable, they can be combined with a resin to have a stacked structure that is thermally stable and has a low relative dielectric constant. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, and the like), polyimide, polycarbonate, and acryl.

  In addition, a transistor including an oxide semiconductor can have stable electrical characteristics by being surrounded by an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen. Therefore, an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen can be used for the insulator 214, the insulator 212, the insulator 350, and the like.

  Examples of the insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen include boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, and zirconium. , Lanthanum, neodymium, hafnium, or an insulator containing tantalum may be used as a single layer or a stacked layer. Specifically, as an insulator having a function of suppressing transmission of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or A metal oxide such as tantalum oxide, silicon nitride oxide, silicon nitride, or the like can be used.

  Conductors that can be used for wiring and plugs include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, and indium. A material containing at least one metal element selected from ruthenium and the like can be used. Alternatively, a semiconductor having high electric conductivity, represented by polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

  For example, as the conductor 328, the conductor 330, the conductor 356, the conductor 218, the conductor 112, and the like, a metal material, an alloy material, a metal nitride material, a metal oxide material, or the like formed using the above materials. Can be used as a single layer or a stacked layer. It is preferable to use a high melting point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and it is preferable to use tungsten. Alternatively, it is preferable to use a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, wiring resistance can be reduced.

<Wiring or plug in a layer provided with an oxide semiconductor>
Note that in the case where an oxide semiconductor is used for the transistor 200, an insulator having an excess oxygen region may be provided in the vicinity of the oxide semiconductor in some cases. In that case, an insulator having a barrier property is preferably provided between the insulator having the excess oxygen region and a conductor provided in the insulator having the excess oxygen region.

  For example, in FIG. 17, an insulator 276 may be provided between the insulator 224 containing excess oxygen and the conductor 245. When the insulator 276 is provided in contact with the insulator 222 and the insulator 272, the insulator 224 and the transistor 200 can have a structure in which the insulator 224 and the transistor 200 are sealed with an insulator having a barrier property. Further, it is preferable that the insulator 276 be in contact with part of the insulator 280. When the insulator 276 extends to the insulator 280, diffusion of oxygen and impurities can be further suppressed.

  That is, by providing the insulator 276, the excess oxygen included in the insulator 224 can be suppressed from being absorbed by the conductor 245. In addition, with the use of the insulator 276, diffusion of hydrogen which is an impurity to the transistor 200 through the conductor 245 can be suppressed.

  Note that as the insulator 276, an insulating material having a function of suppressing diffusion of impurities such as water or hydrogen and oxygen is preferably used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. In addition, for example, a metal oxide such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, or tantalum oxide, silicon nitride oxide, or silicon nitride can be used.

  The above is the description of the configuration example. With the use of this structure, in a semiconductor device including a transistor including an oxide semiconductor, change in electrical characteristics can be suppressed and reliability can be improved. Alternatively, a transistor including an oxide semiconductor with high on-state current can be provided. Alternatively, a transistor including an oxide semiconductor with low off-state current can be provided. Alternatively, a semiconductor device with reduced power consumption can be provided.

[Storage device 2]
FIG. 18 illustrates an example of a memory device using the semiconductor device of one embodiment of the present invention. The memory device illustrated in FIG. 18 includes a transistor 400 in addition to the semiconductor device including the transistor 200, the transistor 300, and the capacitor 100 illustrated in FIG.

  The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held in this structure, the voltage between the first gate and the source and the voltage between the second gate and the source of the transistor 400 become 0 V. In the transistor 400, the drain current when the second gate voltage and the first gate voltage are 0 V is extremely small; therefore, without supplying power to the transistor 200 and the transistor 400, the second gate of the transistor 200 A negative potential can be maintained for a long time. Thus, the memory device including the transistor 200 and the transistor 400 can hold stored data for a long time.

  Therefore, in FIG. 18, the wiring 1001 is electrically connected to the source of the transistor 300, and the wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and the drain of the transistor 200, the wiring 1004 is electrically connected to the gate of the transistor 200, and the wiring 1006 is electrically connected to the back gate of the transistor 200. . Further, the gate of the transistor 300 and the other of the source and the drain of the transistor 200 are electrically connected to one of the electrodes of the capacitor 100, and the wiring 1005 is electrically connected to the other of the electrodes of the capacitor 100. . The wiring 1007 is electrically connected to the source of the transistor 400; the wiring 1008 is electrically connected to the gate of the transistor 400; the wiring 1009 is electrically connected to the back gate of the transistor 400; Is electrically connected to Here, the wiring 1006, the wiring 1007, the wiring 1008, and the wiring 1009 are electrically connected.

  The memory device illustrated in FIG. 18 can form a memory cell array by being arranged in a matrix, similarly to the memory device illustrated in FIG. Note that one transistor 400 can control the second gate voltage of the plurality of transistors 200. Therefore, the number of the transistors 400 is preferably smaller than that of the transistor 200.

<Transistor 400>
The transistor 400 is formed in the same layer as the transistor 200 and can be manufactured in parallel. The transistor 400 includes a conductor 460 (a conductor 460a and a conductor 460b) functioning as a first gate, a conductor 405 (a conductor 405a and a conductor 405b) functioning as a second gate, An insulator 222 and an insulator 450 functioning as layers, an oxide 430c including a channel formation region, a conductor 442a, an oxide 443a, an oxide 431a, and an oxide 431b functioning as a source, and functioning as a drain The semiconductor device includes the conductor 442b, the oxide 443b, the oxide 432a, and the oxide 432b, and the conductor 440 (the conductor 440a and the conductor 440b) functioning as a plug.

  In the transistor 400, the conductor 405 is the same layer as the conductor 205. The oxide 431a and the oxide 432a are the same layer as the oxide 230a, and the oxide 431b and the oxide 432b are the same layer as the oxide 230b. The conductor 442 is the same layer as the conductor 242. The oxide 443 is the same layer as the oxide 243. The oxide 430c is the same layer as the oxide 230c. The insulator 450 is the same layer as the insulator 250. The conductor 460 is the same layer as the conductor 260.

  Note that the structures formed in the same layer can be formed at the same time. For example, the oxide 430c can be formed by processing an oxide film to be the oxide 230c.

  In the oxide 430c functioning as an active layer of the transistor 400, oxygen vacancies are reduced and impurities such as hydrogen and water are reduced as in the oxide 230 and the like. Accordingly, the threshold voltage of the transistor 400 is higher than 0 V, the off-state current is reduced, and the drain current when the second gate voltage and the first gate voltage are 0 V can be extremely low.

<Dicing line>
Hereinafter, a dicing line (which may be referred to as a scribe line, a division line, or a cutting line) provided when a large-area substrate is divided into semiconductor elements to take out a plurality of semiconductor devices in a chip shape will be described. . As a dividing method, for example, there is a case where a groove (dicing line) for dividing a semiconductor element is first formed on a substrate, and then cut along the dicing line to be divided (divided) into a plurality of semiconductor devices.

  Here, for example, as shown in FIG. 18, it is preferable to design a region where the insulator 272 and the insulator 222 are in contact with each other to be a dicing line. That is, an opening is provided in the insulator 224 in the vicinity of a memory cell including a plurality of transistors 200 and a region to be a dicing line provided at an outer edge of the transistor 400. Further, an insulator 272 is provided so as to cover a side surface of the insulator 224.

  That is, the insulator 222 and the insulator 272 are in contact with each other at the opening provided in the insulator 224. For example, at this time, the insulator 222 and the insulator 272 may be formed using the same material and the same method. When the insulator 222 and the insulator 272 are provided using the same material and the same method, adhesion can be improved. For example, it is preferable to use aluminum oxide.

  With the structure, the insulator 224, the transistor 200, and the transistor 400 can be covered with the insulator 222 and the insulator 272. Since the insulator 222 and the insulator 272 have a function of suppressing diffusion of oxygen, hydrogen, and water, the substrate is divided for each circuit region where the semiconductor element described in this embodiment is formed. Accordingly, even when the chip is processed into a plurality of chips, impurities such as hydrogen or water can be prevented from entering the transistor 200 and the transistor 400 from the lateral direction of the separated substrate.

  Further, with this structure, excess oxygen in the insulator 224 can be prevented from diffusing to the outside through the insulator 272 and the insulator 222. Accordingly, the excess oxygen in the insulator 224 is efficiently supplied to the oxide in which the channel in the transistor 200 or the transistor 400 is formed. With the use of the oxygen, oxygen vacancies in the oxide in which a channel in the transistor 200 or the transistor 400 is formed can be reduced. Accordingly, the oxide in which the channel is formed in the transistor 200 or the transistor 400 can be an oxide semiconductor having low density of defect states and stable characteristics. That is, change in electrical characteristics of the transistor 200 or the transistor 400 can be suppressed and reliability can be improved.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 3)
In this embodiment, a transistor including an oxide as a semiconductor (hereinafter, may be referred to as an OS transistor) and a capacitor according to one embodiment of the present invention are described with reference to FIGS. A storage device (hereinafter, may be referred to as an OS memory device) that is located will be described. An OS memory device is a storage device including at least a capacitor and an OS transistor that controls charging and discharging of the capacitor. Since the off-state current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a nonvolatile memory.

<Configuration example of storage device>
FIG. 19A illustrates an example of a configuration of an OS memory device. The storage device 1400 includes a peripheral circuit 1411 and a memory cell array 1470. The peripheral circuit 1411 includes a row circuit 1420, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460.

  The column circuit 1430 includes, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, and the like. The precharge circuit has a function of precharging a wiring. The sense amplifier has a function of amplifying a data signal read from a memory cell. Note that the above wiring is a wiring connected to a memory cell included in the memory cell array 1470, and will be described later in detail. The amplified data signal is output to the outside of the storage device 1400 as a data signal RDATA via the output circuit 1440. The row circuit 1420 includes, for example, a row decoder, a word line driver circuit, and the like, and can select a row to be accessed.

  A low power supply voltage (VSS), a high power supply voltage (VDD) for the peripheral circuit 1411, and a high power supply voltage (VIL) for the memory cell array 1470 are externally supplied to the storage device 1400. Further, a control signal (CE, WE, RE), an address signal ADDR, and a data signal WDATA are externally input to the storage device 1400. The address signal ADDR is input to a row decoder and a column decoder, and WDATA is input to a write circuit.

  The control logic circuit 1460 processes an external input signal (CE, WE, RE) to generate a control signal for a row decoder and a column decoder. CE is a chip enable signal, WE is a write enable signal, and RE is a read enable signal. The signal processed by the control logic circuit 1460 is not limited to this, and another control signal may be input as needed.

  The memory cell array 1470 has a plurality of memory cells MC and a plurality of wirings arranged in a matrix. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cells MC, the number of memory cells MC in one column, and the like. Further, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cells MC, the number of memory cells MC included in one row, and the like.

  Note that FIG. 19A illustrates an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane; however, this embodiment is not limited to this. For example, as illustrated in FIG. 19B, a memory cell array 1470 may be provided over part of a peripheral circuit 1411. For example, a structure in which a sense amplifier is provided so as to overlap below the memory cell array 1470 may be employed.

  FIG. 20 illustrates a configuration example of a memory cell applicable to the above-described memory cell MC.

[DOSRAM]
20A to 20C show circuit configuration examples of a memory cell of a DRAM. In this specification and the like, a DRAM including a memory cell of one OS transistor and one capacitor may be referred to as a DOSRAM (Dynamic Oxide Semiconductor Random Access Memory). A memory cell 1471 illustrated in FIG. 20A includes a transistor M1 and a capacitor CA. Note that the transistor M1 has a gate (sometimes called a front gate) and a back gate.

  A first terminal of the transistor M1 is connected to a first terminal of the capacitor CA, a second terminal of the transistor M1 is connected to a wiring BIL, a gate of the transistor M1 is connected to a wiring WOL, and a back gate of the transistor M1. Are connected to the wiring BGL. The second terminal of the capacitor CA is connected to the wiring CAL.

  The wiring BIL functions as a bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CA. It is preferable that a low-level potential be applied to the wiring CAL during data writing and data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M1. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M1 can be increased or decreased.

  Further, the memory cell MC is not limited to the memory cell 1471, and the circuit configuration can be changed. For example, the memory cell MC may have a structure in which the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL as in a memory cell 1472 illustrated in FIG. For example, the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M1 without a back gate, like the memory cell 1473 illustrated in FIG. 20C.

  In the case where the semiconductor device described in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1 and the capacitor 100 can be used as the capacitor CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be extremely low. That is, the written data can be held for a long time by the transistor M1, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leak current is extremely low, multi-valued data or analog data can be held in the memory cell 1471, the memory cell 1472, and the memory cell 1473.

  In the DOSRAM, as described above, when the sense amplifier is provided so as to overlap below the memory cell array 1470, the bit line can be shortened. As a result, the bit line capacity is reduced, and the storage capacity of the memory cell can be reduced.

[NOSRAM]
FIGS. 20D to 20H show circuit configuration examples of a gain cell memory cell having two transistors and one capacitor. The memory cell 1474 illustrated in FIG. 20D includes a transistor M2, a transistor M3, and a capacitor CB. Note that the transistor M2 has a front gate (which may be simply referred to as a gate) and a back gate. In this specification and the like, a storage device including a gain cell memory cell including an OS transistor as the transistor M2 may be referred to as a NOSRAM (Nonvolatile Oxide Semiconductor RAM).

  A first terminal of the transistor M2 is connected to a first terminal of the capacitor CB, a second terminal of the transistor M2 is connected to a wiring WBL, a gate of the transistor M2 is connected to a wiring WOL, and a back gate of the transistor M2. Are connected to the wiring BGL. The second terminal of the capacitor CB is connected to the wiring CAL. A first terminal of the transistor M3 is connected to the wiring RBL, a second terminal of the transistor M3 is connected to the wiring SL, and a gate of the transistor M3 is connected to a first terminal of the capacitor CB.

  The wiring WBL functions as a write bit line, the wiring RBL functions as a read bit line, and the wiring WOL functions as a word line. The wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of the capacitor CB. It is preferable that a low-level potential be applied to the wiring CAL during data writing, data holding, and data reading. The wiring BGL functions as a wiring for applying a potential to the back gate of the transistor M2. By applying an arbitrary potential to the wiring BGL, the threshold voltage of the transistor M2 can be increased or decreased.

  Further, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration can be changed as appropriate. For example, the memory cell MC may have a structure in which the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL as in a memory cell 1475 illustrated in FIG. For example, the memory cell MC may be a single-gate transistor, that is, a memory cell including a transistor M2 without a back gate, like the memory cell 1476 illustrated in FIG. For example, the memory cell MC may have a structure in which the wiring WBL and the wiring RBL are combined as one wiring BIL as in a memory cell 1477 illustrated in FIG.

  In the case where the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, the transistor 200 can be used as the transistor M2, the transistor 300 can be used as the transistor M3, and the capacitor 100 can be used as the capacitor CB. By using an OS transistor as the transistor M2, the leakage current of the transistor M2 can be extremely low. Thus, the written data can be held for a long time by the transistor M2, so that the frequency of refreshing the memory cell can be reduced. Further, the refresh operation of the memory cell can be made unnecessary. Further, since the leakage current is extremely low, multi-valued data or analog data can be held in the memory cell 1474. The same applies to memory cells 1475 to 1477.

  Note that the transistor M3 may be a transistor including silicon in a channel formation region (hereinafter, may be referred to as a Si transistor). The conductivity type of the Si transistor may be an n-channel type or a p-channel type. The Si transistor may have higher field-effect mobility than the OS transistor. Therefore, a Si transistor may be used as the transistor M3 functioning as a reading transistor. In addition, by using a Si transistor as the transistor M3, the transistor M2 can be provided over the transistor M3, so that the area occupied by the memory cell can be reduced and the memory device can be highly integrated.

  Further, the transistor M3 may be an OS transistor. In the case where OS transistors are used for the transistors M2 and M3, a circuit can be formed using the memory cell array 1470 using only n-type transistors.

  FIG. 20H illustrates an example of a gain cell memory cell including three transistors and one capacitor. The memory cell 1478 illustrated in FIG. 20H includes transistors M4 to M6 and a capacitor CC. The capacitor CC is provided as appropriate. The memory cell 1478 is electrically connected to the wirings BIL, RWL, WWL, BGL, and GNDL. The wiring GNDL is a wiring that applies a low-level potential. Note that the memory cell 1478 may be electrically connected to the wirings RBL and WBL instead of the wiring BIL.

  The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to the wiring BGL. Note that the back gate and the gate of the transistor M4 may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate.

  Note that each of the transistors M5 and M6 may be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, a circuit can be formed using the memory cell array 1470 using only n-type transistors.

  In the case where the semiconductor device described in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor 100 can be used as the capacitor CC. When an OS transistor is used as the transistor M4, the leakage current of the transistor M4 can be extremely low.

  Note that the structures of the peripheral circuit 1411, the memory cell array 1470, and the like described in this embodiment are not limited to the above. Arrangement or function of these circuits and wirings, circuit elements, and the like connected to the circuits may be changed, deleted, or added as necessary.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 4)
In this embodiment, an example of a chip 1200 in which the semiconductor device of the present invention is mounted is described with reference to FIGS. A plurality of circuits (systems) are mounted on the chip 1200. Such a technique of integrating a plurality of circuits (systems) on a single chip may be referred to as a system-on-chip (SoC).

  As shown in FIG. 21A, a chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or a plurality of analog operation units 1213, one or a plurality of memory controllers 1214, one or a plurality of Interface 1215, one or a plurality of network circuits 1216, and the like.

  The chip 1200 is provided with bumps (not shown) and is connected to a first surface of a printed circuit board (PCB) 1201 as shown in FIG. In addition, a plurality of bumps 1202 are provided on the back surface of the first surface of the PCB 1201, and are connected to the motherboard 1203.

  The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM described in the above embodiment can be used as the DRAM 1221. For example, the NOSRAM described in the above embodiment can be used for the flash memory 1222.

  The CPU 1211 preferably has a plurality of CPU cores. Further, the GPU 1212 preferably has a plurality of GPU cores. Further, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. As the memory, the above-described NOSRAM or DOSRAM can be used. In addition, the GPU 1212 is suitable for parallel calculation of a large number of data, and can be used for image processing and product-sum operation. By providing the GPU 1212 with an image processing circuit or a product-sum operation circuit using the oxide semiconductor of the present invention, image processing and product-sum operation can be performed with low power consumption.

  In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, wiring between the CPU 1211 and the GPU 1212 can be shortened, data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, After the calculation by the GPU 1212, the calculation result can be transferred from the GPU 1212 to the CPU 1211 at high speed.

  The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Further, the above-described product-sum operation circuit may be provided in the analog operation unit 1213.

  The memory controller 1214 includes a circuit functioning as a controller of the DRAM 1221 and a circuit functioning as an interface of the flash memory 1222.

  The interface 1215 has an interface circuit with an external device such as a display device, a speaker, a microphone, a camera, or a controller. The controller includes a mouse, a keyboard, a game controller, and the like. USB (Universal Serial Bus), HDMI (registered trademark) (High-Definition Multimedia Interface), or the like can be used as such an interface.

  The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). Further, a circuit for network security may be provided.

  The circuit (system) can be formed on the chip 1200 by the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, the number of manufacturing processes does not need to be increased, and the chip 1200 can be manufactured at low cost.

  The PCB 1201 provided with the chip 1200 having the GPU 1212, the DRAM 1221, and the motherboard 1203 provided with the flash memory 1222 can be referred to as a GPU module 1204.

  Since the GPU module 1204 has the chip 1200 using the SoC technology, the size can be reduced. In addition, since it is excellent in image processing, it is preferably used for portable electronic devices such as smartphones, tablet terminals, laptop PCs, and portable (portable) game machines. In addition, a product-sum operation circuit using the GPU 1212 allows a deep neural network (DNN), a convolutional neural network (CNN), a recursive neural network (RNN), a self-encoder, a deep Boltzmann machine (DBM), a deep belief network ( Since operations such as DBN) can be performed, the chip 1200 can be used as an AI chip or the GPU module 1204 can be used as an AI system module.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 5)
In this embodiment, an application example of a memory device including the semiconductor device described in the above embodiment will be described. The semiconductor device described in the above embodiment is, for example, a storage device of various electronic devices (for example, an information terminal, a computer, a smartphone, an electronic book terminal, a digital camera (including a video camera), a recording and playback device, a navigation system, and the like). Applicable to Here, the computer includes a tablet computer, a notebook computer, a desktop computer, and a large computer such as a server system. Alternatively, the semiconductor device described in the above embodiment is applied to various types of removable storage devices such as a memory card (for example, an SD card), a USB memory, and an SSD (solid state drive). FIG. 22 schematically illustrates some configuration examples of the removable storage device. For example, the semiconductor device described in any of the above embodiments is processed into a packaged memory chip, and used for various storage devices and removable memories.

  FIG. 22A is a schematic diagram of a USB memory. The USB memory 1100 includes a housing 1101, a cap 1102, a USB connector 1103, and a board 1104. The substrate 1104 is housed in the housing 1101. For example, a memory chip 1105 and a controller chip 1106 are attached to the substrate 1104. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1105 or the like of the substrate 1104.

  FIG. 22B is a schematic diagram of the external appearance of the SD card, and FIG. 22C is a schematic diagram of the internal structure of the SD card. The SD card 1110 has a housing 1111, a connector 1112, and a board 1113. The substrate 1113 is housed in the housing 1111. For example, a memory chip 1114 and a controller chip 1115 are attached to the substrate 1113. By providing the memory chip 1114 also on the back side of the substrate 1113, the capacity of the SD card 1110 can be increased. Further, a wireless chip having a wireless communication function may be provided over the substrate 1113. Thus, data can be read from and written to the memory chip 1114 by wireless communication between the host device and the SD card 1110. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1114 or the like of the substrate 1113.

  FIG. 22D is a schematic diagram of the external appearance of the SSD, and FIG. 22E is a schematic diagram of the internal structure of the SSD. The SSD 1150 includes a housing 1151, a connector 1152, and a board 1153. The substrate 1153 is housed in the housing 1151. For example, a memory chip 1154, a memory chip 1155, and a controller chip 1156 are attached to the substrate 1153. The memory chip 1155 is a work memory of the controller chip 1156, and for example, a DOSRAM chip may be used. By providing the memory chip 1154 also on the back surface side of the substrate 1153, the capacity of the SSD 1150 can be increased. The semiconductor device described in the above embodiment can be incorporated in the memory chip 1154 or the like of the substrate 1153.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

(Embodiment 6)
In this embodiment, specific examples of electronic devices that can be applied to the semiconductor device of one embodiment of the present invention will be described with reference to FIGS.

  More specifically, the semiconductor device according to one embodiment of the present invention can be used for a processor such as a CPU or a GPU or a chip. FIG. 23 illustrates a specific example of an electronic device including a processor such as a CPU or a GPU or a chip according to one embodiment of the present invention.

<Electronic equipment and systems>
The GPU or the chip according to one embodiment of the present invention can be mounted on various electronic devices. Examples of the electronic device include a relatively large game machine such as a television device, a desktop or notebook personal computer, a monitor for a computer, a digital signage (digital signage), and a large game machine such as a pachinko machine. In addition to an electronic device having a screen, a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, a sound reproducing device, and the like can be given. In addition, by providing an integrated circuit or a chip according to one embodiment of the present invention in an electronic device, artificial intelligence can be mounted on the electronic device.

  The electronic device of one embodiment of the present invention may include an antenna. By receiving a signal with the antenna, an image, information, or the like can be displayed on the display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for wireless power transmission.

  The electronic device of one embodiment of the present invention includes sensors (force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, (Including a function of measuring voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared light).

  The electronic device of one embodiment of the present invention can have various functions. For example, a function of displaying various information (still images, moving images, text images, etc.) on the display unit, a touch panel function, a function of displaying a calendar, date or time, a function of executing various software (programs), a wireless communication It can have a function, a function of reading a program or data recorded on a recording medium, and the like. FIG. 23 illustrates an example of an electronic device.

[mobile phone]
FIG. 23A illustrates a mobile phone (smartphone) which is a kind of information terminal. The information terminal 5500 includes a housing 5510 and a display portion 5511. A touch panel is provided in the display portion 5511 as an input interface, and buttons are provided in the housing 5510.

  The information terminal 5500 can execute an application using artificial intelligence by applying the chip of one embodiment of the present invention. Examples of the application using artificial intelligence include an application that recognizes a conversation and displays the content of the conversation on a display portion 5511, and recognizes characters, graphics, and the like input by a user on a touch panel provided in the display portion 5511, An application displayed on the display portion 5511, an application for performing biometric authentication such as a fingerprint or a voiceprint, and the like can be given.

[Information terminal 1]
FIG. 23B illustrates a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display 5302, and a keyboard 5303.

  The desktop information terminal 5300 can execute an application utilizing artificial intelligence by applying the chip of one embodiment of the present invention, similarly to the information terminal 5500 described above. Examples of applications using artificial intelligence include design support software, text correction software, menu automatic generation software, and the like. In addition, by using the desktop information terminal 5300, a new artificial intelligence can be developed.

  Note that, in the above description, a smartphone and a desktop information terminal are illustrated as examples in FIGS. 23A and 23B, respectively. However, an information terminal other than the smartphone and the desktop information terminal may be applied. it can. Examples of the information terminal other than the smartphone and the desktop information terminal include a PDA (Personal Digital Assistant), a notebook information terminal, and a workstation.

[Electric appliances]
FIG. 23C illustrates an electric refrigerator-freezer 5800 which is an example of an electric appliance. The electric refrigerator-freezer 5800 includes a housing 5801, a refrigerator door 5802, a refrigerator door 5803, and the like.

  By applying the chip of one embodiment of the present invention to the electric refrigerator-freezer 5800, the electric refrigerator-freezer 5800 having artificial intelligence can be realized. By utilizing artificial intelligence, the electric refrigerator-freezer 5800 has a function of automatically generating menus based on the ingredients stored in the electric refrigerator-freezer 5800, the expiration date of the ingredients, and the like, and is stored in the electric refrigerator-freezer 5800. It can have a function of automatically adjusting the temperature to the food material.

  In this example, the electric refrigerator-freezer has been described as an electric appliance. Utensils, washing machines, dryers, audiovisual equipment and the like.

[game machine]
FIG. 23D illustrates a portable game machine 5200 which is an example of a game machine. The portable game machine includes a housing 5201, a display portion 5202, a button 5203, and the like.

  By applying the GPU or the chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 with low power consumption can be realized. In addition, heat generation from a circuit can be reduced by low power consumption, so that influence of the heat generation on the circuit itself, peripheral circuits, and modules can be reduced.

  Further, by applying the GPU or the chip of one embodiment of the present invention to the portable game machine 5200, the portable game machine 5200 having artificial intelligence can be realized.

  Originally, the expression of the progress of the game, the behavior of the creature appearing in the game, the phenomenon occurring in the game, etc. is determined by the program of the game, but by applying artificial intelligence to the portable game machine 5200, Thus, expressions that are not limited to game programs are possible. For example, it is possible to express such a content that a player asks a question, a progress of a game, a time, a behavior of a person appearing in the game changes.

  In addition, when a game requiring a plurality of players is performed on the portable game machine 5200, a game player can be configured as an anthropomorphic person by artificial intelligence. Can play games.

  FIG. 23D illustrates a portable game machine as an example of a game machine; however, a game machine to which the GPU or the chip of one embodiment of the present invention is applied is not limited thereto. As a game machine to which the GPU or the chip of one embodiment of the present invention is applied, for example, a stationary game machine for home use, an arcade game machine installed in an entertainment facility (a game center, an amusement park, or the like), or a sport facility Pitching machine for batting practice.

[Mobile]
The GPU or the chip of one embodiment of the present invention can be applied to an automobile which is a mobile object and a periphery of a driver's seat of the automobile.

  FIG. 23E1 illustrates an automobile 5700 which is an example of a moving object, and FIG. 23E2 illustrates an area around a windshield in the interior of the automobile. FIG. 23E2 illustrates a display panel 5701, a display panel 5702, and a display panel 5703 attached to a dashboard, and a display panel 5704 attached to a pillar.

  The display panels 5701 to 5703 can provide various kinds of information such as a speedometer, a tachometer, a traveling distance, a refueling amount, a gear state, and setting of an air conditioner. Further, display items, layouts, and the like displayed on the display panel can be appropriately changed in accordance with the user's preference, and the design can be improved. The display panels 5701 to 5703 can also be used as lighting devices.

  By displaying an image from an imaging device (not shown) provided in the car 5700 on the display panel 5704, the field of view (blind spot) blocked by the pillar can be complemented. That is, by displaying an image from an imaging device provided outside the automobile 5700, blind spots can be compensated and safety can be improved. In addition, by displaying an image that complements an invisible part, safety can be confirmed more naturally and without a sense of incongruity. The display panel 5704 can be used as a lighting device.

  Since the GPU or the chip of one embodiment of the present invention can be applied as a component of artificial intelligence, the chip or the chip can be used for an automatic driving system of an automobile 5700, for example. Further, the chip can be used in a system for performing road guidance, danger prediction, and the like. The display panels 5701 to 5704 may be configured to display information such as road guidance and danger prediction.

  In the above description, a car is described as an example of a moving body, but the moving body is not limited to a car. For example, examples of a moving object include a train, a monorail, a ship, and a flying object (a helicopter, an unmanned aerial vehicle (drone), an airplane, a rocket), and the like. The chip of one embodiment of the present invention is applied to these moving objects. Thus, a system using artificial intelligence can be provided.

[Broadcasting system]
The GPU or the chip of one embodiment of the present invention can be applied to a broadcast system.

  FIG. 23F schematically shows data transmission in a broadcast system. Specifically, FIG. 23F illustrates a path until a radio wave (broadcast signal) transmitted from the broadcast station 5680 reaches a television receiver (TV) 5600 in each home. The TV 5600 includes a receiving device (not shown), and a broadcast signal received by the antenna 5650 is transmitted to the TV 5600 via the receiving device.

  FIG. 23F illustrates an UHF (Ultra High Frequency) antenna as the antenna 5650, but a BS / 110 ° CS antenna, a CS antenna, or the like can be used as the antenna 5650.

  The radio waves 5675A and 5675B are broadcast signals for terrestrial broadcasting, and the radio tower 5670 amplifies the received radio wave 5675A and transmits the radio wave 5675B. At each home, a terrestrial TV broadcast can be viewed on the TV 5600 by receiving the radio wave 5675B with the antenna 5650. Note that the broadcasting system is not limited to the terrestrial broadcasting shown in FIG. 23F, and may be a satellite broadcasting using an artificial satellite, a data broadcasting using an optical line, or the like.

  The above-described broadcasting system may be a broadcasting system using artificial intelligence to which the chip of one embodiment of the present invention is applied. When the broadcast data is transmitted from the broadcast station 5680 to the TV 5600 of each home, the broadcast data is compressed by the encoder. When the antenna 5650 receives the broadcast data, the decoder of the receiving device included in the TV 5600 decodes the broadcast data. Restore is performed. By using artificial intelligence, for example, in a motion compensation prediction which is one of the compression methods of an encoder, a display pattern included in a display image can be recognized. In addition, it is also possible to perform intra-frame prediction using artificial intelligence. Further, for example, when receiving broadcast data having a low resolution and displaying the broadcast data on a TV 5600 having a high resolution, an image interpolation process such as up-conversion can be performed in the restoration of the broadcast data by the decoder.

  The above-described broadcasting system using artificial intelligence is suitable for ultra-high definition television (UHDTV: 4K, 8K) broadcasting in which the amount of broadcast data increases.

  Further, as an application of artificial intelligence on the TV 5600 side, for example, a recording device having artificial intelligence may be provided in the TV 5600. With such a configuration, the recording device can automatically record a program that meets the user's preference by causing the artificial intelligence to learn the user's preference.

  The electronic device described in this embodiment, functions of the electronic device, application examples of artificial intelligence, effects thereof, and the like can be combined with descriptions of other electronic devices as appropriate.

  The structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

  In this example, a sample containing a metal oxide was prepared, and the carrier concentration of the metal oxide was measured. The carrier concentration of the metal oxide was measured using a Hall effect meter.

  A method for manufacturing a sample will be described. First, a 40-nm-thick metal oxide was formed over a quartz substrate by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Next, heat treatment was performed in a nitrogen atmosphere at a temperature of 400 ° C. for one hour, and in an oxygen atmosphere, heat treatment was performed at a temperature of 400 ° C. for one hour. Next, a 110-nm-thick silicon oxynitride film was formed over the metal oxide by a CVD method.

  Here, the sample was divided into three samples, Sample A, Sample B, and Sample C. Sample A was not subjected to heat treatment, and Sample B was subjected to heat treatment at 350 ° C. for 1 hour in a nitrogen atmosphere. Sample C was subjected to a heat treatment at 350 ° C. for 24 hours in a nitrogen atmosphere.

  Next, the carrier concentration of each of Sample A, Sample B, and Sample C was measured using a Hall effect meter.

FIG. 24 shows a graph of the carrier concentration measurement result of each sample. Sample A, which was not subjected to the heat treatment, was 1.8 × 10 ²⁰ / cm ³ , and Sample B, which was subjected to a heat treatment at 350 ° C. for 1 hour in a nitrogen atmosphere, was 5.6 × 10 ¹⁹ / cm ^3. Sample C that had been subjected to a heat treatment at 350 ° C. for 24 hours in a nitrogen atmosphere was 3.0 × 10 ¹⁸ / cm ³ .

  From the above results, by performing the heat treatment at a temperature of 350 ° C. in a nitrogen atmosphere, the carrier concentration of the metal oxide is reduced, and the longer the heat treatment time, the lower the carrier concentration. Was confirmed.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

  In this example, a sample containing a metal oxide was prepared, and the hydrogen concentration in the metal oxide was measured. The hydrogen concentration in the metal oxide was measured using secondary ion mass spectrometry (SIMS).

  A method for manufacturing a sample will be described. First, a silicon oxide film having a thickness of 100 nm was formed on a silicon substrate by a thermal oxidation method. Next, a 40-nm-thick metal oxide was formed by a sputtering method using a target of In: Ga: Zn = 4: 2: 4.1 [atomic ratio]. Next, heat treatment was performed in a nitrogen atmosphere at a temperature of 400 ° C. for one hour, and in an oxygen atmosphere, heat treatment was performed at a temperature of 400 ° C. for one hour. Next, a 110-nm-thick silicon oxynitride film was formed over the metal oxide by a CVD method.

  Here, the sample was divided into three samples, Sample D, Sample E, and Sample F. Sample D was not subjected to heat treatment, and Sample E was subjected to heat treatment at 350 ° C. for 1 hour in a nitrogen atmosphere. The sample F was subjected to a heat treatment at 350 ° C. for 24 hours in a nitrogen atmosphere.

  Next, SIMS analysis was performed on Sample D, Sample E, and Sample F, and the hydrogen concentration profile in the metal oxide of each sample was measured. The analysis was performed from the back surface to the front surface of the sample, and the amount of hydrogen in the metal oxide was determined.

FIG. 25 shows a profile of the hydrogen concentration of each sample. The hydrogen concentration in the metal oxide of Sample D is approximately 1 × 10 ²⁰ atoms / cm ³ , the hydrogen concentration in the metal oxide of Sample E is approximately 8 × 10 ¹⁹ atoms / cm ³ , and the metal concentration of Sample F is The hydrogen concentration in the oxide was approximately 5 × 10 ¹⁹ atoms / cm ³ . That is, the hydrogen concentration of the sample D that was not subjected to the heat treatment was the highest, and the hydrogen concentration of the sample E that was subjected to the heat treatment at 350 ° C. for 1 hour in the nitrogen atmosphere was lower than that of the sample D, and the hydrogen concentration was lower than the sample D. Sample F that had been subjected to a heat treatment at a temperature of 350 ° C. for 24 hours was lower than Sample E.

  From the above results, by performing the heat treatment at 350 ° C. in a nitrogen atmosphere, the hydrogen concentration in the metal oxide is reduced, and the longer the heat treatment time, the further the hydrogen concentration is reduced. It was confirmed that.

  The structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and examples.

In this example, when hydrogen and excess oxygen located in oxygen vacancies were present in the metal oxide, whether or not hydrogen located in the oxygen vacancies escaped from the oxygen vacancies was evaluated by calculation. Specifically, in IGZO having surplus oxygen at one oxygen site, a hydrogen atom located in an oxygen vacancy requires energy (also referred to as an activation barrier) required to escape from the oxygen vacancy and frequency of exiting from the oxygen vacancy. Was calculated. Here, a hydrogen atom located in the oxygen vacancy is referred to as H 2 _O (sometimes referred to as V _O H). Further, one of the oxygen atoms present at the oxygen site is referred to as surplus oxygen for convenience.

  Using a NEB (Nudged Elastic Band) method, the energy change in the movement path of hydrogen atoms and excess oxygen until a hydrogen atom located in the oxygen vacancy escapes from the oxygen vacancy and bonds with an oxygen atom near the oxygen vacancy is calculated. did. For the calculation, first-principles calculation software VASP (The Vienna Ab initio simulation package) was used. Table 1 shows the calculation conditions.

  FIG. 26A shows a model in an initial state, and FIG. 26B shows a model in a final state. Here, the initial state is a state in which a hydrogen atom is located in an oxygen vacancy and excess oxygen exists near the oxygen vacancy. Note that the surplus oxygen is close to the oxygen vacancy and is present at an oxygen site in the In layer. That is, as indicated by a broken line in FIG. 26A, two oxygen atoms (one of which is surplus oxygen) exist in the oxygen site. The final state is a state in which a hydrogen atom is bonded to an oxygen atom bonded to one Ga and two Zns. That is, in the final state, the oxygen deficiency is compensated (restored) by the excess oxygen.

Hydrogen located in an oxygen vacancy and a hydrogen atom bonded to an oxygen atom may function as a donor which emits electrons. Therefore, the calculation is performed by setting the number of electrons in the model to be a number obtained by subtracting 1 from the original number of electrons. Thus, in the model in the initial state and the model in the final state, the highest level occupied by electrons is the level at the upper end of the valence band.

FIG. 27 shows a change in energy of each model when the model changes from the initial state to the final state. The horizontal axis in FIG. 27 is the movement distance [nm] between the hydrogen atom and the middle point of surplus oxygen. The vertical axis in FIG. 27 is the energy [eV] of each model, with the energy of the model in the final state as a reference (0.0 eV). From FIG. 27, if the excess oxygen is present in the vicinity of the oxygen deficiency, activation barrier E _a at the time of the hydrogen atoms located inside the oxygen vacancies get out of oxygen vacancies was about 0.36 eV.

Next, if the excess oxygen is present in the vicinity of the oxygen deficiency, the frequency with which the hydrogen atom located in the oxygen vacancies get out of oxygen deficiency gamma, using Equation 1, the obtained value of activation barrier E _a by calculation Calculated.

Here, _{k B} is the Boltzmann constant, T is the absolute temperature [K], [nu denotes a frequency factor. Also assume that the frequency factor ν = 10 ¹³ s ⁻¹ .

The frequency Γ was about 8.3 × 10 ⁶ times per hour at room temperature (27 ° C.). This suggests that the presence of excess oxygen near the oxygen vacancy causes hydrogen atoms located in the oxygen vacancy to escape from the oxygen vacancy.

  From the above, it was found that hydrogen located in the oxygen vacancy escapes from the oxygen vacancy due to excess oxygen. It was also found that hydrogen that escaped from oxygen vacancies was easily released from the metal oxide.

  As described above, the structures, structures, methods, and the like described in this embodiment can be combined as appropriate with any of the structures, structures, methods, and the like described in the other embodiments and other examples.

DESCRIPTION OF SYMBOLS 10 Oxide semiconductor, 20 conductor, 22 solid solution region of oxygen, 30 oxide, 100 capacitor element, 110 conductor, 112 conductor, 120 conductor, 130 insulator, 150 insulator, 200 transistor, 205 conductor, 205a conductor, 205b conductor, 205c conductor, 205d conductor, 205e conductor, 205f conductor, 205g conductor, 210 insulator, 212 insulator, 214 insulator, 216 insulator, 218 conductor, 222 insulation Body, 224 insulator, 224A insulating film, 230 oxide, 230a oxide, 230A oxide film, 230b oxide, 230B oxide film, 230c oxide, 230C oxide film, 240 conductor, 240a conductor, 240b conductor, 241 Insulator, 241a insulator, 241b insulator, 242 conductor, 242a conductor, 242A conductive film, 242b conductor, 242B conductor layer, 243 oxide, 243a oxide, 243A oxide film, 243b oxide, 243B oxidation Object layer, 245 conductor, 246 conductor, 246a conductor, 246b conductor, 250 insulator, 250A insulating film, 260 conductor, 260a conductor, 260Aa conductive film, 260Ab conductive film, 260b conductor, 272 insulator 272A insulator, 273A insulator, 273A insulator, 274 insulator, 276 insulator, 280 insulator, 281 insulator, 282 insulator, 283 insulator, 300 transistor, 311 substrate, 313 semiconductor region, 14a low resistance region, 314b low resistance region, 315 insulator, 316 conductor, 320 insulator, 322 insulator, 324 insulator, 326 insulator, 328 conductor, 330 conductor, 350 insulator, 352 insulator, 354 insulator, 356 conductor, 400 transistor, 405 conductor, 405a conductor, 405b conductor, 430c oxide, 431a oxide, 431b oxide, 432a oxide, 432b oxide, 440 conductor, 440a conductor 440b conductor, 442 conductor, 442a conductor, 442b conductor, 443 oxide, 443a oxide, 443b oxide, 450 insulator, 460 conductor, 460a conductor, 460b conductor, 1001 wiring, 10 02 wiring, 1003 wiring, 1004 wiring, 1005 wiring, 1006 wiring, 1007 wiring, 1008 wiring, 1009 wiring, 1010 wiring

Claims (10)

Forming a first insulator on the substrate,
Forming a first oxide film, a second oxide film, and a first conductive film on the first insulator in order;
Processing the first oxide film, the second oxide film, and the first conductive film to form a first oxide, an oxide layer, and a conductor layer;
A first insulating film and a second insulating film are sequentially formed to cover the first oxide, the oxide layer, and the conductor layer;
Forming an opening in which the first oxide is exposed in the oxide layer, the conductor layer, the first insulating film, and the second insulating film;
Forming a second oxide, a third oxide, a first conductor, a second conductor, a second insulator, and a third insulator;
Forming a third oxide film, a third insulating film, and a second conductive film in this order;
By performing a planarization process, the third oxide film, the third insulating film, and the second conductive film are removed until a part of the third insulator is exposed, and a fourth oxide film is removed. Forming a fourth insulator and a third conductor;
Perform a first heat treatment,
Perform a second heat treatment,
Forming a fourth insulating film on the third conductor;
A method for manufacturing a semiconductor device, comprising: In claim 1,
The method for manufacturing a semiconductor device, wherein the first heat treatment is performed at 300 ° C. or higher and 450 ° C. or lower in a nitrogen atmosphere. In claim 1 or claim 2,
The method for manufacturing a semiconductor device, wherein the first heat treatment is performed for one hour or more. In any one of claims 1 to 3,
The method for manufacturing a semiconductor device, wherein the second heat treatment and the formation of the fourth insulating film are sequentially performed under reduced pressure. In any one of claims 1 to 4,
The method for manufacturing a semiconductor device, wherein the fourth insulator includes one of aluminum oxide and silicon nitride. In any one of claims 1 to 5,
The fourth insulator includes a first material and a second material,
The method for manufacturing a semiconductor device, wherein the first material is located below the second material and is in contact with a lower surface of the second material. In any one of claims 1 to 6,
The first material comprises aluminum oxide;
The second material comprises silicon nitride;
The method for manufacturing a semiconductor device, wherein the second material is different from the first material. In any one of claims 1 to 7,
The method for manufacturing a semiconductor device, wherein the first to fourth oxides include In, an element M (M is Al, Ga, Y, or Sn), and Zn. A first insulator;
A first oxide on the first insulator;
A second oxide and a third oxide on the first oxide;
A first conductor on the second oxide;
A second conductor on the third oxide;
A fourth oxide on the first oxide;
A second insulator on the fourth oxide;
A third conductor on the second insulator;
A third insulator on the third conductor,
A fourth insulator on the third insulator,
The fourth oxide includes an upper surface of the first oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the second oxide, and the third oxide. Touching the sides of
The first oxide includes In, an element M (M is Al, Ga, Y, or Sn), and Zn;
The fourth oxide has at least one of the constituent elements of the first oxide,
The second oxide and the third oxide each include an element M,
The second oxide and the third oxide have a region where the concentration of the element M is higher than that of the first oxide.
A semiconductor device characterized by the above-mentioned. In claim 9,
The third insulator includes oxygen and aluminum,
The semiconductor device, wherein the fourth insulator contains nitrogen and silicon.