JP2020025437A - Storage battery system - Google Patents

Abstract

To provide a storage battery system that appropriately blocks switching elements connected in parallel.SOLUTION: A storage battery system comprises: a switch SW1 which is provided on an electric path L1 connecting a storage battery 11 and a rotational electric machine 14 and has a plurality of MOSFETs 30 connected in parallel with each other; a MOS driver 35 that places each MOSFET 30 in a closed state by applying a voltage difference between a gate terminal 31 and a source terminal 32 in each MOSFET 30; a control unit 21 that outputs an opening and closing command signal for the plurality of MOSFETs 30 to the MOS driver 35; a comparator 43 and a timer IC 45 that output a blocking request for the plurality of MOSFETs 30 on the basis of a conduction current flowing in the switch SW1; and an output switch 52 and short circuit switches 54 and 55 that block the plurality of MOSFETs 30 by equalizing a voltage of the source terminal 32 in the plurality of MOSFETs 30 with the voltage of the gate terminal 31 when a blocking request is output from the comparator 43 and the timer IC 45.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a storage battery system.

  In a power supply circuit for driving a load, opening and closing of the power supply circuit is generally controlled using a semiconductor switching element or the like. Such a power supply circuit may be shut off, for example, when an overcurrent is detected. As a technique for shutting off a power supply circuit when an overcurrent occurs, for example, in the configuration of Patent Document 1, an inverter control circuit outputs a stop signal to a drive circuit that drives an inverter according to the number of times an overcurrent is detected. Then, the control signal from the drive circuit to the inverter is cut off. Thus, when an overcurrent is detected a predetermined number of times or more, the control signal to the inverter can be cut off.

JP 2015-186425 A

  By the way, in recent years, it has been proposed that the semiconductor switching elements are arranged in parallel in order to increase the current of the power supply path. In such a case, the semiconductor switching elements are cut off in response to the occurrence of overcurrent. In addition, the following measures will be required. That is, for example, when an overcurrent occurs, the control unit simultaneously outputs a command to open the semiconductor switching elements to the driver IC of each semiconductor switching element in order to simultaneously use the semiconductor switching elements in parallel. However, when the semiconductor switching elements are actually driven to open and close, variations in operation timing may occur due to individual differences in driver ICs and the like, and there may be a time difference in the opening and closing timings of the semiconductor switching elements. If the paralleled semiconductor switching elements are not opened at the same time, there is a disadvantage that an excessive load is applied to the closed semiconductor switching elements.

  The present invention has been made in view of the above problems, and a main object of the present invention is to provide a storage battery system that appropriately shuts off switching elements connected in parallel.

  According to a first means, a switch unit provided in an electric path (L1, L2) connecting a storage battery (11, 12) and an electric device (14) and having a plurality of semiconductor switching elements (30) connected in parallel to each other. (SW1, SW2), and applying a voltage difference between the control terminal (31) of the plurality of semiconductor switching elements and the first terminal among the other first terminal (31) and second terminal (32). A drive circuit (35) for closing the semiconductor switching element, a control unit (21) for outputting an opening / closing command signal for the plurality of semiconductor switching elements to the drive circuit, and an energization flowing through the switch unit. A shutoff request output unit (43, 45) for outputting a shutoff request for the plurality of semiconductor switching elements based on the current; and a case where the shutoff request is output from the shutoff request output unit. In this case, by setting the voltage of the first terminal in the plurality of semiconductor switching elements to be the same as the voltage of the control terminal, an interruption circuit (52, 54, 55, 60) for interrupting the plurality of semiconductor switching elements is provided. , Is provided.

  In this means, the switching current is not based on the open / close command signal of the control unit operated by software, but based on the current flowing by cutting off the plurality of semiconductor switching devices by hardware such as a cutoff request output unit and a cutoff circuit. Blocking can be performed quickly.

  Also, the semiconductor switching element is not cut off by the driving circuit of the semiconductor switching element connected in parallel, but the cutoff circuit sets the voltage of the first terminal to be the same as the voltage of the control terminal. Cut off. For this reason, it is possible to suppress variations in the cutoff timing of the semiconductor switching elements connected in parallel due to individual differences of the drive circuits and the like.

  When the application of the voltage to the control terminal by the drive circuit is stopped, the voltage on the first terminal side is reduced due to a surge current or the like, so that a potential difference occurs between the control terminal and the first terminal. However, there is a possibility that current will continue to flow through the semiconductor switching element. On the other hand, in this means, since the voltage of the first terminal is set to be the same as the voltage of the control terminal, it is possible to cut off the current flowing through the semiconductor switching element.

  As described above, the voltage applied to the control terminal from the drive circuit is not stopped, but the voltage at the first terminal is made equal to the voltage at the control terminal by the cutoff circuit, whereby the voltage can be appropriately cut off.

  In the second means, the cut-off circuit is provided in a short-circuit path for short-circuiting the control terminal and the first terminal in the plurality of semiconductor switching elements, and a short-circuit switch (54) for opening and closing the short-circuit path , 55), and when the cutoff request is output from the cutoff request output unit, the short-circuit switch is closed to make the voltage of the first terminal the same as the voltage of the control terminal.

  A short-circuit switch is provided in a short-circuit path for short-circuiting between the control terminal and the first terminal. Thus, when the shut-down request is output from the shut-off request output unit, the short-circuit switch is closed to short-circuit the control terminal and the first terminal, and the voltage of the first terminal is changed to the voltage of the control terminal. By making the same, it is possible to cut off the current flowing through the semiconductor switching element.

  In the third means, the shutoff circuit is connected to an electric path (L12) between the control terminal and the drive circuit in the plurality of semiconductor switching elements, and is connected to the first terminal, and And a discharge circuit (60) for causing discharge from the terminal and the first terminal, wherein when the cutoff request is output from the cutoff request output unit, the discharge circuit causes the control terminal and the first terminal to output a signal from the control terminal and the first terminal. By causing discharge, the voltage of the first terminal is made equal to the voltage of the control terminal.

  A configuration was provided in which a discharge circuit for causing discharge from the control terminal and the first terminal was provided. Thus, when the shut-down request is output from the shut-down request output unit, the discharge circuit causes the control terminal and the first terminal to discharge. Then, by causing the voltage of the first terminal to be equal to the voltage of the control terminal by discharging, the current flowing through the semiconductor switching element can be cut off.

  In a fourth aspect, the drive circuit is provided for each of the plurality of semiconductor switching elements that are parallel to each other.

  By providing a drive circuit for each of the semiconductor switching elements that are in parallel with each other, redundancy of the drive circuit can be ensured. Even if one drive circuit becomes abnormal, the parallel connection of the semiconductor switching elements can be achieved. It can be driven. However, in such a configuration in which a drive circuit is provided for each of the semiconductor switching elements in parallel, a problem of simultaneous interruption of the semiconductor switching elements connected in parallel due to individual differences of the drive circuits is likely to occur. Therefore, it is suitable to use the first means.

  In a fifth means, the control unit outputs a forced shutoff signal for shutting off the plurality of semiconductor switching elements to the shutoff circuit based on a current flowing through the switch unit, and the shutoff request output unit outputs After outputting the cutoff request based on the current flowing through the switch unit, the cutoff request is maintained at least until the control unit outputs the forced cutoff signal.

  When the semiconductor switching element is cut off in response to the cutoff request, the semiconductor switching element is cut off first by the shutoff circuit, and the state is maintained, and thereafter, the cutoff state of the semiconductor switching element is maintained by the forced shutoff signal from the control unit. In this case, since the control unit can also grasp the situation, it is possible to implement quick fail-safe and the like as a system while enabling quick response by the cutoff circuit.

  The sixth means includes a current detection circuit that detects and outputs an energizing current flowing through the switch unit, wherein the current detecting circuit detects a energizing current flowing through the switch unit (41); A first amplifier (42a) that outputs a detection result of the detection unit to the cutoff request output unit, and a second amplifier (42b) that outputs a detection result of the detection unit to the control unit.

  By separately providing a detection unit for detecting a current flowing through the switch unit, a first amplifier for outputting a detection result of the detection unit to a cutoff request output unit, and a second amplifier for outputting to a control unit a current detection circuit Redundancy can be ensured.

  The seventh means is a main control unit that is the control unit, and an open command signal that monitors the main control unit and opens the plurality of semiconductor switching elements based on a monitoring result of the main control unit. An output sub-control unit.

  The sub-control unit monitors the main control unit and outputs an open command signal for opening the semiconductor switching element based on the monitoring result of the main control unit. Accordingly, the configuration for outputting a command to open the semiconductor switching element is made redundant, and when the main control unit cannot perform appropriate control, current is prevented from flowing through the electric path by the sub control unit. . Therefore, overcharge and overdischarge of the storage battery can be suppressed. In addition, in the storage battery system, in addition to a measure for appropriately shutting down when an overcurrent flows, a suitable measure for a case where an abnormality occurs in the main control unit can be performed, and system reliability can be improved.

  In an eighth aspect, the sub control unit outputs the open command signal to the shutoff circuit based on a monitoring result of the main control unit.

  The sub-control circuit is configured to output an open command signal for opening the semiconductor switching element to the shutoff circuit based on a monitoring result of the main control unit. Thus, the sub-control unit can open the semiconductor switching element by a mechanism different from the drive circuit. Therefore, no matter what control command the main control unit issues to the drive circuit, the semiconductor switching element can be reliably opened.

  The ninth means is that the main control unit and the sub control unit are connected to different power supply devices, and power is supplied from the different power supply devices.

  The main control unit and the sub control unit are connected to different power supply devices, and power is supplied from the different power supply devices. Thus, even if the power supply is not supplied to the main control unit from the power supply device due to the failure of one of the power supply devices, the semiconductor switching element can be opened by the sub control unit.

Schematic diagram of storage battery system FIG. 2 is a schematic diagram illustrating a shutoff configuration of a switch unit according to the first embodiment. Flow chart showing the processing procedure of the control unit Time chart showing the process of the storage battery system FIG. 4 is a schematic diagram illustrating a shutoff configuration of a switch unit according to a second embodiment. FIG. 4 is a schematic diagram illustrating a shutoff configuration of a switch unit according to a third embodiment. Schematic diagram showing the configuration of the switch unit in the fourth embodiment FIG. 4 is a schematic diagram showing a shutoff configuration of a switch unit according to another embodiment.

<First embodiment>
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, portions that are the same or equivalent to each other are denoted by the same reference numerals in the drawings. In the present embodiment, in a vehicle running with an engine (internal combustion engine) as a drive source, an on-board power supply system that supplies electric power to various devices of the vehicle is embodied.

  As shown in FIG. 1, the power supply system is a dual power supply system including a lead storage battery 11 as a first storage battery and a lithium ion storage battery 12 as a second storage battery. Power can be supplied from each of the storage batteries 11 and 12 to the starter 13, the rotating electric machine 14, and various electric loads 15. The rechargeable batteries 11 and 12 can be charged by the rotating electric machine 14. In the power supply system, the lead storage battery 11 and the lithium ion storage battery 12 are connected in parallel to the rotating electric machine 14, and the lead storage battery 11 and the lithium ion storage battery 12 are connected in parallel to the electric load 15. In the present embodiment, the lead storage battery 11 and the lithium ion storage battery 12 correspond to “storage batteries”, and the rotating electric machine 14 corresponds to “electric devices”.

  The lead storage battery 11 is a known general-purpose storage battery. On the other hand, the lithium-ion storage battery 12 is a high-density storage battery that has a smaller power loss during charging and discharging, a higher output density, and a higher energy density than the lead storage battery 11. The lithium ion storage battery 12 is preferably a storage battery having higher energy efficiency during charging and discharging than the lead storage battery 11. Further, the lithium ion storage battery 12 is configured as an assembled battery having a plurality of unit cells. Each of these storage batteries 11 and 12 has the same rated voltage, for example, 12V.

  Although a specific description by illustration is omitted, the lithium ion storage battery 12 is housed in a housing case and configured as a battery unit U integrated with a substrate. In FIG. 1, the battery unit U is shown surrounded by a broken line. The battery unit U has external terminals P0, P1 and P2, of which the lead-acid battery 11 and the starter 13 are connected to the external terminal P0, the rotary electric machine 14 is connected to the external terminal P1, and the electric terminal P2 is electrically connected. The load 15 is connected. The external terminal P0 is connected to the lead storage battery 11 via the fuse 16, and the external terminal P2 is connected to the electric load 15 via the fuse 17. In the present embodiment, the battery unit U corresponds to a “storage battery system”.

  The rotating electric machine 14 is a generator with a motor function having a three-phase AC motor and an inverter as a power conversion device, and is configured as an ISG (Integrated Starter Generator) integrated with electromechanical. The rotating electric machine 14 has a power generation function of generating power (regenerative power generation) by rotation of an engine output shaft and an axle, and a power running function of applying a rotational force to the engine output shaft. The power running function of the rotating electric machine 14 can apply a rotating force to the engine when the automatically stopped engine is restarted during idling stop. The rotating electric machine 14 supplies the generated power to each of the storage batteries 11 and 12 and the electric load 15.

  The electric load 15 includes a constant voltage load that requires a constant supply voltage or a fluctuation within a predetermined range. Specific examples of the electric load 15 that is a constant voltage request load include various ECUs such as a navigation device, an audio device, a meter device, and an engine ECU. In this case, by suppressing the voltage fluctuation of the supplied power, the occurrence of unnecessary reset or the like in each of the above devices is suppressed, and a stable operation can be realized. The electric load 15 may include a travel system actuator such as an electric steering device or a brake device.

  Next, the battery unit U will be described. As an electric path in the battery unit U, an electric path L1 connecting the external terminals P0 and P1 and an electric path L2 connecting the connection point N1 on the electric path L1 and the lithium ion storage battery 12 are provided. The switch SW1 is provided on the electric path L1, and the switch SW2 is provided on the electric path L2. The electric paths L1 and L2 are large current paths assuming that an input / output current flows to the rotating electric machine 14, and the mutual paths between the storage batteries 11 and 12 and the rotating electric machine 14 via the electric paths L1 and L2. Is conducted. In the present embodiment, the switches SW1 and SW2 correspond to a “switch unit”. Each of the switches SW1 and SW2 has a plurality of semiconductor switching elements arranged in parallel with each other, the details of which will be described later.

  Further, in the battery unit U of the present embodiment, in addition to the electric paths L1 and L2, a connection point N2 (a point between the external terminal P0 and the switch SW1) on the electric path L1 is connected to the external terminal P2. It has an electrical path L3. The electric path L3 forms a path that enables power supply from the lead storage battery 11 to the electric load 15. A switch SW3 is provided on the electric path L3 (specifically, between the connection point N2 and the connection point N4).

  In the battery unit U, a connection point N3 of the electric path L2 (a point between the switch SW2 and the lithium ion storage battery 12) and a connection point N4 on the electric path L3 (a point between the switch SW3 and the external terminal P2). , Is provided with an electric path L4. The electric path L4 forms a path that enables power supply from the lithium-ion storage battery 12 to the electric load 15. A switch SW4 is provided on the electric path L4 (specifically, between the connection point N3 and the connection point N4).

  Each of the switches SW3 and SW4 includes a pair of semiconductor switching elements. The semiconductor switching element is a MOSFET, and a pair of the MOSFETs is connected in series such that the parasitic diodes of the MOSFETs are opposite to each other. By configuring each of the switches SW3 and SW4 such that the parasitic diodes are opposite to each other, for example, when the switch SW3 is turned off, current flowing through the parasitic diode is completely cut off. Note that an IGBT, a bipolar transistor, or the like can be used instead of the MOSFET as the semiconductor switching element used for the switches SW3 and SW4. When an IGBT or a bipolar transistor is used, diodes that replace the parasitic diodes may be connected in parallel.

  Further, the battery unit U is provided with a bypass path B that allows the lead storage battery 11 to be connected to the electric load 15 without passing through the switch SW3 in the unit. That is, the bypass path B is provided so as to bypass the switch SW3 on the electric path L3. One end of the bypass path B is connected to the connection point N2 on the electric path L1 inside the unit, and the other end is connected between the connection point N4 on the electric path L3 and the external terminal P2 inside the unit. The bypass path B is provided with a bypass opening / closing circuit RE for turning the bypass path B on or off. The bypass switching circuit RE has, for example, a normally closed mechanical relay. If the bypass path B is turned on by the bypass switching circuit RE, power is supplied from the lead storage battery 11 to the electric load 15 via the bypass path B even when the switch SW3 is turned off. It is possible.

  The battery unit U includes a control unit 21 that controls the switches SW1 to SW4 and the bypass switching circuit RE. The control unit 21 is configured by a microcomputer including a CPU, a ROM, a RAM, an input / output interface, and the like.

  The control unit 21 controls the switches SW1 to SW4 and the like based on the storage state of each of the storage batteries 11 and 12. For example, the control unit 21 calculates the SOC (remaining capacity: State Of Charge) of the lithium ion storage battery 12. Then, the control unit 21 controls each of the switches SW1 to SW4 to output an open / close command signal so that the SOC is maintained within a predetermined use range, and charges and charges the lead storage battery 11 and the lithium ion storage battery 12. Control discharge. That is, the control unit 21 performs charging and discharging by selectively using the lead storage battery 11 and the lithium ion storage battery 12.

  Further, the control unit 21 performs an abnormality determination regarding the battery unit U. For example, the control unit 21 monitors whether an abnormality has occurred in the lithium ion storage battery 12. Specifically, a current sensor or a temperature sensor is used to detect that an overcurrent is flowing through the lithium ion storage battery 12 or that the temperature of the lithium ion storage battery 12 is excessively high. Perform processing. As fail-safe processing, for example, after turning off all the switches SW1 to SW4, the bypass path B is turned on, or an abnormality is notified to another ECU. Further, the control unit 21 also determines an abnormality in each of the switches SW1 to SW4.

  The control unit 21 is connected to an ECU 22 composed of, for example, an engine ECU. The ECU 22 is configured by a microcomputer including a CPU, a ROM, a RAM, an input / output interface and the like, and controls the operation of the engine based on the engine operating state and the vehicle running state each time. The control unit 21 and the ECU 22 are connected to each other by a communication network such as a CAN and can communicate with each other, and various data stored in the control unit 21 and the ECU 22 can be shared with each other.

  Next, a description will be given of a configuration for detecting and interrupting a current flow in each of the switches SW1 and SW2. FIG. 2 is a schematic diagram of a configuration for detecting and interrupting an energizing current in the switch SW1. A portion surrounded by a broken line indicates the switch SW1. Although the description will be made using the switch SW1 for convenience, even in the case of the switch SW2, the connected storage battery is not the lead storage battery 11 but the lithium ion storage battery 12, and the electric path L1 provided with the switch SW1 is the electric path L2. Only the configuration is the same.

  Four MOSFETs 30a to 30d are used for the switch SW1. Each of the MOSFETs 30a to 30d is a well-known high-power n-type MOSFET, which is a normally open semiconductor switching element, and includes a gate terminal 31, a source terminal 32, and a drain terminal 33. The current flowing between the drain terminal 33 and the source terminal 32 is controlled by the voltage between the gate terminal 31 and the source terminal 32. Further, a parasitic diode 34 caused by a PN junction of the MOSFET is provided between the source terminal 32 and the drain terminal 33. In the present embodiment, the MOSFETs 30a to 30d correspond to “semiconductor switching elements”. The gate terminal 31 corresponds to a “control terminal”, the source terminal 32 corresponds to a “first terminal”, and the drain terminal 33 corresponds to a “second terminal”. In the following description, the MOSFETs 30a to 30d are collectively referred to as a MOSFET 30.

  As a drive circuit for driving the MOSFET 30, a MOS driver 35 is connected to the gate terminal 31 via a path L12. The MOS driver 35 is provided for each MOSFET 30, and in the present embodiment, four MOS drivers are provided. The MOS driver 35 drives the MOSFET 30 based on an open / close command signal from the control unit 21. Specifically, when a command is issued by the control unit 21 to turn on the MOSFET 30 (current flows as a closed state), a predetermined voltage is applied to the gate terminal 31 and the control unit 21 turns off the MOSFET 30. (When no current flows as an open state), the voltage applied to the gate terminal 31 is set to zero. In the present embodiment, the MOS driver 35 corresponds to a “drive circuit”.

  The MOS driver 35 may not be provided individually for each MOSFET 30 but may be provided for each of the plurality of MOSFETs 30 that are parallel to each other. That is, the MOSFETs 30a and 30b may be driven by the same MOS driver 35, and the MOSFETs 30c and 30d may be driven by the same MOS driver 35. By doing so, the redundancy of the MOS driver 35 can be ensured. Therefore, even if an abnormality occurs in one MOS driver 35, the MOSFET 30 can be opened and closed and a current can flow through a path of the MOSFET 30 connected in parallel with the MOSFET 30 driven by the MOS driver 35.

  The electric path L1 provided with the switch SW1 branches at the branch point N11 in parallel with the paths L11a and L11b, and at the connection point N12, the paths L11a and L11b join to form the electric path L1 again. In the switch SW1, the MOSFETs 30a and 30b are provided in the path L11a, and the MOSFETs 30c and 30d are provided in the path L11b. That is, the MOSFETs 30a and 30c are connected in parallel, and the MOSFETs 30b and 30d are connected in series to the respective MOSFETs 30a and 30c. That is, a set of MOSFETs 30a and 30b connected in series on the path L11a and MOSFETs 30c and 30d connected in series on the path L11b is connected in parallel. These MOSFETs 30a and 30b are connected in series such that the parasitic diodes 34 are opposite to each other. The same applies to MOSFETs 30c and 30d. In the present embodiment, the number of MOSFETs 30 connected in series provided in a set of MOSFETs 30 connected in parallel is the same.

  A resistor 41 for measuring a current flowing through the path L11a is provided between the MOSFETs 30a and 30b connected in series. That is, on the path L11a, the MOSFET 30a, the resistor 41, and the MOSFET 30b are provided in a state of being connected in series. Similarly, a resistor 41 is provided between the MOSFETs 30c and 30d. An amplifier 42 for detecting a voltage between terminals at both ends of the resistor 41 is connected to both ends of the resistor 41. The resistor 41 and the amplifier 42 constitute a “current detection circuit” that detects and outputs a current flowing through each of the paths L11a and L11b (switch SW1).

  The detection voltage V (the voltage across the resistor 41) detected by the amplifier 42 is output to the control unit 21 and the comparator 43. The control unit 21 and the comparator 43 determine whether or not an overcurrent has flowed through the electric path L1 based on the detected voltage V. The comparator 43 receives two predetermined types of reference voltages Vref1 and Vref2 from the reference voltage circuit 44. Two types of reference voltage Vref1 when a current flows from the lead storage battery 11 to the rotating electric machine 14 and a reference voltage Vref2 when a current flows from the rotating electric machine 14 to the lead storage battery 11 are input to the comparator 43 from the reference voltage circuit 44. You. Then, the comparator 43 compares the reference voltages Vref1 and Vref2 with the detected voltage V of the amplifier 42, and outputs a comparison result to the timer IC 45 based on the comparison result. Here, when the absolute value of the detection voltage V is larger than the absolute values of the reference voltages Vref1 and Vref2, an ON signal is output as a comparison result, and the detection voltage V is higher than the absolute values of the reference voltages Vref1 and Vref2. If the absolute value is large, an off signal is output. When the ON signal is input from the comparator 43 as a comparison result, the timer IC 45 continues to output the ON signal as a cutoff request for a certain period of time. The comparator 43 and the timer IC 45 of the present embodiment correspond to an “interruption request output unit”.

  The interruption request (ON signal) output from the timer IC 45 is amplified to a predetermined voltage by the bipolar transistor 51 via the diode, and drives the output switch 52. The output switch 52 is a normally open semiconductor switching element, and uses a p-type MOSFET. An element having a Zener diode connected face to face, a capacitor, and a resistor are connected in parallel with the gate terminal and the source terminal of the output switch 52. Although a resistor is connected between the base and the base-emitter of the bipolar transistor 51, the bipolar transistor 51 may be a transistor with a built-in resistor incorporating these resistors. Further, the output switch 52 may be another semiconductor switching element such as an n-type MOSFET or IGBT.

  The output switch 52 is provided on a path L13 that connects the shutoff power supply 53 and the two short-circuit switches 54 and 55. The path L13 branches at a branch point N13, and the gate terminals of the short-circuit switches 54 and 55 are connected to the branched paths L13a and L13b, respectively. The output switch 52 is closed by an ON signal (current) from the timer IC 45 and a current flows through the path L13, so that a predetermined voltage is applied from the output switch 52 to the short-circuit switches 54 and 55. In the present embodiment, the output switch 52 and the short-circuit switches 54 and 55 correspond to an “interruption circuit”.

  The short-circuit switches 54 and 55 are normally-open semiconductor switching elements, and use n-type MOSFETs. The elements having the Zener diodes connected face-to-face, the capacitors, and the resistors are connected so that the gate terminals and the source terminals of the short-circuit switches 54 and 55 are in parallel. Note that the short-circuit switch 54 may be another semiconductor switching element such as a p-type MOSFET or IGBT.

  Paths L14a, L14b, L14c, and L14d are connected to a connection point N14 provided on a path L12 connecting each MOS driver 35 and the gate terminal 31. A diode 56 is provided in each of the paths L14a, L14b, L14c, and L14d, and regulates the direction of the current flowing through each of the paths L14a, L14b, L14c, and L14d. The path L12 connected to the MOS driver 35 for driving the MOSFET 30a is connected to the path L14a at the connection point N14, and the path L12 connected to the MOS driver 35 for driving the MOSFET 30b is connected to the path L14b at the connection point N14. are doing. Then, the path L14a and the path L14b merge at the connection point N15a to become the path L15a, and the path L15a is connected to the path L11a at the connection point N16a.

  The short-circuit switch 54 is provided on the path L15a. When a current flows through the path L13 and a predetermined voltage is applied to the short-circuit switch 54, the short-circuit switch 54 is closed. When the short-circuit switch 54 is closed, the short-circuit paths L12, L14a, L15a, and L11a are connected, and the gate terminal 31 and the source terminal 32 of the MOSFET 30a are short-circuited via the diode 56. When the short-circuit switch 54 is closed, the short-circuit path L12, the path L14b, the path L15a, and the path L11a are connected, and the gate terminal 31 and the source terminal 32 of the MOSFET 30b are short-circuited via the diode 56. You. That is, a short-circuit path that short-circuits the two MOSFETs 30 a and 30 b connected in series is controlled by opening and closing the short-circuit switch 54.

  Similarly, the path L12 connected to the path L12 of the MOS driver 35 for driving the MOSFET 30c is connected to the path L14c, and the path L12 connected to the MOS driver 35 for driving the MOSFET 30d is connected to the path L14d at the connection point N14. Connected to Then, the path L14c and the path L14d join at the connection point N15b to form the path L15b, and the path L15b is connected to the path L11b to the connection point N16b.

  The short-circuit switch 55 is provided on the path L15b. When a current flows through the path L13 and a predetermined voltage is applied to the short-circuit switch 55, the short-circuit switch 55 is closed, so that the short-circuit paths L12, L14c, L15b, and L11b are connected, and the MOSFET 30c Between the gate terminal 31 and the source terminal 32 via the diode 56. Further, by closing the short-circuit switch 55, the short-circuit path L12, the path L14d, the path L15b, and the path L11b are connected, and the gate terminal 31 and the source terminal 32 of the MOSFET 30d are short-circuited via the diode 56. You.

  Further, between the MOS driver 35 and the gate terminal 31 (on the path L12 and between the connection point N14 and the gate terminal 31), an adjusting resistor 36 for adjusting the speed at the time of shutoff is provided. . The adjusting resistor 36 has a relatively small resistance value, and has such a resistance value that the shut-off speed is faster than at the time of normal ON / OFF.

  The drain terminal 33 and the gate terminal 31 of each MOSFET 30 are connected by a path L16. On the path L16, a limiting diode 37 and a clamping diode 38, which are opposite to each other, are provided in a state of being connected in series. In this case, the limiting diode 37 is a Zener diode, and is provided with its cathode facing the gate terminal 31. By providing the limiting diode 37, the current from the gate terminal 31 to the drain terminal 33 is limited.

  Further, the clamping diode 38 is a Zener diode that is provided with its cathode facing the drain terminal 33 side and becomes conductive when a predetermined high voltage is applied to the drain terminal 33. The clamping diode 38 is an element for protecting the MOSFET 30, and becomes conductive at a voltage lower than the withstand voltage between the drain terminal 33 and the source terminal 32 of the MOSFET 30.

  For example, when a surge voltage is applied between the drain terminal 33 and the source terminal 32 due to the interruption of the current, the clamping diode 38 becomes conductive, a voltage is applied to the gate terminal 31, and a current flows through the MOSFET 30. . Therefore, when a surge voltage is generated by being cut off by the cutoff request, the clamping diode 38 becomes conductive, and a current flows through the MOSFET 30, thereby suppressing the destruction of the MOSFET 30.

  Next, the abnormality determination of the switch unit in the control unit 21 will be described with reference to FIG. FIG. 3 is a flowchart illustrating an abnormality determination process of the control unit 21 in the battery unit U. This process is repeatedly performed by the control unit 21 at a predetermined cycle.

  First, in step S11, the detection voltage V detected by the amplifier 42 is obtained. Then, in a step S12, it is determined whether or not the acquired detection voltage V is higher than the reference value. The reference value at this time may be the same as the reference voltage Vref generated by the reference voltage circuit 44, or may have an absolute value smaller than the reference voltage Vref. If it is determined that the detection voltage V is smaller than the reference value, the process ends, assuming that no abnormality has occurred.

  If it is determined in step S12 that the detected voltage V is higher than the reference value (if it is determined that an abnormality such as an overcurrent has occurred), a forced shutoff signal is output as an open / close command signal in step S13. Specifically, a command to set the applied voltage to 0 is issued to each MOS driver 35. On the other hand, a current flows through the bipolar transistor 51 through the diode, closing the output switch 52 and keeping the short-circuit switches 54 and 55 closed. Then, in step S13, a fail-safe process is performed, and the process ends.

  Next, the timing for turning off the switches SW1 and SW2 will be described with reference to FIG. FIG. 4 illustrates a case where an overcurrent flows in the switch SW1 and an abnormality is detected. Although the description will be given using the switch SW1 for convenience, the timing of the cutoff is the same in the case of the switch SW2.

  In normal times (before timing t1), the comparator 43 determines that the detection voltage V detected by the amplifier 42 is smaller than the reference voltage Vref, and the comparator 43 outputs an OFF signal to the timer IC 45. Since the input signal from the comparator 43 is an off signal, the timer IC 45 outputs an off signal. That is, the timer IC 45 does not flow a current for driving the bipolar transistor 51. Also, the control unit 21 does not determine that the detected voltage V exceeds the reference value. In this state, no current flows through the bipolar transistor 51, and the output switch 52 is turned off. When the output switch 52 is in the off state (open state), no current flows through the path L13, so the short-circuit switches 54 and 55 are turned off (open state), and no current flows through the short-circuit path. Therefore, the MOSFETs 30a and 30c are opened and closed by driving from the MOS driver 35 according to an opening and closing command signal of the control unit 21. By opening and closing the MOSFETs 30a and 30c, the current between the lithium ion storage battery 12 and the rotating electric machine 14 is controlled, and charging and discharging are performed.

  Then, at timing t1, when an overcurrent flows through the switch SW1 and the comparator 43 determines that the detection voltage V detected by the amplifier 42 exceeds the reference voltages Vref1 and Vref2, the comparator 43 is turned on by the timer IC 45. Output a signal. When the ON signal is input from the comparator 43, the timer IC 45 outputs an ON signal as a cutoff signal for a predetermined time T. When the timer IC 45 outputs an ON signal (a current for driving the bipolar transistor 51 flows), a current flows to the bipolar transistor 51, and the output switch 52 is turned on. When the output switch 52 is turned on, a current for driving the short-circuit switches 54 and 55 flows through the path L13, the short-circuit switches 54 and 55 are turned on almost simultaneously, and a short-circuit path is established.

  When the short-circuit path is established, the voltage at the source terminal 32 of the MOSFET 30 becomes equal to the voltage at the gate terminal 31, so that no current flows through the MOSFET 30. Then, by applying the voltage to the short-circuit switches 54 and 55 by the same output switch 52, the short-circuit switches 54 and 55 are simultaneously turned on. Therefore, the MOSFETs 30a and 30c connected in parallel can be cut off at the same time. The timing at which the short-circuit switches 54 and 55 are turned on may be slightly shifted depending on the length of the paths L13a and L13b. However, the timing is small compared to the shift in the drive timing of the MOS driver 35, and this is a problem. No. In addition, the current flowing through the switch SW1 can be quickly interrupted by interrupting by such hardware rather than by interrupting by the control unit 21 using software to determine an abnormality.

  When the current stops flowing through the MOSFET 30, the detection voltage V at the amplifier 42 becomes 0 at timing t2. When the detection voltage V becomes 0, the comparator 43 outputs an off signal to the timer IC 45. However, since the timer IC 45 continues to output the ON signal during the predetermined time T, the output switch 52 and the short-circuit switches 54 and 55 maintain the ON state, and the state in which no current flows through the MOSFET 30 is maintained. That is, the output switch 52 is turned on by the output from the timer IC 45 until the control unit 21 makes the determination (during the predetermined time T), and the current of the switch SW1 can be kept off.

  Then, the control unit 21 performs the abnormality determination processing shown in FIG. 3 within the predetermined time T. Then, when the control unit 21 determines an abnormality at the timing t3, a current flows through the bipolar transistor 51 through the diode as a cutoff signal, and the output switch 52 is kept on. In this way, when the control unit 21 determines that an overcurrent is flowing, the output switch 52 is turned on, and the current of the switch SW1 is cut off. When the control unit 21 determines that it is necessary to cut off the current, not only the MOS driver 35 is controlled so as to stop the application to the gate terminal 31, but also by flowing a current through the bipolar transistor 51, Blocking can be performed reliably.

  Then, when the predetermined time T has elapsed, at a timing t4, the timer IC 45 is turned off. On the other hand, since the control unit 21 supplies a current to the bipolar transistor 51 as a cutoff signal (is in an ON state), the output switch 52 and the short-circuit switches 54 and 55 maintain the ON state, and a current flows to the MOSFET 30. No state is maintained. That is, the control unit 21 can maintain the ON state of the output switch 52 and the short-circuit switches 54 and 55 without holding the timer IC 45 in the ON state.

  According to the embodiment described above, the following excellent effects can be obtained.

  Not only the opening and closing of the MOSFET 30 based on the opening and closing command signal of the control unit 21 operated by software, but also the plurality of MOSFETs 30 is shut off by hardware such as a comparator 43, a timer IC 45, an output switch 52, and short-circuit switches 54 and 55. Therefore, the interruption based on the current flowing in the paths L11a and L11b can be quickly performed.

  Further, the short-circuit switches 54 and 55 are provided in a short-circuit path for short-circuiting between the gate terminal 31 and the source terminal 32, instead of cutting off the MOSFET 30 by the MOS driver 35 of the MOSFET 30 connected in parallel. As a result, when the timer IC 45 outputs an ON signal (interruption request) based on the comparison result of the comparator 43, the output switch 52 is closed. Then, by closing the output switch 52, the short-circuit switches 54 and 55 are closed. As a result, the gate terminal 31 and the source terminal 32 are short-circuited, the voltage of the source terminal 32 is made equal to the voltage of the gate terminal 31, and the current flowing through the MOSFET 30 can be cut off. Therefore, it is possible to suppress variations in the cutoff timing of the MOSFETs 30 connected in parallel due to individual differences of the MOS drivers 35 and the like.

  When the application of the voltage to the gate terminal 31 is stopped by the MOS driver 35, the voltage on the source terminal 32 side is reduced due to a surge current or the like, so that the voltage between the gate terminal 31 and the source terminal 32 is reduced. There is a possibility that a potential difference (voltage) is generated between them, and a current continuously flows through the MOSFET 30. Even in such a case, in the present embodiment, since the voltage of the source terminal 32 is the same as the voltage of the gate terminal 31, the current flowing through the MOSFET 30 can be cut off.

  By providing a MOS driver 35 for each MOSFET 30 or providing a MOS driver 35 for each MOSFET 30 connected in parallel as in the present embodiment, redundancy of the MOS driver 35 can be ensured. For example, even when an abnormality occurs in a certain MOS driver 35, it is possible to drive the MOSFETs 30 in parallel. In such a configuration in which the MOS driver 35 is provided for each MOSFET 30 or for each MOSFET 30 in parallel, the problem of simultaneous interruption of the MOSFETs 30 connected in parallel due to individual differences of the MOS drivers 35 is likely to occur. Therefore, it is suitable to use the configuration as in the present embodiment.

  When the MOSFET 30 is cut off in response to the cut-off request, the MOSFET 30 is cut off by the output switch 52 and the short-circuit switches 54 and 55 first, and the state is maintained by the timer IC 45. The cut-off state of the MOSFET 30 is maintained. In this case, since the control unit 21 can also grasp the situation, it is possible to implement quick fail-safe and the like as a system while enabling quick response by hardware. Further, it is not necessary to keep the timer IC 45 in the ON state.

  In this manner, the voltage applied to the gate terminal 31 from the MOS driver 35 is not stopped, but the voltage at the source terminal 32 is made equal to the voltage at the gate terminal 31 by the short-circuit switches 54 and 55, so that the voltage is appropriately cut off. be able to.

<Second embodiment>
In the first embodiment, the MOSFETs 30a and 30b connected in series are cut off by the same short-circuit switch 54. However, in the second embodiment, the MOSFETs 30a and 30c connected in parallel (opposing) are cut off by the same short-circuit switch 54. You. Hereinafter, this will be described in detail with reference to FIG.

  Paths L24a, L24b, L24c, and L24d are connected at a connection point N14 provided on a path L12 connecting each MOS driver 35 and the gate terminal 31. A diode 56 is provided in each of the paths L24a, L24b, L24c, and L24d, and regulates the direction of the current flowing through each of the paths L24a, L24b, L24c, and L24d. The path L12 connected to the MOS driver 35 for driving the MOSFET 30a is connected to the path L24a at a connection point N14, and the path L12 connected to the MOS driver 35 for driving the MOSFET 30c is connected to the path L24c at the connection point N14. are doing. Then, the path L24a and the path L24c merge at the connection point N25a to form the path L25a, and the path L25a is connected to the paths L11a and L11b at connection points N26a and N26c, respectively.

  The short-circuit switch 54 is provided on the path L25a. When a current flows through the path L13 and a predetermined voltage is applied to the short-circuit switch 54, the short-circuit switch 54 is closed, so that the short-circuit path L12, the path L24a, the path L25a, and the path L11a are connected, and the MOSFET 30a Between the gate terminal 31 and the source terminal 32 via the diode 56. When the short-circuit switch 54 is closed, the short-circuit path L12, the path L24c, the path L25a, and the path L11b are connected, and the gate terminal 31 and the source terminal 32 of the MOSFET 30b are short-circuited via the diode 56. You. That is, the MOSFETs 30 a and 30 c connected in parallel are cut off by the same short-circuit switch 54.

  Similarly, the path L12 connected to the MOS driver 35 for driving the MOSFET 30b is connected to the path L24b at the connection point N14, and the path L12 connected to the MOS driver 35 for driving the MOSFET 30d is connected to the path L12 at the connection point N14. L24d. Then, the path L24b and the path L24d join at a connection point N25b to form a path L25b, and the path L25b is connected to the paths L11a and L11b at connection points N26b and N26d, respectively.

  The short-circuit switch 55 is provided on the path L25b. When a current flows through the path L13 and a predetermined voltage is applied to the short-circuit switch 55, the short-circuit switch 55 is closed, so that the short-circuit paths L12, L24b, L25b, and L11a are connected, and the MOSFET 30b Between the gate terminal 31 and the source terminal 32 via the diode 56. When the short-circuit switch 55 is closed, the short-circuit path L12, the path L24d, the path L25b, and the path L11b are connected, and the gate terminal 31 and the source terminal 32 of the MOSFET 30d are short-circuited via the diode 56. You.

  When the short-circuit path is connected, the voltage at the source terminal 32 of the MOSFET 30 is made equal to the voltage at the gate terminal 31, so that no current flows through the MOSFET 30. Further, since the voltage at the source terminal 32 becomes equal to the voltage at the gate terminal 31, even if the voltage at the source terminal 32 is reduced by a negative surge current or the like, no current flows through the MOSFET 30. Then, the MOSFETs 30a and 30c connected in parallel can be cut off by the same short-circuit switch 54. Similarly, since the MOSFETs 30b and 30d connected in parallel can be cut off by the same short-circuit switch 55, there is no difference in cut-off timing due to the length of the path. In addition, the current flowing through the switch SW1 can be quickly interrupted by interrupting by hardware rather than by the control unit 21 by using software to determine an abnormality.

<Third embodiment>
In the third embodiment, discharge is performed from the gate terminal 31 and the source terminal 32 of the MOSFETs 30a and 30c connected in parallel by the discharge circuit 60. The voltage at the source terminal 32 is made equal to the voltage at the gate terminal 31 by discharging, so that the current flowing through the MOSFET 30 is cut off. Hereinafter, this will be described in detail with reference to FIG.

  The electric path L1 provided with the switch SW1 branches at the branch point N11 in parallel with the paths L31a and L31c, and at the connection point N37, the paths L11a and L11b join to form a path L31e. Then, the path L31e branches in parallel with the paths L31b and L31d at the branch point N38, and at the connection point N12, the paths L31b and L31d merge to become the electric path L1 again.

  In the switch SW1, the MOSFET 30a is provided in the path L31a, the MOSFET 30b is provided in the path L31b, the MOSFET 30c is provided in the path L31c, and the MOSFET 30d is provided in the path L31d. That is, the MOSFETs 30a and 30c are connected in parallel, and the MOSFETs 30b and 30d are connected in parallel. The path L31e is provided with a resistor 41 for measuring a current flowing through the path L31e (switch SW1). The MOSFET 30a and the MOSFET 30b are connected in series via a resistor 41, and the MOSFET 30c and the MOSFET 30d are connected in series via a resistor 41. These MOSFETs 30a and 30b are connected in series such that the parasitic diodes 34 are opposite to each other. The same applies to MOSFETs 30c and 30d.

  An amplifier 42 for detecting a voltage between terminals at both ends of the resistor 41 is connected to both ends of the resistor 41. Then, the detection voltage V (the voltage at both ends of the resistor 41) detected by the amplifier 42 is output to the control unit 21 and the comparator 43. The comparator 43 compares the reference voltages Vref1 and Vref2 with the detection voltage V of the amplifier 42, and outputs the comparison result to the timer IC 45 based on the comparison result. When an ON signal is input from the comparator 43, the timer IC 45 outputs an ON signal to the discharge circuit 60 as a cutoff request for a predetermined time T.

  The discharge circuit 60 is provided at each of the gate terminal 31 and the source terminal 32 of the plurality of MOSFETs 30 connected in parallel, and is provided by the number of MOSFETs 30 connected in series, that is, two in this embodiment. . One discharge circuit 60a is discharged from the MOSFETs 30a and 30c connected in parallel, and the other discharge circuit 60b is discharged from the MOSFETs 30b and 30d connected in parallel.

  The battery unit U is provided with a path L36 connecting the discharge circuit 60 and the connection point N39 on the path L12, and a path L37 connecting the discharge circuit 60 and the connection point N37, respectively. A diode 56 is provided in each of the paths L36 and L37, and regulates the direction of the current flowing through each of the paths L36 and L37. More specifically, the cathode of each diode 56 is connected to each discharge circuit 60. In a normal state, the discharge circuit 60 applies a predetermined voltage so that the discharge from each MOSFET 30 and the MOS driver 35 is not performed. The predetermined voltage is higher than the voltage applied to the gate terminal 31 and the source terminal 32 of each MOSFET 30. That is, at normal times, each discharge circuit 60 is maintained at a voltage higher than the voltage applied by each MOS driver 35.

  When an ON signal as a cutoff request is input from the timer IC 45, the discharge circuit 60a lowers the voltage to a voltage sufficiently lower than the voltage applied to the gate terminal 31 and the source terminal 32 of each MOSFET 30. That is, the voltage of the discharge circuit 60 is lower than the voltages of the gate terminal 31 and the source terminal 32 of the MOSFETs 30a and 30c. When the voltage of the discharge circuit 60a decreases, the voltage is discharged from the gate terminals 31 of the MOSFETs 30a and 30c to the discharge circuit 60a via the path L36, and from the source terminal 32 of the MOSFETs 30a and 30c to the discharge circuit 60a via the path L37. Discharge is performed. Similarly, when an ON signal as a cutoff request is input from the timer IC 45 to the discharge circuit 60b, the voltage becomes sufficiently lower than the voltage applied to the gate terminal 31 and the source terminal 32 of each MOSFET 30. When the voltage of the discharge circuit 60b decreases, the discharge from the gate terminal 31 and the source terminal 32 of the MOSFETs 30b and 30d is performed. By causing the discharge from the gate terminal 31 and the source terminal 32 of the MOSFET 30 in this manner, the voltage at the source terminal 32 can be made equal to the voltage at the gate terminal 31, and no current flows through the MOSFET 30.

  Further, also in the present embodiment, the control unit 21 performs an abnormality determination process. When the control unit 21 determines that there is an abnormality, the control unit 21 outputs an ON signal to the discharge circuit 60 as a forced cutoff signal. In this way, when the control unit 21 determines that an overcurrent is flowing, it outputs an ON signal to the discharge circuit 60, whereby the current of the switch SW1 is cut off. When the control unit 21 determines that it is necessary to shut off, the control unit 21 not only controls the MOS driver 35 to stop the application to the gate terminal 31 but also outputs an ON signal to the discharge circuit 60. Thus, the shutoff can be performed more reliably.

  In the present embodiment, a configuration is provided in which the discharge circuit 60 for discharging the gate terminal 31 and the source terminal 32 is provided. Thus, when an ON signal is input to the discharge circuit 60 as a cutoff request from the timer IC 45, the discharge circuit 60 causes the discharge from the gate terminal 31 and the source terminal 32. Then, by causing the voltage of the source terminal 32 to be equal to the voltage of the gate terminal 31 by discharging, the current flowing through the MOSFET 30 can be cut off.

<Fourth embodiment>
In the fourth embodiment, the configuration for controlling the switches SW1 and SW2 in the configuration of the first embodiment is made redundant. More specifically, the main control unit 21 is a control unit that outputs an open / close command signal for the MOSFET 30, and the main control unit 21 is monitored, and the plurality of MOSFETs 30 are opened based on the monitoring result of the main control unit 21. And a sub-control unit 23 that outputs an open command signal. Hereinafter, a detailed description will be given with reference to FIGS. 1, 2 and 7.

  A switch SW2 is provided on an electric path L2 connecting the lithium ion storage battery 12 and the rotary electric machine 14. MOSFETs 30a to 30d are used for the switch SW2. A MOS driver 35 for driving each of the MOSFETs 30a to 30d is provided. The configuration of the present embodiment may be used for the switch SW1 of the electric path L1 that connects the lead storage battery 11 and the rotating electric machine 14.

  Each MOS driver 35 drives each MOSFET 30 based on an open / close command signal from the main control unit 21. The main control unit 21 outputs an open / close command signal to each MOS driver 35 based on the state of charge of each of the storage batteries 11 and 12 and, when an overcurrent is detected, causes the shutoff unit 70 to shut off each MOSFET 30. Output the forced cutoff signal.

  The cutoff unit 70 includes a short-circuit path (paths L12, L14a, L14b, L14c, L14d, L15a, L15b, L11a, L11b), a bipolar transistor 51, an output switch 52, and short-circuit switches 54, 55, and these are attached to these. And a path and configuration for blocking. In order to detect the current flowing through each MOSFET 30, the voltage between the terminals at both ends of the resistor 41 is detected by the amplifier 42 and output. Based on the detection voltage V detected and output by the amplifier 42, the comparator 43 determines an overcurrent. The timer IC 45 outputs a cutoff request based on the result of the determination by the comparator 43. In response to the shutoff request output from the timer IC 45, the shutoff unit 70 short-circuits the gate terminal 31 and the source terminal 32 of the MOSFET 30 and shuts off the MOSFET 30.

  Note that, as in the third embodiment, the shutoff unit 70 may be configured to have the discharge circuit 60. Specifically, the cutoff unit 70 has a discharge circuit 60, a path L36 connecting the discharge circuit 60 and the gate terminal 31 via the path L12, and a path L27 connecting the discharge circuit 60 and the source terminal 32. May be. In this case, the cutoff unit 70 cuts off the MOSFET 30 by lowering the voltage of the discharge circuit 60 and equalizing the voltage of the gate terminal 31 and the source terminal 32 in response to the cutoff request.

  Further, a sub control unit 23 for monitoring the main control unit 21 is provided. The main control unit 21 and the sub control unit 23 monitor each other's state. For example, the main control unit 21 and the sub-control unit 23 monitor each other's situation by a detection mechanism that determines whether the same command has been executed in a certain period of time called a so-called watchdog timer. The sub control unit 23 may monitor the power supply voltage of the main control unit 21 and determine that the main control unit 21 is abnormal when the power supply voltage becomes lower than a predetermined value.

  Further, the main control unit 21 and the sub control unit 23 are connected to different power supply devices V1 and V2, and power is supplied from the different power supply devices V1 and V2. That is, even when the power supply from the power supply devices V1 and V2 to one of the main control unit 21 and the sub control unit 23 is stopped, the power is supplied to the other. Each of the power supply devices V1 and V2 is a power supply IC that supplies electric power supplied from the power supply of each of the storage batteries 11 and 12 to a constant voltage and supplies the electric power to each of the control units 21 and 23. It is desirable that the power supplies that supply power to the power supply devices V1 and V2 are different.

  When determining that the main control unit 21 is abnormal, the sub control unit 23 outputs an open command signal for opening the MOSFET 30 to the shutoff unit 70. When the open command signal is input, the cutoff unit 70 short-circuits the gate terminal 31 and the source terminal 32 of the MOSFET 30 to cut off the MOSFET 30. By outputting the open command signal to the cutoff unit 70, the MOSFET 30 can be opened even when the MOS driver 35 has an abnormality.

  In the present embodiment, the sub-control unit 23 monitors the main control unit 21 and outputs an open command signal for opening the MOSFET 30 when any trouble is suspected in the main control unit 21. This makes the configuration for outputting a command to open the MOSFET 30 redundant to prevent current from flowing through the electric path L2 when appropriate control cannot be performed. Therefore, overcharge and overdischarge of the lithium ion storage battery 12 can be suppressed. Further, in addition to the measures for quickly shutting off when an overcurrent flows in the first embodiment, it is possible to appropriately deal with an abnormality occurring in the main control unit 21 and improve system reliability.

  The sub-control unit 23 is configured to output an open command signal for opening the MOSFET 30 to the shut-off unit 70 based on the monitoring result of the main control unit 21. Thereby, the sub control unit 23 can open the MOSFET 30 by a mechanism different from each MOS driver 35. Therefore, no matter what control command the main control unit 21 issues to each MOS driver 35, the MOSFET 30 can be reliably opened. Further, even when the main control unit 21 and the MOS driver 35 fail simultaneously, the MOSFET 30 can be opened.

  Further, the main control unit 21 and the sub control unit 23 are connected to different power supply devices V1 and V2, and power is supplied from the different power supply devices V1 and V2. Thus, even if power is not supplied from the power supply device V1 to the main control unit 21, the sub-control unit 23 can open the MOSFET 30.

<Other embodiments>
The present invention is not limited to the above embodiment, and may be implemented, for example, as follows. Incidentally, the configuration of the following another example may be individually applied to the configuration of the above-described embodiment, or may be arbitrarily combined and applied.

  In the above-described embodiment, the dual power supply system includes two storage batteries, but may include only one of the storage batteries.

  In the above embodiment, the lithium ion storage battery 12 is provided as the second storage battery, but this may be changed. As the second storage battery, a high-density storage battery other than the lithium-ion storage battery 12, for example, a nickel-metal hydride battery may be used. In addition, the same storage battery (for example, a lead storage battery or a lithium ion storage battery) can be used as the first storage battery and the second storage battery.

  In the above embodiment, the MOSFETs 30 in the switches SW1 and SW2 are connected in parallel with each other. However, the switches 30 and SW4 may be connected in parallel with each other so that the MOSFETs 30 are connected in parallel. In that case, the “electric device” includes the electric load 15.

  In the above embodiment, the resistor 41 for detecting the current is provided between the MOSFETs 30 connected in series. However, the circuit for detecting the current (the resistor 41) is provided before and after the MOSFET 30. You may. That is, the circuit for detecting the current only needs to be provided on the energizing path of the switches SW1 and SW2. Further, the configuration for detecting the current is not limited to the resistor 41 and the amplifier 42, and may be detected by another configuration.

  In the above embodiment, the amplifier 42 outputs to the comparator 43 and the controller 20. However, the amplifier 42 that outputs to the comparator 43 and the first amplifier 42a and the second amplifier 42b that outputs to the controller 20 It may be provided. For example, FIG. 8 shows an example in which an amplifier 42 for outputting to the comparator 43 and an amplifier 42 for outputting to the control unit 20 are provided in the circuit of the first embodiment. A first amplifier 42a and a second amplifier 42b for detecting a terminal-to-terminal voltage at both ends of the resistor 41 are connected to both ends of the resistor 41 serving as a detection unit. Then, the detection voltage V is output from each of the amplifiers 42a and 42b to the comparator 43 and the control unit 20. As described above, by dividing the amplifiers 42a and 42b that output to the comparator 43 and the control unit 20, the redundancy of the current detection circuit can be ensured. Although the first embodiment has been illustrated, the second and third embodiments may similarly include a first amplifier 42a that outputs to the comparator 43 and a second amplifier 42b that outputs to the control unit 20. Further, the first amplifier 42a and the second amplifier 42b output the voltage between the terminals at both ends of the resistor 41 to the comparator 43 and the control unit 20, but a current sensor is provided as a detecting unit instead of the resistor 41. The detection result of the current sensor may be output by the first amplifier 42a and the second amplifier 42b.

  In the above embodiment, the control unit 21 also outputs the ON signal on the same path as the timer IC 45. However, the control unit 21 may output only the open / close command signal to the MOS driver 35 as the forced cutoff signal. .

  In the above embodiment, the MOSFET 30 is used as the “semiconductor switching element” used for the switches SW1 and SW2, but another semiconductor switching element such as an IGBT may be used. For example, when an IGBT is used, the gate terminal corresponds to a “control terminal”, the emitter terminal corresponds to a “first terminal”, and the collector terminal corresponds to a “second terminal”.

  In the above-described second embodiment, the resistors 41 and the amplifier 42 are provided in each of the paths L11a and L11b. However, as in the third embodiment, the paths are merged and branched so as to be one resistor 41 and the amplifier 42. May be.

  In the fourth embodiment, the sub control unit 23 outputs the open command signal to the cutoff unit 70, but may output the open command signal to the MOS driver 35 instead of the cutoff unit 70. Further, an open command signal may be output to both the shutoff unit 70 and the MOS driver 35.

  DESCRIPTION OF SYMBOLS 11 ... Lead storage battery, 12 ... Lithium ion storage battery, 13a ... Path, 13b ... Path, 14 ... Rotating electric machine, 21 ... Control part, 30 ... MOSFET, 31 ... Gate terminal, 32 ... Source terminal, 35 ... MOS driver, 54 ... Short circuit switch, 55 short circuit switch, 60 discharge circuit, L1 electric path, L2 electric path, L3 electric path, L4 electric path, SW1 switch, SW2 switch.

Claims (9)

A switch unit (SW1, SW2) provided in an electric path (L1, L2) connecting the storage batteries (11, 12) and the electric device (14) and having a plurality of semiconductor switching elements (30) connected in parallel with each other; ,
By applying a voltage difference between the control terminal (31) and the first terminal among the other first terminal (32) and the second terminal (33) in the plurality of semiconductor switching elements, A drive circuit (35) for closing the circuit;
A control unit (21) that outputs an opening / closing command signal for the plurality of semiconductor switching elements to the drive circuit;
A cutoff request output unit (43, 45) that outputs a cutoff request for the plurality of semiconductor switching elements based on a current flowing through the switch unit;
When the cutoff request is output from the cutoff request output unit, the plurality of semiconductor switching elements are cut off by making the voltage of the first terminal equal to the voltage of the control terminal in the plurality of semiconductor switching elements. Interrupting circuits (52, 54, 55, 60)
A storage battery system comprising: The shutoff circuit,
A short-circuit switch (54, 55) that is provided on a short-circuit path that short-circuits the control terminal and the first terminal in the plurality of semiconductor switching elements and that can open and close the short-circuit path;
2. The storage battery according to claim 1, wherein when the cutoff request is output from the cutoff request output unit, the short-circuit switch is closed to make the voltage of the first terminal equal to the voltage of the control terminal. 3. system. The shutoff circuit,
The plurality of semiconductor switching elements are connected to an electric path (L12) between the control terminal and the drive circuit, and are connected to the first terminal to perform discharge from the control terminal and the first terminal. A discharge circuit (60) for causing
When the cutoff request is output from the cutoff request output unit, the discharge circuit causes the control terminal and the first terminal to discharge, so that the voltage of the first terminal is equal to the voltage of the control terminal. The storage battery system according to claim 1, which is the same.   4. The storage battery system according to claim 1, wherein the drive circuit is provided for each of the plurality of semiconductor switching elements that are parallel to each other. 5. The control unit outputs a forcible shutoff signal for shutting off the plurality of semiconductor switching elements to the shutoff circuit, based on a current flowing through the switch unit.
The interrupt request output unit, after outputting the interrupt request based on the current flowing through the switch unit, maintains the interrupt request at least until the forcible interrupt signal is output from the control unit. The storage battery system according to any one of claims 1 to 4. A current detection circuit that detects and outputs a conduction current flowing through the switch unit,
The current detection circuit includes: a detection unit (41) that can detect a current flowing through the switch unit; a first amplifier (42a) that outputs a detection result of the detection unit to the cutoff request output unit; The storage battery system according to claim 5, further comprising a second amplifier (42b) that outputs a detection result of the unit to the control unit. A main control unit (21) which is the control unit;
The sub-control unit (23) that monitors the main control unit and outputs an open command signal for opening the plurality of semiconductor switching elements based on a monitoring result of the main control unit. The storage battery system according to claim 6.   The storage battery system according to claim 7, wherein the sub-control unit outputs the open command signal to the shut-off circuit based on a monitoring result of the main control unit.   The storage battery system according to claim 7, wherein the main control unit and the sub control unit are connected to different power supply devices, and configured to be supplied with power from the different power supply devices.

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