JP2020012977A - Display - Google Patents

Abstract

To provide a display that can further prevent extension of the wiring length accompanying expansion of a display area.SOLUTION: A display 1 comprises: an electrode layer on which a plurality of reflecting electrodes are arranged; and a circuit layer that is provided on a layer lower than the electrode layer, the circuit layer provided with memories storing data for driving pixels and source line driver circuits 5 outputting data to be written in the memories. The plurality of reflecting electrodes are included in any of a plurality of sub-pixel arrays according to the arrangement; the source line driving circuits are provided respectively in the sub-pixel arrays; an interface circuit is shared by the adjacent sub-pixel arrays.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a display device.

  When the display area is simply enlarged in the display device, the wiring length for signal transmission to each of the plurality of pixels arranged in the display area becomes longer. When the wiring length is long, problems such as an increase in power required for stable signal transmission occur. Therefore, there is a method of providing a solar cell in a display device installed outdoors to supplement power for display (for example, Patent Document 1).

JP 2006-308713 A

  However, power supply by solar cells whose power generation amount changes due to weather conditions and the like has been unstable. Further, the solar cell has not been able to solve other problems caused by the increase in the length of the wiring accompanying the expansion of the display area. Therefore, in the related art, it has been difficult to solve the problem due to the increase in the wiring length due to the enlargement of the display area.

  An object of the present invention is to provide a display device that can further suppress an increase in wiring length due to an increase in a display area.

  A display device of one embodiment of the present invention includes an electrode layer in which a plurality of reflective electrodes are arranged, and a circuit layer provided below the electrode layer, and the circuit layer is provided corresponding to each reflective electrode. A plurality of memories, a signal output circuit that outputs data written to each memory, and an interface circuit that controls the signal output circuit based on an external signal, wherein the plurality of reflective electrodes are grouped into a plurality of groups. In addition, the signal output circuits are provided for each group, and the interface circuits are shared by the adjacent groups.

FIG. 1 is a schematic diagram illustrating a main configuration example provided in the display device of the embodiment. FIG. 2 is a schematic diagram showing a schematic laminated structure of the display device. FIG. 3 is a schematic diagram showing a schematic laminated structure of the display device. FIG. 4 is a schematic diagram illustrating an example of a wiring connecting a reflective electrode and a sub-pixel circuit. FIG. 5 is a schematic diagram illustrating an example of the arrangement of the reflective electrodes. FIG. 6 is a schematic diagram illustrating an example of the positional relationship between the reflective electrode, the connection line, and the sub-pixel circuit near the vertex of the display device. FIG. 7 is a diagram showing an example of the arrangement of circuits provided in the same layer as the circuit section near the top of the same display device as in FIG. FIG. 8 is a sectional view of the display device of the embodiment. FIG. 9 is a schematic explanatory diagram showing a configuration related to sub-pixels included in one sub-pixel array and gradation control of the sub-pixels. FIG. 10 is a diagram illustrating an arrangement of sub-pixels in a pixel of the display device according to the embodiment. FIG. 11 is a diagram illustrating a circuit configuration of the display device of the embodiment. FIG. 12 is a diagram illustrating a circuit configuration of a sub-pixel of the display device of the embodiment. FIG. 13 is a diagram illustrating a circuit configuration of a memory of a sub-pixel of the display device of the embodiment. FIG. 14 is a diagram illustrating a circuit configuration of an inversion switch of a sub-pixel of the display device of the embodiment. FIG. 15 is a timing chart showing the operation timing of the display device of the embodiment. FIG. 16 is a schematic diagram illustrating an example of a circuit configuration included in the display device according to the first modification. FIG. 17 is a schematic diagram illustrating an example of a circuit configuration of Modification Example 2. FIG. 18 is a diagram illustrating an application example of the embodiment and the like. FIG. 19 is a sectional view taken along line VV of FIG.

  An embodiment (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited by the contents described in the following embodiments. The components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be appropriately combined. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention, which are naturally included in the scope of the present invention. In addition, in order to make the description clearer, the width, thickness, shape, and the like of each part may be schematically illustrated as compared with actual embodiments, but this is merely an example, and the interpretation of the present invention is not limited thereto. It is not limited. In the specification and the drawings, components similar to those described in regard to a drawing thereinabove are marked with like reference numerals, and a detailed description is omitted as appropriate.

(Embodiment)
FIG. 1 is a schematic diagram illustrating an example of a main configuration of a display device 1 according to an embodiment. The display device 1 includes an interface circuit 4, a source line drive circuit 5, a common electrode drive circuit 6, an inversion drive circuit 7, a memory selection circuit 8, a gate line drive circuit 9, a gate line selection circuit 10, a static protection circuit 20, It includes a power protection circuit 40, a clock buffer 80, a sub-pixel array 90, a flexible printed circuit board FPC, and the like. In the display device 1, one common electrode drive circuit 6 is provided, and a plurality of other configurations are provided.

  In the following description, two directions along a plane on which the sub-pixels SPix (see FIG. 9) provided in the sub-pixel array 90 are arranged are defined as an X direction and a Y direction, and a direction orthogonal to the X direction and the Y direction is defined as a Z direction. I do. The X direction and the Y direction are orthogonal.

  The sub-pixel array 90 includes sub-pixel circuits 70 corresponding to the number of sub-pixels SPix and the reflective electrode 15 (see FIG. 5 and the like). The sub-pixel circuits 70 and the reflective electrodes 15 are arranged in a matrix along the X and Y directions.

  FIG. 1 illustrates the display device 1 in which the X direction × Y direction = 2 × 3, that is, a total of six sub-pixel arrays 90 is provided. Each sub-pixel array 90 forms a group with the individual source line driving circuit 5, memory selecting circuit 8, gate line driving circuit 9, and gate line selecting circuit 10. That is, in the display device 1 shown in FIG. 1, six source line driving circuits 5, memory selection circuits 8, gate line driving circuits 9, and six gate line selection circuits 10 are provided. In FIG. 1 and FIG. 5 described later, in order to distinguish the positions of the six source line driving circuits 5, the memory selecting circuit 8, the gate line driving circuit 9, the gate line selecting circuit 10, and the sub-pixel array 90, a lower case alphabet (a , B, c, d, e, f) are appended to the end of the reference numerals. For example, the source line driving circuit 5a, the memory selection circuit 8a, the gate line driving circuit 9a, the gate line selection circuit 10a, and the sub-pixel array 90a form one group. The source line driving circuit 5, the memory selecting circuit 8, the gate line driving circuit 9, the gate line selecting circuit 10, and the sub-pixel array 90, which are suffixed with other lowercase alphabets (b, c, d, e, f). The same is true and can be replaced by replacing the end of the code. That is, the sub-pixel array 90 is divided into a plurality of groups. Each group is provided with a source line driving circuit 5, a memory selection circuit 8, a gate line driving circuit 9, and a gate line selection circuit 10.

  In FIG. 1, the X direction × Y direction = 1 × 3, that is, a total of three interface circuits 4, an inversion drive circuit 7, an electrostatic protection circuit 20, an electrostatic protection circuit 40, a clock buffer 80, and a flexible printed circuit board FPC. The illustrated display device 1 is illustrated. The two sub-pixel arrays 90 provided in the Y direction share the interface circuit 4, the inversion drive circuit 7, the electrostatic protection circuit 20, the electrostatic protection circuit 40, the clock buffer 80, and the flexible printed circuit board FPC. 1 and 5, upper case alphabets (A, B, C) are used to distinguish the positions of the three interface circuits 4, the inversion drive circuit 7, the electrostatic protection circuit 20, the electrostatic protection circuit 40, and the clock buffer 80. Is appended to the end of the code. In addition, the sharing relationship is shown as (α: β, γ), where α is an uppercase alphabet assigned to a shared configuration, and β and γ are lowercase alphabets assigned to two configurations sharing one configuration. In this case, (A: a, b), (B: c, d), (C: e, f) hold. For example, the sub-pixel array 90a and the sub-pixel array 90b share the interface circuit 4A, the inversion drive circuit 7A, the electrostatic protection circuit 20A, the electrostatic protection circuit 40A, the clock buffer 80A, and the flexible printed circuit board FPCA. The same applies to other sharing relationships, which can be replaced by replacing the end of the code.

  In the description of the embodiment, the description in which the reference numerals in which the lowercase alphabet or the uppercase alphabet is omitted is used for the function of the configuration, and does not distinguish the position where the configuration is provided.

  A signal flow in a configuration included in the same group as one sub-pixel array 90 will be described. Signals (command data CMD, image data ID) related to gradation control of the sub-pixel SPix are input from the flexible printed circuit board FPC and transmitted to the interface circuit 4 via the electrostatic protection circuit 20. The electrostatic protection circuit 20 functions as an input buffer. The interface circuit 4 outputs various signals for operating the source line driving circuit 5, the inversion driving circuit 7, the memory selection circuit 8, the gate line driving circuit 9, and the gate line selection circuit 10 based on the input signals. . The source line drive circuit 5, the inversion drive circuit 7, the memory selection circuit 8, the gate line drive circuit 9, and the gate line selection circuit 10 operate according to the signal from the interface circuit 4, and control the gradation of the sub-pixel array 90. Do. Further, the reference clock signal CLK is input from the flexible printed circuit board FPC and transmitted to the clock buffer 80 via the electrostatic protection circuit 40. The electrostatic protection circuit 40 functions as an input buffer. The clock buffer 80 buffers the reference clock signal CLK and outputs it to the inversion drive circuit 7 and the memory selection circuit 8. The inversion drive circuit 7 and the memory selection circuit 8 are synchronously controlled based on the reference clock signal CLK output from the clock buffer 80.

  In FIG. 1, two sub-pixel arrays 90 provided in the Y direction share the interface circuit 4 and the inversion drive circuit 7. That is, signals (command data CMD, image data ID) relating to gradation control of the sub-pixels SPix provided in the two sub-pixel arrays 90 are input to the interface circuit 4, and are individually connected to each of the two sub-pixel arrays 90. The signals are individually output to the source line driving circuit 5, the memory selecting circuit 8, the gate line driving circuit 9, and the gate line selecting circuit 10 forming a group. The two sub-pixel arrays 90 share the clock buffer 80. That is, the memory selection circuits 8 individually forming a group with each of the two sub-pixel arrays 90 operate synchronously based on the reference clock signal CLK output from one shared clock buffer 80. The two sub-pixel arrays 90 share the inversion drive circuit 7. That is, the inversion drive cycle of the sub-pixel SPix by the inversion drive circuit 7 is also synchronized based on the reference clock signal CLK output from one shared clock buffer 80.

  The flow of the signals described above is indicated by arrows in FIG. The display device 1 has a configuration (wiring, switch, and the like) for electrical connection to realize a signal flow indicated by an arrow in FIG. The term “connection” in the following description refers to “electrical connection” via a wiring, a switch, and the like, unless otherwise specified.

  The source line drive circuit 5 and the gate line selection circuit 10 are arranged so as to be adjacent to one side of a rectangular region in which the sub-pixel circuits 70 of the sub-pixel array 90 included in the same group are arranged. The source line driving circuit 5 is provided so that the longitudinal direction is along one direction (for example, the X direction) in which the sub-pixel circuits 70 are arranged. The gate line selection circuit 10 is provided so that the longitudinal direction is along the other direction (for example, the Y direction) in which the sub-pixel circuits 70 are arranged. The memory selection circuit 8 and the gate line drive circuit 9 are provided in parallel with the gate line selection circuits 10 of the same group. The memory selection circuit 8 is provided for each group, and is disposed at least partially between a memory group of the same group and a memory group of a group adjacent to the group. For example, the memory selection circuit 8c is disposed between the sub-pixel circuits 70 of the sub-pixel array 90c included in the same group and the sub-pixel circuits 70 of the sub-pixel array 90a. Further, the memory selection circuit 8d is arranged between the sub-pixel circuits 70 of the sub-pixel array 90d included in the same group and the sub-pixel circuits 70 of the sub-pixel array 90b.

  Further, the inversion drive circuit 7A and the clock buffer 80A are a circuit group including the memory selection circuit 8, the gate line drive circuit 9, and the gate line selection circuit 10 which are respectively owned by two groups sharing the inversion drive circuit 7A and the clock buffer 80A. (For example, between a region where the memory selection circuit 8a, the gate line driving circuit 9a and the gate line selection circuit 10a are arranged, and a region where the memory selection circuit 8b, the gate line driving circuit 9b and the gate line selection circuit 10b are arranged). To position. The same applies to other sharing relationships, which can be replaced by replacing the end of the code.

  The difference between the memory selection circuit 8 and the clock buffer 80 of the two groups that share the clock buffer 80 is that the difference between the groups is that the difference between the synchronization control based on the reference clock signal CLK and the display control timing of the sub-pixel array 90. It is difficult to visually recognize as a deviation, and a certain difference (ideally, 0) is provided. In other words, the clock buffer 80 converts the reference clock signal CLK input from the flexible printed circuit board FPC and passed through the electrostatic protection circuit 40 into a position and a wiring that can be used for synchronous control of the two groups of memory selection circuits 8. Buffer and relay the reference clock signal CLK.

  Similar to the relationship between the memory selection circuit 8 and the clock buffer 80, two groups of the source line drive circuit 5, the memory selection circuit 8, the gate line drive circuit 9, and the gate line which share the interface circuit 4 and the inversion drive circuit 7 are shared. The selection circuit 10 and the sub-pixel array 90 are provided to minimize the difference in signal transmission path length so that the difference in signal transmission time between groups is as small as possible. For example, the interface circuit 4 is located between two sub-pixel arrays 90 sharing the interface circuit 4. Specifically, the interface circuit 4 is provided, for example, between two source line drive circuits 5 included in a group of two sub-pixel arrays 90 sharing the interface circuit 4. For example, the interface circuit 4A is provided so as to be located between the source line driving circuit 5a and the source line driving circuit 5b. These configurations in the circuit layer 17L include the sub-pixel array 90a, the source line driving circuit 5a, the interface circuit 4A, the source line driving circuit 5b, and the sub-pixel array 90b along the Y direction from the opposite side of the flexible printed circuit board FPCA. Are arranged in this order. The positions of the electrostatic protection circuits 20A and 40D in the Y direction are between the sub-pixel array 90b and the flexible printed circuit board FPCA. The same applies to other sharing relationships, which can be replaced by replacing the end of the code. Thereby, the synchronization control of the two groups arranged in the Y direction can be made easier.

  The sub-pixel array 90 includes a plurality of sub-pixels SPix arranged in the X direction × Y direction. Each sub-pixel SPix includes a reflective electrode 15 and a sub-pixel circuit 70. The sub-pixel circuit 70 includes an interface circuit 4, a source line drive circuit 5, a common electrode drive circuit 6, an inversion drive circuit 7, a memory selection circuit 8, a gate line drive circuit 9, a gate line selection circuit 10, an electrostatic protection circuit 20, It is provided on the same layer as the circuits such as the electrostatic protection circuit 40 and the clock buffer 80. The reflective electrode 15 is provided on a different layer from those circuits.

  FIG. 2 and FIG. 3 are schematic diagrams illustrating a schematic stacked structure of the display device 1. The display device 1 has a first panel 2 and a second panel 3. The first panel 2 and the second panel 3 are arranged to face each other. A liquid crystal layer 30 is provided between the first panel 2 and the second panel 3. The liquid crystal layer 30 is sealed by a seal member SM.

  The flexible printed circuit board FPC is provided on one end side of the first panel 2 via FOG (Film On Glass). Further, the first panel 2 is provided with an insulating layer 12 and an alignment film 18 stacked on the insulating layer 12. The sub-pixel circuit 70 is provided below the insulating layer 12. The reflective electrode 15 is provided above the insulating layer 12 and below the alignment film 18. The display device 1 is a display device in which a plurality of sub-pixels SPix having a reflective electrode 15 that reflects light on one surface (display surface 1a) side displaying an image are arranged.

FIG. 4 is a schematic diagram illustrating an example of a wiring connecting the reflective electrode 15 and the sub-pixel circuit 70. Each reflective electrode 15 is connected to a different sub-pixel circuit 70 via the laminated wiring 16. In FIGS. 3 and 4, for example, the three reflective electrodes 15, the laminated wiring 16, and the sub-pixel circuit 70 are denoted by subscripts. For example, the reflective electrode 15 ₁ is connected via the laminated wiring 16 ₁ and the sub-pixel circuit 70 _1. The same applies to the connection between the reflective electrode 15 and the sub-pixel circuit 70 by another laminated wiring 16 (replacement by subscript replacement). Reflective electrodes 15 ₁ - laminated wiring 16 ₁ - a connection path of the sub-pixel circuit 70 _1, the reflective electrode 15 ₂ - laminated wiring 16 ₂ - and connection path of the sub-pixel circuit 70 _2, the reflective electrode 15 ₃ - laminated wiring 16 ₃ - connection path of the sub-pixel circuit 70 ₃ are each independent and these connection path is disconnected. Specifically, for example, as shown in FIG. 4, the stacked wirings 16 are provided so as not to be in contact with each other when viewed in a plan view. Here, the connection path between the three reflective electrodes 15, the laminated wiring 16, and the sub-pixel circuit 70, which are denoted by subscripts, is illustrated. Is the same, and the connection paths are not connected.

  In FIG. 4, the positions of the reflective electrode 15, the laminated wiring 16, and the sub-pixel circuit 70 are shown shifted for the purpose of clarifying the connection relationship between the reflective electrode 15, the laminated wiring 16, and the sub-pixel circuit 70. Has a positional relationship in which the reflective electrode 15, the laminated wiring 16, and the sub-pixel circuit 70 are laminated such that the reference position CP in the X direction coincides with the XY plane (see FIG. 3).

  3 and 4 show an example in which the multilayer wiring 16 is formed using a plurality of wiring layers including the contact hole CH, but the multilayer wiring 16 uses a single wiring layer. May be formed. Further, in order to prevent a short circuit between the stacked wirings 16, it is also possible to adopt a configuration in which the insulating layers are formed in a plurality of layers, the stacked wirings 16 are provided between the respective layers, and connected by contact portions.

  FIG. 5 is a schematic diagram showing an example of the arrangement of the reflection electrodes 15. A plurality of reflective electrodes 15 are arranged on the electrode layer 15L. Specifically, as shown in FIG. 3, the reflective electrode 15 is stacked closer to the display surface 1a than circuits such as the interface circuit 4, the source line driving circuit 5, the electrostatic protection circuit 20, and the sub-pixel circuit 70. . The plurality of reflective electrodes 15 are included in any of a plurality of groups (for example, the sub-pixel arrays 90a to 90f) depending on the arrangement. When viewed from the display surface 1a side, as shown in FIG. 5, the circuit layer 17L provided with circuits such as the interface circuit 4, the source line driving circuit 5, the electrostatic protection circuit 20, and the sub-pixel circuit 70 includes: It is covered with an electrode layer 15L provided with a plurality of reflective electrodes 15 arranged along the XY plane. That is, in the display device 1 of the embodiment, a frame region for providing a circuit is not required in the display region where the reflective electrode 15 is provided. Therefore, an image can be displayed over a wider range of the display surface 1a.

The reflective electrode 15 and the sub-pixel circuit 70 connected via the stacked wiring 16 may be located at positions overlapping in the Z direction or may be located at positions not overlapping in the Z direction. In the example shown in FIGS. 4 and 5, the reflective electrode 15 ₁ and the sub-pixel circuit 70 _1, a positional relationship of position in the Y direction is deviated not to overlap in the Z direction. FIG. 4 shows an example in which the positional relationship in the X direction matches, but the positional relationship between the reflective electrode 15 and the sub-pixel circuit 70 in the X direction can be changed as appropriate.

  FIG. 6 is a schematic diagram illustrating an example of the positional relationship between the reflective electrode 15, the stacked wiring 16, and the sub-pixel circuit 70 near the apex of the display device 1. FIG. In FIG. 6, an electrode unit 150 provided with a reflection electrode 15 of X direction × Y direction = 6 × 7, a circuit unit 170 provided with a subpixel circuit 70 of X direction × Y direction = 6 × 7, The relationship between the X direction × Y direction = 6 × 7 reflective electrodes 15 and the wiring layer 160 including the 42 stacked wirings 16 that individually connect the sub-pixel circuits 70 is illustrated. As illustrated in FIG. 6, even if the reflective electrode 15 and the sub-pixel circuit 70 connected via the laminated wiring 16 are displaced in the X direction and the Y direction and have a positional relationship such that they do not overlap in the Z direction. Good. By connecting the reflective electrode 15 and the sub-pixel circuit 70 using the laminated wiring 16, the reflective electrode 15 can be provided without being limited by the arrangement of the sub-pixel circuit 70.

  FIG. 7 is a diagram illustrating an example of the arrangement of circuits provided on the same layer as the circuit unit 170 near the top of the same display device 1 as in FIG. The common electrode drive circuit 6 is arranged, for example, near the vertex of the display device 1. Further, for example, the electrostatic protection circuit 20 </ b> A is arranged adjacent to the circuit section 170 in the Y direction. Further, for example, the gate line selection circuit 10b is arranged adjacent to the circuit section 170 in the X direction. Further, for example, a gate line driving circuit 9b and a memory selection circuit 8b are arranged so as to be arranged in the X direction with the gate line selection circuit 10b. Further, for example, an electrostatic protection circuit 40A is arranged so as to be located between the common electrode drive circuit 6 and the electrostatic protection circuit 20A. The common electrode drive circuit 6 and the electrostatic protection circuit 40A, and a part of the memory selection circuit 8b, the gate line drive circuit 9b, the gate line selection circuit 10b, and the electrostatic protection circuit 20A are arranged at positions overlapping the electrode unit 150. . By connecting the reflective electrode 15 and the sub-pixel circuit 70 using the laminated wiring 16, the degree of freedom of arrangement of various circuits on the back side of the reflective electrode 15 with respect to the display surface 1a is further improved.

  Although not shown in FIG. 7, the memory selection circuit 8, the gate line drive circuit 9, the gate line selection circuit 10, the electrostatic protection circuit 20, the electrostatic protection circuit 40, and the like having different reference numerals (lowercase alphabet or uppercase alphabet) are also It is disposed on the back side of the reflective electrode 15 with respect to the display surface 1a, and in the same layer as the sub-pixel circuit 70. Although not shown in FIGS. 3 and 7, the inversion drive circuit 7 and the clock buffer 80 are also arranged on the back side of the reflective electrode 15 with respect to the display surface 1 a and on the same layer as the sub-pixel circuit 70. .

  One reflective electrode 15 is, for example, a rectangular reflective electrode of 1 [mm] square, but this is an example of the dimensions of the reflective electrode 15 and is not limited thereto, and can be changed as appropriate.

  FIG. 8 is a sectional view of the display device of the embodiment. Light incident from the outside on the display surface 1a side is reflected by the reflective electrode 15 of the first panel 2 and exits from the display surface 1a. The display device 1 of the embodiment is a reflection type liquid crystal display device that displays an image on the display surface 1a using the reflected light. The first panel 2 includes an insulating layer 12, a reflective electrode 15, an alignment film 18, and the like stacked on the circuit layer 17L of the first substrate 11 (on the display surface 1a side).

  The insulating layer 12 is provided on the first substrate 11 and planarizes the entire surface of circuit elements and various wirings included in the circuit layer 17L. A plurality of reflective electrodes 15 are provided on the insulating layer 12. The alignment film 18 is provided between the reflective electrode 15 and the liquid crystal layer 30. The reflective electrode 15 and the laminated wiring 16 are formed of a metal exemplified by aluminum (Al) or silver (Ag). Further, the reflective electrode 15 may have a configuration in which these metal materials and a light-transmitting conductive material exemplified by ITO (Indium Tin Oxide) are stacked. The reflective electrode 15 is made of a material having a good reflectance, and functions as a reflective plate that diffusely reflects light incident from the outside.

  Although the light reflected by the reflective electrode 15 is scattered by diffuse reflection, it travels in a uniform direction toward the display surface 1a. When the voltage level applied to the reflective electrode 15 changes, the light transmission state of the liquid crystal layer 30 on the reflection electrode, that is, the light transmission state of each sub-pixel changes. That is, the reflective electrode 15 also has a function as a sub-pixel electrode.

  The second panel 3 includes a second substrate 21, a color filter 22, a common electrode 23, an alignment film 28, a 波長 wavelength plate 24, a 波長 wavelength plate 25, and a polarizing plate 26. A color filter 22 and a common electrode 23 are provided in this order on a surface facing the first panel 2 of both surfaces of the second substrate 21. An alignment film 28 is provided between the common electrode 23 and the liquid crystal layer 30. A 表示 wavelength plate 24, a 波長 wavelength plate 25, and a polarizing plate 26 are stacked in this order on the surface of the second substrate 21 on the display surface 1a side.

  The common electrode 23 is formed of a translucent conductive material exemplified by ITO. The common electrode 23 is arranged to face the plurality of reflective electrodes 15 and supplies a common potential to each sub-pixel SPix. The color filter 22 has, for example, three color filters of R (red), G (green), and B (blue), but the present disclosure is not limited thereto, and can be appropriately changed.

  The liquid crystal layer 30 includes, for example, a nematic liquid crystal. In the liquid crystal layer 30, the alignment state of the liquid crystal molecules changes by changing the voltage level between the common electrode 23 and the reflective electrode 15. As a result, light transmitted through the liquid crystal layer 30 is modulated for each sub-pixel SPix.

  External light or the like becomes incident light that enters from the display surface 1 a side of the display device 1, passes through the second panel 3 and the liquid crystal layer 30, and reaches the reflective electrode 15. Then, the incident light is reflected by the reflection electrode 15 of each sub-pixel SPix. The reflected light is modulated for each sub-pixel SPix and emitted from the display surface 1a. As a result, an image is displayed. The first substrate 11 and the second substrate 21 are, for example, glass substrates or resin substrates, but are not limited thereto, and can be changed as appropriate.

  Next, the sub-pixel SPix included in one sub-pixel array 90 and gradation control of the sub-pixel SPix will be described. FIG. 9 is a schematic explanatory diagram illustrating a sub-pixel SPix included in one sub-pixel array 90 and a configuration related to gradation control of the sub-pixel SPix.

  In the embodiment, one pixel Pix is constituted by a predetermined number of sub-pixels SPix in one sub-pixel array 90. In the embodiment, the number of sub-pixels SPix constituting one pixel Pix is R (red), G (green), and B (blue) arranged in the X direction, but the present disclosure is not limited thereto. The number of sub-pixels SPix constituting one pixel Pix may be four (R) (red), G (green), and B (blue) plus W (white). Alternatively, the number of sub-pixels SPix constituting one pixel Pix may be five or more having different colors, or may be two.

  In the embodiment, since the sub-pixels SPix constituting one pixel Pix are three sub-pixels SPix arranged in the X direction, if the number of pixels Pix is X direction × Y direction = M × N, one sub pixel SPix In the array 90, M × N × 3 sub-pixels SPix are arranged.

  Each sub-pixel SPix includes a plurality (n) of memories (see FIG. 10). In the following description with reference to FIGS. 11 to 15, the case where n = 3 is taken as an example, but the present disclosure is not limited to this. n may be a natural number of 2 or more. The n memories are provided in the sub-pixel circuit 70. As described above, in the circuit layer 17L in which the sub-pixel circuit 70 is disposed, the memory for storing the data for driving the sub-pixel SPix and the source line driving circuit 5 for outputting the data to be written to the memory are provided. The gradation of each sub-pixel SPix is controlled based on the sub-pixel data stored in one selected memory out of the n memories.

  The interface circuit 4 includes a serial-parallel conversion circuit 4a and a timing controller 4b. The timing controller 4b includes a setting register 4c. Command data CMD and image data ID are serially supplied from an external circuit to the serial-parallel conversion circuit 4a. The interface circuit 4 controls the source line driving circuit 5 based on an external signal. The external circuit is exemplified by a host CPU (Central Processing Unit) or an application processor, but the present disclosure is not limited to these.

  The serial-parallel conversion circuit 4a converts the supplied command data CMD into parallel and outputs it to the setting register 4c. In the setting register 4c, values for controlling the source line driving circuit 5, the inversion driving circuit 7, the memory selection circuit 8, the gate line driving circuit 9, and the gate line selection circuit 10 are set based on the command data CMD.

  The serial-parallel conversion circuit 4a converts the supplied image data ID into parallel and outputs it to the timing controller 4b. The timing controller 4b outputs the image data ID to the source line driving circuit 5 based on the value set in the setting register 4c. The timing controller 4b controls the inversion drive circuit 7, the memory selection circuit 8, the gate line drive circuit 9, and the gate line selection circuit 10 based on the value set in the setting register 4c.

  A reference clock signal CLK is supplied from an external circuit to the common electrode drive circuit 6, the inversion drive circuit 7, and the memory selection circuit 8 via an electrostatic protection circuit 40 and a clock buffer 80. The external circuit is exemplified by a clock generator, but the present disclosure is not limited to this.

  In order to display an image on the display device, it is necessary to store subpixel data in the first to third memories of each subpixel SPix. In order to store the sub-pixel data in each memory, the gate line driving circuit 9 outputs a gate signal for selecting one row of the M × N pixels Pix under the control of the timing controller 4b. .

  In the embodiment, n gate lines are arranged per row. The n gate lines are respectively connected from the first memory to the n-th memory of each of the sub-pixels SPix included in one row. In the case where the sub-pixel SPix operates not only with the gate signal but also with an inverted gate signal obtained by inverting the gate signal for inversion driving described later, (2n) gate lines are arranged per row. Is done.

  The n or (2n) gate lines arranged per one row constitute a gate line group. In the embodiment, since the display device 1 includes M rows of pixels Pix, M groups of gate lines are arranged.

  The gate line drive circuit 9 sequentially outputs a gate signal for selecting one of the M rows from the M output terminals under the control of the timing controller 4b.

  The gate line selection circuit 10 selects one of the three gate lines arranged in one row under the control of the timing controller 4b. As a result, the gate signal output from the gate line driving circuit 9 is supplied to a selected one of the three gate lines arranged in one row.

  The source line drive circuit 5 outputs the sub-pixel data to the memory selected by the gate signal under the control of the timing controller 4b. As a result, the sub-pixel data is sequentially stored in the first memory to the third memory of each sub-pixel.

  The display device 1 scans the pixels Pix of the M rows line-sequentially, so that the sub-pixel data of one frame data is stored in the first memory of each sub-pixel SPix. Then, the display device 1 executes the line-sequential scanning n times to store n frame data from the first memory to the n-th memory of each sub-pixel SPix. By performing such scanning from the first column to the M-th column, sub-pixel data can be stored in the first to n-th memories of each sub-pixel SPix by one line sequential scanning.

  In the embodiment, n memory selection lines are arranged for one row. The n memory selection lines are respectively connected from the first memory to the n-th memory of each of the N × n sub-pixels SPix included in one row. When the inversion driving is adopted, (2n) memory selection lines are arranged per one row.

  The n or (2n) memory selection lines arranged for one row constitute a memory selection line group. In the embodiment, since the display device 1 includes M rows of pixels Pix, M groups of memory selection lines are arranged.

  Under the control of the timing controller 4b, the memory selection circuit 8 simultaneously selects one of the first to n-th memories of each sub-pixel SPix in synchronization with the reference clock signal CLK. For example, the first memories of all the sub-pixels SPix included in one sub-pixel array 90 are selected at the same time. Alternatively, the second memories of all the sub-pixels SPix included in one sub-pixel array 90 are simultaneously selected. As these examples show, the display device 1 switches one of the n patterns of images stored in the n memories by switching the selection from the first memory to the n-th memory of each sub-pixel SPix. Images can be displayed. Thereby, the display device 1 can change the image all at once, and can change the image in a short time. Further, the display device 1 can perform animation display (moving image display) by sequentially switching the selection from the first memory to the n-th memory of each sub-pixel SPix. As described above, the memory selection circuit 8 selects one of the memories provided for one sub-pixel SPix to be used for driving the one sub-pixel SPix.

FIG. 10 is a diagram illustrating an arrangement of sub-pixels in a pixel of the display device according to the embodiment. The pixel Pix includes an R (red) sub-pixel SPix _R , a G (green) sub-pixel SPix _G, and a B (blue) sub-pixel SPix _B. The sub-pixels SPix _R , SPix _G and SPix _B are arranged in the X direction.

Subpixel SPix _R includes a memory block 50, the reversing switch 61, the. The memory block 50 includes n memories from the first memory 51 to the n-th memory 5n. The inversion switch 61 and the n memories are arranged, for example, in the Y direction.

  Each of the n memories is a memory cell that stores 1-bit data, but the present disclosure is not limited to this. Each of the n memories may be a memory cell storing data of 2 bits or more.

  The inversion switch 61 functions as a switch for inversion driving, and is connected between the n memories and the reflection electrode 15.

  FIG. 11 is a diagram illustrating a circuit configuration of the display device of the embodiment. In the description with reference to FIGS. 11 to 15, n = 3 is taken as an example. That is, a case where the memory block 50 includes the first memory 51, the second memory 52, and the third memory 53 will be described as an example. FIG. 11 shows 2 × 2 sub-pixels SPix of each sub-pixel SPix. The sub-pixel SPix includes a liquid crystal LQ, a storage capacitor C, and a reflection electrode 15 in addition to the memory block 50 and the inversion switch 61.

  The common electrode drive circuit 6 inverts the common potential VCOM common to the sub-pixels SPix in synchronization with the reference clock signal CLK and outputs the inverted common potential VCOM to the common electrode 23. The common electrode drive circuit 6 may output the reference clock signal CLK to the common electrode 23 as it is as the common potential VCOM, or may output the reference clock signal CLK to the common electrode 23 as the common potential VCOM via a buffer circuit that amplifies the current driving capability. Is also good.

Gate line driving circuit 9 on the basis of the control signal Sig ₄ is supplied from the timing controller 4b, and the gate signal for selecting a row of the M rows are sequentially output from the M output terminals.

The gate line drive circuit 9 may be a scanner circuit that sequentially outputs gate signals from M output terminals based on the control signal Sig ₄ (scan start signal and clock pulse signal). Alternatively, the gate line drive circuit 9 decodes the control signal Sig ₄ encoded, it may be a decoder circuit for outputting a gate signal to the output terminal specified by the control signal Sig _4.

The gate line selection circuit 10, corresponding to the pixel Pix of M rows, including M switches _{SW 4_1, SW 4_2,} a .... M switches _{SW 4_1, SW 4_2,} ··· it is commonly controlled by the control signal Sig ₅ supplied from the timing controller 4b.

On the first panel 2, M groups of gate line groups GL ₁ , GL ₂ ,... Are arranged corresponding to the pixels Pix of M rows. Each of the M groups of gate line groups GL ₁ , GL ₂ ,... Includes a _first gate line GCL ₁ connected to the first memory 51 in the row and a second gate line connected to the second memory 52. GCL ₂ and a third gate line GCL ₃ connected to the third memory 53. Each of the M groups of gate line groups GL ₁ , GL ₂ ,... Runs along the X direction in the sub-pixel array 90.

M switches _{SW 4_1, SW 4_2,} each ... switches the gate lines and the connection target in accordance with the control signal Sig _5. For example, the control signal Sig ₅ in the case of a value for selecting the first gate line GCL ₁ is connected to the output terminal of the gate line driving circuit 9, a first gate line GCL _1, a. In this case, the gate signal is supplied to the first memory 51 of each sub-pixel SPix. Thus, in accordance with the control signal Sig _5, M number of switches _{SW 4_1, SW 4_2,} each ... is, the first gate line GCL _1, the second gate line GCL ₂ or the third gate line GCL ₃ One of them is connected to the output terminal of the gate line driving circuit 9. The gate signal is supplied to a memory connected to the output terminal of the gate line driving circuit 9.

On the first panel 2, N × 3 source lines SGL ₁ , SGL ₂ ,... Are arranged corresponding to the N × 3 columns of sub-pixels SPix. Each of the source lines SGL ₁ , SGL ₂ ,... Extends along the Y direction in the sub-pixel array 90. The source line driving circuit 5 outputs sub-pixel data to the three memories of each sub-pixel SPix selected by the gate signal via source lines SGL ₁ , SGL ₂ ,.

  The sub-pixel SPix in the row to which the gate signal has been supplied reads the sub-pixel data supplied to the source line SGL from the first memory 51 to the third memory 53 in accordance with the gate line GCL to which the gate signal has been supplied. It is stored in one of the memories.

Memory selection circuit 8 includes a switch SW _2, a latch 71, a switch SW _3, a. Switch SW ₂ is controlled by the control signal Sig ₂ supplied from the timing controller 4b.

A case where an image is displayed, that is, a case where image data is read from any one of the M × N × 3 first memories 51, the second memories 52, and the third memories 53 will be described. In this case, the timing controller 4b outputs a control signal Sig ₂ for the first value to the switch SW _2. Switch SW ₂ is based on the control signal Sig ₂ for the first value supplied from the timing controller 4b, turned on. As a result, the reference clock signal CLK is supplied to the latch 71.

In the case where the image is not displayed, that is, the image is displayed from any of the M × N × 3 first memories 51, the M × N × 3 second memories 52, and the M × N × 3 third memories 53. A case where data is not read will be described. In this case, the timing controller 4b outputs a control signal Sig ₂ for the second value to the switch SW _2. Switch SW ₂ is based on the control signal Sig ₂ for the second value supplied from the timing controller 4b, it turned off. As a result, the reference clock signal CLK is not supplied to the latch 71.

Latch 71, the switch SW ₂ is when the reference clock signal CLK is supplied in the on state, the high level of the reference clock signal CLK 1 cycle retention of the reference clock signal CLK. Latch 71, when the switch SW ₂ is the reference clock signal CLK is not supplied in the off state maintains the high level.

On the first panel 2, M groups of memory selection line groups SL ₁ , SL ₂ ,... Are arranged corresponding to M rows of pixels Pix. Each of the M groups of memory selection line groups SL ₁ , SL ₂ ,... Is connected to a first memory selection line SEL ₁ connected to the first memory 51 of the row and a second memory selection line SEL ₁ connected to the second memory 52. It includes a memory selection line SEL _2, and the third memory selection line SEL ₃ which is connected to the third memory 53, a. Each of the M memory selection line groups SL ₁ , SL ₂ ,... Runs along the X direction in the sub-pixel array 90.

Switch SW ₃ is controlled by the control signal Sig ₃ supplied from the timing controller 4b. When the control signal Sig ₃ is a value for selecting the first memory selection line SEL ₁ , for example, the switch SW ₃ outputs the output terminal of the latch 71 and the M group of memory selection line groups SL ₁ , SL ₂ ,. a first memory select line SEL ₁ each ..., connecting. As described above, the output terminal of the latch 71 is connected to the first memory selection line SEL ₁ , the second memory selection line SEL _2, or the third memory selection line SEL ₃ according to the control signal Sig ₃ .

  Each of the sub-pixels SPix is provided with a liquid crystal based on sub-pixel data stored in one of the first to third memories 51 to 53 according to the memory selection line SEL to which the memory selection signal is supplied. Modulate layers. Thus, the gradation control of the sub-pixel SPix is performed. As a result, an image (frame) is displayed on the display surface.

On the first panel 2, M display signal lines FRP ₁ , FRP ₂ ,... Are arranged corresponding to the pixels Pix of M rows. Each of the M display signal lines FRP ₁ , FRP ₂ ,... Extends in the sub-pixel array 90 in the X direction. When the inversion drive is adopted, the display signal line FRP and the second display signal line xFRP are provided for one row. For example, by providing an inverter circuit whose input terminal is electrically connected to the display signal line FRP and whose output terminal is electrically connected to the second display signal line xFRP, an inverted display signal is provided to the second display signal line xFRP. It is possible to supply. A signal in phase with the common potential VCOM is supplied to the display signal line FRP. The potential (xVCOM) having a phase difference of π from the common potential VCOM is supplied to the second display signal line xFRP.

Inversion drive circuit 7 includes a switch SW _1. Switch SW ₁ is controlled by a control signal Sig ₁ supplied from the timing controller 4b. Switch SW _1, when the control signal Sig ₁ is the first value, the reference clock signal CLK the _FRP respective display signal lines 1, _FRP 2, supplies the .... Switch SW _1, the control signal Sig ₁ is in the case of the second value, the reference potential (ground potential) the display signal lines _FRP 1 to GND, _FRP 2, supplies the ....

FIG. 12 is a diagram illustrating a circuit configuration of a sub-pixel of the display device of the embodiment. FIG. 12 shows one sub-pixel SPix. The sub-pixel SPix includes a memory block 50. Memory block 50 includes a first memory 51, a second memory 52, and third memory 53, and the switch gsw ₁ to gsw _3, and from the switch Msw ₁ to Msw _3, a.

The control input of the switch gsw ₁ is connected to the first gate line GCL _1. The switch Gsw ₁ is turned on when a high-level gate signal is supplied to the first gate line GCL ₁ , and connects the source line SGL ₁ and the input terminal of the first memory 51. Thus, the first memory 51, the sub-pixel data supplied to the source line SGL ₁ is stored. Having described the relationship between the switch gsw ₁ first gate line GCL ₁ and the first memory 51, the switch gsw ₂ and the second gate line GCL ₂ relationship and switch gsw ₃ of the second memory 52 3 the same applies to the relationship between the gate line GCL ₃ and the third memory 53.

When the switch gsw ₁ until gsw ₃ is operated in a gate signal of a high level, as shown in FIG. 12, the gate line group GL ₁ includes a first gate line GCL ₁ to the third gate line GCL ₂ . An N-channel transistor is exemplified as a switch that operates with a high-level gate signal, but the present disclosure is not limited to this.

The control input of the switch Msw ₁ is connected to the first memory select line SEL _1. The switch Msw ₁ is turned on when a high-level memory selection signal is supplied to the first memory selection line SEL ₁ , and connects between the output terminal of the first memory 51 and the input terminal of the inversion switch 61. . As a result, the sub-pixel data stored in the first memory 51 is supplied to the inversion switch 61. Above, a switch Msw ₁ first memory select line SEL ₁ and has been described relationship between the first memory 51, the relationship and the switch Msw ₃ the switch Msw ₂ and the second memory selection line SEL ₂ and the second memory 52 a third memory selection line SEL ₃ the same applies to the relationship between the third memory 53.

  Next, inversion driving of the sub-pixel SPix will be described. Driving methods such as common inversion, column inversion, line inversion, dot inversion, and frame inversion are known as driving methods for suppressing screen burn-in of a liquid crystal display device.

  The display device 1 can employ any of the above-described driving methods. In the embodiment, the display device 1 employs a common inversion driving method. Since the display device 1 employs the common inversion driving method, the common electrode driving circuit 6 inverts the potential of the common electrode (common potential) in synchronization with the reference clock signal CLK. The inversion driving circuit 7 inverts the potential of the reflection electrode in synchronization with the reference clock signal CLK under the control of the timing controller 4b. Thereby, the display device 1 can realize the common inversion driving method. In the embodiment, the display device 1 is a so-called normally black liquid crystal display device that displays black when no voltage is applied to the liquid crystal and displays white when a voltage is applied to the liquid crystal. In a normally black liquid crystal display device, black is displayed when the potential of the reflective electrode and the common potential are in phase, and white is displayed when the potential of the reflective electrode and the common potential are out of phase.

  The inversion switch 61 is a sub-pixel output from one of the n memories based on a display signal supplied from the inversion drive circuit 7 and inverted in synchronization with the reference clock signal CLK. The data is inverted at regular intervals and output to the reflective electrode 15. The cycle in which the display signal is inverted is, for example, the same as the cycle in which the potential (common potential) of the common electrode 23 is inverted. A signal having a plurality of types of periods may be generated from the reference clock signal CLK using a frequency dividing circuit or the like, and the period in which the display signal is inverted and the period in which the common potential is inverted may be set to be different periods.

  FIG. 13 is a diagram illustrating a circuit configuration of a memory of a sub-pixel of the display device of the embodiment. FIG. 13 is a diagram showing a circuit configuration of the first memory 51. Since the circuit configurations of the second memory 52 and the third memory 53 are the same as the circuit configuration of the first memory 51, illustration and description are omitted.

  The first memory 51 has an SRAM (Static Random Access Memory) cell structure including an inverter circuit 81 and an inverter circuit 82 connected in parallel to the inverter circuit 81 in the reverse direction. The input terminal of the inverter circuit 81 and the output terminal of the inverter circuit 82 form a node N1, and the output terminal of the inverter circuit 81 and the input terminal of the inverter circuit 82 form a node N2. The inverter circuits 81 and 82 operate using electric power supplied from the power supply line VDD on the high potential side and the power supply line VSS on the low potential side.

Further, the memory block 50, the source line SGL _1, a gate line GCL _1, the selection signal line SEL _1, in addition to the power supply line VDD on the high potential side, and the gate line XGCL _1, the selection signal lines XSEL ₁ , Are connected to the power supply line VSS on the low potential side.

Node N1 is connected to the output terminal of the switch gsw _1. FIG. 13 shows an example in which a switch gsw _1, transfer gate is used. One control input terminal of the switch gsw ₁ is connected to the gate line GCL _1. The other control input of the switch gsw ₁ is connected to the gate line xGCL _1. The gate line XGCL ₁ is a gate signal supplied to the gate line GCL ₁ inverted, the inverted gate signal is supplied.

The switch gsw ₁ until gsw _3, in addition to the gate signal, when operating in the inverted gate signal obtained by inverting the gate signal for the inversion driving, gate line group GL ₁ further inverting gate signal supply further comprising a fourth gate line XGCL ₁ is up to the sixth gate line xGCL _3. A switch operated by the gate signal and the inverted gate signal is exemplified by a transfer gate, but the present disclosure is not limited to this.

Input terminal connected to the first gate line GCL _1, the output terminal by providing the inverter circuit connected to the fourth gate line XGCL _1, can supply the inverted gate signal to the fourth gate line XGCL _a is there. The same applies to the second gate line GCL ₂ and the fifth gate line XGCL ₂ and the third gate line GCL ₃ sixth gate line XGCL _3.

Input terminal of the switch gsw ₁ is connected to a source line SGL _1. Output terminals of the switch gsw ₁ is connected to the node N1. The switch Gsw ₁ is connected when the gate signal supplied to the gate line GCL ₁ is at a high level and the inverted gate signal supplied to the gate line xGCL ₁ is at a low level, and the switch Gsw ₁ is connected to the source line SGL ₁ and the node N 1. Connect between. Thus, the sub-pixel data supplied to the source line SGL ₁ is stored in the first memory 51.

Node N2 is connected to the input terminal of the switch Msw _1. FIG. 13 shows an example in which a switch Msw _1, transfer gate is used. One control input terminal of the switch Msw ₁ is connected to the selection signal line SEL ₁ . The other control input of the switch Msw ₁ is connected to a selection signal line XSEL _1. The selection signal lines XSEL _1, it is inverted potential of the signal supplied to the selection signal line SEL ₁ potential is supplied. For example, the input terminal is connected to the first memory select line SEL _1, the output terminal by providing the inverter circuit connected to the fourth memory selection lines XSEL _1, the inverted memory select signal to the fourth memory selection lines XSEL ₁ It is possible to supply. The same applies to the second memory selection line SEL ₂ and the fifth memory selection lines XSEL ₅ and the third memory selection line SEL ₃ sixth memory selection lines XSEL _6.

Input terminal of the switch Msw ₁ is connected to the node N2. Output terminals of the switch Msw ₁ is connected to the node N3. The node N3 is an output node of the first memory 51, and is connected to the inversion switch 61. The switch Msw ₁ is connected when the potential of the signal supplied to the selection signal line SEL ₁ is at a high level and the potential of the signal supplied to the selection signal line xSEL ₁ is at a low level. Thus, node N2 via the switch Msw ₁ and node N3, is connected to an input terminal of the reversing switch 61. As a result, the sub-pixel data stored in the first memory 51 is supplied to the inversion switch 61. When both the switch Gsw ₁ and the switch Msw ₁ are not connected, the sub-pixel data circulates in a loop including the inverter circuits 81 and 82. Therefore, the first memory 51 continues to hold the sub-pixel data.

  In the embodiment, the case where the first memory 51 is an SRAM has been described as an example, but the present disclosure is not limited to this. The first memory 51 may be, for example, a DRAM (Dynamic Random Access Memory).

  FIG. 14 is a diagram illustrating a circuit configuration of an inversion switch of a sub-pixel of the display device of the embodiment. Inverting switch 61 includes an inverter circuit 91, N-channel transistors 92 and 95, and P-channel transistors 93 and 94.

  The input terminal of the inverter circuit 91, the gate terminal of the P-channel transistor 94, and the gate terminal of the N-channel transistor 95 are connected to the node N4. The node N4 is an input node of the inversion switch 61, and is connected to the node N3. The sub-pixel data is supplied to the node N4 from the node N3. The inverter circuit 91 operates using power supplied from the high-potential-side power supply line VDD and the low-potential-side power supply line VSS.

N-channel transistor 92 is connected to one of the source and drain to the signal line XFRP _1. P-channel transistor 93 is connected to one of the source and drain to the signal line FRP _1. P-channel transistor 94 is connected to one of the source and drain to the signal line XFRP _1. N-channel transistor 95 is connected to one of the source and drain to the signal line FRP _1. The other of the N-channel transistor 92, the P-channel transistor 93, the P-channel transistor 94, and the N-channel transistor 95 is connected to the node N5.

  The node N5 is an output node of the inversion switch 61, and is connected to the reflection electrode 15. When the sub-pixel data supplied from the node N3 is at a high level, the output signal of the inverter circuit 91 goes to a low level. When the output signal of the inverter circuit 91 is at a low level, the N-channel transistor 92 is disconnected and the P-channel transistor 93 is connected.

When the sub-pixel data supplied from the node N3 is at a high level, the P-channel transistor 94 is in a non-connected state, and the N-channel transistor 95 is in a connected state. Therefore, when the sub-pixel data supplied from the node N3 is at a high level, a display signal supplied to the signal line FRP _1, via the P-channel transistor 93 and N-channel transistor 95, supplied to the reflective electrode 15 Is done.

Common potential is supplied to the display signal and the common electrode 23 are supplied to the signal line FRP ₁ VCOM in synchronization with inverted example the reference clock signal CLK. When the display signal and the common potential VCOM are in phase, no voltage is applied to the liquid crystal LQ, so that the direction of the molecules does not change. As a result, the sub-pixel displays black (a state in which reflected light is not transmitted; a state in which reflected light does not pass through the color filter and no color is displayed).

  When the sub-pixel data supplied from the node N3 is at a low level, the output signal of the inverter circuit 91 goes to a high level. When the output signal of the inverter circuit 91 is at a high level, the N-channel transistor 92 is connected and the P-channel transistor 93 is not connected.

When the sub-pixel data supplied from the node N3 is at a low level, the P-channel transistor 94 is connected and the N-channel transistor 95 is not connected. Therefore, when the sub-pixel data supplied from the node N3 is at a low level, the inverted display signal supplied to the signal line XFRP _1, via the N-channel transistor 92 and P-channel transistor 94, the reflective electrode 15 Supplied.

Highlight signal supplied to the signal line XFRP ₁ in synchronization with inverted reference clock signal CLK. When the display signal and the common potential VCOM are out of phase, a voltage is applied to the liquid crystal LQ, so that the direction of the molecule changes. As a result, the sub-pixel is in a white display (a state in which reflected light is transmitted; a state in which the reflected light is transmitted through the color filter and a color is displayed).

The reference clock signal CLK is input to the inversion driving circuit 7. Inversion driving circuit 7, as shown in FIG. 11, a switch SW _1. Switch SW ₁ is controlled by a control signal Sig ₁ supplied from the timing controller 4b. The inversion drive circuit 7 includes a configuration such as an amplifier circuit for amplifying the reference clock signal CLK. The inversion drive circuit 7 supplies a signal obtained by amplifying the reference clock signal CLK to the display signal line FRP.

  FIG. 15 is a timing chart showing the operation timing of the display device of the embodiment. 15, the common electrode drive circuit 6 supplies the common electrode 23 with a common potential that is inverted in synchronization with the reference clock signal CLK.

From the timing t ₀ to time t ₃ is a period for writing the sub-pixel data to the first memory 51 included in each of the one row of N × 3 pieces of sub-pixels SPix to the third memory 53.

At timing _{t 0,} the timing controller 4b is a control signal Sig ₅ of the values to select the first gate line GCL _1, and outputs to the switch SW ₄ of the gate line selection circuit 10. Switch SW ₄ is connected to the output terminal of the gate line driving circuit 9, a first gate line GCL _1, a. Gate line driving circuit 9 outputs a gate signal to the first gate line GCL ₁ of each row. When the gate signal of the high level is supplied to the first gate line GCL _1, the first memory 51 of each of the sub-pixels SPix belonging to the row is selected as the write destination of the sub-pixel data.

Further, at timing t _0, the source line driving circuit 5, the sub-pixel data for displaying an image (frame) of "A" into the source line SGL. Thus, the sub-pixel data for displaying the image “A” is written in the first memory 51 of each of the sub-pixels SPix belonging to each row. Further, over the timing t ₀ of the next timing (timing t _1), such operation is performed by the line sequential from the first row to the M line. As a result, a signal for forming the image “A” is written and stored in the first memory of all the sub-pixels SPix.

At timings t ₁ and t ₂ , the same processing as at timing t ₀ is performed. However, if the timing _{t 1,} a first gate line GCL ₁ at the timing _{t 0} of the above, the first memory 51 and "A" the second gate line GCL _2, replaced in the second memory 52 and "B". Also, if the timing _{t 2,} the first gate line GCL ₁ at the timing _{t 0} of the above, the first memory 51 and "A" the third gate line GCL _3, replaced in the third memory 53, and "C".

From time t ₄ to time t _10, "A", "B" and sequentially switch and animation display for displaying the three images (three frames) "C" (moving image display) period.

At timing _{t 4,} the timing controller 4b is a control signal Sig ₂ for the first value, and outputs to the switch SW ₂ in the memory selection circuit 8. Switch SW ₂ is based on the control signal Sig ₂ for the first value supplied from the timing controller 4b, turned on. As a result, the reference clock signal CLK is supplied to the latch 71.

Further, at the timing _{t 4,} the timing controller 4b is a control signal Sig ₃ of values for selecting the first memory select line SEL _1, and outputs to the switch SW ₃ in the memory selection circuit 8. Switch SW ₃ is connected to the output terminal of the latch 71, the memory select line group in M group _SL 1, _SL 2, the first memory select line SEL ₁ each ..., a. Thus, the memory selection signal, a memory select line group in M group _SL 1, _SL 2, is supplied to the first memory select line SEL ₁ each ....

Each first memory 51 connected to each first memory selection line SEL ₁ outputs sub-pixel data for displaying an image “A” to the inversion switch 61. Thus, at time t _4, the display device 1 displays the image "A".

At timings t ₅ and t ₆ , the same processing as at timing t ₄ is performed. However, if the timing _{t 5,} the first memory select line SEL ₁ at the timing _{t 4} of the above, the first memory 51 and "A" the second memory selection line SEL _2, replaced in the second memory 52 and "B". Also, if the timing _{t 2,} the first memory select line SEL ₁ at the timing _{t 0} of the above, the first memory 51 and "A" the third memory selection line SEL _3, replaced in the third memory 53, and "C". The operation of each unit from the timing t ₇ to the time t ₉ is the same as the operation of each section from the timing t ₄ to time t _6.

As described above, the display device 1 in the period from the timing t ₄ to the time t _10, "A", "B" and sequentially switch and animation display for displaying the three images (three frames) "C" (Moving image display) can be performed.

From the timing t ₁₀ to the timing t ₁₂ is a still-image display period for displaying an image of "A".

At timing _{t 10,} the timing controller 4b is a control signal Sig ₂ for the second value, and outputs to the switch SW ₂ in the memory selection circuit 8. Switch SW ₂ is based on the control signal Sig ₂ for the second value supplied from the timing controller 4b, it turned off. As a result, the reference clock signal CLK is not supplied to the latch 71. The latch 71 holds a high level.

Further, at a timing _{t 10,} the timing controller 4b is a control signal Sig ₃ of values for selecting the first memory select line SEL _1, and outputs to the switch SW ₃ in the memory selection circuit 8. Switch SW ₃ is connected to the output terminal of the latch 71, the memory select line group in M group _SL 1, _SL 2, the first memory select line SEL ₁ each ..., a. The same driving as the above, in the timing t ₁₀ to the timing t _12, the display device 1 is still image display the image "A".

Incidentally, at the timing t ₁₁ in the still-image display period displaying still picture images "A", the second memory 52 included in each sub-pixel SPix, for displaying an image (frame) as "X" Can be written.

At timing _{t 11,} the timing controller 4b is a control signal Sig ₅ of the values to select the second gate line GCL _2, and outputs to the switch SW ₄ of the gate line selection circuit 10. Switch SW ₄ is connected to the output terminal of the gate line driving circuit 9, and the second gate line GCL _2, a. Gate line driving circuit 9, a gate signal, and outputs to the second gate line GCL ₂ of each row. When the gate signal of the second gate line GCL ₂ to a high level is supplied, the second memory 52 of each of the sub-pixels SPix belonging to the row is selected as the write destination of the sub-pixel data.

Further, at a timing t _11, the source line driving circuit 5, the sub-pixel data for displaying an image of "X" into the source line SGL. Thus, the sub-pixel data for displaying the image “X” is written in the second memory 52 of each of the sub-pixels SPix belonging to each row.

In FIG. 15, at the timing t ₁₁ in the still-image display period displaying still picture images "A", the second memory 52 included in each sub-pixel SPix, displays an image of "X" Of writing sub-pixel data for this purpose has been described. However, for example, the animation display (moving image display) within the period, at the timing t ₆ that animate an image of "C" and "A" (moving image display) to the timing t _8, the sub-pixels SPix It is also possible to write sub-pixel data for displaying an image “X” in the included second memory 52.

Timing t ₁₂ after the "X", "C" and animated sequentially switching and displaying the three images of "A" (three frames) (moving image display) period. Timing _{t 12} later, except that the "B" is replaced with "X", it is similar to the timing _{t 5, t 6, t 4} .

  Next, the number of memories included in one sub-pixel SPix will be described. In the embodiment, a case where, for example, n = 20, that is, the number of memories included in one sub-pixel SPix is 20 will be described. In this case, the number of memories to be used for displaying moving images and the like can be arbitrarily determined within a range of 20 or less. Also, in applications where the number of memories to be used is less than 20, there is a margin that some memories can be intentionally made unused.

  As an example, it is assumed that n = 20 and the number of memories desired to be used is 10. In this case, even if a part (less than 10) of the 20 memories included in one sub-pixel SPix causes some unsuitable use, the number of memories to be sufficiently used in the memory excluding the partial memory Can be secured. That is, redundancy can be provided by increasing the number of memories included in one sub-pixel SPix.

Note that use any memory of the plurality of memory included in one sub-pixel SPix, either does not use any memory, for example, by the control signal Sig ₅ may be controlled in groups of sub-pixel array 90 and it may be controllable subpixels SPix row so as to provide a separate control signal Sig ₅ for each switch SW ₄ for each sub-pixel SPix row. Further, by installing a function of independently controlling the connection of the source line driving circuit 5 and the gate line selection circuit 10 for each sub-pixel SPix, the memory to be used may be settable for each sub-pixel SPix. In these cases, the setting of the memory to be used is, for example, based on the inspection result information of the display device 1, a panel for outputting the command data CMD including information on various settings including the control signal Sig ₅ to the display device 1. It can be realized by a method such as feeding back the inspection result information to the driving program.

  As described above, according to the embodiment, the sub-pixel array 90 is provided in a plurality of groups, divided and arranged in groups, and the source line driving circuit 5 is arranged inside the circuit layer 17L of the first panel 2 for each group. The length of the source line SGL between the source line driving circuit 5 and the sub-pixel SPix is made shorter than when the signal lines are extended from the one source line driving circuit 5 to the sub-pixels SPix of all groups. be able to. That is, according to the embodiment, the load at the time of transmitting the sub-pixel data via the source line SGL can be further reduced. This makes it possible to further reduce the requirement regarding the level of the output voltage of the signal required for the source line driving circuit 5 based on the electric resistance of the source line SGL. Therefore, the sub-pixel data can be more stably written into the memory block 50. The fact that the output voltage of a signal may be relatively low also means that the margin of stable operation with the same output voltage is improved. For this reason, even if a slight leak occurs in the source line SGL, the sub-pixel data can be safely written. Therefore, since the accuracy requirement of the source line SGL in the first panel 2 can be further relaxed, the yield of the display device 1 can be further improved.

  Also, it is generally known that the thinner the wiring, the higher the electrical resistance of the wiring. On the other hand, the fact that the length of the source line SGL can be relatively shortened as in the embodiment means that sub-pixel data can be written even if the resistance of the source line SGL per unit distance is slightly increased. That's what it means. Therefore, the source line SGL can be made thinner than when a signal line is extended from one source line driving circuit 5 to the sub-pixels SPix of all groups. Therefore, it is possible to ensure a larger interval between the source lines SGL. This makes it easier to suppress the occurrence of a short circuit due to foreign matter or the like entering between the source lines SGL. That is, since the accuracy requirement of the source line SGL in the first panel 2 can be further relaxed, the yield of the display device 1 can be further improved. In addition, since the requirement for accuracy can be further relaxed, the design of the display device 1 becomes easier.

  Further, the fact that the load when transmitting the sub-pixel data via the source line SGL can be further reduced means that the length of the source line SGL between the source line driving circuit 5 and the sub-pixel SPix due to the enlargement of the display device 1 is increased. The greater the resistance to transformation. Therefore, the size of the display device 1 can be easily increased.

  As described above, the merits of reducing the load by providing a plurality of groups of sub-pixel arrays 90 and dividing them in units of groups and arranging the source line driving circuit 5 inside the circuit layer 17L of the first panel 2 for each group have been described. However, this also applies to the case where the gate line selection circuit 10 is arranged inside the circuit layer 17L of the first panel 2 for each group. That is, according to the embodiment, the gate between the gate line selection circuit 10 and the sub-pixel SPix is different from the case where the signal line is extended from one gate line selection circuit 10 to the sub-pixels SPix of all groups. The length of the line GCL can be further reduced. Therefore, the same advantages as those of the source line driving circuit 5 and the source line SGL can be obtained for the gate line selection circuit 10 and the gate line GCL.

  The circuit layer 17L is covered with the electrode layer 15L when viewed from the display surface 1a side. Therefore, the display surface 1a can be occupied as an image display region by the reflective electrode 15 without exposing a region for arranging circuits on the display surface 1a. For this reason, when a plurality of display devices 1 are arranged, it is possible to suppress the occurrence of “a gap between images” in which a frame region for a circuit is interposed between the display devices 1. Therefore, it is easier to realize a larger image display area by combining a plurality of display devices 1.

  Further, since the interface circuit 4 shared by the two groups is located between the source line drive circuits 5 of the two groups, the interface circuit 4 between each of the source line drive circuits 5 of the two groups and the interface circuit 4 It becomes easier to approximate the difference in signal transmission path length. For this reason, the synchronization control of the source line drive circuits 5 of the two groups becomes easier.

(Modification)
Next, modified examples of the embodiment will be sequentially described with reference to FIGS. In the description of the modification, components having the same functions as those of the embodiment are denoted by the same reference numerals, and description thereof will be omitted.

(Modification 1)
FIG. 16 is a schematic diagram illustrating a circuit configuration example included in the display device 100 according to the first modification. FIG. 16 illustrates a display device 1A in which four subpixel arrays 90 are provided in the X direction. Also in the modified example, as in the embodiment, the sub-pixel array 90 forms a group with the individual source line driving circuit 5, the memory selecting circuit 8, the gate line driving circuit 9, and the gate line selecting circuit 10. For example, the source line driving circuit 5g, the memory selecting circuit 8g, the gate line driving circuit 9g, the gate line selecting circuit 10g, and the sub-pixel array 90g form one group. The same applies to the source line driving circuit 5, the memory selection circuit 8, the gate line driving circuit 9, the gate line selection circuit 10, and the sub-pixel array 90 suffixed with other lowercase alphabets (h, i, j). It can be read by replacing the end of the code.

  FIG. 16 illustrates a display device 1A provided with three interface circuits 4 and an inversion drive circuit 7 in the X direction. In FIG. 16, capital letters (D, E, F) are added to the end of the reference numerals for the purpose of distinguishing the positions of the three interface circuits 4 and the inversion drive circuit 7. The group of the two sub-pixel arrays 90h and 90i shares the interface circuit 4E and the inversion drive circuit 7E. The interface circuit 4D and the inversion drive circuit 7D are in the same group as the sub-pixel array 90g. The interface circuit 4F and the inversion drive circuit 7F are in the same group as the sub-pixel array 90j. These configurations in the circuit layer 17L include a sub-pixel array 90g, a source line driving circuit 5g, an interface circuit 4D, a sub-pixel array 90h, a source line driving circuit 5h, an interface, along the Y direction from the opposite side of the flexible printed circuit board FPCD. The circuit 4E, the source line driving circuit 5i, the sub-pixel array 90i, the interface circuit 4F, the source line driving circuit 5j, and the sub-pixel array 90j are arranged in this order.

  The positions of the electrostatic protection circuits 20D and 40D in the Y direction are between the sub-pixel array 90j and the flexible printed circuit board FPCD. The group of the four sub-pixel arrays 90g, 90h, 90i, and 90j shares the electrostatic protection circuit 20D, the electrostatic protection circuit 40D, and the clock buffer 80D.

  The positional relationship among the sub-pixel arrays 90 of each group, the memory selection circuit 8, the gate line drive circuit 9, and the gate line selection circuit 10 in the first modification is the same as that of the embodiment. The inversion driving circuit 7D is arranged between a region where the memory selection circuit 8g, the gate line driving circuit 9g and the gate line selection circuit 10g are arranged, and a region where the memory selection circuit 8h, the gate line driving circuit 9h and the gate line selection circuit 10h are arranged. To position. The inversion drive circuit 7E and the clock buffer 80D have a region where the memory selection circuit 8h, the gate line drive circuit 9h and the gate line selection circuit 10h are arranged, and a region where the memory selection circuit 8i, the gate line drive circuit 9i and the gate line selection circuit 10i are arranged. Located between. The inversion driving circuit 7F is arranged between a region where the memory selection circuit 8i, the gate line driving circuit 9i and the gate line selection circuit 10i are arranged, and a region where the memory selection circuit 8j, the gate line driving circuit 9j and the gate line selection circuit 10j are arranged. To position.

  According to the first modification, even when three or more sub-pixel arrays 90 are provided in the Y direction, the operation of the circuit related to the gradation control of each sub-pixel array 90 can be more reliably synchronized. Even when three or more sub-pixel arrays 90 are provided in the Y direction, as in the embodiment, the source line SGL between the source line driving circuit 5 and the sub-pixel SPix and the gate line selection circuit 10 and the sub-pixel SPix Of the gate line GCL can be shortened.

  In FIG. 16, two of the four groups provided in the Y direction share one interface circuit 4 and the inversion drive circuit 7, and the other two groups have the individual interface circuit 4 and the inversion drive circuit 7. Although an example having the circuit 7 is shown, this is an example of a specific configuration of the circuit and is not limited to this. For example, two sets sharing one interface circuit 4 and one inversion drive circuit 7 may be provided in the Y direction.

(Modification 2)
FIG. 17 is a schematic diagram illustrating an example of a circuit configuration of Modification Example 2. The signal line selection circuit 130 is a circuit that outputs a signal to any one of a plurality of selection lines (for example, selection lines SG1, SG2, and SG3). The switch SSW1 connects the trunk source line MSGL and the branch source line SSGL1 according to a signal output to the selection line SG1. The switch SSW2 connects the trunk source line MSGL and the branch source line SSGL2 according to a signal output to the selection line SG2. The switch SSW3 connects the trunk source line MSGL and the branch source line SSGL3 according to a signal output to the selection line SG3. That is, the signal line selection circuit 130 and the switches SSW1, SSW2, and SSW3 are circuits that connect any one of the plurality of sub signal lines (the branch source line SSGL1, the branch source line SSGL2, or the branch source line SSGL3) to the trunk source line MSGL. Function. The plurality of sub signal lines (branch source line SSGL1, branch source line SSGL2, and branch source line SSGL3) are respectively connected to the sub-pixel circuits 70 included in the sub-pixels SPix in different columns (positions in the X direction).

  The signal line selection circuit 130 is provided as a configuration for relaying subpixel data between the source line driving circuit 5 and the subpixel array 90, for example. In this case, the signal line selection circuit 130 outputs a signal to any one of the selection lines SG1, SG2, and SG3, and connects one of the branch source line SSGL1, the branch source line SSGL2, and the branch source line SSGL3 to the trunk source line MSGL. Connect with Source line drive circuit 5 outputs sub-pixel data to main source line MSGL. The sub-pixel data is transmitted to the memory included in the sub-pixel circuit 70 of the sub-pixel SPix connected to one of the branch source line SSGL1, the branch source line SSGL2, or the branch source line SSGL3 connected to the main source line MSGL. As described above, the signal line selection circuit 130 partially transmits the subpixel data among the plurality of branch source lines SSGL that individually transmit the subpixel data to the plurality of memories provided for the plurality of subpixels SPix. Is selected.

  The signal line selection circuit 130 may be provided as a configuration interposed between the source line driving circuit 5 shared by a plurality of groups and the sub-pixel array 90 to relay sub-pixel data. In this case, the subpixel data is transmitted to the memory included in the subpixel circuit 70 of the subpixel SPix in the subpixel array 90 of any group.

  In the description with reference to FIG. 17 and FIG. 17, an example is given in which the number of selection lines and the number of switches and sub-signal lines that operate according to the signals output to the selection lines is three, but this number is two. Or four or more.

  According to the second modification, sub-pixel data can be transmitted from one trunk source line MSGL via a plurality of branch source lines SSGL. Therefore, as compared with the case where the source lines SGL are provided directly for the columns of all the sub-pixels SPix that obtain the sub-pixel data from one source line driving circuit 5, a path passing through the main source line MSGL-the branch source line SSGL. , The number of trunk source lines MSGL can be reduced to a smaller number of lines extending from the source line driving circuit 5. Also, when outputting sub-pixel data to one branch source line SSGL among a plurality of branch source lines SSGL connectable to one trunk source line MSGL, no signal flows to another branch source line SSGL. Therefore, the load of the other branch source line SSGL does not reach the source line driving circuit 5, and the operation of the source line driving circuit 5 can be further stabilized.

  Further, in the display device 1 of the embodiment, the memory selection circuit 8 provided outside the sub-pixel array 90 simultaneously selects one of the first memory 51 to the n-th memory n of each sub-pixel SPix. Therefore, the display device 1 can display one of n kinds of images (n frames). Thereby, the display device 1 can change the image all at once, and can change the image in a short time. The display device 1 can perform animation display (moving image display) by sequentially switching the selection of n memories of each sub-pixel SPix.

  Furthermore, in the display device 1 of the embodiment, when writing the sub-pixel data, the gate line selection circuit 10 selects any one of the first memory 51 to the n-th memory 5n. When reading the sub-pixel data, the memory selection circuit 8 arranged in the frame area GD selects any one of the first memory 51 to the n-th memory 5n. Therefore, each pixel Pix does not need to include a circuit for switching memories. Accordingly, the display device 1 can meet the demand for miniaturization and higher definition of the image display panel in addition to the above-described effects.

  Further, in the display device 1 of the embodiment, during the period when an image is displayed based on the sub-pixel data stored in any one of the first memory 51 to the n-th memory 5n, The sub-pixel data can be written to any one of the other memory units up to the n-th memory 5n. Thus, the display device 1 can also write the sub-pixel data of another image while displaying the image.

(Application example)
FIG. 18 is a diagram illustrating an application example of the embodiment and the like. FIG. 19 is a sectional view taken along line VV of FIG. In FIG. 18, reference numerals 1A, 1B, 1C, 1D, 1E, and 1F are used for the purpose of distinguishing a plurality of display devices 1 at different positions. Display device to which the example is applied). As shown in FIG. 18, a display area capable of displaying a larger image can be formed by tiling in which a plurality of display devices 1 are arranged. Further, as shown in FIG. 19, the flexible printed circuit board FPC is bent almost vertically, and the display devices 1 are laid on the panels in the Y direction, thereby enabling tiling with a smaller gap between the display devices 1 arranged in the Y direction. Become.

  The preferred embodiments and the like of the present invention have been described above, but the present invention is not limited to such embodiments and the like. The contents disclosed in the embodiments and the like are merely examples, and various modifications can be made without departing from the gist of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, replacements, and changes of the components can be performed without departing from the gist of the above-described embodiment and the like.

1,100 display device 1a display surface 2 first panel 3 second panel 4 interface circuit 5 source line drive circuit 6 common electrode drive circuit 7 inversion drive circuit 8 memory selection circuit 9 gate line drive circuit 10 gate line selection circuit 11 first Substrate 15 Reflective electrode 15L Electrode layer 16 Stacked wiring 17L Circuit layer 20, 40 Electrostatic protection circuit 21 Second substrate 23 Common electrode 30 Liquid crystal layer 41 Serial-parallel conversion circuit 42 Timing controller 43 Setting register 50 Memory block 51 First memory 52 Second memory 53 Third memory 5n nth memory 61 Inverting switch 70 Sub-pixel circuit 80 Clock buffer 90 Sub-pixel array FPC Flexible printed circuit board FRP Display signal line GL Gate line group GCL Gate line Pix Pixel SPix Sub-pixel SL Memory selection Line group SEL memory selection line

Claims (8)

An electrode layer on which a plurality of reflective electrodes are arranged,
A circuit layer provided below the electrode layer,
The circuit layer, a plurality of memories provided corresponding to each reflective electrode, a signal output circuit that outputs data written to each memory, and an interface circuit that controls the signal output circuit based on an external signal With
The plurality of reflective electrodes are divided into a plurality of groups, and the signal output circuit is provided for each group, and
The display device, wherein the interface circuit is shared by the adjacent groups. The display device according to claim 1, wherein the interface circuit is located between the signal output circuits of the adjacent groups. A plurality of signal lines for individually transmitting the data to the plurality of memories, and a signal line selection circuit for selecting some of the plurality of signal lines to transmit the data,
The display device according to claim 2, wherein the signal line selection circuit is interposed between the signal output circuit and the memory. A selecting circuit for selecting one of the memories provided for the one reflecting electrode;
4. The display device according to claim 1, wherein the selection circuit is provided for each of the groups and is disposed on the circuit layer. 5. A clock buffer that buffers and outputs an external reference clock signal,
The display device according to claim 4, wherein the selection circuits of the two groups are synchronously controlled based on the reference clock signal output from the clock buffer. The display device according to claim 1, wherein the circuit layer includes the memory, the signal output circuit, and the interface circuit covered by the electrode layer. An electrode layer on which a plurality of the reflective electrodes are arranged,
A plurality of memories provided corresponding to the reflective electrode, and a circuit layer provided with a signal output circuit that outputs data written to each memory,
The plurality of reflective electrodes are included in any of a plurality of groups depending on the arrangement,
The signal output circuit is provided in the group,
The display device, wherein the circuit layer is covered with the electrode layer. An electrode layer on which a plurality of reflective electrodes are arranged,
A circuit layer provided below the electrode layer,
The circuit layer includes a plurality of memories provided corresponding to each reflective electrode, a signal output circuit that outputs data written to each memory, and a memory selection circuit that selects any of the plurality of memories.
The plurality of reflective electrodes are divided into a plurality of groups, and the memory selection circuit is provided for each group, and at least a part of the memory group of the same group and a memory group of a group adjacent to the group are included. Display device placed between.

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