JP2020009498A - Memory controller and memory control method - Google Patents

Abstract

To provide a memory controller and a memory control method with which it is possible to flexibly set a memory area by a simple method.SOLUTION: Provided is a memory controller for controlling a memory in a microcomputer system including a memory in which instructions for executing a program are stored and a central processing unit that executes a program in accordance with instructions specified by a program counter in which addresses corresponding to instructions are stored in order and which sequentially reads out the addresses and specifies corresponding instructions, comprising: a designated address register for holding the addresses stored in the program counter; a post-translation instruction holding part for holding post-translation instructions different from the pre-translation instructions of the memory corresponding to the designated addresses; and an instruction translation part for sending a post-translation instruction to the central processing unit as an instruction for executing the program when the address read out from the program counter matches the designated address held in the designated address register.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a memory control device and a memory control method, and in particular, in a microcomputer system including a CPU (Central Processing Unit) and a memory under the control thereof, controls a storage area and the like of the memory. The present invention relates to a memory control device and a memory control method to be executed.

  Program data to be processed in the microcomputer system is usually stored in a storage device (a memory, for example, a nonvolatile memory such as a flash (FLASH) memory). The execution of the predetermined processing based on the program is performed by sequentially specifying addresses of a memory in which program data is stored by a program counter (PC) provided in the CPU, reading out the program data at the address, and reading the program data. Is executed as an instruction.

  In the execution of processing by the CPU, a change in the contents or order of the processing may be required to correct a defect in the program. One example of a conventional technique for changing the processing is remapping. Remapping means that during execution of a program based on a PC, a program space different from the program space originally executed by the CPU can be seen in a memory area designated by the PC, and instructions in the different program space are executed. This is a technique for changing the content of the processing by causing the processing to be performed.

  As a document that discloses the remapping function as described above, there is an interrupt control device described in Patent Document 1. The interrupt control device disclosed in Patent Literature 1 includes a CPU, a memory, an interrupt controller, and a remap circuit, and the remap circuit is configured to include a remap register area and a selector. The remap register area includes a number of registers corresponding to the number of interrupt requests.Each register is a register mapped to an address on the same memory, and each register has an interrupt request number. A jump instruction to a corresponding interrupt processing routine is stored. The selector selects one of the registers in which the jump instruction to the interrupt processing routine corresponding to the interrupt request is stored from the registers in the remap register area based on the interrupt request number notified from the interrupt controller. The mapping function is realized by mapping to the above interrupt vector address.

  On the other hand, the memory is generally divided into areas having specific attributes such as a program area and a data area. The program area is an area for storing program processing instructions. The data area is an area for storing data necessary for the program processing, and is an area from which data is read or written when the program processing is executed. In some cases, it is desired to designate a specific area of the memory as a rewritable area or a non-rewritable (write-protected) area.

  As a conventional technique related to reading and writing control, predetermined data is arranged in a part of a memory such as a flash memory in advance, and the data is read by a logic circuit mounted on the flash memory, and a code option of the data is set. There is known a block enable that limits a read or write function by controlling a memory from the outside by using the memory.

  Further, in a nonvolatile memory having no write protection function, a semiconductor information processing device disclosed in Patent Document 2 is known as a conventional technique for implementing nonvolatile write protection. In the semiconductor information processing device disclosed in Patent Literature 2, a write protection storage register for storing an address of an area where write protection is to be performed is set in an attribute area of a flash memory, and the system is protected by using the write protection storage register. A range is set.

JP 2012-141667 A JP 2007-207277 A

  However, in the remapping method disclosed in Patent Literature 1, a program is executed in such a manner that data of an area different from a normal memory area is shown to a CPU by designating a PC. However, there is a problem that it is difficult to use many remapping functions at the same time due to the limitation of the memory capacity and the like.

  In the write protection disclosed in Patent Document 2, it is possible to set access restrictions on a memory, but it is only possible to prohibit operations such as writing, reading, or erasing in memory block units. However, there is a problem that the memory cannot be used in accordance with various software applications.

  SUMMARY An advantage of some aspects of the invention is to provide a memory control device and a memory control method capable of setting a memory area in a simple manner and flexibly. .

  Further, the memory control device according to the present invention includes a program area in which an instruction for executing the program is stored, a data area in which data associated with the execution of the program is stored, and rewrite setting data for specifying a memory space dividing method. A memory control device that controls the memory in a microcomputer system including a memory including a setting data area in which a memory is stored, and a central processing unit that sequentially specifies an instruction stored in the memory according to the program and executes the program. And a rewrite setting register for holding the value of the rewrite setting data, reading the setting data area, holding the read rewrite setting data value in the rewrite setting register, and holding the rewrite setting register. Previous based on the value of the rewrite setting data Comprising a setting unit for setting the area division of the memory space, the.

  In addition, the memory control method according to the present invention includes a program area in which an instruction for executing a program is stored, a data area in which data associated with the execution of the program is stored, and rewrite setting data for specifying a memory space dividing method. A memory control method for controlling the memory in a microcomputer system including a memory including a setting data area in which a program is stored, and a central processing unit that sequentially specifies an instruction stored in the memory according to the program and executes the program The setting unit reads the setting data area, holds the value of the read rewriting setting data in the rewriting setting register, and sets the memory space based on the value of the rewriting setting data held in the rewriting setting register. Set the area division.

  According to the present invention, it is possible to provide a memory control device and a memory control method capable of setting a memory area flexibly with a simple method.

FIG. 1 is a functional block diagram illustrating an example of a configuration of a microcomputer system according to an embodiment. FIG. 2 is a functional block diagram illustrating an example of a configuration of a memory control device according to the first embodiment, and a schematic diagram illustrating an example of instruction conversion register set contents. FIG. 3 is a functional block diagram illustrating an example of a configuration of an instruction conversion unit according to the first embodiment. FIG. 4 is a schematic diagram for explaining instruction conversion using the setting circuit according to the first embodiment. FIG. 9 is a functional block diagram illustrating an example of a configuration of a memory control device according to a second embodiment, and a schematic diagram illustrating an example of instruction conversion register set contents. FIG. 13 is a schematic diagram for explaining instruction conversion using a setting register according to the second embodiment. It is a schematic diagram for explaining instruction conversion by a plurality of program counters according to the third embodiment. FIG. 19 is a functional block diagram illustrating an example of a configuration of a memory control device according to a fourth embodiment, and a schematic diagram illustrating an example of the contents of a rewrite setting register set. FIG. 14 is a schematic diagram for explaining an operation of the memory control device according to the fourth embodiment. FIG. 14 is a schematic diagram illustrating an example of area division of a memory according to a fourth embodiment. FIG. 14 is a schematic diagram illustrating an example of area division of a memory according to a fourth embodiment. FIG. 14 is a schematic diagram illustrating an example of area division of a memory according to a fourth embodiment.

  Hereinafter, embodiments for carrying out the present invention will be described in detail with reference to the drawings.

[First Embodiment]
A memory control device according to the present embodiment will be described with reference to FIGS. The memory control device according to the present embodiment specifies the program counter (PC) of the CPU by using a setting circuit provided in advance, so that the specified instruction of the PC is not the instruction stored in the memory but to be executed originally. Has a function (instruction conversion function) of being converted into an instruction set artificially by hardware and executing the converted instruction by the CPU. Hereinafter, an example in which the instruction executed after the conversion is a jump instruction (pseudo jump instruction) will be described.

  FIG. 1 is a functional block diagram showing a microcomputer system 1 according to the embodiment. As shown in FIG. 1, the microcomputer system 1 includes a memory control device 10, a memory 12, and a CPU 14. The memory control device 10 is a memory control device according to the present embodiment. Although the type of the memory 12 is not particularly limited, in the present embodiment, a nonvolatile memory such as a flash memory is assumed. The CPU 14 is a general CPU and includes a program counter 140 therein.

  FIG. 2A shows a functional block diagram of the memory control device 10 according to the present embodiment. As shown in FIG. 2A, the memory control device 10 includes an instruction conversion unit 100, a converted instruction setting circuit 112, and an instruction conversion register set 120.

  FIG. 2B shows the contents of the registers included in the instruction conversion register set 120 according to the present embodiment. As shown in FIG. 2B, the instruction conversion register set 120 includes the following three registers.

  That is, the “PCON” register is a register that stores a specification as to whether or not to use the instruction conversion function of the memory control device 10. In the present embodiment, the “PCON” register is used when the logical value = 1 and the logical value = 0. They do not use it. Of course, this correspondence may be a reverse logical value. The “CSR” register is a register for storing segment data in the memory 12 of a PC to be converted into an instruction (hereinafter, “designated PC”). The “PC designation” register is a register for storing address data of the designated PC.

  The post-conversion command setting circuit 112 is a circuit for setting a post-conversion command, and is a hardware circuit that specifies the command using a 4-digit hexadecimal number.

  FIG. 3A shows an example of the configuration of the instruction conversion section 100 according to the present embodiment. As shown in FIG. 3A, the instruction conversion unit 100 includes an AND circuit 102, an OR circuit 104, and selectors 106, 108, and 110. (1) and (0) given to each selector are codes representing input terminals, and are input terminals selected when the logic value of the select signal is “1” and “0”, respectively. It is shown that. A circuit including the AND circuit 102, the OR circuit 104, and the selectors 106 and 108, which is a part of the instruction conversion unit 100, is referred to as a “selection circuit 114” for convenience, and the output terminal of the AND circuit 102 in the selection circuit 114 is denoted by “ a ”, and the output terminal of the selector 106 is denoted by a symbol“ b ”.

  As shown in FIG. 3A, the outputs “INST1” and “INST2” of the post-conversion instruction setting circuit 112 are connected to the (1) input terminal of the selector 106 and the (1) terminal input of the selector 108, respectively. I have. The output of the post-conversion instruction setting circuit 112 indicating the post-conversion instruction is two because the jump instruction assumed in the present embodiment is composed of two words, each of which has four digits of 16 bits. Expressed in hexadecimal. The converted instruction INST1 indicates an instruction for one upper word, and the converted instruction INST2 indicates an instruction for one lower word. Of course, when the converted instruction is a one-word instruction, the output of the converted instruction setting circuit 112 is one converted instruction INST.

  Next, the operation of the instruction conversion unit 100 will be described. First, the segment data of the designated PC is set in the CSR register, the address data of the designated PC is set in the PC designation register, and the PC to be converted from the instruction to be executed to the pseudo jump instruction is set. Next, the PCON register is set to a logical value “1” to specify that the present instruction conversion function is to be used.

  When the PCON register is valid, the CPU compares the segment data of the PC held by the CPU (CPU_CSR) with the segment data of the CSR register, and compares the PC address data held by the CPU (CPU_PC) with the address data of the PC designation register. A comparison process is performed. If the comparison results do not match, no processing is performed, but if they do match, the data CPU_DIN output to the CPU is output from the data (memory data) stored in the memory by the post-conversion instruction setting circuit 112. The converted instructions INST1 and INST2 are converted into data of the pseudo jump instruction 1 and the pseudo jump instruction 2 in this embodiment.

  An example of a circuit that realizes the above operation will be described based on a block diagram of the instruction conversion unit 100 shown in FIG. In FIG. 3A, the symbol X == Y is a symbol indicating that the logical value is “1” when X and Y match, and that the logical value is “0” when X and Y do not match. is there. That is, when the PCON register and 1 are compared and matched (that is, when the value of the PCON register is “1”), the logical value is set to “1”. When the comparison result between the CSR register and CPU_CSR matches, the logical value is set. It is set to "1", and when the comparison result between the PC designation register and CPU_PC matches, the logical value is set to "1".

  The AND circuit 102 is a three-input AND circuit, and receives the logical value of the PCON register, the comparison result between the CSR register and CPU_CSR, and the comparison result between the PC designation register and CPU_PC. The output of the AND circuit 102 outputs “1” when the logical values of all three inputs are “1”, and outputs the logical value “0” otherwise.

  The selector 110 is switched by the output of the AND circuit 102, and when the output of the AND circuit 102 is “0”, the memory data that is the data stored in the memory 12 is output when the output of the AND circuit 102 is “1”. Is selected, and is output to the bus 16 as CPU_DIN data. The output CPU_DIN data is taken into the CPU 14 and executed.

  The OR circuit 104 is a two-input OR circuit, which receives a comparison result between the PC designation register and the CPU_PC and a comparison result between the PC designation register +1 and the CPU_PC. Is output. The PC designation register +1 means the register next to the PC designation register. That is, in the present embodiment, a two-word instruction is assumed.

  When the comparison result between the PC designation register and the CPU_PC matches, a logical value “1” is input to one input of the OR circuit 104, and the selector 106 outputs (1) the instruction INST1 after the conversion of the input terminal. When the input terminal is selected and the selector 110 selects the (1) input terminal, INST1 is output as CPU_DIN.

  When the comparison result between the PC designation register +1 and the CPU_PC matches, a logical value “1” is input to the other input of the OR circuit 104, and the selector 108 outputs (1) after the conversion of the input terminal. The instruction INST2 is selected. At this time, since the select signal of the selector 106 has the logical value “0”, the selector 106 selects the (0) input terminal connected to the output of the selector 108 and the selector 110 selects the (1) input terminal. If it is, INST2 is output as CPU_DIN.

  The instruction conversion unit 100 operates as described above, and converts an instruction designated by the PC, which should be executed by the CPU, into another instruction. That is, in the present embodiment, the instruction conversion unit 100 converts the instruction into a pseudo jump instruction. Execute

Next, the relationship between the operation of the instruction conversion unit 100 and the storage area of the memory 12 will be described with reference to FIG. 4. First, the operation of the above-described instruction conversion unit 100 will be summarized below.
[1] Store data in the CSR register and the PC designation register. In this example, this data is assumed to be 0: 0330H (segment = 0, address = 0330H, hereinafter referred to as “setting data”).
[2] Set PCON to a logical value “1” to enable this function.
[3] A comparison process between the value of the CSR register and CPU_CSR and a comparison process between the PC designation register and CPU_PC are executed.
[4] If all the comparison results match, the post-conversion instruction setting circuit 112 executes an instruction to jump to a memory address set in hardware.
[5] The process specified at the jump destination is executed, and the process returns to the jump source under predetermined conditions.

  FIG. 4 shows a state where the programs stored in the memory 12 are sequentially executed according to the address specified by the PC of the CPU 14. Then, as a result of the comparison process in [3], if the segment and address corresponding to the PC match the setting data set in [1], the pre-conversion instruction 20 to be executed is the post-conversion instruction. It is converted into the instruction 22 after the conversion. More specifically, the pre-conversion instruction 20 represented by the combination of the instructions MOV R0, # 01H specified by PC = 0: 0330H and the instructions MOV R1, # 01H specified by PC = 0: 0332H is B 2: C000H (segment address = 2: jump instruction to C000H) is converted into the converted instruction 22. As a result, as shown by [4] in FIG. 4, the program jumps to the segment address = 2: C000H of the memory 12, and executes the program stored at the address. Thereafter, the value returns to the value of the next PC under predetermined conditions ([5]).

  As described above, in the memory control device 10 according to the present embodiment, the instruction specified by the program counter 140 of the CPU 14 is converted, and the area in the memory 12 in which the instruction to be executed is stored is changed. Therefore, according to the memory control device 10 of the present embodiment, it is possible to flexibly set the memory area by a simple method.

<Modification of First Embodiment>
With reference to FIG. 3B, a memory control device 10a according to the present embodiment will be described.
The present embodiment is an embodiment in which a plurality of designated PCs are used, and instructions to be converted by each designated PC are different. Therefore, the instruction conversion unit 100 of the memory control device 10a has been changed to a compound instruction conversion unit 100a.

  FIG. 3B is a functional block diagram showing an example of the configuration of the compound instruction converter 100a when the number of designated PCs is three. The composite instruction converter 100a includes three selection circuits 114-1, 114-2, 114-3 (not shown), OR circuits 130, 132, and a selector 110a corresponding to each designated PC. . Output signals a-1, a-2, and a-3 are output from terminals a of the three selection circuits 114-1, 114-2, and 114-3, and output signals b-1, b- are output from terminals b. 2, and b-3 are output. The output signals a-1, a-2, and a-3 are input to the OR circuit 130, and the output signals b-1, b-2, and b-3 are input to the OR circuit 132.

  Each of the selection circuits 114-1, 114-2, and 114-3 has the same configuration as the selection circuit 114 shown in FIG. 3A, that is, the input of each of the selection circuits 114 is a PCON register == 1, the calculation result of the CSR register == CPU_CSR, the calculation result of the PC designation register == CPU_PC, the calculation result of the PC designation register + 1 == CPU_PC, the converted instructions INST1, INST2, the memory data, and 0000H. Each of the selection circuits 114-1, 114-2, 114-3 outputs an output signal a-1, a-2, a-3 and an output signal b-1, b-2, b- corresponding to the respective input. 3 is output.

  If the input of any one of the selection circuits 114 satisfies the above condition and the value of the output signal a becomes a = 1, the output signal of the OR circuit 130 becomes 1 and the selector 110a outputs the signal of the OR circuit 132 The output signal is selected. At this time, the output signal of the OR circuit 132 is the post-conversion instruction INST1 or INST2 in the selection circuit 114 in which a = 1, due to any of the output signals b-1, b-2, and b-3. The instruction INST1 or INST2 after the conversion by the selection circuit 114 is output from the selector 110a, taken into the CPU 14 via the bus 16, and executed. On the other hand, when the input of any of the selection circuits 114 does not satisfy the above condition, the output signal of the OR circuit 130 becomes 0, so that the memory data is selected by the selector 110a and is taken into the CPU 14 via the bus 16. Will be executed.

  In the present embodiment, the case where the number of designated PCs of the compound instruction conversion unit 100a is three has been described as an example. However, the present invention is not limited to this, and any number of designated PCs may be used. Further, the address of the designated PC in the present embodiment may be different or the same, or the post-conversion instruction INST corresponding to the designated PC may be different or the same.

  As described in detail above, in the memory control device according to the present embodiment, the designated PC is set in the setting circuit in advance, and when the CPU attempts to execute the instruction of the PC, it is simulated by hardware. By converting the instructions, that is, in this embodiment, by converting only the instructions corresponding to the jump instructions, the instructions in the intended area are replaced with the instructions in the intended area stored in the memory. That is, the program can be executed. Therefore, unlike the remapping, it is not necessary to show the address of a certain area of the memory to the CPU in the form of a conversion, and when it is desired to set a plurality of designated PCs, a circuit (instruction conversion unit 100) is added. Thus, there is an effect that the setting can be easily performed.

[Second embodiment]
The memory control device 10b according to the present embodiment will be described with reference to FIGS. While the memory control device 10 sets the post-conversion instruction INST in hardware by the post-conversion instruction setting circuit 112, the present embodiment sets the post-conversion instruction INST in hardware using a dedicated register. It is.

  FIG. 5A shows a block diagram of the memory control device 10b according to the present embodiment. As shown in FIG. 5A, the memory control device 10b includes an instruction conversion unit 100 and an instruction conversion register set 120a. That is, the post-conversion command setting circuit 112 of the memory control device 10 shown in FIG. 2A is not provided. The instruction converter 100 shown in FIG. 5A is the same as the instruction converter 100 shown in FIG.

  FIG. 5B shows an example of the contents of the instruction conversion register set 120a according to the present embodiment. 5B, the instruction conversion register set 120a includes a PCON register, a CSR register, a PC designation register, and a converted instruction register RINST. The PCON register, the CSR register, and the PC designation register 2B is the same as that of FIG.2 (b), and the detailed description is omitted.The converted instruction register RINST is a register for storing the converted instruction INST, and its output is ( 1) The input terminal is connected to the (1) input terminal of the selector 108 (see FIG. 3A).

The memory control device 10b according to the present embodiment operates as follows.
[1] Store data in the CSR register and the PC designation register. In this example, this data is assumed to be 0: 0330H (segment = 0, address = 0330H, hereinafter referred to as “setting data”).
[2] Store the converted instruction in the converted instruction register RINST. In this example, this instruction is B2: C000H (segment address = 2: jump instruction to C000H).
[3] Set PCON to a logical value “1” to enable this function.
[4] A comparison process between the value of the CSR register and CPU_CSR and a comparison process between the PC designation register and CPU_PC are executed.
[5] When all of the above comparison results match, an instruction for jumping to a memory address set by hardware in the converted instruction register RINST is executed.
[6] The process specified at the jump destination is executed, and the process returns to the jump source under predetermined conditions.

  FIG. 6 shows a state where the programs stored in the memory 12 are sequentially executed according to the address specified by the PC of the CPU 14. Then, as a result of the comparison processing in [4], if the segment and address corresponding to the PC match the setting data set in [1], the pre-conversion instruction 20 to be executed is the post-conversion instruction. It is converted into the instruction 22 after the conversion. More specifically, the pre-conversion instruction 20 represented by the combination of the instructions MOV R0, # 01H specified by PC = 0: 0330H and the instructions MOV R1, # 01H specified by PC = 0: 0332H is B 2: C000H (segment address = 2: jump instruction to C000H) is converted into the converted instruction 22. As a result, as shown by [5] in FIG. 6, the program jumps to the segment address = 2: C000H of the memory 12, and executes the program stored at the address. Thereafter, the value returns to the value of the next PC under predetermined conditions ([6]).

[Third Embodiment]
With reference to FIG. 7, a memory control device 10c according to the present embodiment will be described. The present embodiment is an embodiment in which a plurality of designated PCs are supported by using a post-conversion instruction register RINST. FIG. 7 is a diagram showing the correspondence between the address of the designated PC and the jump destination address (jump destination address) jumped by the jump instruction. FIG. 7 shows that, for example, when the address of the designated PC is PC0, the converted instruction is a jump instruction B2: C000H.

  As shown in FIG. 7, when there are a plurality of PCs that can be set, that is, when there are a plurality of designated PCs, numbers are assigned to the designated PCs to change the jump destination address. The processing flow is the same as that of the case where the number of designated PCs is one. However, as for the jump destination address, a leading address is set by a parameter, and the address is set as the jump destination of the designated PC PC0. Changes the destination by shifting the address. At this time, the interval between addresses may be such that one jump instruction is inserted. Further, since it is possible to determine from which PC the user jumped depending on the jump destination, it is convenient when returning from the jump destination.

[Fourth Embodiment]
The memory control device 10d according to the present embodiment will be described with reference to FIGS. In the above embodiment, the instruction conversion function of the memory control device converts the instruction to be executed by setting the designated PC. As an example, the instruction is jumped to an address different from the originally specified address in the memory. A process different from the process to be executed was executed. On the other hand, in the present embodiment, the memory area is divided so that the area of the memory at the jump destination jumped in the above embodiment becomes an area having an appropriate attribute according to the processing content. More specifically, this is a form in which a function is further expanded to support various software applications while performing processing similar to block enableable using a code option of a memory. Here, the code option refers to a parameter for controlling a memory to be subjected to area division, and in the present embodiment, particularly refers to a parameter to be stored in a rewrite setting register set.

  FIG. 8A shows a functional block diagram of a memory control device 10d according to the present embodiment. As shown in FIG. 8A, the memory control device 10d includes a memory loader (setting unit) 200 and a rewrite setting register set 202. Although the memory control device 10d shown in FIG. 8A extracts and describes only the configuration related to the present embodiment, it goes without saying that the memory control device 10d shown in FIG. 2A and FIG. It may include the instruction conversion unit 100, the instruction conversion register set 120 (120a), and the converted instruction setting circuit 112.

  Although the type of the memory 12 is not particularly limited, in the present embodiment, a non-volatile memory such as a flash memory is assumed, and a memory space area includes a program area 210 and a data area, like a general memory. 214. The memory 12 according to the present embodiment further includes a test (setting data) area 212. The test area 212 is an area in which parameters for operating peripheral circuits of the memory 12 are stored. In the present embodiment, a code option, that is, data for rewrite setting (hereinafter, “rewrite setting data”) Is stored.

  The memory loader 200 reads the rewrite setting data from the test area 212 of the memory 12 and stores each parameter of the rewrite setting data in each register of the rewrite setting register set 202.

  The rewrite setting register set 202 is a set of registers for storing parameters for dividing an area of the memory space of the memory 12. FIG. 8B shows the contents of the rewrite setting register set 202. As shown in FIG. 8B, the rewrite setting register set 202 according to the present embodiment includes three registers: a rewrite acceptor register, a rewrite program area start address register, and a rewrite area division setting register. The memory space of the memory 12 is divided according to the contents of these three registers.

  The rewrite acceptor register stores data (acceptor setting data) for setting the rewrite acceptor. The acceptor setting refers to setting whether or not to allow a program to rewrite or erase a memory or to execute a program in accordance with a pattern of area division. The acceptor setting data is data for performing this switching. It is. When the value of this data is a predetermined value, the rewriting process or the like is enabled. After the rewriting process is enabled, the area of the memory 12 is divided into a fixed area and a rewriting area based on the rewriting program area start address data and the area division setting data. Here, the fixed area is an area where erasing (erasing) / writing (writing) cannot be performed from software, and the rewriting area is an area where erasing / writing can be performed from a program.

  The rewrite program area start address register stores data (program area start address data) that specifies an address at which the rewrite program area starts. When the rewriting process is enabled by the above-described acceptor setting, the area after the designated address becomes the rewriting program area.

  The rewriting area division setting register stores data (area division data) specifying the number of rewriting areas. When the rewriting process is enabled by the above-described acceptor setting, for example, if the value of the area division data is “0x0”, one area of the rewriting area is secured, and if the area division data is “0x1”. , Two rewrite areas are secured. However, in the present embodiment, the execution area of the CPU 14 when the two areas are secured is the value of a predetermined register (a register that specifies an area that can be accessed by the CPU 14, hereinafter referred to as an “access area specification register”). , Only one area is provided.

  In the memory control device 10d according to the present embodiment, by setting the above three data, that is, the three data of the acceptor setting data, the program area start address data, and the area division data shown in FIG. The method of controlling the memory division by the memory control device 10d changes.

Next, a division control method of the memory 12, that is, a flow until data of the test area 212 (code option) is stored in each register and the memory space of the memory 12 is divided will be described with reference to FIG. . [1] to [3] of FIG. 9 show the procedure of the division control of the memory 12 according to the present embodiment, and the contents are as follows.
[1] The memory loader 200 loads (reads) the code option stored in the test area 212 when the memory control device 10d is reset before the CPU 14 is started.
[2] Each data (acceptor setting data, program area start address data, and area division data) loaded by the memory loader 200 is stored in each register of the rewrite setting register set.
[3] The method of setting the area division of the memory 12 is determined based on the code option data, and the area division is performed.
By executing the above division control, an access method of the CPU 14 to the memory 12 (hereinafter, referred to as “CPU access”) is set. Hereinafter, each CPU access will be described. As shown in FIG. 9, in the following description, the program area start address data is described as “0xYYYY”.

  FIG. 10A shows CPU access when rewriting is disabled, that is, when the acceptor setting data is set to be invalid in the rewriting acceptor register. FIG. 10B shows the value of each register at that time. , Respectively. In the present embodiment, rewriting is disabled when the value of the acceptor setting is “0”, and rewriting is enabled when the value is “1”. Of course, this correspondence may be a reverse logical value. As shown in FIG. 10A, when the acceptor setting data is in an invalid state, the entire area of the program memory space is a fixed program area, so that ROM reading (data reading) is possible, but Erase / Write ( Erase and write) cannot be performed. Here, the “fixed program area” in the present embodiment is an area in which the “fixed program” is stored, and the “fixed program” is a program for operating the microcomputer system 1 according to the present embodiment. It is.

  FIG. 11A shows a case where rewriting is valid, that is, a case where acceptor setting data is set to be valid in the rewriting acceptor register, and a CPU access when the rewriting region division setting is set to one region is shown in FIG. FIG. 11B shows the values of the respective registers at that time. When the acceptor setting is valid, the program memory space is divided into a fixed program area and a rewrite program area. The rewrite program area occupies a certain area in the memory space starting from the rewrite program area start address YYYY.

  Here, the “rewrite program area” in the present embodiment refers to an area in which a “rewrite program” is stored. Further, the “rewrite program” is a program combined with the “fixed program”, and in the present embodiment, one program is constituted by “fixed program” + “rewrite program”. That is, for example, by shifting to the rewriting program by a jump instruction described in the fixed program, both functions as an integrated program. In the fixed program area, ROM reference is possible, but Erase / Write cannot be performed. Since the rewritable program area is a rewritable area, erase / write can be performed in addition to ROM reference. In the present embodiment, an example in which the rewrite program area start address YYYY is set immediately below the fixed program area will be described. However, the present invention is not limited to this. For example, a certain storage area is provided between the fixed program area and the fixed program area. May be specified as the address YYYY.

FIG. 12A shows the CPU access when the rewrite is valid and the rewrite area division setting is set to two areas, and FIG. 12B shows the values of the respective registers at that time.
In this case, the program memory space is divided into a fixed program area, a rewrite program area 0 and a rewrite program area 1.

  In the present embodiment, “rewrite program area 0” refers to an area in which “rewrite program 0” is stored, and “rewrite program area 1” refers to an area in which “rewrite program 1” is stored. In the fixed program area, ROM reference is possible, but Erase / Write cannot be performed. On the other hand, in the present embodiment, the configuration is such that each of the rewrite program area 0 and the rewrite program area 1 can be switched between an area where a program can be executed and an area where erase / write is possible. Have been.

  The area dividing method of the memory control device 10d according to the present embodiment will be described in more detail. In the area dividing method according to the present embodiment, when the rewrite program area start address YYYY is specified, an area for storing the rewrite program is stored after the address YYYY (in this embodiment, immediately below the fixed program area). Two areas of the same capacity are secured. Hereinafter, as shown in FIG. 12A, the two areas are referred to as “area A” and “area B” in order from the one closer to the fixed program area. In the present embodiment, the case where the capacities of the two regions are the same will be described as an example, but of course, these capacities may be different.

  In this embodiment, the area A is an area where a program can be executed, and the area B is an area where erase / write is possible. Then, in the present embodiment, the configuration is such that the program is shifted to the program stored in the area A after the execution of the fixed program by a jump instruction described in the fixed program. In the present embodiment, the memory control device 10d controls the attributes of the area A and the area B. That is, of the rewrite programs 0/1, the one stored in the area A is a rewrite program that can execute the program, and the one stored in the area B is a rewrite program that can be erased / written. As a result, supposing that the rewrite program 0 is stored in the area A and the rewrite program 1 is stored in the area B, on the one hand, the fixed program + the rewrite program 0 is executed, and on the other hand, the rewrite program 0 is executed. For 1, the operation of performing an operation such as updating can be performed.

  In addition to the above, in the present embodiment, the rewriting program 0/1 stored in the area A and the area B can be switched. That is, as described above, the area to be used as a program can be determined for the rewrite program area by setting the access area designation register. More specifically, when the value of the access area designation register is “0x00”, the rewrite program area 0 is stored in the area A as shown in FIG. Space), it is treated the same as a fixed program area. Therefore, the rewrite program area 0 is an area in which ROM reference is possible but Erase / Write cannot be performed. At this time, since the rewrite program area 1 is stored in the area B, it becomes a rewritable area, so that it becomes an area in which ROM reference and erase / write are possible (updatable).

  On the other hand, when the value of the access area designation register is “0x01”, the rewrite program area 1 is stored in the area A as shown in FIG. It is treated the same as the program area. Therefore, the area can be referred to the ROM, but cannot perform the erase / write. At this time, since the rewrite program area 0 is stored in the area B, it becomes a rewritable area, so that it becomes an area in which ROM reference and erase / write are possible (updatable).

  The operation of the area dividing method of the memory control device 10d according to the present embodiment having the above-described configuration will be described in more detail. As an initial state, consider a state in which the rewrite program 0 is stored in the area A and the rewrite program 1 is stored in the area B, that is, a state in which the value of the access area designation register is “0x00”. In this case, the program of the microcomputer system 1 is created by a program (initial program) consisting of a fixed program + a rewriting program 0.

  Thereafter, when the initial program needs to be updated, for example, after writing the rewriting program 1 in the area B via external communication means (not shown), the value of the access area designation register is set to “0x01”. I do. As a result, the rewrite program 1 is stored in the area A instead of the rewrite program 0, so that the rewrite program 1 is a program executed by the CPU 14. On the other hand, the rewriting program 0 in the initial program is a program capable of erase / write, and can be prepared for the next update.

  As described in detail above, in the area dividing method of the memory control device 10d according to the present embodiment, the rewriting program stored in the area A and the rewriting program stored in the area B can be switched by the access area designation register. With this configuration, the rewrite program can be updated without changing the program in the fixed program area.

  As described above, the memory control device according to the present embodiment uses the data set by the code option as data for controlling the memory, thereby dividing the memory space in detail according to the purpose of use of the memory. Can be. Also, regarding security, by setting an area that cannot be rewritten, even if the program runs out of control, data in that area cannot be erased or written. This has the effect of ensuring reliability. Therefore, for example, the area of the memory at the jump destination jumped by the instruction conversion function can be set as an area having an appropriate attribute according to the processing content.

1 Microcomputer system 10, 10a, 10b, 10c, 10d Memory controller 12 Memory 14 CPU
16 Bus 20 Instruction before conversion 22 Instruction after conversion 100, 100-1, 100-2, 100-3 Instruction conversion unit 100a Compound instruction conversion unit 102 AND circuit 104 OR circuit 106 Selector 108 Selector 110, 110a Selector 112 Conversion instruction setting Circuit 114 Selection circuit 120, 120a Instruction conversion register set 130, 132 OR circuit 140 Program counter 200 Memory loader 202 Rewrite setting register set 210 Program area 212 Test area 214 Data area INST, INST1, INST2 Instruction after conversion

Claims (5)

A memory including a program area in which instructions for executing the program are stored, a data area in which data accompanying the execution of the program is stored, and a setting data area in which rewrite setting data for specifying a method of dividing the memory space is stored; And a memory control device for controlling the memory in a microcomputer system including a central processing unit that sequentially specifies instructions stored in the memory according to the program and executes the program,
A rewrite setting register for holding a value of the rewrite setting data;
The setting data area is read, and the value of the read rewriting setting data is held in the rewriting setting register, and the area division of the memory space is set based on the value of the rewriting setting data held in the rewriting setting register. A setting section,
A memory control device comprising: The rewrite setting data is rewrite acceptor data indicating whether to set a rewrite program area that is a program area newly added by the area division, rewrite program area start address data indicating a start address of the rewrite program area, and Including rewriting area division setting data indicating the number of divisions of the rewriting program area,
The setting unit includes:
If the rewrite acceptor data does not set a rewrite program area, the entire program area of the memory is a fixed program area where writing and erasing is impossible,
If the rewrite acceptor data specifies that a rewrite program area is to be set, and if the number of divisions is set to 1 in the rewrite area division setting data, one write and erase operation is performed in addition to the fixed program area. Divides and sets the rewrite program area where
If the rewrite acceptor data specifies that a rewrite program area is to be set, and if the number of divisions is set to 2 in the rewrite area division setting data, one write and erase operation is performed in addition to the fixed program area. 2. The memory control device according to claim 1, wherein two rewrite program areas, a rewrite program area capable of performing writing and erasing and a rewriting program area in which writing and erasing cannot be performed, are divided and set. When the number of divisions is set to 2 in the rewrite area division setting data, one of the two rewrite program areas is a writable / erasable area and the other is not writable / erasable. Further includes access area designation data to be
3. The memory control device according to claim 2, wherein the setting unit switches between enabling and disabling writing and erasing of the two rewrite program areas by switching the access area designation data. 4. A memory including a program area in which instructions for executing the program are stored, a data area in which data accompanying the execution of the program is stored, and a setting data area in which rewrite setting data for specifying a method of dividing the memory space is stored; And a memory control method for controlling the memory in a microcomputer system including a central processing unit that sequentially specifies instructions stored in the memory according to the program and executes the program,
The setting unit reads the setting data area, holds the value of the read rewriting setting data in the rewriting setting register, and divides the area of the memory space based on the value of the rewriting setting data held in the rewriting setting register. Set the memory control method. The rewrite setting data is rewrite acceptor data indicating whether to set a rewrite program area that is a program area newly added by the area division, rewrite program area start address data indicating a start address of the rewrite program area, and Including rewriting area division setting data indicating the number of divisions of the rewriting program area,
The setting by the setting unit is
If the rewrite acceptor data does not set a rewrite program area, the entire program area of the memory is a fixed program area where writing and erasing is impossible,
If the rewrite acceptor data specifies that a rewrite program area is to be set, and if the number of divisions is set to 1 in the rewrite area division setting data, one write and erase operation is performed in addition to the fixed program area. Divides and sets the rewrite program area where
If the rewrite acceptor data specifies that a rewrite program area is to be set, and if the number of divisions is set to 2 in the rewrite area division setting data, one write and erase operation is performed in addition to the fixed program area. 5. The memory control method according to claim 4, further comprising dividing and setting two rewrite program areas: a rewrite program area capable of performing write and a rewrite program area in which writing and erasing cannot be performed.