JP2015035155A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve access protection by a peripheral device unit.SOLUTION: An information processor 100 includes: a memory protection unit 11; and an access control part 20. The address space of a CPU 10 includes a plurality I/O alias address ranges, and a plurality of peripheral devices D1 to Dn disposed in the information processor 100 are mapped for each I/O alias address range. The memory protection unit 11 sets an access permission area for permitting access from the CPU 10 in the address space. The access control part 20 switches whether the access from the CPU is valid or invalid for each of the peripheral devices D1 to Dn according to which I/O alias address range among the plurality of I/O alias address ranges is accessed by the CPU 10.

Description

  The present invention relates to an information processing apparatus that restricts access to a memory and peripheral devices using a memory protection unit.

  As the scale of embedded software increases, the need for memory protection is increasing in embedded systems in order to operate each function safely. Memory protection is to limit the accessible memory and peripheral devices for each application software constituting the embedded software.

  In embedded systems, memory protection is often realized by hardware called a memory protection unit (MPU). The MPU sets a plurality of areas in the address space and gives an access right for each area (for example, refer to the following non-patent documents 1 and 2 for an overview of the MPU).

Renesas Electronics, “V850E2M Microprocessor Core User's Manual Architecture”, Volume 3 Chapter 6 Memory Protection, Rev.1.00, October 2010 ARM, "Cortex-M3 Revision r2p1 Technical Reference Manual", Chap.5 Memory Protection Unit

  There is an upper limit to the number of areas that can be set by the MPU, and is usually 10 or less. For this reason, when a general OS and an application program are operated, a large number of areas are used for memory protection, and the number of areas usable for protection of peripheral devices is insufficient. As a result, there arises a problem that access protection for each peripheral device cannot be realized.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  An information processing apparatus according to an embodiment includes a memory protection unit and an access control unit. The CPU address space includes a plurality of I / O alias address ranges, and a plurality of peripheral devices provided in the information processing apparatus are mapped for each I / O alias address range. The memory protection unit sets an access permission area for permitting access from the CPU in the address space. The access control unit switches whether the access from the CPU is valid or invalid for each peripheral device according to which I / O alias address range of the plurality of I / O alias address ranges is accessed by the CPU. .

  According to the information processing apparatus of the above-described embodiment, access protection in units of peripheral devices can be realized.

1 is a block diagram schematically showing a configuration of an information processing device according to a first embodiment. It is a figure which shows an example of the address space of CPU. It is a figure which shows the address mapping of a peripheral device in detail. FIG. 3 is a diagram showing, in a table format, which peripheral devices are set to be accessible when executing which application software in the information processing apparatus according to the first embodiment. It is a figure for demonstrating the area | region setting by MPU at the time of operation | movement of the application software 1. FIG. It is a figure for demonstrating operation | movement of an access control part at the time of operation | movement of the application software. It is a figure for demonstrating the area | region setting by MPU at the time of operation | movement of the application software 2. FIG. It is a figure for demonstrating operation | movement of an access control part at the time of operation | movement of the application software. It is a figure which shows which peripheral device is set so that it becomes accessible at the time of execution of which application software in the information processing apparatus of a comparative example. It is a figure for demonstrating the area | region setting by MPU at the time of operation | movement of the application software 1 in the information processing apparatus of a comparative example. It is a figure for demonstrating the area | region setting by MPU at the time of operation | movement of the application software 2 in the information processing apparatus of a comparative example. 6 is a block diagram illustrating a configuration of an information processing device according to Embodiment 2. FIG. FIG. 10 is a diagram showing, in a tabular form, which peripheral devices are set to be accessible when executing which application software in the information processing apparatus according to the second embodiment. It is a figure for demonstrating operation | movement of the information processing apparatus in the setting example of FIG. FIG. 10 is a block diagram illustrating a configuration of an information processing device according to a third embodiment.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. The same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

<Embodiment 1>
[Configuration of information processing device]
FIG. 1 is a block diagram schematically showing the configuration of the information processing apparatus according to the first embodiment.

  Referring to FIG. 1, information processing apparatus 100 is configured as a computer system such as an embedded system. The information processing apparatus 100 includes a central processing unit (CPU) 10, a flash memory 12, a DRAM (Dynamic Random Access Memory) 13, n peripheral devices 1 to n (D1 to Dn), a memory A protection unit (MPU: Memory Protection Unit) 11, an access control unit 20, and a bus 14 are included. As shown in FIG. 1, the elements constituting the information processing apparatus 100 are connected to each other via a common bus 14.

  The CPU 10 performs control processing and arithmetic processing for the entire information processing apparatus. In this embodiment, the number of bits of data that can be handled by the CPU 10 is 32 bits. The CPU 10 is connected to the flash memory 12, the DRAM 13, and the peripheral devices 1 to n (D1 to Dn) via the bus 14, and accesses these memories and the peripheral devices.

  The flash memory 12 is used as a ROM (Read Only Memory) and an external storage device. The flash memory 12 stores an OS (Operating System) and a plurality of application programs in advance. The DRAM 13 is used as a main storage device, and a program necessary for execution is called from the flash memory 12. Although not illustrated in FIG. 1, the information processing apparatus 100 may include other memories such as a processor built-in memory.

  The peripheral devices 1 to n (D1 to Dn) correspond to, for example, a timer, a serial communication interface, a DMA (Direct Memory Access) controller, an interrupt controller, a general-purpose input / output port, and a display controller. In this specification, the peripheral device may be simply referred to as a device.

  The MPU 11 is hardware specialized for memory protection. In embedded systems, memory protection is often realized by MPU rather than by virtual storage using a memory management unit (MMU).

  Specifically, the MPU 11 can designate a plurality of areas (also referred to as access permission areas) in the address space of the CPU 10 and can give an access right (read / write) for each area. Only one of read / write may be permitted, or both may be permitted. In general, the area is specified by specifying an upper limit and a lower limit of the address, but a start address and a size may be specified. There is an upper limit to the number of regions that can be created, and generally no more than ten. This is because when the number of regions is increased, the number of comparators increases, so that not only the circuit area increases but also a delay occurs.

[About device access protection]
Next, features of access protection for peripheral devices in the information processing apparatus 100 according to the first embodiment will be described. The information processing apparatus 100 has the following features.

  (1) A plurality of address ranges (hereinafter referred to as I / O (Input / Output) alias address ranges) are provided in the address space for data input / output to / from peripheral devices. Peripheral devices 1 to n (D1 to Dn) are mapped for each I / O alias address range.

  (2) A processor (CPU) having a memory protection unit (MPU) is used. Preferably, any one of a plurality of I / O alias address ranges is permitted by the MPU.

  (3) A mechanism (access control unit) is provided for switching access to each peripheral device to be valid or invalid according to which I / O alias address range is accessed among a plurality of I / O alias address ranges. . Hereinafter, each feature will be described in detail.

(1. Peripheral device mapping method)
FIG. 2 is a diagram illustrating an example of the address space of the CPU 10.

  In the example shown in FIG. 2, in the 4 GB (gigabyte) address space (0x0000000 to 0xFFFFFFFF), the flash memory 12 is mapped to 0x0000000 to 0x0FFFFFFF and the DRAM 13 is mapped to 0x1000000 to 0x1FFFFFFF. Note that “0x” is added to the head of the address to clearly indicate that the address is a hexadecimal number.

  In this embodiment, a memory mapped I / O is used as a method for inputting / outputting data to / from each peripheral device. In memory-mapped I / O, a memory and a peripheral device coexist in the address space, and a memory read / write command is also used for each peripheral device. Specifically, in the example of FIG. 2, the peripheral devices 1 to n (D1 to Dn) are mapped to 0x20000000 to 0x2FFFFFFF.

FIG. 3 is a diagram showing the address mapping of peripheral devices in more detail.
Referring to FIG. 3, the address space of CPU 10 is provided with a plurality of address ranges (I / O alias address ranges 1, 2, 3,...) For accessing peripheral devices 1 to n (D1 to Dn). It is done. Peripheral devices 1 to n (D1 to Dn) are mapped for each I / O alias address range. For example, as shown in FIG. 3, the device 1 is mapped to the address range 0x20010000 to 0x20010FFF in the I / O alias address range 1 and is mapped to the address range 0x20000000 to 0x20020FFF in the I / O alias address range 2. ing. The device 1 is further mapped to the address range 0x20030000 to 0x20030FFF in the I / O alias address range 3. The same applies to the other devices 2, 3,.

(2. Protection area setting by MPU)
Each of the above I / O alias address ranges individually corresponds to each application software. For example, the I / O alias address ranges 1, 2, 3,... Correspond to the application software 1, 2, 3, respectively. The MPU designates an I / O alias address range corresponding to the operating application software as an access permission area. Therefore, the I / O alias address range of FIG. 3 is required for the number of application software. The protection area switching by the MPU is executed by system software such as an OS when switching application software to be operated.

(3. Access control unit)
The access control unit 20 determines whether access is valid or invalid for each peripheral device depending on which I / O alias address range is accessed by the CPU among the above I / O alias address ranges 1, 2, 3,. Switch between. By combining this function of the access control unit 20 and setting of the protection area by the MPU, it is possible to switch the accessible peripheral device for each peripheral device according to the application software. Hereinafter, access control for each device will be further described using a specific example.

(4. Specific examples of device access control)
FIG. 4 is a diagram showing in tabular form which peripheral device is set to be accessible when executing which application software in the information processing apparatus of the first embodiment. In the example shown in FIG. 4, the peripheral devices 1 and 4 are set so that they can be accessed when the application software 1 operates, but cannot be accessed when other application software operates. The peripheral devices 2 and 3 are set so that they can be accessed when the application software 2 operates, but cannot be accessed when other application software operates. In order to realize such device access control for each application on a device basis, an MPU 11 and an access control unit 20 are provided.

  Although different from the case of FIG. 4, for example, the device 1 can be set to be accessible during the operation of the application software 1 and 2.

  FIG. 5 is a diagram for explaining region setting by the MPU during operation of the application software 1. Referring to FIG. 5, when the application software 1 operates, the MPU 11 in FIG. 1 sets the I / O alias address range 1 (0x20010000 to 0x2001FFFF) as the access permission area (MPU area 1). Access to other address ranges is not permitted. Note that the strikethrough shown in FIG. 5 is invalidated when accessed as described in FIG.

  FIG. 6 is a diagram for explaining the operation of the access control unit 20 during the operation of the application software 1. Note that the strikethrough shown in FIG. 6 indicates that it becomes invalid when accessed as described below.

  Referring to FIG. 6, according to the control of access control unit 20, device 1 (D1) is valid when accessed by address 0x20010000-0x20010FFF in I / O alias address range 1, but I / O alias address When accessed by address 0x20000000 to 0x20020FFF in range 2, it becomes invalid. Device 2 (D2) is invalid when accessed by address 0x20011000-0x200111FFF in I / O alias address range 1, but enabled when accessed by address 0x20021000-0x20021FFF in I / O alias address range 2 Become. Device 3 (D3) is invalid when accessed by address 0x20012000-0x200112FFF in I / O alias address range 1, but valid when accessed by address 0x20022000-0x20022FFF in I / O alias address range 2 Become. Device 4 (D4) is valid when accessed by address 0x20013000-0x200113FFF in I / O alias address range 1, but is invalid when accessed by address 0x20022000-0x20022FFF in I / O alias address range 2 Become.

  By combining the control operation of the access control unit 20 and the area setting by the MPU described with reference to FIG. 5, the devices 1 and 4 can be accessed from the CPU 10 during the operation of the application software 1. Cannot be accessed from the CPU 10. That is, device access control with the settings shown in FIG. 4 can be realized.

  FIG. 7 is a diagram for explaining area setting by the MPU during the operation of the application software 2. Referring to FIG. 7, during operation of application software 2, I / O alias address range 2 (0x20000000 to 0x2002FFFF) is set in the access permission area by MPU 11 in FIG. Access to other address ranges is not permitted. Note that the strikethrough shown in FIG. 7 is invalidated when accessed.

  FIG. 8 is a diagram for explaining the operation of the access control unit 20 during the operation of the application software 2. Referring to FIG. 8, the control operation itself of access control unit 20 is the same as the operation of application software 1 described in FIG. By combining the control operation of the access control unit 20 and the area setting by the MPU described with reference to FIG. 7, when the application software 2 operates, the devices 2 and 3 can be accessed from the CPU 10, and the devices 1 and 4 are connected to the CPU Can no longer be accessed. That is, device access control with the settings shown in FIG. 4 can be realized. Note that the strikethrough shown in FIG. 8 is invalidated when accessed.

  Here, when FIG. 6 is compared with FIG. 8, only one continuous area (referred to as MPU area 1) is set as an access permission area by the MPU. That is, in the case of FIG. 6 (when the application software 1 is executed), the I / O alias address range 1 (0x20010000 to 0x2001FFFF) is set in the MPU area 1. On the other hand, in the case of FIG. 8 (when the application software 2 is executed), the I / O alias address range 2 (0x20000000 to 0x2002FFFF) is set in the MPU area 1. That is, the number of MPU areas set for device access control can be reduced to one.

[Effect of Embodiment 1]
Hereinafter, effects of the first embodiment will be described.

  First, the information processing apparatus 100 according to the first embodiment can realize access protection in units of peripheral devices. In other words, if only the MPU area is set, all peripheral devices arranged in the set MPU area can be accessed. Therefore, by combining the setting of the MPU area and the function of the access control unit 20 capable of setting the validity / invalidity of access in units of peripheral devices, it is possible to realize the setting of accessibility in units of peripheral devices for each application.

  Furthermore, when switching applications, only the setting of one area needs to be changed by the MPU, so that the execution overhead can be reduced. As a result, high-speed application switching processing is realized. Furthermore, since there is no need to change the CPU, a general-purpose CPU can be used.

  Hereinafter, the effects of the first embodiment will be supplemented by comparing with the information processing apparatus of the comparative example. Here, in the information processing apparatus of the comparative example, the access control unit 20 shown in FIG. 1 is not provided, and a plurality of I / O alias address ranges as shown in FIG. 3 are not set. Assume that a device is mapped to a single address range.

  FIG. 9 is a diagram showing in tabular form which peripheral device is set to be accessible when executing which application software in the information processing apparatus of the comparative example. In the example shown in FIG. 9, the peripheral devices 1, 2, and 5 are set so that they can be accessed when the application software 1 operates, but cannot be accessed when other application software operates. The peripheral devices 3, 4, 6 and 8 are set so that they can be accessed when the application software 2 operates, but cannot be accessed when other application software operates. The peripheral device 7 is set so that it can be accessed when the application software 3 operates, but cannot be accessed when other application software operates.

  FIG. 10 is a diagram for explaining region setting by the MPU during the operation of the application software 1 in the case of the information processing apparatus of the comparative example.

  Referring to FIG. 10, first, address mapping of peripheral devices will be described. Device 1 is mapped to a single address range 0x20010000 to 0x20011000. The same applies to the other devices 2, 3,..., And they are mapped to a single address range set individually. Which device is mapped to which address range is determined at the time of hardware design.

  In order to realize the access setting of FIG. 9, it is necessary to set the peripheral devices 1, 2 and 5 to be accessible when the application software 1 operates. Here, the MPU can designate only one area as a continuous address range. However, since the devices used by each application differ from system to system, there are many cases where all the devices used are not arranged at consecutive addresses.

  Specifically, the peripheral devices 1 and 2 are mapped to a continuous address range, but the peripheral device 5 is mapped to an address range separated from the peripheral devices 1 and 2. Therefore, it is necessary to set the address range 0x20010000-0x200111FFF to which the peripheral devices 1 and 2 are mapped to the MPU area 1 and set the address range 0x20014000 to 0x20014FFF to which the peripheral device 5 is set to the MPU area 2. The number of MPU areas to be set is two.

  FIG. 11 is a diagram for explaining region setting by the MPU during the operation of the application software 2 in the case of the information processing apparatus of the comparative example.

  Referring to FIG. 11, when application software 2 operates, peripheral devices 3, 4, 6 and 8 need to be set to be accessible. Here, although the peripheral devices 3 and 4 are mapped to a continuous address range, the address ranges of the peripheral devices 6 and 8 are separated from each other and are also separated from the address ranges of the peripheral devices 3 and 4. Therefore, the address range 0x20012000 to 0x2001FFF to which the peripheral devices 3 and 4 are mapped is set in the MPU area 1, and the address range 0x20015000 to 0x200115FFF to which the peripheral device 6 is mapped is set in the MPU area 2. Furthermore, it is necessary to set the address range 0x2001000 to 0x20017FFF to which the peripheral device 8 is mapped in the MPU area 3.

  Here, when a general OS and an application program are operated, a large number of MPU areas are used for memory protection. Therefore, the number of MPU areas that can be used for protecting peripheral devices is small. As a result, when the addresses of a plurality of peripheral devices used by the application software are not arranged in a continuous address range, there is a problem that the number of MPU areas is insufficient and some devices cannot be used. In the case of FIG. 11, when the number of MPU areas available for device protection is limited to two, the peripheral device 8 cannot be set as the MPU area. In the information processing apparatus 100 according to the first embodiment, the number of MPU areas to be set is sufficient, so the above problem can be avoided.

[Modification]
In the above embodiment, the case of the memory mapped I / O method has been described. On the other hand, also in the case of the port mapped I / O method, a plurality of I / O alias address ranges are set in the address space for peripheral devices, and each I / O alias address range is set in the information processing apparatus. If a plurality of peripheral devices are mapped, device access protection similar to the above can be realized.

<Embodiment 2>
[Configuration of information processing device]
FIG. 12 is a block diagram illustrating a configuration of the information processing apparatus 101 according to the second embodiment. In the information processing apparatus 101 in FIG. 12, the access control unit 20 in FIG. 1 is specifically realized by the address decoder 21. Since the configuration of other information processing apparatus 101 is the same as that in FIG. 1, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. In particular, the address mapping for each peripheral device shown in FIG. 3 is the same in the second embodiment.

  In FIG. 12, the flash memory 12 and the DRAM 13 of FIG. 1 are not shown. As for the peripheral devices 1 to n (D1 to Dn), only four peripheral devices D1 to D4 are representatively shown.

  Referring to FIG. 12, address decoder 21 includes a comparator group 22. The comparators (equal comparators) A1, A2,... Included in the comparator group 22 correspond to the peripheral devices 1, 2,. Each comparator determines whether the upper 20 bits of the address output from the CPU 10 match the reference value held in its own register. In the following description, the most significant bit (MSB) is bit 31 and the least significant bit (LSB) is bit 0. The upper 20 bits correspond to bits 31-12.

  Specifically, the comparator A1 determines whether or not the upper 20 bits of the address output by the CPU match the reference value “0x200X0” (the value X of the bits 19 to 16 will be described later). If they match, the comparator A1 outputs the activated chip select signal 15 to the enable port EN of the device 1 (D1) corresponding to itself (comparator A1). When the chip select signal 15 is activated, access to the device 1 (D1) is valid.

  Similarly, the comparator A2 determines whether or not the upper 20 bits of the address output by the CPU matches the reference value “0x200X1”, and outputs the same to the enable port EN of the corresponding device 2 (D2) if they match. The chip select signal 15 to be activated is activated. The comparator A3 determines whether or not the upper 20 bits of the address output by the CPU match the reference value “0x200X2”, and if it matches, the chip select that is output to the enable port EN of the corresponding device 3 (D3) The signal 15 is activated. The comparator A4 determines whether or not the upper 20 bits of the address output by the CPU match the reference value “0x200X3”, and if it matches, the chip select that is output to the enable port EN of the corresponding device 4 (D4) The signal 15 is activated.

  Here, the value “X” of bits 19 to 16 is set to a value corresponding to the application software. In the case of application software 1, X = 0x1, and in the case of application software 2, X = 0x2. When both the application software 1 and 2 are supported, the comparator determines whether the value of the bits 19 to 16 of the address matches either X = 0x1 or X = 0x2. In this case, for example, two equal comparators and a logic circuit that performs an OR operation on the outputs of these comparators are provided for the device 1.

  As another method, if it is possible to set access prohibition / permission in bit units by devising address allocation, a plurality of application software can be allocated to one device. For example, referring to FIG. 5 and FIG. 12, when the value of bit 16 is “1” (the values of bits 19 to 17 are arbitrary), it is assumed that access to device 1 is possible. , 3, 5,... Can be accessed when the device 1 is executed. In general, for each device, prepare (1) a register (address pattern register) that sets the bit pattern of the address to be permitted, and (2) a register (address mask register) that sets the bit used for access permission. For example, it is possible to permit access to a plurality of application software for each device.

  Bits 15 to 12 are used to specify peripheral devices 1, 2,... (D1, D2,...). Peripheral device 1 is indicated when the values of bits 15-12 are 0x0. Similarly, peripheral device 2 is indicated when the values of bits 15 to 12 are 0x1, peripheral device 3 is indicated when the values of bits 15 to 12 are 0x2, and peripheral device 4 is indicated when the values of bits 15 to 12 are 0x3.

[Specific operation example]
Hereinafter, a specific operation example of the information processing apparatus 101 according to the second embodiment will be described.

  FIG. 13 is a diagram showing in tabular form which peripheral device is set to be accessible when executing which application software in the information processing apparatus of the second embodiment. In the example shown in FIG. 13, the peripheral devices 1 and 4 are set so that they can be accessed when the application software 1 operates, but cannot be accessed when the other application software operates. The peripheral devices 2 and 3 are set so that they can be accessed when the application software 2 operates, but cannot be accessed when other application software operates.

  In the case of the above setting example, the reference values compared with the addresses in the comparators A1 to A4 in FIG. 12 are 0x20010, 0x20021, 0x20022, and 0x20013, respectively. These reference values are set by system software such as an OS when the information processing apparatus 101 is started up. It is not necessary to reset when switching application software.

  FIG. 14 is a diagram for explaining the operation of the information processing apparatus 101 in the setting example of FIG. Referring to FIG. 14, based on the comparison operation by address decoder 21, when device 1 (D 1) is accessed from CPU 10 by address 0x20010000 to 0x20010FFF, the access becomes valid. Similarly, when the device 2 (D2) is accessed from the CPU 10 by the address 0x20021000 to 0x20021FFF, the access becomes valid. When the device 3 (D3) is accessed from the CPU 10 by the address 0x20022000 to 0x20022FFF, the access becomes valid. When the device 4 (D4) is accessed from the CPU 10 by the address 0x20013000 to 0x20013FFF, the access becomes valid. When each device is accessed by an address other than the above, the access becomes invalid. Note that the strikethrough shown in FIG. 14 is invalidated when accessed.

  When the application software 1 is operating, the MPU 11 sets the I / O alias address range 1 (0x20010000 to 0x2001FFFF) in FIG. 3 as the access permission area (MPU area 1), as in the first embodiment. Access to other address ranges is not permitted. Therefore, in combination with the function of the address decoder 21, when the application software 1 is operating, the devices 1 and 4 can be accessed from the CPU 10, and the devices 2 and 3 cannot be accessed from the CPU 10.

  When the application software 2 operates, the MPU 11 sets the I / O alias address range 2 (0x20000000 to 0x2002FFFF) in FIG. Access to other address ranges is not permitted. Therefore, in combination with the function of the address decoder 21, the devices 2 and 3 can be accessed from the CPU 10 and the devices 1 and 4 cannot be accessed from the CPU 10 when the application software 2 operates.

[Effect of Embodiment 2]
As described above, according to the information processing apparatus 101 of the second embodiment, the access control unit 20 in FIG. 1 is specifically realized as the address decoder 21. As a result, the same effect as in the first embodiment can be obtained.

<Embodiment 3>
FIG. 15 is a block diagram illustrating a configuration of the information processing apparatus 102 according to the third embodiment. In FIG. 15, the flash memory 12 and the DRAM 13 of FIG. 1 are not shown. As for the peripheral devices 1 to n (D1 to Dn), only four peripheral devices D1 to D4 are representatively shown.

  Referring to FIG. 15, information processing apparatus 102 according to Embodiment 3 includes comparators C1, C2, C3 provided in peripheral devices 1, 2, 3,... (D1, D2, D3,...), Respectively. Are different from the information processing apparatus 101 in FIG. The access from the CPU to the device body (B1, B2, B3,...) Of each peripheral device is performed together with the comparison results of the corresponding comparators A1, A2, A3,. , C2, C3,..., C2, C3,.

  Each of the comparators A1, A2, A3, A4 determines whether or not the corresponding peripheral device is accessed by the CPU 10. Specifically, each of the comparators A1, A2, A3, and A4 indicates whether bits 31 to 20 and bits 15 to 12 of the address output from the CPU 10 match the reference value determined for each comparator. Determine whether or not. The reference values compared with the addresses in the comparators A1, A2, A3, and A4 are 0x200X0, 0x200X1, 0x200X2, and 0x200X3 (where X is an arbitrary value).

  Each of the comparators C1, C2, C3, and C4 provided in each of the peripheral devices 1 to 4 is provided to determine application software to be operated in the corresponding peripheral device. Specifically, each of the comparators C1, C2, C3, and C4 determines whether or not bits 19 to 16 in the address output from the CPU 10 match a reference value determined for each comparator. . In the example shown in FIG. 15, the reference values are 0x1, 0x2, 0x2, and 0x1 in the case of the comparators C1, C2, C3, and C4, respectively.

  Accordingly, in the example shown in FIG. 15, the peripheral devices 1 and 4 are accessible when the application software 1 is operating, and the peripheral devices 2 and 3 are accessible when the application software 2 is operating.

  Other points in FIG. 15 are the same as those in FIGS. 12 and 14, and thus the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated. Note that the strikethrough shown in FIG. 15 is invalidated when accessed.

  As described above, in the case of the third embodiment, the comparators A1, A2, A3,... Provided in the address decoder 21 and the comparators C1, C2, C3,. 13 (that is, the function of the access control unit 20 in FIG. 1) equivalent to the address decoder 21 shown in FIG. As a result, the information processing apparatus 102 according to the third embodiment has the same effect as in the first and second embodiments.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  10 CPU, 11 Memory protection unit (MPU), 12 Flash memory, 13 DRAM, 14 bus, 15 Chip select signal, 20 Access control unit, 21 Address decoder, 22 Comparator group, 100, 101, 102 Information processing device, A1 -A4, C1-C4 comparator, D1-D4 peripheral device.

Claims (7)

CPU (Central Processing Unit)
With multiple peripheral devices,
The CPU address space includes a plurality of I / O alias address ranges, and the plurality of peripheral devices are mapped for each I / O alias address range.
Furthermore, a memory protection unit that sets an access permission area for permitting access from the CPU in the address space;
An access control unit that switches whether access from the CPU is valid or invalid for each peripheral device, depending on which I / O alias address range of the plurality of I / O alias address ranges is accessed by the CPU. An information processing apparatus comprising:   The information processing apparatus according to claim 1, wherein the memory protection unit sets any one of the plurality of I / O alias address ranges as the access permission area. The plurality of I / O alias address ranges respectively correspond to a plurality of application software executed by the information processing apparatus,
The information processing apparatus according to claim 2, wherein the memory protection unit sets an I / O alias address range corresponding to the application software being executed in the access permission area. The access control unit includes a plurality of comparators corresponding to the plurality of peripheral devices,
Each of the comparators determines whether or not the values of a plurality of specific bits in the address output from the CPU match a reference value determined for each of the comparators,
The information processing apparatus according to claim 1, wherein access from the CPU to each peripheral device is enabled when the values of the plurality of specific bits match the reference value defined for a corresponding comparator. The access control unit
A plurality of first comparators respectively corresponding to the plurality of peripheral devices;
A plurality of second comparators respectively corresponding to the plurality of peripheral devices;
Each of the first comparators determines whether or not the values of a plurality of first specific bits in the address output from the CPU match a first reference value determined for each of the first comparators. Determine whether
Each of the second comparators determines whether or not the values of a plurality of second specific bits in the address output from the CPU match a second reference value determined for each of the second comparators. Determine whether
The access from the CPU to each of the peripheral devices is such that the values of the plurality of first specific bits coincide with the first reference value determined for the corresponding first comparator, and The information processing apparatus according to claim 1, wherein the information processing apparatus is effective when a value of a specific bit of 2 matches the second reference value determined for a corresponding second comparator.   The information processing apparatus according to claim 5, wherein each of the second comparators is provided inside a corresponding peripheral device.   The information processing apparatus according to claim 1, wherein the plurality of peripheral devices are mapped to the address space by a memory mapped I / O method.

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