JPH0635751A - Chip for evaluation - Google Patents

Abstract

PURPOSE:To provide a chip (common name is an evaluation chip) for evaluation provided with a function capable of expanding an on-chip RAM (incorpolated RAM) and changing a mask ROM capacity by an identical chip for the evaluation. CONSTITUTION:As the chip 1 for the evaluation, a means (d) for setting two kinds (or more) of addresses (a, b) from the outside of the chip, the means (e) for performing the large/small comparison of the set address (a, b) and the address (c) to be executed, the means for permitting/inhibiting an external memory access operation based on the compared result and the means (f) for inputting/outputting the address to be executed and data (or instructions) are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory mapping function of an evaluation chip (also called an evaluation chip for short) which is used in a debugging device such as a microcomputer (hereinafter abbreviated as a microcomputer), and particularly, a RAM for a microcomputer. It relates to a (data) space mapping function.

[0002]

2. Description of the Related Art As is well known, in a microcomputer such as a one-chip LSI, at the beginning of development, a program is debugged and software is written in a mask ROM after a function satisfying the specifications is obtained. Therefore, an evaluation chip is used.

Generally, a microcomputer has an internal RAM (random access memory) and an external RAM area, and the internal RAM capacity is often tens or hundreds of bytes.
Therefore, in the case of an application program that stores several kilobytes of data in the RAM, the data is necessarily stored in the external RAM. However, recently, there is a tendency to incorporate this RAM into a microcomputer chip. So on-chip RAM space (non-external R
A function for designating the (AM space) is required as an evaluation chip.

As a conventional memory capacity changing method, an on-chip ROM (read only memory) (mask RO
Regarding the mapping of M), there is one disclosed in Japanese Patent Laid-Open No. 1-237843. The method of this document is a method of storing information indicating address area allocation (mapping) of a memory, determining an instruction address to be executed, and permitting access to the allocated memory,
The memory map is made variable so that a common evaluation chip can be specified even if the ROM version is different.

[0005]

However, in the evaluation chip having the structure described in the above-mentioned document, in the case of a microcomputer having a memory map as shown in FIG. Can not cope with the change. Especially for the target microcomputer, EA terminal (external R
There is a problem when there is an OM control terminal). Normally, when the EA terminal is activated, the mask ROM space does not exist and all becomes the external ROM space. Therefore, the method of the above document cannot deal with the on-chip RAM.

That is, for example, as shown in FIG. 6, it has a built-in mask ROM as a general-purpose memory space and an external memory space, and is constituted by a RAM and SFR (special function register so-called built-in I / O) as a local memory. In a microcomputer having a memory structure (FFFFH, 3FFFH, etc. in FIG. 6 represent addresses as is well known), when the internal RAM capacity is expanded from 256 bytes to 4 Kbytes or more, there is an architectural limitation (local memory space). On-chip RAM (built-in RAM) will be added to the general-purpose memory space. In such a case, the on-chip RAM must be built in the evaluation chip in the above configuration. That is,
In the evaluation chip of the above document, if the RAM capacity is changed (expanded) as described above, the built-in RAM cannot be changed unless the RAM having a capacity to which a value to be expanded is assigned is built-in. In other words, on-chip RAM
An external ROM is required if it is not built-in.

As described above, the present invention uses the same evaluation chip to change the mask ROM capacity and on-chip RA.
An object is to provide an evaluation chip having a function capable of expanding M (built-in RAM).

[0008]

To achieve the above object, the present invention provides a means for setting two kinds of addresses from outside the chip in an evaluation chip and a means for comparing the set address with the address to be executed. And a means for permitting / prohibiting the external memory access operation based on the comparison result and a means for inputting / outputting an address and data (or an instruction) to be executed.

[0009]

As described above, according to the present invention, the evaluation chip is provided with the terminals for inputting data representing two kinds of addresses, and the comparison unit for comparing the input value and the address executed by the evaluation chip is provided. Further, based on the comparison result, a mode control unit for instructing prohibition / permission of the external memory access operation is provided. Therefore, the area sandwiched by the data representing the above-mentioned two types of addresses is the state of the EA terminal. The internal memory access operation can be performed regardless of this.

Therefore, it is possible to deal with the derivative products having different internal ROM / RAM capacities by simply changing the two kinds of data values input to the evaluation chip.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS As an embodiment of the present invention, in a microcomputer having a memory structure as shown in FIG.
An example of adding an on-chip RAM of bytes is shown as an example.

FIG. 1 is a conceptual diagram of a debug device when an evaluation chip having the function of this embodiment is used. Breaks and trace circuits, command input keyboards, and the like, which are not directly related to the present invention, are not shown.

In the example of FIG. 1, 4 bits are input as two types of address inputs (a, b) to the evaluation chip 1 having the general-purpose memory space shown in FIG. 6 of 64 Kbytes. By doing so, addressing can be performed in units of 64K / 16 = 4K bytes.

FIG. 2 shows a block diagram of the essential parts of the functions of this embodiment.

In FIG. 2, the comparison unit is a program counter (PC which indicates the address of the general-purpose memory space to be executed).
12-15) Output higher 4 bits C (c _0-3 ) value (C)
And the value of a _0-3 input through the internal RAM upper limit address instruction input line a via the address input unit d (A)
And the value (B) of b _0-3 input via the mask ROM upper limit addressing input line b is compared, and if the result is true, B <C < A, C> A, B> C The H level is output as each output signal.

In the mode control section f, the input from the comparison section e and the EA / terminal (Exte) set by the user on the application circuit (the circuit requested by the user to operate by using the microcomputer)
rnalAccess Mode Pin) state is determined and the EXON signal (signal controlling PORT) of the logic shown in FIG.
Output more.

In the evaluation chip 1, the EXON signal is L
When the level is set, the external memory access operation of the port (PROT) is prohibited, and the memory read / write operation is performed from the emulation memory 2 in the evaluation device by using the general-purpose memory address line and data line shown in FIG. . When the EXON signal is at H level, the external memory of the port
The access operation is permitted and the external memory on the application circuit is accessed via the target cable connected to the evaluation chip.

Considering, for example, the case of allocating a general-purpose memory space as shown in FIG. 5, first, by using the system control circuit of the evaluation device, a of the evaluation chip is used.
The data of 3 _H and 2 _H input to the _0-3 and b _0-3 input terminals are set in the address input section d. By doing this, E ₁₂ as shown in FIG. 4 is obtained _{depending on} the value of PC _12-15 indicating the address to be executed.
XON signal is output (however, the signals A, B, and C of the comparison result output in FIGS. 3, 4, and 5 are a _0-3 , b _0-3 , and c, respectively).
Corresponding to _0-3 input).

That is, when the EA / terminal is at the H level,
The address 0 to 12 Kbytes space is treated as a space inside the chip because the port operates statically.

When the EA / terminal is at the L level, the port operates statically only in the space of the address 8K to 12K bytes and is treated as the space inside the chip.

The port operation is performed in this manner because the 0-8K byte space is the mask ROM area, and the 8K-
It means that the 12 Kbyte space is an internal RAM (or internal memory) region, and 12 Kbytes or more is an external memory region.

In this way, two types of addressing values are externally input to the evaluation chip, the input value is compared with the address value executed by the evaluation chip, and the external memory access operation of the port is performed according to the comparison result. By prohibiting / permitting the above, it becomes possible to deal with derivative types having different ROM / RAM capacities of the microcomputer with one type of evaluation chip.

In the present embodiment, two kinds of addressing values are used, but the number is not limited to two kinds, and of course, three kinds or more may be used if necessary.

[0024]

As described above, according to the present invention, the evaluation chip is provided with a terminal for inputting data representing two kinds of addresses, and the input value and a program counter representing an address executed by the evaluation chip are provided. Since the comparison unit for comparing the values is provided, and further the mode control unit for instructing the prohibition / permission of the external memory access operation of the port is provided according to the comparison result and the state of the EA / terminal, the above-mentioned two types of addresses are used. The area sandwiched by the meaning data enables the internal memory access operation regardless of the state of the EA / terminal.

Therefore, only by changing the two types of data values input to the evaluation chip, it is possible to deal with the derivative types having different internal ROM / RAM capacities.

[Brief description of drawings]

FIG. 1 is a conceptual diagram of an embodiment of the present invention.

FIG. 2 is a configuration diagram of main parts of an embodiment of the present invention.

FIG. 3 is an explanatory diagram of EXON state

FIG. 4 is an explanatory diagram of a mapping state.

FIG. 5: General memory space setting example

[Figure 6] Example of memory map of microcomputer

[Explanation of symbols]

 1 Evaluation chip 2 Emulation memory a Built-in RAM upper limit addressing input line b Mask ROM upper limit addressing input line c Program counter output upper 4 bits d Address input section e Comparison section f Mode control section g EA / pin input signal line h External Access permission output signal

Claims (1)

[Claims] 1. A comparison unit having two or more kinds of data inputting means representing an address and comparing the data input value with an address executed by a computer unit, and an external memory access operation based on a comparison result of the comparison unit. An evaluation chip having a control unit for controlling the permission or prohibition of the above, and having a unit for making a memory space sandwiched by the data input value into a built-in memory space.