KR20050097212A - Micro-controller unit for extending internal memory area - Google Patents

Abstract

SUMMARY OF THE INVENTION The present invention provides a microcontroller unit for efficiently expanding an internal memory area without expanding an address bus. The present invention provides a memory management unit for generating a memory access signal; A plurality of memory areas controlled by the memory management unit to output a value corresponding to the address; A program bank register for storing information identifying the plurality of memory areas; And a selector configured to be selectively controlled by the program bank register to selectively output the output signals of the plurality of memory regions.

Description

MICRO-CONTROLLER UNIT FOR EXTENDING INTERNAL MEMORY AREA}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a micro-controll unit (hereinafter referred to as 'MCU'), and more particularly to an MCU and a method therefor for expanding an internal memory area.

Frequently used in many modern embedded systems, 8-bit MCUs offer the advantages of simple control programs and easy adaptation to a variety of applications. Recently, in order to achieve higher performance using these 8-bit MCUs, the frequency of operation is increased and various functions are implemented in one chip, and the size of program memory required is rapidly increasing accordingly.

1 is a diagram illustrating a memory map of an Intel 8051 MCU according to the prior art.

Referring to FIG. 1, a memory is largely divided into a program memory area 10 for storing an application program and a data memory area 20 for storing data. Specifically, 128 bytes within the range of 0000h to 007Fh in the program memory 10 area are spaces for storing an interrupt vector for processing interrupts, and program codes are stored for the remaining areas of 0080h to FFFFh.

The data memory area 20 has an address address of 80h to ffh in the area and an area 22 for a special funtion register (hereinafter referred to as 'SFR') accessed through a direct addressing mode. And an area 24 for a user having an address address of 80h to ffh and accessed through indirect addressing mode, and a general user having an address address of 00h to 7fh and accessed in direct addressing mode or indirect addressing mode. It is divided into a memory area 26. As described above, the data memory area 20 has 256 bytes, and the data memory area 20 can be expanded by attaching a maximum of 64K bytes of memory to the outside.

On the other hand, when the CPU accesses the memory to read the code stored in the program memory area by using the memory map according to the related art, accesses only a predetermined area regardless of the size of the actual program memory or data memory. can do.

Therefore, only the size of the address bus determined when designing an existing CPU can be accessed. In other words, considering an 8-bit CPU, the size of the program memory address bus is 16-bit, so the size of the accessible memory is 64K bytes. To access more than 64K bytes of memory, the address bus must be expanded, which must be modified in the address generation module inside the CPU core. However, since the address bus is related to the execution of the actual application program and the operation of the data path, modifying the CPU core in this regard must verify not only the access of the memory but also the functions involved in the overall CPU core.

In addition, since the size of the memory is changed every time according to the designing system, the design must be modified each time, and the function of the modified CPU must be newly verified.

The present invention has been proposed to solve the above problems of the prior art, and provides an MCU for efficiently expanding an internal memory area without expanding an address bus.

According to an aspect of the present invention for achieving the above technical problem, the microcontroller unit includes a memory management unit for generating a memory access signal; A plurality of memory areas controlled by the memory management unit to output a value corresponding to the address; A program bank register for storing information identifying the plurality of memory areas; And a selector for selectively outputting the output signals of the plurality of memory regions under the control of the program-bank register.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention. do.

The following example shows how to use the lower two bits of PBANK to expand the program memory area to 128K bytes and divide it into three banks.

2 is a diagram illustrating a memory map of an MCU capable of expanding a program memory according to an exemplary embodiment of the present invention.

Referring to FIG. 2, the program memory area 100 of the memory includes 32K bytes of common program memory 120 and 32K bytes each having a space for storing a routine for processing interrupts in 128 bytes within a range of 0000h to 007Fh. It is divided into three program memories (140, 160, 180) having.

That is, each program memory area 140, 160, 180 is configured to share a common program memory area 120 having an interrupt routine, so that all memory banks can handle the same interrupt.

Comparing this with the MCU according to the related art (see FIG. 1), 64K bytes of program memories 160 and 180 are added to the program memory region 100, thereby extending the usable program memory region 100 to 128K bytes. You can see that.

In addition, although the case where the used program memory area 100 includes a plurality of 32K bytes of memory has been described as an example, 128K bytes of program memory may be used.

Table 1 below shows a memory map of a special function register (SFR) in the data memory region of the 8051.

For reference, the SFR is a register for controlling various functional blocks in the MCU. The SFR is accessed by directly accessing the lower 128 to 256 byte areas in the data memory area. SFR can be used by defining a separate register in the SFR memory map when a user needs a new function.

On the other hand, in the present invention, PBANK (Program BANK) is newly set, which is composed of 8-bits like other registers, thereby expanding the area of up to 256 64K byte program memory.

Table 2 below shows program memory addresses and bank divisions according to logic values of PBANK.

Referring to Table 2, when accessing the common program memory, PBANK [1: 0] has 00b, and the address of the accessible program memory area is 0000h to 7FFFh, as if there is no upper 32K byte area. In addition, when the program memory consisting of 32K bytes is referred to as 'bank 0, bank 1, and bank 2', respectively, the address of each bank is set equal to 8000h to FFFFh. Therefore, each bank depends on the value of PBANK [1: 0]. Is selected separately.

Therefore, before accessing the program memory, the value of PBANK should be set according to Table 1 above. As an example, the case of setting the value of PBANK using the MOV instruction will be described.

-MOV PBANK, #BANK_VALUE

When the MOV command is executed, a value of #BANK_VALUE preset in PBANK is stored.

As described above, the circuit implementation of the method of selecting each program memory bank according to the setting of PBANK will be briefly described.

FIG. 3 is a diagram illustrating a circuit implementation for selecting a program memory according to a logic value of PBANK.

Referring to FIG. 3, a MMU (Memory Management Unit) 220 for generating a memory access signal and a program memory for outputting a program code corresponding to a corresponding address under the control of the MMU 220. And a plurality of program codes output from the program memories 230 and 240 under the control of the logic values of the PBANK 280 and the PBANK 280 for storing information distinguishing the plurality of program memories. It is provided with a selection unit 260 for outputting.

In brief, the MMU 220 generates a memory access signal, and each program memory 230 or 240 outputs a program code stored at a corresponding address in response thereto. Next, the selector 260 selects a plurality of program codes output from the program memories 230 and 240 according to a setting value of the PBANK 280, and transmits them to the MMU 220. Finally, the MMU 220 receives the CPU. (Control Processing Unit, hereinafter called 'CPU', 200).

For reference, the overall operation of the MMU 220 is controlled by the CPU 200.

When the memory area needs to be expanded, the above-described present invention sets a register for distinguishing the memory area within the SFR so that the extended memory area can be selected and accessed without modification of the address bus. Can be extended. Therefore, the verification time required according to the modification of the CPU core can be saved.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

In the present invention, the form of sharing an area called a common program memory area for storing an interrupt routine for expanding the program memory area has been described as an example. However, the present invention can be used not only for the program memory area but also for the expansion of the data memory area.

As described above, the present invention can be easily expanded according to the required memory size without modifying the CPU core, so that it can be applied to an application system requiring a large memory, and the logic implementing the same saves time required for implementation and verification. It has the advantage of being.

1 is a memory map of an Intel 8051 series MCU according to the prior art.

2 illustrates a memory map of a microcontroller capable of expanding program memory without expansion of an address bus in accordance with the present invention.

3 illustrates a circuit implementation for selecting a program memory bank according to a logic value of PBANK.

* Explanation of symbols for main parts of the drawings

230, 240: program memory

260: selection unit

280: PBANK

Claims (3)

A memory management unit for generating a memory access signal; A plurality of memory areas controlled by the memory management unit to output a value corresponding to the address; A program bank register for storing information identifying the plurality of memory areas; And Selector for selectively outputting the output signal of the plurality of memory area under the control of the program-bank register Microcontroller unit having a. The method of claim 1, The plurality of memories, A common program memory for storing interrupt routines; Consists of a plurality of program memories for storing program code, The plurality of program memories sharing the common program memory to have the same interrupt routine Microcontroller unit characterized in that. A control unit for accessing the memory through an N-bit address bus; A plurality of memories having a size of 2 ^N bytes for storing data; And A program bank register for setting information for selecting the plurality of memories; Selecting one of the plurality of memories according to a value stored in the program bank register, and outputting data stored at an address corresponding to an N-bit address of the controller in the selected memory; Microcontroller unit characterized in that.