JP2019508986A - Method for updating clock synchronization topology, method and device for determining clock synchronization path - Google Patents

Abstract

The present application relates to the field of communications, and in particular to a method of updating clock synchronization topology, a method and device for determining clock synchronization paths. The method comprises the steps of receiving a first packet from a first network element, wherein the first packet includes clock synchronization capability information of the first network element, and the first network element is in the first network. The network element, the first network element having clock synchronization capability, and updating the clock synchronization topology of the first network based on clock synchronization capability information of the first network element. Further, the method determines a first clock synchronization path from the clock injection node of the first network to the first network element based on the request of the first network element and the clock synchronization topology of the first network It further includes a step. The clock synchronization topology is automatically updated based on the clock synchronization capability information of the network element to determine the clock synchronization path and reduce the cost of deploying the clock synchronization path.

Description

  This application is entitled "Method for Updating Clock Synchronization Topology, Method and Device for Determining Clock Synchronization Path" and is priority to Patent Application No. CN201610161046.0 filed on March 18, 2016 with China Patent Office This entire patent application is hereby incorporated by reference.

  The present invention relates to the field of communications, and in particular to a method of updating clock synchronization topology, a method and device for determining clock synchronization paths.

  In a network, network devices communicating with each other need to have a synchronous clock. It may be as follows that the two network devices have synchronous clocks.

  (1) Two network devices have clocks having the same frequency, and in particular, the phase difference between clock signals is a constant value.

  (2) The two network devices have clocks with the same phase, and in particular, the phase difference between the clock signals is always zero.

  In mobile backbone networks, it is particularly important that different base stations have synchronous clocks.

  In general, the method of acquiring the synchronization clock by different network devices is as follows: different network devices acquire clock signals from the same clock source directly or indirectly, and based on the clock signals Generate a local system clock. For example, a first hop network device connected to a clock source obtains the clock signal directly from the clock source to generate a local system clock of the network device. The network device sends a clock signal to the next hop network device of the network device, and the next hop network device receives the clock signal to generate a local system clock of the next hop network device. In other words, the next hop network device indirectly obtains the clock signal from the clock source.

  The clock signal transmission path from the clock source to the network device that directly or indirectly acquires the clock signal from the clock source is the clock synchronization path from the clock source to the network device.

  In the prior art, clock synchronization paths are usually planned and deployed by the network manager. With large networks, the deployment of clock synchronization paths can be quite complex. As a result, deployment efficiency is low and deployment errors are likely to occur. Failure of both the primary clock synchronization path and the pre-deployed secondary clock synchronization path to the network device usually prevents the network manager from timely redeploying the clock synchronization path. Therefore, the decrease in clock accuracy of the clock synchronization path node downstream of the faulty node affects the transmission of the service.

  The present application provides a method of updating a clock synchronization topology and a method of determining a clock synchronization path that improves the efficiency of deploying the clock synchronization path.

According to a first aspect, there is provided a method of updating a clock synchronization topology, the method comprising
Receiving the first packet from the first network element, the first packet including clock synchronization capability information of the first network element, the first network element being a network element in the first network The first network element has clock synchronization capability, and
Updating the clock synchronization topology of the first network based on the clock synchronization capability information of the first network element.

  The clock synchronization topology of the first network is updated based on the clock synchronization capability information of the first network to automatically obtain information for calculating the clock synchronization path, whereby the clock synchronization path is correctly calculated. Provide enough information to Thus, the cost of deploying clock synchronization paths is reduced.

  Apart from this, the updated clock synchronization topology of the first network comprises a clock injection node of the first network, the method comprising: from the clock injection node based on the updated clock synchronization topology of the first network The method further includes determining a clock synchronization path to the first network element. The clock synchronization path can be calculated automatically and accurately for the first network element using the updated clock synchronization topology to improve the efficiency of deploying the synchronization path.

  According to a second aspect, there is provided a path computing device comprising a receiver and an updater.

  The receiver is configured to receive the first packet from the first network element. The first packet contains clock synchronization capability information of the first network element, the first network element is a network element in the first network, and the first network element has clock synchronization capability.

  The updating unit is configured to update the clock synchronization topology of the first network based on the clock synchronization capability information of the first network element from the receiving unit.

  Apart from this, the device further comprises a decision unit, the updated clock synchronization topology of the first network comprises a clock injection node of the first network, the decision unit clocking based on the updated clock synchronization topology A clock synchronization path from the injection node to the first network element is configured to be determined.

According to a third aspect, there is provided a path computing device comprising a network interface, a memory and a processor. The memory is configured to store a clock synchronization topology of the first network. The processor is
An operation of receiving a first packet from a first network element using a network interface, the first packet including clock synchronization capability information of the first network element, and the first network element being a first network The first network element having clock synchronization capability;
Updating the clock synchronization topology of the first network based on the clock synchronization topology of the first network and the clock synchronization capability information of the first network element in memory is configured to perform.

  Alternatively, the updated clock synchronization topology of the first network includes the clock injection node of the first network, and the processor is configured to transmit the clock injection node to the first network element based on the updated clock synchronization topology. Are further configured to determine the clock synchronization path of

  Apart from this, in any one of the first aspect, the second aspect and the third aspect, the clock synchronization capability information of the first network element has clock synchronization capability in the first network element. Contains information about at least one port.

According to the fourth aspect,
Receiving the first packet from the first network element, wherein the first packet is used to request to determine a clock synchronization path for the first network element; A network element in a first network, the first network element having clock synchronization capability;
Determining a first clock synchronization path from a clock injection node of the first network to a first network element based on a clock synchronization topology of the first network, wherein the clock synchronization topology of the first network is A method is provided for determining a clock synchronization path including the steps of: a clock injection node; and a first network element.

  When the first network element requests to determine a clock synchronization path, a clock synchronization path is automatically determined for the first network element using the clock synchronization topology of the first network. In this way, the cost and complexity of deploying synchronization paths is reduced.

  According to a fifth aspect, there is provided a path calculation device including a receiver and a determiner.

  The receiver is configured to receive the first packet from the first network element. A first packet is used to request to determine a clock synchronization path for the first network element, the first network element being a network element in the first network, and the first network element being Has clock synchronization capability.

  The determination unit is configured to determine a first clock synchronization path from a clock injection node of the first network to a first network element based on a clock synchronization topology of the first network. The clock synchronization topology of the first network includes a clock injection node and a first network element.

According to a sixth aspect, there is provided a path computing device comprising a network interface, a memory and a processor. The processor is
The operation of receiving a first packet from a first network element using a network interface, wherein the first packet is used to request to determine a clock synchronization path for the first network element, One network element is a network element in a first network, the first network element having clock synchronization capability;
Determining the first clock synchronization path from the clock injection node of the first network to the first network element based on the clock synchronization topology of the first network, wherein the clock synchronization topology of the first network is A program is configured to be read out in memory to perform operations, including a clock injection node and the first network element.

  Apart from this, in any one of the fourth aspect, the fifth aspect and the sixth aspect, it is indicated that there is a failure in the second clock synchronization path from the clock injection node to the first network element. The first packet is further used, and the second clock synchronization path includes at least one network element not on the first clock synchronization path.

  The first clock synchronization path may be automatically determined for the first network, indicating that the second clock synchronization path is faulty, and using the information carried in the first packet. The first clock synchronization path does not include the faulty network element or port. Thus, after a failure in the clock synchronization path, a new synchronization path is quickly obtained for the first network element to reduce the impact of clock signal degradation on the transmission of the service.

According to the seventh aspect,
Receiving a first packet from a path computing device in a first network, the first packet including clock synchronization capability information of a first network element in the first network;
Updating the inter-network clock synchronization topology, including updating the inter-network clock synchronization topology based on clock synchronization capability information of the first network element.

  By receiving the clock synchronization capability information of the first network element, the inter-network clock synchronization topology is updated to automatically obtain information for calculating the inter-network clock synchronization path, thereby the inter-network clock synchronization Provide enough information to calculate the route correctly. In this way, the cost and complexity of deploying an inter-network clock synchronization path is reduced.

  Alternatively, the updated inter-network clock synchronization topology further includes a clock injection node of the second network and a second edge network device with clock synchronization capability in the first network, the method comprising The method further includes determining a clock injection node of the first network based on the updated inter-network clock synchronization topology. A clock injection node is automatically determined for the first network using an inter-network clock synchronization topology. In this way, the cost and complexity of deploying clock synchronization paths is reduced.

  According to an eighth aspect, there is provided an inter-network path calculation device including a receiver and an updater.

  The receiver unit is configured to receive the first packet from a path computing device in the first network. The first packet contains clock synchronization capability information of the first network element in the first network.

  The updating unit is configured to update the inter-network clock synchronization topology based on the clock synchronization capability information of the first network element from the receiving unit, and send the updated inter-network clock synchronization topology to the storage unit.

  Alternatively, the updated inter-network clock synchronization topology further includes a clock injection node of the second network and a second edge network device with clock synchronization capability in the first network. The device further comprises a determiner, wherein the determiner is configured to determine a clock injection node of the first network based on the updated inter-network clock synchronization topology.

According to a ninth aspect, there is provided an inter-network path computing device comprising a network interface, a memory and a processor. The memory is configured to store an inter-network clock synchronization topology. The processor is
Receiving a first packet from a path computing device in a first network using a network interface, the first packet including clock synchronization capability information of a first network element in the first network; Operation,
The operation of updating the inter-network clock synchronization topology based on the inter-network clock synchronization topology in memory and the clock synchronization capability information of the first network element is configured to be performed.

  Apart from this, the updated inter-network clock synchronization topology further comprises a clock injection node of the second network and a second edge network device with clock synchronization capability in the first network, the processor It is further configured to determine a clock injection node of the first network based on the updated inter-network clock synchronization topology.

  Apart from this, in any one of the seventh aspect, the eighth aspect and the ninth aspect, the first network element is a first edge network device in the first network.

  Apart from this, in any one of the seventh aspect, the eighth aspect and the ninth aspect, the clock synchronization capability information of the first network element has clock synchronization capability in the first network element. Contains information about at least one port.

According to the tenth aspect,
Receiving a first packet from a path computation device in the first network, the first packet being used to request to determine a clock injection node of the first network;
Determining a first edge network device in the first network as a first clock injection node of the first network based on the inter-network clock synchronization topology, wherein the inter-network clock synchronization topology is the first edge Comprising a network device and a second clock injection node of a second network, the second network being an upstream network of the first network,
Determining a clock synchronization path from the second clock injection node to the first clock injection node. A method of determining a clock synchronization path is provided.

  A clock injection node and a clock synchronization path of the clock injection node for acquiring a clock signal are automatically determined for the first network using an inter-network clock synchronization topology. In this way, the cost and complexity of deploying clock synchronization paths is reduced.

  According to an eleventh aspect, there is provided an inter-network path calculation device including a receiver and a determiner.

  The receiver unit is configured to receive the first packet from a path computing device in the first network. The first packet is used to request to determine the clock injection node of the first network.

  The determination unit is configured to determine a first edge network device in the first network as a first clock injection node of the first network based on an inter-network clock synchronization topology. The inter-network clock synchronization topology includes a first edge network device and a second clock injection node of a second network, the second network being an upstream network of the first network.

  The determination unit is further configured to determine a clock synchronization path from the second clock injection node to the first clock injection node.

According to a twelfth aspect, there is provided an inter-network path computing device comprising a network interface, a memory and a processor. The processor is
An operation of receiving a first packet from a route computing device in a first network using a network interface, the first packet being used to request to determine a clock injection node of the first network , And
An operation of determining a first edge network device in a first network as a first clock injection node of a first network based on an inter-network clock synchronization topology, wherein the inter-network clock synchronization topology is a first edge Operation comprising a network device and a second clock injection node of a second network, the second network being an upstream network of the first network;
An operation of determining a clock synchronization path from the second clock injection node to the first clock injection node is configured to read a program in the memory.

  Apart from this, in the tenth aspect, the eleventh aspect and the twelfth aspect, the first packet further includes an identifier of the third clock injection node of the first network, and the third clock injection node and The first clock injection node is a different edge network device. The identifier of the third clock injection node carried in the first packet can be used to automatically determine for the first network a clock injection node different from the third clock node. Thus, if the third clock injection node can not meet the requirements of the first network for acquisition of clock signals, then a new clock injection node for the first network is rapidly acquired, whereby the clock signal The impact of degraded services on transmission is reduced.

  Apart from this, in any one of the first to twelfth aspects, the first packet is a Path Computation Element Protocol PCEP packet. If the information in the first packet is carried using PCEP packets, the devices in the network do not need to jointly deploy and define a new communication protocol for information exchange. Thus, the cost of implementing this solution is reduced.

It is the schematic of the application assumption example which concerns on embodiment of this application. FIG. 7 is a schematic view of another application scenario according to an embodiment of the present application. 5 is a flowchart of a method of updating a clock synchronization topology according to an embodiment of the present application. 3 is a flow chart of a method of determining a clock synchronization path according to an embodiment of the present application. 3 is a flowchart of a method of updating an inter-network clock synchronization topology according to an embodiment of the present application. 7 is a flowchart of another method of determining a clock synchronization path according to an embodiment of the present application. It is a schematic block diagram of the path | route calculation device which concerns on embodiment of this application. It is a schematic block diagram of another path | route calculation device based on embodiment of this application. FIG. 7 is a schematic block diagram of still another path calculation device according to an embodiment of the present application. FIG. 7 is a schematic block diagram of still another path calculation device according to an embodiment of the present application. 1 is a schematic configuration diagram of an inter-network route calculation device according to an embodiment of the present application. It is a schematic block diagram of another inter-network route calculation device concerning an embodiment of this application. FIG. 7 is a schematic block diagram of another inter-network route calculation device according to an embodiment of the present application. FIG. 7 is a schematic block diagram of another inter-network route calculation device according to an embodiment of the present application.

  In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clarified with reference to the accompanying drawings of the embodiments of the present invention as follows. And fully explained. It is obvious that the described embodiments are part of the embodiments of the present invention and not all.

In the present application, the "network element" may be a network device. For example, “network element” may be a router, a switch, an optical transport network (English name: optical transport network, OTN for short) device,
It may be a transport network (English name: packet transport network, abbreviated as PTN) device, wavelength division multiplexing (English name: wavelength division multiplexing, abbreviated as WDM) device or server. The "node" may be a network device. For example, a "node" may be a router, switch, OTN device, PTN device, WDM device or server.

  In the present application, the “connection” relationship between devices or nodes may be replaced by a “coupling” relationship or a “communication” relationship.

  In the present application, a clock signal transmitted by the first network device is received by the second network device through one or more network devices, and a path of the clock signal transmitted by the first network device to the second network device is It is called a clock synchronization path from one network device to a second network device.

  When there are two adjacent network devices on the clock synchronization path, the network device sending the clock signal is referred to as a previous hop clock synchronization path node, and the network device receiving the clock signal is referred to as a next hop clock synchronization path node.

  In the present application, the clock synchronization topology of the network includes a plurality of network devices having clock synchronization capability in the network, and a port having a clock synchronization capability, which is a port of a plurality of network devices having clock synchronization capability. And a connection relationship of a plurality of network devices which have clock synchronization capability and are connected to each other using a port having clock synchronization capability. The connection between ports may be a physical connection or a logical connection.

  FIG. 1 is a schematic view of a possible application scenario according to an embodiment of the present application. Network 100 includes network device 101, network device 102, network device 103, network device 104, network device 105, and network device 106. The network devices may be routers, network switches, firewalls, wavelength division multiplexing devices, packet transport network devices, base stations, base station controllers, data centers, etc. The network 100 may be a carrier network, in particular a mobile backbone network using wireless communication. Network 100 may be a network domain that includes several network devices in a carrier network. For example, the network 100 may be an autonomous system (English name: autonomous system, abbreviated as AS) formed in accordance with Border Gateway Protocol (English name: Border Gateway Protocol, abbreviated as BGP). Alternatively, the network 100 may be a network domain obtained by the division performed by the network manager based on the network topology configuration. For example, network 100 may be an access ring, aggregation ring or core ring.

  Some network devices of the network 100 need to obtain clock signals from the clock source to perform clock synchronization with the clock source. For example, network device 106 is a base station and it is necessary to perform clock synchronization between the clock source and the base station to perform clock synchronization with the base station. In the process where the user is handed over from the first base station to the second base station, if the clock of the first base station is not synchronized with the clock of the second base station, the user may drop call or drop There may be an anomaly such as one-way audio. Thus, the base stations of the carrier network, including base station 106, need to obtain clock signals from the same clock source or synchronous clock source to perform clock synchronization.

  In the network 100, a base station 106 is connected to a network device 105. Thus, the base station 106 needs to indirectly obtain the clock signal from the clock source using the network device 105, and at least one clock synchronization path needs to be deployed from the clock source to the network device 105. The clock synchronization path from the clock source to the network device 105 may include one or more intermediate network devices. Instead of this, the clock source may be connected directly to the network device 105. Of course, the base station 106 may be connected directly to the clock source instead.

  The network device 101 in the network 100 of FIG. 1 is connected to a clock source 120 and obtains a clock signal from the clock source 120. The clock source may be referred to as a time source. For example, clock source 120 may be a building integrated timing supply (English name: BITS for short) device. Clock source 120 may be located within network 100 or outside network 100. Of course, the network 100 may not have a network device connected to the clock source 120, and the network devices in the network 100 obtain clock signals from network devices in another network.

  In this application, in a network, the first network device that obtains a clock signal from a clock source or a network device of another network is referred to as a clock injection node of the network. For example, assuming that network device 101 is a network device in network 100, network device 101 is the first network node that is in network 100 and obtains clock signals from clock source 120. Therefore, the network device 101 is referred to as a clock injection node of the network 100. Of course, the network device 101 may be used as a clock injection node and connected directly to the clock source, or alternatively, the network device 101 may be connected to an edge device in another network to obtain clock signals from the edge network device It is also good. For a specific example, refer to the description of FIG.

  A network device not directly connected to a clock source in the network may obtain the clock signal directly from the clock injection node of the network or may obtain it indirectly. It should be noted that there may be more than one clock injection node of the network.

  When there are multiple clock injection nodes in the network, multiple clock injection nodes may obtain clock signals from the same clock source or synchronous clock source. The plurality of clock injection nodes include one primary clock injection node and one or more secondary clock injection nodes. When the primary clock injection node fails, the secondary clock injection node provides clock signals to network devices in the network. Alternatively, multiple clock injection nodes may be synchronized with one another to provide clock signals to network devices in the network. For network devices that need to obtain a clock signal from a clock injection node, the network device may receive a clock signal from one of the multiple clock injection nodes, or the network device may be multiple from the multiple clock injection nodes And select a clock signal having a relatively high priority based on a preset priority of the network device to generate a local system clock of the network device. For example, a clock signal having a relatively high priority may be a clock signal transmitted from a clock injection node to a network device with only a relatively small number of hops.

  For ease of explanation, the embodiments of the present application mainly describe an example in which there is one clock injection node in the network. One skilled in the art may consider that the method of the present application may be applied to the case where there are multiple clock injection nodes.

  There may be one or more clock synchronization paths from a clock injection node of network 100 to a network device (eg, network device 105). When having a plurality of clock synchronization paths, the plurality of clock synchronization paths may include one primary clock synchronization path and one or more secondary clock synchronization paths. When there is a failure in the primary clock synchronization path, the clock signal is sent to the network device 105 on the secondary clock synchronization path. Alternatively, clock signals may be sent simultaneously to the network device 105 on multiple clock synchronization paths, and the network device 105 selects the clock signal on one of the paths according to the policy set in the device. Then, the local system clock of the network device 105 is generated. The preset policy may be a policy that generates a local system clock of the network device by selecting a clock signal having a relatively high priority based on the priority preset in the network device. For example, a clock signal having a relatively high priority may be a clock signal transmitted from a clock injection node to a network device with only a relatively small number of hops.

  The path computing device 110 is configured to calculate a clock synchronization path for each network device in the network 100 that needs to perform clock synchronization. The path computing device 110 may be located within the network 100 or outside the network 100. For example, the path computing device may be an independent physical device such as a server. Alternatively, the path computing device may be a functional module of a network device in the network 100. The route computing device may be located within the network or outside the network. For example, path computing device 110 communicates with network devices in network 100 using pre-established connections. The route computing device 110 receives clock synchronization capability information sent by the network device, receives a clock synchronization route calculation request sent by the network device, and sends information on the clock synchronization route calculated for the network device to the network device. Are configured to In one example, after each network device accesses the network 100, a connection is established between each network device in the network 100 and the route computing device 110. In another possible example, a connection is established only between the path computing device 110 and a network device in the network 100 with clock synchronization capability.

  For example, a connection is established between the route computing device 110 in the network 100 and each of the network devices 101, 102, 103, 104 and 105. The connection may be established by a Path Computation Element Communication Protocol (abbreviated as PCEP). For example, the path calculation device 110 may be a path calculation element (English name: Path Computation Element, abbreviated as PCE) in a PCEP model. Each of the network devices 101, 102, 103, 104 and 105 may be a path computation client (English name: Path Computation Client, abbreviated as PCC) in a PCEP model. For PCE and PCC network architectures, reference is made to the Request for Comments (RF) 4655 from the Internet Engineering Task Force.

  For example, synchronous Ethernet technology may be used to obtain the clock signal and generate the local system clock of the network device. The next hop clock synchronization node extracts a clock signal from the physical layer serial codestream sent by the previous hop clock synchronization node to generate a system clock of the next hop clock synchronization node. For example, a phase locked loop (English name: phase locked loop, PLL for short) is incorporated in the interface circuit of the next hop clock sync node, and a clock signal sent by the previous hop clock sync node is used as an input signal of the phase locked loop. Generate a system clock whose frequency is the same as the frequency of the clock signal sent by the previous hop clock synchronization node.

  For example, instead of this, the method of acquiring the clock signal and generating the local system clock generates the system clock based on the steps of acquiring a timestamp from the packet sent by the previous hop clock synchronization node and the timestamp And step may be included. For a particular implementation that generates a system clock based on a timestamp, a precision time protocol (English name: PTP for short), for example, Institute of Electrical and Electronics Engineers (English Name: Institute of Electrical and Technology) See Electronics Engineers, abbreviated IEEE) 1588.

  In a solution that performs clock synchronization using a phase synchronization circuit, the network device obtains a clock signal from the network device's previous hop clock synchronization node, and then checks the local system clock of the network device based on the clock signal. One skilled in the art may consider it understood that clock signals generated by the network device's local system clock are sent to the network device's next hop clock synchronization node. In a solution that performs clock synchronization based on timestamps, the network device checks the local system clock of the network device based on the timestamp sent by the previous hop clock synchronization node and then uses the local system clock of the network device A new timestamp may be generated to send the new timestamp to the next hop clock synchronization node of the network device, or the network device carries the timestamp and a packet sent by the network device's previous hop clock synchronization node May be transmitted transparently directly to the next hop clock synchronization node of the network device. That is, the clock signal sent by the network device to the next hop clock synchronization node may be transmitted transparently directly without being processed by the network device, or it may be the local system clock of the network device and obtained after clock synchronization. May be generated by the local system clock.

  FIG. 2 is a schematic view of another application scenario according to an embodiment of the present application. Network 100 and network 200 are two network domains in the network. The network 100 may be a carrier network or a part of a carrier network, and the network 100 may be a company network or a part of a company network. The network 200 may be a carrier network or a part of a carrier network, and the network 200 may be a company network or a part of a company network. Network 100 and network 200 may both be network domains in a carrier network. Alternatively, network 100 and network 200 may be network domains in a carrier network and network domains in a corporate network, respectively. Network 100 and network 200 may both be network domains in a corporate network. For example, the network 100 and the network 200 may be two autonomous systems (English name: AS), which are formed according to Border Gateway Protocol (English name: Border Gateway Protocol, abbreviated as BGP). There may be two network domains obtained by the division performed by the network manager based on the topology configuration. The path computation device 110 calculates a clock synchronization path for the network devices in the network 100 based on the clock synchronization capability and clock synchronization request of each network device in the network 100. The path computation device 210 calculates a clock synchronization path for the network devices in the network 200 based on the clock synchronization capability of each network device in the network 200 and the clock synchronization request. For example, the network 100 of FIG. 2 may be the network 100 shown in FIG.

  The path computing device 110 may be located within the network 100 or outside the network 100. Path computing device 210 may be located within network 200 or outside network 200.

  Path computing device 110 and path computing device 210 communicate separately with inter-network path computing device 230. The inter-network path computing device 230 may be an independent physical device such as a server. Alternatively, the inter-network path calculation device 230 may be a functional module of the network device. The inter-network path computing device 230 may be located within the network 100 or the network 200, or the inter-network path computing device 230 may be located outside the network 100 and the network 200. The inter-network path calculation device 230 is configured to determine a clock injection node for each network, and the clock injection node is configured to obtain a clock synchronization path of the clock signal.

  Similar to FIG. 1, the first network device that obtains a clock signal from a clock source or a network device of another network is referred to as a clock injection node of the network. For example, assuming that network device 101 is a network device in network 100, network device 101 obtains clock information from network device 203 in network 200. Network device 101 is the first network node that is in network 100 and obtains clock signals from devices in network 200, and thus, network device 101 is referred to as a clock injection node of network 100. Of course, one skilled in the art will understand that one edge network device may be located in multiple networks and used as at least one clock injection node of multiple networks providing clock signals to at least one network. You can think of it.

  It is assumed that there are no clock sources or devices directly connected to the clock sources in the network 100. Before computing clock synchronization paths for network devices in network 100, path computing device 110 first requests inter-network path computing device 230 to determine a clock injection node for network 100, and then network 100. It is necessary to calculate a clock synchronization path from a clock injection node of network 100 to another network device in network 100 based on the clock synchronization topology of

  The inter-network path computing device 230 may store the clock synchronization topology of network devices in multiple networks. For example, the inter-network route calculation device 230 stores the clock synchronization topology of network devices in the network 100 and the clock synchronization topology of network devices in the network 200. The clock synchronization topology of the network devices in the network 100 and the clock synchronization topology of the network devices in the network 200 may be pre-stored in the inter-network route calculation device 230, or by the route calculation device 110 and the route calculation device 210 respectively. It may be sent to the inter-network route calculation device 230. Apart from this, the inter-network path calculation device 230 is an edge network device having clock synchronization capability in the network 100 and the network 200, a port of the edge network device, having a clock synchronization capability, and clock synchronization capability. The connection relationship between edge network devices connected using ports having may be stored.

  FIG. 3 is a flowchart of a method of updating a clock synchronization topology according to an embodiment of the present application. For example, the method may be applied to the network 100 shown in FIG. 1, and may be applied to the network 100 shown in FIG. 2 or to the network 200 shown in FIG. You may An example in which the method is applied to the network 100 shown in FIG. 1 will be used for the description. For example, the first network element of FIG. 3 may be the network device 105 shown in FIG. 1, and the clock injection node of the first network of FIG. 3 is the network device 101 shown in FIG. It may be.

  The method for updating the clock synchronization topology of the network provided in FIG. 3 includes S301 and S302. For example, S301 and S302 may be performed by the path computing device 110 shown in FIG.

  S301. Receiving a first packet from a first network element, the first packet including clock synchronization capability information of the first network element, the first network element being a network element in the first network; Network elements have clock synchronization capabilities.

  In this application, the clock synchronization capability information of the network element may include a clock synchronization protocol supported by the network element. Alternatively, clock synchronization capability information of the network element may further include information on ports of the network element and clock synchronization protocols supported by each port of the network element.

  Apart from this, the clock synchronization capability information of the first network element comprises information on at least one port with clock synchronization capability in the first network element.

  For example, the first network element may be the network device 105 shown in FIG. 1, where the network device 105 includes port A, port B and port C. The network device 105 communicates with the network device 102 using port A, communicates with the network device 104 using port B, and communicates with the network device 103 using port C. The information carried in the first packet includes that the network device 105 has clock synchronization capability, that port A and port B have clock synchronization capability, and that port C has no clock synchronization capability. . One skilled in the art may consider that the first packet may only indicate that port A and port B have clock synchronization capability. The first network element comprises at least one port with clock synchronization capability. In other words, the first network element has clock synchronization capability.

  For example, the first packet may only carry index information indicating that the first network element has clock synchronization capability and does not carry port synchronization capability information. After receiving the first packet, path computation device 110 determines all ports in the first network element that have clock synchronization capabilities.

  Apart from this, the first packet is the Path Computation Element Communication Protocol PCEP packet, and the clock synchronization capability information is carried in the PCEP packet.

  S302. The clock synchronization topology of the first network is updated based on the clock synchronization capability information of the first network element.

  For example, the clock synchronization topology of the first network is stored in the memory of the path computing device 110 shown in FIG.

  In a possible example, the path computing device 110 does not obtain clock synchronization capability information of the first network element prior to S301, so the clock synchronization topology of the first network before updating includes the first network element Absent. For example, the first network element is a network device newly added to the network 100, and the first packet is transmitted to the first network element after establishing a connection between the first network element and the path computing device 110. A packet sent when a network element reports clock synchronization capability information. In the updated clock synchronization topology, path computing device 110 includes a first network element, a port with clock synchronization capability in the first network element, and a port with clock synchronization capability in the first network element. Add a connection with a port having clock synchronization capability in another network device having clock synchronization capability.

  In another possible example, the path computing device 110 may be configured to update the first network element and a number of ports with clock synchronization capabilities in the first network element to the clock synchronization topology of the first network before updating. to add. In the first network element, some ports that originally have clock synchronization capability lose clock synchronization capability due to some port failure, and some ports that do not originally have clock synchronization capability because of service request. In order to enable the clock synchronization function, the first network element sends the first packet to the path computation device 110. The path computation device 110 adjusts the clock synchronization topology of the first network based on whether the first network element has clock synchronization capability. For example, the path computing device 110 may remove a port in the first network element that will no longer have clock synchronization capability and the connection relationship with that port from the clock synchronization topology of the first network, or may synchronize the clock. The clock synchronization function is enabled in the first network element, and the port having the connection relationship with the port is added to the clock synchronization topology of the first network, although it has no function originally.

  In another possible example, the path computing device 110 may be configured to update the first network element and a number of ports with clock synchronization capabilities in the first network element to the clock synchronization topology of the first network before updating. to add. For example, a port that originally has clock synchronization capability in the first network element may lose clock synchronization capability for some reason, or a port that originally has clock synchronization capability may have clock synchronization capability for service requests. When invalidating, the first network element sends the first packet to the route computing device 110. The path computation device 110 adjusts the clock synchronization topology of the first network based on whether the first network element has clock synchronization capability. For example, the path computation device 110 removes the first network element from the clock synchronization topology of the first network.

  One skilled in the art may consider that there is a further need for the path computing device to obtain topology information of the first network based on clock synchronization capability information of the first network element to update the clock synchronization topology. For example, if the clock synchronization topology is one that includes physical links, there is a further need for the path computing device to obtain physical topology information of the first network. Physical topology information includes the physical port of the first network element and the connection between this physical port and another physical port of another network device. For example, if the clock synchronization topology is a topology that includes logical links, the path computing device further needs to obtain logical topology information of the first network. The logical topology includes the logical port of the first network element and the relationship between the logical links established between the logical port and another network device. The topology information of the first network element may be pre-stored in the path computing device or may be sent to the path computing device by the first network element. When the topology information of the first network element is sent by the first network element to the route computing device, the topology information may be carried in the first packet or in another packet.

  Apart from this, the updated clock synchronization topology comprises a clock injection node of the first network and the method comprises a clock synchronization path from the clock injection node to the first network element based on the updated clock synchronization topology Further includes step S303 of determining. For example, S303 may be performed by the route computing device 110 in the network 100.

  For example, the path computing device determines a computation policy of the clock synchronization path from the clock injection node to the first network element based on the updated clock synchronization topology. The calculation policy may be pre-stored in the route computing device, may be sent to the route computing device by the first network element, or may be sent to the route computing device by the controller. The controller may be the inter-network path computing device of FIG.

  For example, the route calculation policy is a point-to-multipoint (English name: point to multipoint, abbreviated as P2MP) multiprotocol label switching (English name: multi-protocol label switching, abbreviated as MPLS) traffic engineering label -Route calculation policy of traffic engineering label switched paths (abbreviated TE LSP) may be used, or general purpose multi-protocol label switching (English name: generalized multi-protocol label switching, abbreviated GMPLS) It may be a route calculation policy of traffic engineering label switched path (abbreviated TE LSP). For example, the route calculation device 110 uses a clock injection node of the network 100 such as the network device 101 as an ingress node of the TE LSP, and a first such as the network device 105 as an egress node of the TE LSP. Perform route calculations using network elements. Refer to RFC 6006 for the specific route calculation method.

  For example, the path calculation policy may be to obtain the shortest path from the clock injection node to the first network element. For example, if each of the network devices 101, 102, 103, 104 and 105 in FIG. 1 includes a port with clock synchronization capability, the path, network device 101 in FIG. 1 → network device 102 → network device 105 is the shortest path. is there. Thus, the path computing device determines that the previous hop clock synchronization node of network device 105 is network device 102, and network device 105 uses port A to obtain a clock signal from network device 102.

  For example, after determining the clock synchronization path from the clock injection node to the first network element, the path computing device sends the first indication information to the first network element. The first indication information is used to instruct the first network element to obtain a clock signal from a previous hop clock synchronization node of the first network element on the clock synchronization path. Alternatively, the path computation device may further send the second indication information to the previous hop clock synchronization node of the first network element on the clock synchronization path. The second indication information is used to indicate to the previous hop clock synchronization node of the first network element on the clock synchronization path to send a clock signal to the first network element.

  FIG. 4 is a flow chart of a method of determining a clock synchronization path according to an embodiment of the present application. For example, the method of FIG. 4 may be applied to the network 100 shown in FIG. 1, and may be applied to the network 100 shown in FIG. 2 or the network shown in FIG. It may be applied to 200. An example in which the method is applied to the network 100 shown in FIG. 1 will be used for the description. The first network element of FIG. 4 may be the network device 105 of FIG. The steps of FIG. 4 may be performed by the path computing device 110 shown in FIG. The method includes S401 and S402.

  S401. A first packet is used to receive a first packet from a first network element and request to determine a clock synchronization path for the first network element, the first network element being a first network element The first network element has clock synchronization capability.

  For example, the first packet is a Path Computation Element Protocol PCEP packet.

  S402. A first clock synchronization path from the clock injection node of the first network to the first network element is determined based on the clock synchronization topology of the first network, the clock synchronization topology of the first network being the clock injection node and And a first network element.

  In particular, the clock synchronization topology of the first network is a plurality of network devices having clock synchronization capability and a port having clock synchronization capability in the first network, wherein the ports of the plurality of network devices having clock synchronization capability And a connection relationship of a plurality of network devices connected to each other by using the port having clock synchronization ability and having the clock synchronization ability.

  For example, the clock synchronization topology of the first network may be pre-stored in the path calculation device 110, or from a network device having clock synchronization capability in the network 100, the clock synchronization capability information may be It may be generated after the route calculation device 110 has acquired it.

  The first network element has clock synchronization capability, so the clock synchronization topology of the first network comprises the first network element. The clock synchronization topology of the first network further includes a clock injection node of the first network.

  The path calculation policy for determining the first clock synchronization path from the clock injection node of the first network to the first network element may be the same as the path calculation policy in S304 of FIG.

  In a possible example, the first network element may request the path computation device 110 to calculate a clock synchronization path for the first network element without any clock synchronization path prior to S401. Packets are used.

  In another possible example, the first network element is on a second clock synchronization path from the clock injection node of the first network to the first network element prior to S401 and the first network element from the clock injection node The first packet is further used to indicate that the second clock synchronization path to the network element is faulty. For example, the clock injection node on the second clock synchronization path is the network device 101, and the network device 101 sends a clock signal to the network device 102, which uses port A of the network device 105 to the network device 105. Send a clock signal.

  The failure of the second clock synchronization path is that even if the first network element detects that the second clock synchronization path can not provide the correct clock signal to the first network element. Alternatively, the first network element may detect that the local system clock signal of the first network element is degraded. In particular, the failure of the second clock synchronization path is the failure of network devices other than the first network element on the second clock synchronization path, and the failure of the link between the two network devices. And / or failure of port A of the first network element. Failure of port A of the first network element may include that port A can not properly receive the clock signal, or after port A of the first network element receives the clock signal. It may include that the substrate of A can not process the clock signal properly.

  For example, when the first packet in S401 carries information indicating that the second clock synchronization path is defective, the first clock synchronization path determined in S402 is not on the second clock synchronization path. Includes one network element. For example, based on the fact that the clock synchronization topology of the first network further includes port B of the network device 105, the path calculation device 110 determines that the first clock synchronization path is a predetermined synchronization path, ie, network device 101 → network It is determined whether the device 103 → network device 104 → port B of the network device 105.

  FIG. 5 is a flow chart of a method of updating an inter-network clock synchronization topology according to an embodiment of the present application. For example, the method may be applied to the scenario shown in FIG. For example, the steps of the method of FIG. 5 may be performed by the inter-network path computing device 230 shown in FIG. The path computing device in the first network in the method of FIG. 5 may be the path computing device 110 shown in FIG. 2 and the first edge network device network element of FIG. 5 is the network device 101 of FIG. It may be The method includes S501 and S502.

  S501. A first packet is received from a path computing device in a first network, the first packet including clock synchronization capability information of a first network element in the first network.

  For example, the particular type of clock synchronization capability information of the first network element may be the same as the particular type of synchronization capability information of the first network element of S301 of FIG. For example, the clock synchronization capability information of the first network element includes information on at least one port in the first network element having clock synchronization capability.

  Apart from this, the first packet is a Path Computation Element Protocol PCEP packet.

  In a possible example, the first network element is a first edge network device in a first network. For example, the path computing device 110 only sends the clock synchronization capability information of the edge network devices in the first network to the inter-network route computing device 230 and does not send the clock synchronization capability information of the network devices in the network.

  In another possible example, the first network element may be any network device in the first network. For example, the route computing device 110 sends to the inter-network route computing device 230 clock synchronization capability information of all network devices in the first network or all network devices with clock synchronization capability.

  S502. The inter-network clock synchronization topology is updated based on the clock synchronization capability information of the first network element.

  For example, the inter-network clock synchronization topology may be stored in the inter-network path calculation device 230 shown in FIG.

  In a possible example, the inter-network clock synchronization topology is an edge network device with clock synchronization capability and a port with clock synchronization capability in each of a plurality of networks, with the edge network device port with clock synchronization capability. It includes a certain port and a connection between edge network devices connected to each other by using a port having clock synchronization capability and having clock synchronization capability.

  In another possible example, the inter-network clock synchronization topology is a clock synchronization topology of each of the plurality of networks, an edge network device with clock synchronization capability in each of the plurality of networks, and a port with clock synchronization capability. A port is a port of an edge network device having clock synchronization capability, and a connection between edge network devices having clock synchronization capability and connected to each other using the port having clock synchronization capability.

  In a possible example, the inter-network path calculation device 230 does not obtain the clock synchronization capability information of any network device in the first network before S501, so the inter-network clock topology before updating is the first network Does not include the clock synchronization topology of

  In another possible example, the pre-update inter-network clock synchronization topology includes network devices in the first network or only edge network devices in the first network. Since the clock synchronization capability information of the first network element is changed, the path computing device in the first network sends the first packet of S501.

  One skilled in the art may consider that there is a further need for the path computing device to obtain topology information of the first network based on clock synchronization capability information of the first network element to update the clock synchronization topology. For example, if the clock synchronization topology is one that includes physical links, there is a further need for the path computing device to obtain physical topology information of the first network. Physical topology information includes the physical port of the first network element and the connection between this physical port and another physical port of another network device. For example, if the clock synchronization topology is a topology that includes logical links, the path computing device further needs to obtain logical topology information of the first network. The logical topology includes the logical port of the first network element and the relationship between the logical links established between the logical port and another network device. The topology information of the first network element may be pre-stored in the path computing device or may be sent to the path computing device by the first network element. When the topology information of the first network element is sent by the first network element to the route computing device, the topology information may be carried in the first packet or in another packet.

  Alternatively, the updated inter-network clock synchronization topology further includes a clock injection node of the second network and a second edge network device with clock synchronization capability in the first network, the method comprising The method further includes determining 503 a clock injection node of the first network based on the updated inter-network clock synchronization topology.

  Alternatively, the clock injection node of the first network may be a second edge network device or another edge network device in the first network. Alternatively, if the clock injection node of the second network is an edge network device located in the first network and the second network, the clock injection node of the first network is the clock injection node of the second network. It is.

  For example, the first network element may be the same network device as the second edge network device or may be a different network device than the second edge network device.

  For example, the second network is the network 200 of FIG. 2 and the first network is the network 100 of FIG. The second edge network device is network device 101, and the third edge network device is network device 203. The particular implementation in which the inter-network path calculation device 230 determines whether the network device 101 is a clock injection node of the first network may be the particular implementation of FIG.

  FIG. 6 is a flowchart of another method of determining a clock synchronization path according to an embodiment of the present application. For example, the method shown in FIG. 6 may be applied to the hypothetical example shown in FIG. The method includes S601, S602 and S603. The method steps may be performed by the inter-network route computing device 230 of FIG.

  S601. The first packet is used to receive a first packet from a path computation device in the first network and request to determine a clock injection node of the first network.

  For example, the first network may be the network 100 of FIG. 2 and the path computing device of the first network may be the path computing device 110. Suppose that there is no clock source in the network 100. An inter-network path such that path computing device 110 in the first network sends a first packet to inter-network path computing device 230 and determines a clock injection node for the first network based on an inter-network clock synchronization topology It requests the computing device 230. The clock injection node of the first network needs to obtain the clock signal from a network device outside the first network.

  For example, the first packet is a Path Computation Element Protocol PCEP packet.

  S602. The first edge network device in the first network is determined as the first clock injection node of the first network based on the inter-network clock synchronization topology, and the inter-network clock synchronization topology is determined with the first edge network device and the first edge network device And a second clock injection node of the two networks.

  In particular, the second network is a network upstream of the first network. A clock injection node of the first network obtains a clock signal from a network device with clock synchronization capability in the second network.

  In this application example, if the clock injection node of the network (e.g. network 1) gets the clock signal from a network device in another network (e.g. network 2), network 1 is referred to as the network downstream of network 2 The network 2 is referred to as an upstream network of the network 1.

  For example, when determining the clock injection node for each network, the inter-network path calculation device 230 first calculates the clock injection node of the upstream network and then calculates the clock injection node of the downstream network. In one example, the upstream / downstream relationship between networks is preset by the network manager in the inter-network route calculation device 230. In another example, the upstream / downstream relationship of the network is calculated by the inter-network path computing device 230 using the same method of computing the clock synchronization path of the network device. In the method, each network is used as a node, a network with a clock source is used as a clock injection node, and two networks with interconnected edge network devices are used as interconnected nodes.

  In a possible example, the inter-network clock synchronization topology is an edge network device with clock synchronization capability and a port with clock synchronization capability in each of a plurality of networks, with the edge network device port with clock synchronization capability. It includes a certain port and a connection between edge network devices connected to each other by using a port having clock synchronization capability and having clock synchronization capability. The plurality of networks include a first network and a second network.

  In another possible example, the inter-network clock synchronization topology is a clock synchronization topology of each of the plurality of networks, an edge network device with clock synchronization capability in each of the plurality of networks, and a port with clock synchronization capability. A port is a port of an edge network device having clock synchronization capability, and a connection between edge network devices having clock synchronization capability and connected to each other using the port having clock synchronization capability. The plurality of networks include a first network and a second network.

  For example, the inter-network clock synchronization topology may further include a clock source. The clock source may be located in the second network or may be located outside the first network and the second network. The clock injection node of the second network may be determined by the inter-network path calculation device and may be recorded in the inter-network clock synchronization topology prior to S602.

  S603. A clock synchronization path is determined from the second clock injection node to the first clock injection node.

  In a possible example, as described in S602, the inter-network clock synchronization topology includes only the clock topology of edge network devices in the first network and the second network. For example, in the application scenario of FIG. 2, the inter-network clock synchronization topology includes clock injection nodes of network 200, ie, network device 201, and edge network device 202 and edge network device 203 in network 200. The inter-network clock synchronization topology further includes edge devices in network 100, eg, network device 101 and network device 102. In the inter-network synchronization topology, network device 101 is connected to network device 203 and network device 102 is connected to network device 202.

  In this example, it is assumed that the inter-network clock synchronization topology does not include network devices inside the network. Therefore, the inter-network route calculation device 230 can not directly determine the clock synchronization route from the clock injection node of the network 200 to the edge network device 202 or the edge network device 203. Accordingly, the inter-network route calculation device 230 sends an inquiry packet to the route calculation device 210 to determine a clock synchronization route from the network device 201 to the network device 202 or a clock synchronization route from the network device 201 to the network device 203. If the route calculation device 210 determines that there is a clock synchronization route from the network device 201 to the network device 202 and there is a clock synchronization route from the network device 201 to the network device 203, the inter-network route calculation device 230 determines the network 100. The network device 101 or the network device 102 may be selected as a clock injection node of Apart from this, the inter-network path computing device 230 selects, from the network device 101 and the network device 102, a network device having a relatively small number of hops up to the network device 201 as a clock injection node of the network 100. If there is no clock synchronization path from the network device 201 to the network device 202 and the path calculation device 210 determines that there is a clock synchronization path from the network device 201 to the network device 203, the inter-network path calculation device 230 A network device 101 connected to the network device 203 as a clock injection node 100 is determined.

  For example, the clock synchronization path determined by the inter-network path calculation device 230 for the first clock injection node (network 101) of the network 100 is the clock synchronization path from the network device 201 to the network device 203; And a clock synchronization path from the network device 101. The two clock synchronization paths are both calculated by the path computing device 210.

  For example, path computing device 210 may report a particular network device on the clock synchronization path from network device 201 to network device 203 to inter-network path computing device 230, which may The clock synchronization path to the device 203 and the identifier of the clock synchronization path may be stored, and only the identifier of the clock synchronization path may be sent to the inter-network route calculation device 230.

  In another example, as described in S602, the inter-network clock synchronization topology includes clock topologies of edge network devices in the first network and the second network, and in the first network and the second network. Further includes the clock topology of the non-edge network device of The inter-network path computing device implements S602 and S603 based on the inter-network clock synchronization topology in a manner similar to that used by the inter-network path computing device 230 and the path computing device 210 in the previous example.

  One skilled in the art may consider that S602 and S603 may be performed simultaneously.

  For example, after determining the first edge network device as a clock injection node of the first network, the inter-network path computing device sends the first indication information to the first path computing device. The first indication information is used to indicate to the path calculation device in the first network to use the first edge network device as the first clock injection node of the first network, the first indication information May further comprise an identifier of the network device of the previous hop clock synchronization path node of the first edge network device. Thereafter, the path computation device in the first network sends the second indication information to the first edge network device. The second indication information is used to instruct the first edge network device to obtain a clock signal from the previous hop clock synchronization path node.

  Apart from this, the first packet further comprises an identifier of the third clock injection node of the first network, the third clock injection node and the first clock injection node being different edge network devices. In particular, the first packet of S601 instructs the inter-network route computing device to determine an edge network device different from the third clock injection node for the first network as a clock injection node of the first network It is further used to

  In a possible example, the path computation device of the first network receives alarm information reported by a node downstream of the third clock injection node and the third clock injection for another network device in the first network It determines that the performance of the clock signal provided by the node has degraded or that the third clock injection node can not provide the correct clock signal for another network device, and sends the first packet to Request to redetermine the clock injection node of one network.

  In another possible example, the path calculation device in the first network receives alarm information reported by the third clock injection node, and the third clock injection node synchronizes with the third clock injection node before hop clock. It is determined that the performance of the clock signal received from the node is degraded or abnormal, and the first packet is sent to request to redetermine the clock injection node of the first network.

  In yet another possible example, the network device on the clock synchronization path and in the first network detects that the previous hop clock synchronization node of the network device is faulty and the path in the first network is Request the computing device to recalculate the synchronization path. The path computing device in the first network uses the third clock injection node to determine whether recalculation can not acquire a new synchronization path or determines whether the new synchronization path has excessive hops. Do. Thus, the path computation device of the first network sends the first packet to the inter-network path computation device to redetermine the clock injection node of the first network, or to make the new clock injection node into the first network. Request to add. For example, network device 102 is a third clock injection node, and network device 105 obtains a clock signal from port A. There is a problem with port A of the network device 105. Path computation device 110 is required to recompute clock synchronization paths for network device 105. When the network device 102 is used as a clock injection node, the path calculation device 110 may be another possible clock synchronization path, in particular the clock synchronization network device 102 → network device 101 → network device 103 → network device 104 → network device 105. It determines if the path contains excessive hops and sends the first packet to the inter-network path computing device 230. The inter-network route calculation device 230 changes the clock injection node of the network 100 to the network device 101.

  FIG. 7 is a schematic block diagram of a route calculation device according to an embodiment of the present application. As shown in FIG. 7, the path computing device 700 includes a receiving unit 701 and an updating unit 702.

  The receiver 701 is configured to receive a first packet from a first network element. The first packet contains clock synchronization capability information of the first network element, the first network element is a network element in the first network, and the first network element has clock synchronization capability. The receiver 701 may be a network interface, for example, the network interface 801 shown in FIG.

  The update unit 702 is configured to update the clock synchronization topology of the first network based on the clock synchronization capability information of the first network element from the reception unit 701.

  Apart from this, the clock synchronization capability information of the first network element comprises information on at least one port with clock synchronization capability in the first network element.

  Apart from this, the path calculation device 700 further comprises a determination unit, which is configured to determine a clock synchronization path from the clock injection node to the first network element based on the updated clock synchronization topology. ing.

  The path calculation device 700 provided in the present embodiment may be applied to the application scenario shown in FIG. 1 or 2 to implement the functions of the path calculation device 110 or the path calculation device 210. The path computing device 700 may be configured to perform the method of the embodiment of FIG. 3 to implement the method of the embodiment of FIG. Refer to the description of the path computation device of the method embodiment of FIG. 3 for further additional functions that can be performed by the path computation device and the process of passing on another device. Details will not be described again here.

  FIG. 8 is a schematic block diagram of another path calculation device according to an embodiment of the present application. As shown in FIG. 8, the path computing device 800 includes a network interface 801, a memory 802 and a processor 803. For example, the route computing device 800 may be a separate server. Alternatively, the route computing device 800 may be a software module of the router or a hardware module of the router, and the network interface, memory and processor may be the network interface, memory and processor of the router It is.

  For example, the network interface 801 may be a wired interface, for example, a fiber distributed data interface (English name: Fiber Distributed Data Interface (abbreviated as FDDI)) or Ethernet (English name: Ethernet) interface. Alternatively, the network interface 801 may be a wireless interface, eg a wireless local area network interface.

  The memory 802 is configured to store a clock synchronization topology of the first network. The memory 802 is a random access memory (English name: random-access memory, abbreviated as RAM), a read only memory (English name: read only memory, abbreviated as ROM) and an erasable programmable read only memory (English name: erasable programmable read) Although it contains only memory (abbreviated EPROM), it is not limited thereto.

  The processor 803 may be a central processing unit (abbreviated as CPU: abbreviation), a network processor (abbreviation: network processor, abbreviated as NP), an application-specific integrated circuit (abbreviated as: ASIC) and one or more of programmable logic devices (abbreviated as PLD), but is not limited thereto. PLDs are complex programmable logic devices (English name: CPLD), field-programmable gate arrays (English name: FPGA), generic array logic (English name: English): It may be a generic array logic (abbreviated GAL) or any combination thereof.

  Memory 802 may be incorporated into processor 803. When the memory 802 and the processor 803 are independent components, the memory 802 is connected to the processor 803. For example, memory 802 and processor 803 may communicate using a bus. The network interface 801 and the processor 803 may communicate using a bus, or the network interface 801 may be directly connected to the processor 803.

Processor 803 is
Receiving the first packet from the first network element using the network interface 801, wherein the first packet includes clock synchronization capability information of the first network element, and the first network element is configured to receive the first packet; A network element in the network, the first network element having clock synchronization capability;
Updating the clock synchronization topology of the first network based on the clock synchronization topology of the first network and the clock synchronization capability information of the first network element stored in the memory 802; ing.

  Apart from this, the clock synchronization capability information of the first network element comprises information on at least one port with clock synchronization capability in the first network element.

  Alternatively, processor 803 is further configured to determine a clock synchronization path from the clock injection node to the first network element based on the updated clock synchronization topology.

  The path computation device 800 shown in FIG. 8 and the path computation device 700 shown in FIG. 7 may be the same device, for example, an implementation of the method of FIG. It can be considered that FIG. 8 shows the contents included in the path calculation device from the physical point of view, and FIG. 7 shows the contents included in the path calculation device from the logical point of view. Alternatively, the network interface 801 shown in FIG. 8 may implement the receiver 701 shown in FIG. 7 and the memory 802 and processor 803 shown in FIG. The updating unit 702 shown in FIG.

  FIG. 9 is a schematic block diagram of a route calculation device according to an embodiment of the present application. As shown in FIG. 9, the path calculation device 900 includes a receiving unit 901 and a determining unit 902.

  Receiver 901 is configured to receive a first packet from a first network element. A first packet is used to request to determine a clock synchronization path for the first network element, the first network element being a network element in the first network, and the first network element being Has clock synchronization capability.

  The determining unit 902 is configured to determine a first clock synchronization path from the clock injection node of the first network to the first network element based on the clock synchronization topology of the first network. The clock synchronization topology of the first network includes a clock injection node and a first network element.

  Alternatively, the first packet is further used to indicate that the second clock synchronization path from the clock injection node to the first network element is faulty, the second clock synchronization path being the first It includes at least one network element not on the clock synchronization path.

  The function of the route calculation device 110 may be implemented by applying the route calculation device 900 provided in the present embodiment to the application assumed example shown in FIG. 1 or 2. The path computing device 900 may be configured to perform the method of the embodiment of FIG. 4 to implement the method of the embodiment of FIG. For further additional functions that can be performed by the path computing device and the process of passing on another device, refer to the description of the path computing device of the method embodiment of FIG. Details will not be described again here.

  FIG. 10 is a schematic block diagram of another path calculation device according to an embodiment of the present application. As shown in FIG. 10, the path computing device 1000 includes a network interface 1001, a memory 1002 and a processor 1003.

  For example, the route computing device 1000 may be a separate server. Alternatively, the route computing device 1000 may be a software module of the router or a hardware module of the router, and the network interface, memory and processor may be the network interface, memory and processor of the router It is.

  For example, the network interface 1001 may be a wired interface, for example, a fiber distributed data interface (English name: Fiber Distributed Data Interface (abbreviated as FDDI)) or Ethernet (English name: Ethernet) interface. Alternatively, network interface 1001 may be a wireless interface, eg, a wireless local area network interface.

  The memory 1002 is a random access memory (English name: random-access memory, abbreviated as RAM), a read only memory (English name: read only memory, abbreviated as ROM) and an erasable programmable read only memory (English name: erasable programmable read) Although it contains only memory (abbreviated EPROM), it is not limited thereto.

  The processor 1003 includes a central processing unit (English name: central processing unit, abbreviated as CPU), a network processor (English name: network processor, abbreviated as NP), application-specific integrated circuit (English name: abbreviated) ASIC) and one or more of programmable logic devices (abbreviated as PLD), but is not limited thereto. PLDs are complex programmable logic devices (English name: CPLD), field-programmable gate arrays (English name: FPGA), generic array logic (English name: English): It may be a generic array logic (abbreviated GAL) or any combination thereof.

  Memory 1002 may be incorporated into processor 1003. When the memory 1002 and the processor 1003 are independent components, the memory 1002 is connected to the processor 1003. For example, memory 1002 and processor 1003 may communicate using a bus. The network interface 1001 and the processor 1003 may communicate using a bus, or the network interface 1001 may be directly connected to the processor 1003.

The processor 1003 is
An operation of receiving a first packet from a first network element using network interface 1001, wherein the first packet is used to request to determine a clock synchronization path for the first network element, A first network element being a network element in the first network, the first network element having clock synchronization capability;
Determining the first clock synchronization path from the clock injection node of the first network to the first network element based on the clock synchronization topology of the first network, wherein the clock synchronization topology of the first network is A program is configured to be read out of the memory 1002 for performing operations, including a clock injection node and a first network element.

  Apart from this, the first packet is further used to indicate that the second clock synchronization path from the clock injection node of the first network to the first network element is faulty, the second clock synchronization The path includes at least one network element not on the first clock synchronization path.

  The path computing device 1000 shown in FIG. 10 and the path computing device 900 shown in FIG. 9 may be the same device, eg, an implementation of the method of FIG. FIG. 10 shows the contents included in the route calculation device from the physical point of view, and FIG. 9 can be considered to show the contents included in the route calculation device from the logical point of view. Alternatively, the network interface 1001 shown in FIG. 10 may implement the receiver 901 shown in FIG. 9 and the processor 1003 shown in FIG. The determining unit 902 may be implemented.

  FIG. 11 is a schematic block diagram of an inter-network route calculation device according to an embodiment of the present application. As shown in FIG. 11, the inter-network route calculation device 1100 includes a receiving unit 1101 and an updating unit 1102.

  The receiving unit 1101 is configured to receive the first packet from the route calculation device in the first network. The first packet contains clock synchronization capability information of the first network element in the first network.

  The updating unit 1102 is configured to update the inter-network clock synchronization topology based on the clock synchronization capability information of the first network element from the receiving unit 1101.

  Apart from this, the first network element is a first edge network device in the first network.

  Alternatively, the updated inter-network clock synchronization topology further includes a clock injection node of the second network and a second edge network device with clock synchronization capability in the first network. The path computation device 1100 further includes a determination unit, which is configured to determine the clock injection node of the first network based on the updated inter-network clock synchronization topology.

  Apart from this, the clock synchronization capability information of the first network element comprises information on at least one port with clock synchronization capability in the first network element.

  The inter-network path calculation device 1100 provided in this embodiment may be applied to the application scenario shown in FIG. 2 to implement the functions of the inter-network path calculation device 230. The inter-network path computing device 1100 may be configured to perform the method of the embodiment of FIG. 5 to implement the method of the embodiment of FIG. Refer to the description of the inter-network path computing device of the method embodiment of FIG. 5 for further additional functions that may be implemented by the inter-network path computing device 1100 and the process of passing on another device. Details will not be described again here.

  FIG. 12 is a schematic block diagram of another inter-network route calculation device according to an embodiment of the present application. As shown in FIG. 12, the inter-network route calculation device 1200 includes a network interface 1201, a memory 1202 and a processor 1203.

  For example, the route computing device 1200 may be a separate server. Alternatively, the inter-network route calculation device 1400 may be a software module of the router or a hardware module of the router, and the network interface, the memory and the processor may be the network interface of the router, the memory And processor.

  The network interface 1201 may be a wired interface, for example, a fiber distributed data interface (English name: Fiber Distributed Data Interface, abbreviated as FDDI) or an Ethernet (English name: Ethernet) interface. Alternatively, the network interface 1201 may be a wireless interface, eg a wireless local area network interface.

  Memory 1202 is configured to store an inter-network clock synchronization topology. The memory 1202 is a random access memory (English name: random-access memory, abbreviated as RAM), a read only memory (English name: read only memory, abbreviated as ROM) and an erasable programmable read only memory (English name: erasable programmable read) Although it contains only memory (abbreviated EPROM), it is not limited thereto.

  The processor 1203 includes a central processing unit (English name: central processing unit (abbreviated as CPU), a network processor (English name: network processor, abbreviated as NP), an application-specific integrated circuit (English name: abbreviated) ASIC) and one or more of programmable logic devices (abbreviated as PLD), but is not limited thereto. PLDs are complex programmable logic devices (English name: CPLD), field-programmable gate arrays (English name: FPGA), generic array logic (English name: English): It may be a generic array logic (abbreviated GAL) or any combination thereof.

  Memory 1202 may be incorporated into processor 1203. When the memory 1202 and the processor 1203 are independent components, the memory 1202 is connected to the processor 1203. For example, memory 1202 and processor 1203 may communicate using a bus. The network interface 1201 and the processor 1203 may communicate using a bus, or the network interface 1201 may be directly connected to the processor 1203.

Processor 1203 is
Receiving the first packet from a path computing device in the first network using the network interface 1201, the first packet including clock synchronization capability information of the first network element in the first network , And
The operation of updating the inter-network clock synchronization topology based on the inter-network clock synchronization topology in the memory 1202 and the clock synchronization capability information of the first network element is configured to be performed.

  Memory 1202 is further configured to store the updated inter-network clock synchronization topology.

  Apart from this, the first network element is a first edge network device in the first network.

  Alternatively, the updated inter-network clock synchronization topology further includes a clock injection node of the second network and a second edge network device with clock synchronization capability in the first network. Processor 1203 is further configured to determine a clock injection node of the first network based on the updated inter-network clock synchronization topology.

  The inter-network path computing device 1200 shown in FIG. 12 and the inter-network path computing device 1100 shown in FIG. 11 may be the same device, for example, an implementation of the method of FIG. FIG. 12 shows the contents included in the inter-network route calculation device from the physical point of view, and FIG. 11 can be considered to show the contents included in the inter-network route calculation device from the logical point of view. Alternatively, the receiver 1101 shown in FIG. 11 may be implemented by the network interface 1201 shown in FIG. 12, and by the memory 1202 and processor 1203 shown in FIG. The updating unit 1102 shown in FIG.

  FIG. 13 is a schematic block diagram of an inter-network route calculation device according to an embodiment of the present application. As shown in FIG. 13, the inter-network route calculation device 1300 includes a receiver 1301 and a determiner 1302.

  The receiver unit 1301 is configured to receive the first packet from the route calculation device in the first network. The first packet is used to request to determine the clock injection node of the first network.

  The determination unit 1302 is configured to determine the first edge network device in the first network as the first clock injection node of the first network based on the inter-network clock synchronization topology. The inter-network clock synchronization topology includes a first edge network device and a second clock injection node of a second network, the second network being an upstream network of the first network.

  The determining unit 1302 is further configured to determine a clock synchronization path from the second clock injection node to the first clock injection node.

  Apart from this, the first packet further comprises an identifier of the third clock injection node of the first network, the third clock injection node and the first clock injection node being different edge network devices.

  The inter-network route calculation device 1300 provided in this embodiment may be applied to the application scenario shown in FIG. 2 to implement the function of the inter-network route calculation device 230. The inter-network path computing device 1300 may be configured to perform the method of the embodiment of FIG. 6 to implement the method of the embodiment of FIG. Refer to the description of the inter-network path computing device of the method embodiment of FIG. 6 for further additional functions that can be implemented by the inter-network path computing device 1300 and the process of passing on with another device. Details will not be described again here.

  FIG. 14 is a schematic block diagram of another inter-network route calculation device according to an embodiment of the present application. As shown in FIG. 14, the inter-network route calculation device 1400 includes a network interface 1401, a memory 1402 and a processor 1403.

  For example, the route computing device 1400 may be a separate server. Alternatively, the inter-network route calculation device 1400 may be a software module of the router or a hardware module of the router, and the network interface, the memory and the processor may be the network interface of the router, the memory And processor.

  The network interface 1401 may be a wired interface, for example, a fiber distributed data interface (English name: Fiber Distributed Data Interface, abbreviated as FDDI) or an Ethernet (English name: Ethernet) interface. Alternatively, network interface 1401 may be a wireless interface, eg, a wireless local area network interface.

  Memory 1402 is configured to store an inter-network clock synchronization topology. The memory 1402 is a random access memory (English name: random-access memory, abbreviated as RAM), a read only memory (English name: read only memory, abbreviated as ROM), an erasable programmable read only memory (English name: erasable programmable read) Although it contains only memory (abbreviated EPROM), it is not limited thereto.

  The processor 1403 includes a central processing unit (English name: central processing unit, abbreviated as CPU), a network processor (English name: network processor, abbreviated as NP), an application-specific integrated circuit (English name: abbreviated) ASIC) and one or more of programmable logic devices (abbreviated as PLD), but is not limited thereto. PLDs are complex programmable logic devices (English name: CPLD), field-programmable gate arrays (English name: FPGA), generic array logic (English name: English): It may be a generic array logic (abbreviated GAL) or any combination thereof.

  Memory 1402 may be incorporated into processor 1403. The memory 1402 is connected to the processor 1403 when the memory 1402 and the processor 1403 are independent components of each other. For example, memory 1402 and processor 1403 may communicate using a bus. The network interface 1401 and the processor 1403 may communicate using a bus, or the network interface 1401 may be directly connected to the processor 1403.

Processor 1403 is
An operation of receiving a first packet from a path computation device in a first network using network interface 1401, the first packet being used to request to determine a clock injection node of the first network Action,
An operation of determining a first edge network device in a first network as a first clock injection node of a first network based on an inter-network clock synchronization topology, wherein the inter-network clock synchronization topology is a first edge Operation comprising a network device and a second clock injection node of a second network, the second network being an upstream network of the first network;
Performing an operation of determining a clock synchronization path from the second clock injection node to the first clock injection node.

  Apart from this, the first packet further comprises an identifier of the third clock injection node of the first network, the third clock injection node and the first clock injection node being different edge network devices.

  The inter-network path computing device 1400 shown in FIG. 14 and the inter-network path computing device 1300 shown in FIG. 13 may be the same device, for example, an implementation of the method of FIG. FIG. 14 shows the contents included in the inter-network route calculation device from the physical point of view, and FIG. 13 can be considered to show the contents included in the inter-network route calculation device from the logical point of view. Alternatively, the receiver 1301 shown in FIG. 13 may be implemented by the network interface 1401 shown in FIG. 14 and by the processor 1403 shown in FIG. The determining unit 1302 may be implemented.

  All of the embodiments herein are described in a progressive manner. Reference is made to these embodiments for the same or similar parts of the embodiments. In each embodiment, attention is paid to differences from the other embodiments. In particular, the system embodiment is basically similar to the method embodiment and is therefore briefly described. For relevant parts, reference is made to some descriptions of the method embodiments.

  All or part of the steps of the method embodiment may be implemented by a program instructing relevant hardware. The program may be stored on a computer readable storage medium. When the program runs, the steps of the method embodiment are performed. A storage medium includes any medium that can store program code, such as a ROM, a RAM, a magnetic disk or an optical disk.

  Finally, it should be noted that the embodiments are only intended to illustrate the technical solution of the present invention, and not to limit the present invention. Although the present invention has been described in detail with reference to the embodiments, the technical solutions described in the embodiments are in this case without departing from the scope of the technical solutions of the embodiments of the present invention. It is naturally understood that a person skilled in the art may make modifications and equivalent substitutions to some or all of the technical features.

1 Network
2 Network
100 network
101 Network Device
102 Network Device
103 Network Device
104 Network Device
105 Network Device
106 base stations
110 route calculation device
120 clock source
200 network
201 Network Device
202 Edge Network Device
203 Edge Network Device
210 route calculation device
230 Inter-network route calculation device
700 route calculation device
701 Receiver
702 Update
800 route calculation device
801 Network interface
802 memory
803 processor
900 route calculation device
901 Receiver
902 Decision Department
1000 route calculation device
1001 network interface
1002 memory
1003 processor
1100 Inter-network route calculation device
1101 Receiver
1102 Update section
1200 Inter-network route calculation device
1201 Network interface
1202 Memory
1203 processor
1300 Inter-network route calculation device
1301 Receiver
1302 Decision Department
1400 Inter-network route calculation device
1401 Network interface
1402 memory
1403 processor

The clock synchronization topology of the first network is updated based on the clock synchronization capability information of the first network element to automatically obtain information for calculating the clock synchronization path, whereby the clock synchronization path is correctly obtained. Provide enough information to calculate. Thus, the cost of deploying clock synchronization paths is reduced.

Apart from this, in the tenth aspect, the eleventh aspect and the twelfth aspect, the first packet further includes an identifier of the third clock injection node of the first network, and the third clock injection node and The first clock injection node is a different edge network device. The identifier of the third clock injection node carried in the first packet can be used to automatically determine, for the first network, a clock injection node different from the third clock injection node. Thus, if the third clock injection node can not meet the requirements of the first network for acquisition of clock signals, then a new clock injection node for the first network is rapidly acquired, whereby the clock signal The impact of degraded services on transmission is reduced.

Apart from this, in any one of the first to twelfth aspects, the first packet is a Path Computation Element Protocol ( PCEP ) packet. If the information in the first packet is carried using PCEP packets, the devices in the network do not need to jointly deploy and define a new communication protocol for information exchange. Thus, the cost of implementing this solution is reduced.

In the present application, the "network element" may be a network device. For example, “network element” may be a router, a switch, an optical transport network ( OTN) device, a packet
It may be a transport network ( PTlet) or a wavelength division multiplexing ( WDM) device or server. The "node" may be a network device. For example, a "node" may be a router, switch, OTN device, PTN device, WDM device or server.

FIG. 1 is a schematic view of a possible application scenario according to an embodiment of the present application. Network 100 includes network device 101, network device 102, network device 103, network device 104, network device 105, and network device 106. The network devices may be routers, network switches, firewalls, wavelength division multiplexing devices, packet transport network devices, base stations, base station controllers, data centers, etc. The network 100 may be a carrier network, in particular a mobile backbone network using wireless communication. Network 100 may be a network domain that includes several network devices in a carrier network. For example, the network 100 may be an autonomous system ( AS for short) formed according to Border Gateway Protocol ( BGP for short). Alternatively, the network 100 may be a network domain obtained by the division performed by the network manager based on the network topology configuration. For example, network 100 may be an access ring, aggregation ring or core ring.

The network device 101 in the network 100 of FIG. 1 is connected to a clock source 120 and obtains a clock signal from the clock source 120. The clock source may be referred to as a time source. For example, clock source 120 may be a built integrated timing supply ( BITS) device. Clock source 120 may be located within network 100 or outside network 100. Of course, the network 100 may not have a network device connected to the clock source 120, and the network devices in the network 100 obtain clock signals from network devices in another network.

For example, a connection is established between the route computing device 110 in the network 100 and each of the network devices 101, 102, 103, 104 and 105. The connection may be established by a Path Computation Element Communication Protocol ( PCEP for short). For example, the path computing device 110 may be a path computation element ( PCE) for short in the PCEP model. Each of the network devices 101, 102, 103, 104, and 105 may be a path computation client ( PCC for short) in the PCEP model. For the PCE and PCC network architecture, reference is made to the Internet Engineering Task Force's Request for Comments ( RFC) 4655.

For example, synchronous Ethernet technology may be used to obtain the clock signal and generate the local system clock of the network device. The next hop clock synchronization node extracts a clock signal from the physical layer serial codestream sent by the previous hop clock synchronization node to generate a system clock of the next hop clock synchronization node. For example, a phase locked loop ( PHase Locked Loop, abbreviated PLL) is incorporated in the interface circuit of the next hop clock sync node, and a clock signal sent by the previous hop clock sync node is used as an input signal of the phase locked loop. A system clock is generated that is the same as the frequency of the clock signal sent by the previous hop clock synchronization node.

For example, instead of this, the method of acquiring the clock signal and generating the local system clock generates the system clock based on the steps of acquiring a timestamp from the packet sent by the previous hop clock synchronization node and the timestamp And step may be included. The particular implementation for generating a system clock based on the time stamp, the high precision time synchronization protocol (p recision time protocol, abbreviated PTP), for example, Institute of Electrical and Electronics Engineers (I nstitute of Electrical and Electronics Engineers , short IEEE) standard 1588.

FIG. 2 is a schematic view of another application scenario according to an embodiment of the present application. Network 100 and network 200 are two network domains in the network. The network 100 may be a carrier network or a part of a carrier network, and the network 100 may be a company network or a part of a company network. The network 200 may be a carrier network or a part of a carrier network, and the network 200 may be a company network or a part of a company network. Network 100 and network 200 may both be network domains in a carrier network. Alternatively, network 100 and network 200 may be network domains in a carrier network and network domains in a corporate network, respectively. Network 100 and network 200 may both be network domains in a corporate network. For example, the network 100 and the network 200 may be two autonomous systems ( ASs for short) formed in accordance with Border Gateway Protocol ( Border Gateway Protocol, for short, BGP), based on the network topology configuration. There may also be two network domains obtained by the partitioning performed by the network manager. The path computation device 110 calculates a clock synchronization path for the network devices in the network 100 based on the clock synchronization capability and clock synchronization request of each network device in the network 100. The path computation device 210 calculates a clock synchronization path for the network devices in the network 200 based on the clock synchronization capability of each network device in the network 200 and the clock synchronization request. For example, the network 100 of FIG. 2 may be the network 100 shown in FIG.

One skilled in the art may consider that there is a further need for the path computing device to obtain topology information of the first network based on clock synchronization capability information of the first network element to update the clock synchronization topology. For example, if the clock synchronization topology is one that includes physical links, there is a further need for the path computing device to obtain physical topology information of the first network. Physical topology information includes the physical port of the first network element and the connection between this physical port and another physical port of another network device. For example, if the clock synchronization topology is a topology that includes logical links, the path computing device further needs to obtain logical topology information of the first network. The logical topology information includes the logical port of the first network element and the relationship between the logical links established between the logical port and another network device. The topology information of the first network element may be pre-stored in the path computing device or may be sent to the path computing device by the first network element. When the topology information of the first network element is sent by the first network element to the route computing device, the topology information may be carried in the first packet or in another packet.

For example, the route calculation policy can be a point-to-multipoint ( point to multipoint, abbreviated as P2MP) multiprotocol label switching ( MPLi, abbreviated as MPLS) traffic engineering label switched path (traffic engineering label switched paths, TE LSP for short) may be a path computation policy, universal multiprotocol label switching (g eneralized multi-protocol label switching , short GMPLS be) traffic engineering label It may be a route calculation policy of a traffic engineering label switched path (abbreviated TE LSP). For example, the route calculation device 110 uses a clock injection node of the network 100 such as the network device 101 as an ingress node of the TE LSP, and a first such as the network device 105 as an egress node of the TE LSP. Perform route calculations using network elements. Refer to RFC 6006 for the specific route calculation method.

Route calculation policy that determines the first clock synchronization path from the clock injection node of the first network to the first network element may be the same as path computation policy in S30 3 in FIG.

FIG. 5 is a flow chart of a method of updating an inter-network clock synchronization topology according to an embodiment of the present application. For example, the method may be applied to the scenario shown in FIG. For example, the steps of the method of FIG. 5 may be performed by the inter-network path computing device 230 shown in FIG. Route computing device in the first network in the method of FIG. 5 may be a path computation device 110 shown in FIG. 2, the first edge network device network of FIG. 5 is a network device in FIG. 2 It may be 101. The method includes S501 and S502.

One skilled in the art may consider that there is a further need for the path computing device to obtain topology information of the first network based on clock synchronization capability information of the first network element to update the clock synchronization topology. For example, if the clock synchronization topology is one that includes physical links, there is a further need for the path computing device to obtain physical topology information of the first network. Physical topology information includes the physical port of the first network element and the connection between this physical port and another physical port of another network device. For example, if the clock synchronization topology is a topology that includes logical links, the path computing device further needs to obtain logical topology information of the first network. The logical topology information includes the logical port of the first network element and the relationship between the logical links established between the logical port and another network device. The topology information of the first network element may be pre-stored in the path computing device or may be sent to the path computing device by the first network element. When the topology information of the first network element is sent by the first network element to the route computing device, the topology information may be carried in the first packet or in another packet.

For example, when determining the clock injection node for each network, the inter-network path calculation device 230 first calculates the clock injection node of the upstream network and then calculates the clock injection node of the downstream network. In one example, the upstream / downstream relationship between networks is preset by the network manager in the inter-network route calculation device 230. In another example, the upstream / downstream relationship of the network is calculated by the inter-network path computing device 230 using the same method of computing clock synchronization paths of network devices. The method uses each network as a node, the network with the clock source as a clock injection node, and interconnects two networks where an edge network device in one network is connected to an edge network device in another network Use as a selected node.

For example, the network interface 801 is a wired interface, for example, Fiber Distributed Data Interface (F iber Distributed Data Interface, short FDDI), Ethernet (registered trademark) may be a (E Thernet) interface. Alternatively, the network interface 801 may be a wireless interface, eg a wireless local area network interface.

The memory 802 is configured to store a clock synchronization topology of the first network. The memory 802 includes random access memory ( RAM), read only memory ( ROM), and erasable programmable read only memory ( EPROM). Including, but not limited to.

The processor 803 may be a central processing unit ( CPU), a network processor ( NP), an application-specific integrated circuit ( ASIC) and programmable Including but not limited to one or more of a logic device ( PLD). PLDs include complex programmable logic devices ( abbreviated CPLDs), field programmable gate arrays ( abbreviated FPGAs), generic array logic ( abbreviated) GAL) or any combination thereof.

For example, the network interface 1001 wired interface, for example, Fiber Distributed Data Interface (F iber Distributed Data Interface, short FDDI), Ethernet (registered trademark) may be a (E Thernet) interface. Alternatively, network interface 1001 may be a wireless interface, eg, a wireless local area network interface.

The memory 1002 includes random access memory ( RAM), read only memory ( ROM), and erasable programmable read only memory ( EPROM). Including, but not limited to.

The processor 1003 can be a central processing unit ( CPU), a network processor ( NP), application-specific integrated circuit ( ASIC) and programmable Including but not limited to one or more of a logic device ( PLD). PLDs include complex programmable logic devices ( abbreviated CPLDs), field programmable gate arrays ( abbreviated FPGAs), generic array logic ( abbreviated) GAL) or any combination thereof.

For example, the inter-network route computing device 1200 may be a separate server. Instead of this, the network between the route calculation device 1 2 00 may be the router software module may be a router hardware modules, also a network interface, a memory and processor, router network interface , Memory and processor.

The network interface 1201 is a wired interface, for example, Fiber Distributed Data Interface (F iber Distributed Data Interface, short FDDI), Ethernet (registered trademark) may be a (E Thernet) interface. Alternatively, the network interface 1201 may be a wireless interface, eg a wireless local area network interface.

Memory 1202 is configured to store an inter-network clock synchronization topology. The memory 1202 includes random access memory ( RAM), read only memory ( ROM), and erasable programmable read only memory ( EPROM). Including, but not limited to.

The processor 1203 can be a central processing unit ( CPU), a network processor ( NP), application-specific integrated circuit ( ASIC) and programmable Including but not limited to one or more of a logic device ( PLD). PLDs include complex programmable logic devices ( abbreviated CPLDs), field programmable gate arrays ( abbreviated FPGAs), generic array logic ( abbreviated) GAL) or any combination thereof.

Network interface 1401 wired interface, for example, Fiber Distributed Data Interface (F iber Distributed Data Interface, short FDDI), Ethernet (registered trademark) may be a (E Thernet) interface. Alternatively, network interface 1401 may be a wireless interface, eg, a wireless local area network interface.

Memory 1402 is configured to store an inter-network clock synchronization topology. The memory 1402 is a random access memory ( random access memory, abbreviated as RAM), a read only memory ( read only memory, abbreviated as ROM), and an erasable programmable read only memory ( erasable programmable read only memory, abbreviated as EPROM) Including, but not limited to.

The processor 1403 may be a central processing unit ( CPU), a network processor ( NP), application-specific integrated circuit ( ASIC) and programmable Including but not limited to one or more of a logic device ( PLD). PLDs include complex programmable logic devices ( abbreviated CPLDs), field programmable gate arrays ( abbreviated FPGAs), generic array logic ( abbreviated) GAL) or any combination thereof.

Claims (30)

Receiving a first packet from a first network element, wherein the first packet comprises clock synchronization capability information of the first network element, the first network element in the first network; A network element, the first network element having clock synchronization capability;
Updating the clock synchronization topology of the first network based on the clock synchronization capability information of the first network element.   The method of claim 1, wherein the clock synchronization capability information of the first network element comprises information on at least one port with the clock synchronization capability in the first network element.   The updated clock synchronization topology of the first network comprises a clock injection node of the first network, the method comprising: from the clock injection node based on the updated clock synchronization topology of the first network The method according to claim 1 or 2, further comprising the step of determining a clock synchronization path to the first network element.   The method according to any one of claims 1 to 3, wherein the first packet is a path computation element protocol PCEP packet. Receiving the first packet from the first network element, wherein the first packet is used to request to determine a clock synchronization path for the first network element; The network element is a network element in a first network, said first network element having clock synchronization capability;
Determining a first clock synchronization path from a clock injection node of the first network to the first network element based on a clock synchronization topology of the first network, comprising: A method of determining a clock synchronization path comprising: said clock synchronization topology comprising said clock injection node and said first network element.   The first packet is further used to indicate that the second clock synchronization path from the clock injection node to the first network element is faulty, the second clock synchronization path being the first clock synchronization path. 6. The method of claim 5, comprising at least one network element not on a clock synchronization path.   The method according to claim 5 or 6, wherein the first packet is a path calculation element protocol PCEP packet. Receiving a first packet from a path computing device in a first network, wherein the first packet comprises clock synchronization capability information of a first network element in the first network;
Updating an inter-network clock synchronization topology based on the clock synchronization capability information of the first network element.   The method of claim 8, wherein the first network element is a first edge network device in the first network. The updated inter-network clock synchronization topology further comprises a clock injection node of a second network and a second edge network device with clock synchronization capability in the first network, the method comprising
The method according to claim 8 or 9, further comprising: determining a clock injection node of the first network based on the updated inter-network clock synchronization topology.   11. The clock synchronization capability information of the first network element comprises information on at least one port with the clock synchronization capability in the first network element. Method.   The method according to any one of claims 8 to 11, wherein the first packet is a path computation element protocol PCEP packet. Receiving a first packet from a path computing device in a first network, wherein the first packet is used to request to determine a clock injection node of the first network; ,
Determining a first edge network device in said first network as a first clock injection node of said first network based on an inter-network clock synchronization topology, wherein said inter-network clock synchronization topology is Comprising a first edge network device and a second clock injection node of a second network, said second network being a network upstream of said first network,
Determining a clock synchronization path from the second clock injection node to the first clock injection node.   14. The first packet further comprises an identifier of a third clock injection node of the first network, and the third clock injection node and the first clock injection node are different edge network devices. The method described in.   The method according to claim 13 or 14, wherein the first packet is a path calculation element protocol PCEP packet. A route calculation device comprising a receiver and an updater, comprising:
The receiving unit receives a first packet from a first network element, the first packet comprises clock synchronization capability information of the first network element, and the first network element is in a first network. The first network element is configured to have clock synchronization capability,
The updating unit is configured to update a clock synchronization topology of the first network based on the clock synchronization capability information of the first network element from the receiving unit.
Path calculation device.   17. The device of claim 16, wherein the clock synchronization capability information of the first network element comprises information regarding at least one port with the clock synchronization capability in the first network element.   The device further comprises a decision unit, the updated clock synchronization topology of the first network comprising a clock injection node of the first network, the decision unit being an updated clock of the first network. 18. The device according to claim 16 or 17, configured to determine a clock synchronization path from the clock injection node to the first network element based on a clock synchronization topology.   The method according to any one of claims 16 to 18, wherein the first packet is a path computation element protocol PCEP packet. A route calculation device comprising a receiver and a determiner, comprising:
The first packet is used to request the receiver to receive a first packet from a first network element and to determine a clock synchronization path for the first network element; The first network element in the first network, wherein the first network element is configured to have clock synchronization capability;
The determination unit determines a first clock synchronization path from a clock injection node of the first network to the first network element based on a clock synchronization topology of the first network, and the first network The clock synchronization topology of is configured to comprise the clock injection node and the first network element.
Path calculation device.   The first packet is further used to indicate that the second clock synchronization path from the clock injection node to the first network element is faulty, the second clock synchronization path being the first 21. The device of claim 20, comprising at least one network element not on a clock synchronization path of.   22. The device according to claim 20 or 21, wherein the first packet is a Path Computation Element Protocol PCEP packet. An inter-network route calculation device comprising a receiving unit and an updating unit, wherein
The receiving unit receives a first packet from a path computing device in a first network, and the first packet comprises clock synchronization capability information of a first network element in the first network. Configured and
The updating unit is configured to update an inter-network clock synchronization topology based on the clock synchronization capability information of the first network element from the receiving unit.
Inter-network route calculation device.   24. The device of claim 23, wherein the first network element is a first edge network device in the first network. The updated inter-network clock synchronization topology further comprises a clock injection node of a second network and a second edge network device with clock synchronization capability in said first network, said device further comprising a determining unit. Equipped
The determination unit is configured to determine a clock injection node of the first network based on the updated inter-network clock synchronization topology.
25. A device according to claim 23 or 24.   26. The clock synchronization capability information of the first network element comprises information on at least one port with the clock synchronization capability in the first network element. Method.   27. A method according to any one of claims 23 to 26, wherein the first packet is a path computation element protocol PCEP packet. An inter-network route calculation device comprising a receiver and a determiner, comprising
The receiver may receive the first packet from a path calculation device in the first network, and use the first packet to request to determine a clock injection node of the first network. Configured and
The determination unit determines a first edge network device in the first network as a first clock injection node of the first network based on an inter-network clock synchronization topology, and the inter-network clock synchronization topology is Comprising the first edge network device and a second clock injection node of a second network, wherein the second network is configured to be a network upstream of the first network;
The determining unit is further configured to determine a clock synchronization path from the second clock injection node to the first clock injection node.
Inter-network route calculation device.   30. The first packet further comprises an identifier of a third clock injection node of the first network, the third clock injection node and the first clock injection node being different edge network devices. Device described in.   The device according to claim 28 or 29, wherein the first packet is a path calculation element protocol PCEP packet.

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