JP2019213303A - Electric power conversion device - Google Patents

Electric power conversion device Download PDF

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JP2019213303A
JP2019213303A JP2018105748A JP2018105748A JP2019213303A JP 2019213303 A JP2019213303 A JP 2019213303A JP 2018105748 A JP2018105748 A JP 2018105748A JP 2018105748 A JP2018105748 A JP 2018105748A JP 2019213303 A JP2019213303 A JP 2019213303A
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absolute value
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達也 小原
Tatsuya Obara
達也 小原
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Meidensha Corp
Meidensha Electric Manufacturing Co Ltd
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Abstract

To provide an electric power conversion device performing system interconnection, in which there is no effect on a system voltage when an internal portion of a system side winding of an interconnection transformer is short-circuited with impedance due to some factor during an interconnection operation, and the interconnection operation is stopped without continuing even if a short circuit current does not reach an overcurrent level.SOLUTION: In a subtracter 1, a difference between d-axis and q-axis system current detection values and d-axis and q-axis INV current detection values or a difference between d-axis and q-axis system current command values and d-axis and q-axis INV current command values is calculated. A first absolute value block ABS1 calculates a first absolute value that is an absolute value of the difference. A first abnormality determination processing portion 2a performs determination of a short circuit abnormality by comparing the first absolute value with a first threshold value. A failure stop processing portion 3 performs failure stop processing when the first abnormality determination processing portion 2a determines that a short circuit abnormality occurs.SELECTED DRAWING: Figure 1

Description

本発明は、電力変換装置における連系トランス内の短絡検出に関する。   The present invention relates to short circuit detection in an interconnection transformer in a power converter.

特許文献1には、モータ制御を行う電力変換装置において、電流指令値と電流検出値の差分の積分値を使用してモータ内の短絡を検出する方法が示されている。   Patent Document 1 discloses a method of detecting a short circuit in a motor using an integral value of a difference between a current command value and a current detection value in a power conversion device that performs motor control.

特許6108043号Japanese Patent No. 6108043

しかし、系統連系された電力変換装置において、連系運転中に何らかの要因によって連系トランス内部の系統側巻線間がインピーダンスを持って短絡すると、系統電圧に影響がない、かつ、短絡電流が過電流レベルに達しない場合、連系運転し続けてしまう問題がある。   However, in the power converter connected to the grid, if the short circuit between the system side windings inside the grid transformer with impedance occurs during the grid operation, there is no effect on the grid voltage and the short circuit current If the overcurrent level is not reached, there is a problem that the interconnection operation continues.

このような状態の場合、連系トランスの系統側電流は不平衡電流となり、インバータ側電流は三相平衡電流を流している状態となる。連系トランスはΔ−Y結線の他、Y−Y結線,Δ−Δ結線,Y−Δ結線がある。   In such a state, the grid-side current of the interconnection transformer is an unbalanced current, and the inverter-side current is in a state of flowing a three-phase balanced current. In addition to the Δ-Y connection, the interconnection transformer includes a YY connection, a Δ-Δ connection, and a Y-Δ connection.

以上示したようなことから、系統連系する電力変換装置において、連系運転中に連系トランスの系統側巻線の内部が何らかの要因によってインピーダンスを持って短絡した際、系統電圧に影響がない、かつ、短絡電流が過電流レベルに達しない場合でも、連系運転を継続せず停止させることが課題となる。   As described above, in the power conversion device connected to the grid, when the internal side of the grid side of the grid transformer is short-circuited with impedance due to some factor during the grid operation, the grid voltage is not affected. Even when the short-circuit current does not reach the overcurrent level, it becomes a problem to stop the interconnection operation without continuing.

本発明は、前記従来の問題に鑑み、案出されたもので、その一態様は、直流−交流変換または交流−直流変換を行う変換器と、前記変換器と交流系統との間に設けられた連系トランスと、前記変換器の制御を行う制御部と、を備えた電力変換装置において、前記制御部は、d軸,q軸系統電流検出値とd軸,q軸INV電流検出値との差分、または、d軸,q軸系統電流指令値とd軸,q軸INV電流指令値との差分を演算する減算器と、差分の絶対値である第1絶対値を演算する第1絶対値ブロックと、前記第1絶対値と第1閾値との比較により短絡異常の判定を行う異常判定部と、前記異常判定部で短絡異常と判定された場合、故障停止処理を行う故障停止処理部と、を備えたことを特徴とする。   The present invention has been devised in view of the conventional problems, and one aspect thereof is provided between a converter that performs DC-AC conversion or AC-DC conversion, and the converter and an AC system. And a control unit that controls the converter, the control unit includes a d-axis and q-axis system current detection value, a d-axis and q-axis INV current detection value, and Or a subtractor that calculates the difference between the d-axis and q-axis system current command value and the d-axis and q-axis INV current command value, and the first absolute value that calculates the first absolute value that is the absolute value of the difference A failure determination unit for determining a short-circuit abnormality by comparing the value block with the first absolute value and the first threshold, and a failure stop processing unit for performing a failure stop process when the abnormality determination unit determines that a short-circuit abnormality has occurred And.

また、他の態様として、直流−交流変換または交流−直流変換を行う変換器と、前記変換器と交流系統との間に設けられた連系トランスと、前記変換器の制御を行う制御部と、を備えた電力変換装置において、前記制御部は、d軸,q軸系統電流検出値とd軸,q軸INV電流検出値との差分、または、d軸,q軸系統電流指令値とd軸,q軸INV電流指令値との差分を演算する減算器と、差分を積分する積分器と、前記積分器の出力の絶対値である第2絶対値を演算する第2絶対値ブロックと、前記第2絶対値と第2閾値との比較により短絡異常の判定を行う異常判定部と、前記異常判定部で短絡異常と判定された場合、故障停止処理を行う故障停止処理部と、を備えたことを特徴とする。   Further, as another aspect, a converter that performs DC-AC conversion or AC-DC conversion, an interconnection transformer provided between the converter and an AC system, and a control unit that controls the converter , The control unit is configured such that a difference between a d-axis / q-axis system current detection value and a d-axis / q-axis INV current detection value or a d-axis / q-axis system current command value and d A subtractor that calculates the difference between the axis and q-axis INV current command values, an integrator that integrates the difference, a second absolute value block that calculates a second absolute value that is an absolute value of the output of the integrator, An abnormality determination unit that determines a short circuit abnormality by comparing the second absolute value and a second threshold value, and a failure stop processing unit that performs a failure stop process when the abnormality determination unit determines that a short circuit abnormality has occurred. It is characterized by that.

また、他の態様として、直流−交流変換または交流−直流変換を行う変換器と、前記変換器と交流系統との間に設けられた連系トランスと、前記変換器の制御を行う制御部と、を備えた電力変換装置において、前記制御部は、d軸,q軸系統電流検出値とd軸,q軸INV電流検出値との差分、または、d軸,q軸系統電流指令値とd軸,q軸INV電流指令値との差分を演算する減算器と、差分の絶対値である第1絶対値を演算する第1絶対値ブロックと、前記第1絶対値と第1閾値との比較により短絡異常の判定を行う第1異常判定部と、差分を積分する積分器と、前記積分器の出力の絶対値である第2絶対値を演算する第2絶対値ブロックと、前記第2絶対値と第2閾値との比較により短絡異常の判定を行う第2異常判定部と、前記第1異常判定部および前記第2異常判定部のうち少なくとも何れか一方が短絡異常と判定した場合、故障停止処理を行う故障停止処理部と、を備えたことを特徴とする。   Further, as another aspect, a converter that performs DC-AC conversion or AC-DC conversion, an interconnection transformer provided between the converter and an AC system, and a control unit that controls the converter , The control unit is configured such that a difference between a d-axis / q-axis system current detection value and a d-axis / q-axis INV current detection value or a d-axis / q-axis system current command value and d A subtractor that calculates a difference between the axis and q-axis INV current command values, a first absolute value block that calculates a first absolute value that is an absolute value of the difference, and a comparison between the first absolute value and the first threshold value A first abnormality determination unit that determines whether or not a short circuit has occurred, an integrator that integrates the difference, a second absolute value block that calculates a second absolute value that is an absolute value of the output of the integrator, and the second absolute value A second abnormality determination unit that determines a short-circuit abnormality by comparing the value with a second threshold value; Abnormality determination unit and the case where the second abnormality at least one of the determination section determines that the abnormal short circuit, characterized by comprising a failure stop processing unit for performing fault stop process, the.

本発明によれば、系統連系する電力変換装置において、連系運転中に連系トランスの系統側巻線の内部が何らかの要因によってインピーダンスを持って短絡した際、系統電圧に影響がない、かつ、短絡電流が過電流レベルに達しない場合でも、連系運転を継続せず停止させることが可能となる。   According to the present invention, in the power conversion device interconnected with the grid, when the inside of the grid side winding of the grid transformer is short-circuited with an impedance due to some factor during the grid operation, the grid voltage is not affected, and Even when the short-circuit current does not reach the overcurrent level, it is possible to stop the interconnection operation without continuing.

実施形態1における短絡検出処理を示す制御ブロック図。FIG. 3 is a control block diagram illustrating a short circuit detection process in the first embodiment. 実施形態1における異常判定処理部のフローチャート。5 is a flowchart of an abnormality determination processing unit in the first embodiment. 実施形態2における短絡検出処理を示す制御ブロック図。FIG. 6 is a control block diagram illustrating a short circuit detection process in the second embodiment. 実施形態3における短絡検出処理を示す制御ブロック図。FIG. 10 is a control block diagram showing a short circuit detection process in the third embodiment.

以下、本願発明における電力変換装置の実施形態1〜4を図1〜図4に基づいて詳述する。   Hereinafter, Embodiments 1 to 4 of the power conversion device according to the present invention will be described in detail with reference to FIGS.

[実施形態1]
本実施形態1の電力変換装置は、直流−交流変換または交流−直流変換を行う変換器(以下、インバータと称する)と、インバータと交流系統との間に設けられた連系トランスと、インバータの制御を行う制御部と、を備えている。
[Embodiment 1]
The power conversion device according to the first embodiment includes a converter that performs DC-AC conversion or AC-DC conversion (hereinafter referred to as an inverter), an interconnection transformer provided between the inverter and the AC system, and an inverter A control unit that performs control.

制御部は、系統電圧,連系トランス一次側(系統側)の電流である系統電流検出値,連系トランス二次側(インバータ側)の電流であるINV電流検出値を検出している。   The control unit detects a system voltage, a system current detection value which is a current on the primary side of the interconnection transformer (system side), and an INV current detection value which is a current on the secondary side of the interconnection transformer (inverter side).

系統電流検出値およびINV電流検出値は、系統電圧の電圧位相θ1および連系トランス二次側の電圧位相θ2に基づいて、d軸,q軸系統電流検出値およびd軸,q軸INV電流検出値に回転座標変換する。短絡検出処理では、このd軸,q軸系統電流検出値およびd軸,q軸INV電流検出値を用いる。   The system current detection value and the INV current detection value are determined based on the voltage phase θ1 of the system voltage and the voltage phase θ2 of the interconnection transformer secondary side, and the d-axis and q-axis system current detection values and the d-axis and q-axis INV current detection. Convert rotating coordinates to a value. In the short-circuit detection process, the d-axis and q-axis system current detection values and the d-axis and q-axis INV current detection values are used.

本実施形態1における短絡検出処理の制御ブロック図を図1に示す。これは、連系トランスの内部短絡を瞬時検出するための処理である。なお、図1に基づいて、d軸の制御ブロックを説明するが、q軸の制御ブロックもd軸の制御ブロックと同様に構成される。   A control block diagram of the short-circuit detection process in the first embodiment is shown in FIG. This is a process for instantaneously detecting an internal short circuit of the interconnection transformer. Although the d-axis control block will be described with reference to FIG. 1, the q-axis control block is configured similarly to the d-axis control block.

図1に示すように、減算器1において、d軸系統電流検出値とd軸INV電流検出値との差分を計算する。次に、ローパスフィルタLPFにおいて、差分を平均化する。次に、第1絶対値ブロックABS1において、平均化された差分の絶対値を第1絶対値として算出する。   As shown in FIG. 1, the subtracter 1 calculates the difference between the d-axis system current detection value and the d-axis INV current detection value. Next, the difference is averaged in the low-pass filter LPF. Next, in the first absolute value block ABS1, the absolute value of the averaged difference is calculated as the first absolute value.

第1異常判定処理部2aは、第1絶対値と第1閾値Aと基づいて異常判定を行う。図2は、第1異常判定処理部2aの処理を示すフローチャートである。   The first abnormality determination processing unit 2a performs abnormality determination based on the first absolute value and the first threshold A. FIG. 2 is a flowchart showing the processing of the first abnormality determination processing unit 2a.

図2に示すように、S1では、第1絶対値と第1閾値Aとの比較行う。ただし、誤動作防止のため、第1閾値Aはマージンを持たせて設定する必要がある。第1絶対値が第1閾値A以上であればS2へ移行し、カウントアップ(+1)する。S2の処理後S4へ移行する。第1絶対値が第1閾値Aよりも小さければS3へ移行し、カウントをリセットしてカウント=0とする。S3の処理が終わったら、その演算周期での処理を終了する。   As shown in FIG. 2, in S1, the first absolute value is compared with the first threshold A. However, in order to prevent malfunction, the first threshold value A needs to be set with a margin. If the first absolute value is greater than or equal to the first threshold A, the process proceeds to S2 and counts up (+1). After the process of S2, the process proceeds to S4. If the first absolute value is smaller than the first threshold value A, the process proceeds to S3, the count is reset, and count = 0. When the process of S3 is finished, the process in the calculation cycle is finished.

S4では、カウンタが所定値に到達しているか否かを判定し、カウンタが所定値に到達している場合S5へ移行し、カウンタが所定値に到達していない場合その演算周期での処理を終了する。S5において停止フラグを立てその演算周期での処理を終了する。   In S4, it is determined whether or not the counter has reached a predetermined value. If the counter has reached the predetermined value, the process proceeds to S5. If the counter has not reached the predetermined value, processing in the calculation cycle is performed. finish. In S5, a stop flag is set and the processing in the calculation cycle is ended.

図1に示すように、故障停止処理部3では、第1異常判定処理部2aで停止フラグが立っていれば故障停止処理を行う。停止フラグが立っていなければ故障停止処理を行わず、通常の運転を継続する。   As shown in FIG. 1, the failure stop processing unit 3 performs failure stop processing if the first abnormality determination processing unit 2a has a stop flag. If the stop flag is not set, the normal operation is continued without performing the failure stop process.

以上示したように、本実施形態1によれば、系統連系する電力変換装置において、連系運転中に連系トランスの系統側巻線の内部が何らかの要因によってインピーダンスを持って短絡した際、系統電圧に影響がない、かつ、短絡電流が過電流レベルに達しない場合でも、連系運転を継続せず停止させることが可能となる。本実施形態1では、短絡の瞬時検出も可能である。   As described above, according to the first embodiment, in the power conversion device that is connected to the grid, when the inside of the grid-side winding of the grid transformer is short-circuited with an impedance due to some factor during the grid operation, Even when the system voltage is not affected and the short-circuit current does not reach the overcurrent level, it is possible to stop the grid operation without continuing. In the first embodiment, instantaneous detection of a short circuit is also possible.

なお、本実施形態1では、短絡インピーダンスが小さい場合に短絡を検出できない。   In the first embodiment, a short circuit cannot be detected when the short circuit impedance is small.

[実施形態2]
本実施形態2における短絡検出処理の制御ブロックを図3に示す。本実施形態2は、連系トランスの内部短絡を時限で検出する方法である。実施形態1と同様の箇所については同一の符号を付し、その説明を省略する。
[Embodiment 2]
FIG. 3 shows a control block of the short circuit detection process in the second embodiment. The second embodiment is a method for detecting an internal short circuit of the interconnection transformer in a time limit. The same parts as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted.

本実施形態2では、ローパスフィルタLPFで平均化した差分を、デッドバンド4に入力する。デッドバンド4は、ローパスフィルタLPFの出力(絶対値)が第3閾値b以下であれば0として出力する。これは後の積分処理での誤検出を防止するための処理である。   In the second embodiment, the difference averaged by the low-pass filter LPF is input to the dead band 4. The dead band 4 is output as 0 if the output (absolute value) of the low-pass filter LPF is equal to or less than the third threshold value b. This is a process for preventing erroneous detection in a later integration process.

積分器5は、デッドバンド4の出力を積分する。なお、積分器5は、停止中などリセットできるようにしておく。第2絶対値ブロックABS2は、デッドバンド4の出力を絶対値を第2絶対値として算出する。第2絶対値ブロックABS2はデッドバンド4の出力を積分したあと絶対値処理を行うことで、第3閾値bを越えるような0をまたぐ変動で正の積分量と負の積分量が相殺されることを防ぐ。   The integrator 5 integrates the output of the dead band 4. The integrator 5 can be reset such as when stopped. The second absolute value block ABS2 calculates the output of the dead band 4 with the absolute value as the second absolute value. The second absolute value block ABS2 integrates the output of the dead band 4 and then performs absolute value processing, so that the positive integration amount and the negative integration amount are canceled out by fluctuations exceeding 0 that exceed the third threshold value b. To prevent that.

第2異常判定処理部2bは、第2絶対値と第2閾値Bの比較を行う。それ以外は実施形態1の第1異常判定処理部2aの動作と同一である。また、故障停止処理部3の動作は実施形態1のと同様である。   The second abnormality determination processing unit 2b compares the second absolute value with the second threshold value B. Other than that, the operation is the same as that of the first abnormality determination processing unit 2a of the first embodiment. The operation of the failure stop processing unit 3 is the same as that of the first embodiment.

以上示したように、本実施形態2によれば、実施形態1と同様の作用効果を奏する。また、実施形態1では、短絡インピーダンスが小さい場合、短絡を検出することができなかったが、本実施形態2では短絡インピーダンスが小さい場合でも短絡を検出することが可能となる。   As described above, according to the second embodiment, the same operational effects as those of the first embodiment can be obtained. In the first embodiment, when the short-circuit impedance is small, the short circuit cannot be detected. However, in the second embodiment, the short circuit can be detected even when the short-circuit impedance is small.

ただし、本実施形態2は、積分により短絡検出まで時限があるため、瞬時検出はできない。   However, in the second embodiment, since there is a time limit until short circuit detection by integration, instantaneous detection cannot be performed.

[実施形態3]
本実施形態3における短絡検出処理の制御ブロック図を図4に示す。本実施形態3は、図4に示すように、実施形態1の第1異常判定処理部2aまでの制御ブロックと、実施形態2の第2異常判定処理部2bまでの制御ブロックと、を備える。そして、2つの第1,第2異常判定処理部2a,2bの出力を論理和回路6に出力する。
[Embodiment 3]
FIG. 4 shows a control block diagram of the short circuit detection process in the third embodiment. As illustrated in FIG. 4, the third embodiment includes a control block up to the first abnormality determination processing unit 2 a according to the first embodiment and a control block up to the second abnormality determination processing unit 2 b according to the second embodiment. Then, the outputs of the two first and second abnormality determination processing units 2 a and 2 b are output to the OR circuit 6.

論理和回路6は、第1異常判定処理部2aと第2異常判定処理部2bのうち少なくともどちらか一方が故障フラグを立てていた場合、故障停止処理部3に「1」レベルの信号を出力する。故障停止処理部3は、第1異常判定処理部2a,第2異常判定処理部2bのうち少なくとも何れか一方が短絡異常と判定した場合、故障停止処理を行う。   The OR circuit 6 outputs a “1” level signal to the failure stop processing unit 3 when at least one of the first abnormality determination processing unit 2a and the second abnormality determination processing unit 2b has set a failure flag. To do. The failure stop processing unit 3 performs failure stop processing when at least one of the first abnormality determination processing unit 2a and the second abnormality determination processing unit 2b determines that a short circuit abnormality has occurred.

以上示したように、本実施形態3は、実施形態1と実施形態2の異常判定結果の論理和としたものである。これにより、短絡インピーダンスが小さい場合でも短絡を検出することができ、瞬時検出も可能となる。よって、実施形態1および実施形態2の問題を解決できる。   As described above, the third embodiment is a logical sum of the abnormality determination results of the first and second embodiments. As a result, even when the short-circuit impedance is small, it is possible to detect a short-circuit, and instantaneous detection is also possible. Therefore, the problem of Embodiment 1 and Embodiment 2 can be solved.

[実施形態4]
本実施形態4は、実施形態3のd軸,q軸INV電流検出値およびd軸,q軸系統電流検出値をd軸,q軸INV電流指令値およびd軸,q軸系統電流指令値に置き換えたものである。電流指令値は電流検出値より安定した値であるため、誤検出を抑制することが可能となる。
[Embodiment 4]
In the fourth embodiment, the d-axis, q-axis INV current detection value and the d-axis, q-axis system current detection value of the third embodiment are changed to the d-axis, q-axis INV current command value, d-axis, q-axis system current command value. It is a replacement. Since the current command value is more stable than the current detection value, it is possible to suppress erroneous detection.

また、実施形態1,2のd軸,q軸INV電流検出値およびd軸,q軸系統電流検出値をd軸,q軸INV電流指令値およびd軸,q軸系統電流指令値としても良い。   Further, the d-axis, q-axis INV current detection value and the d-axis, q-axis system current detection value of the first and second embodiments may be used as the d-axis, q-axis INV current command value, and d-axis, q-axis system current command value. .

以上、本発明において、記載された具体例に対してのみ詳細に説明したが、本発明の技術思想の範囲で多彩な変形および修正が可能であることは、当業者にとって明白なことであり、このような変形および修正が特許請求の範囲に属することは当然のことである。   Although the present invention has been described in detail only for the specific examples described above, it is obvious to those skilled in the art that various changes and modifications are possible within the scope of the technical idea of the present invention. Such variations and modifications are naturally within the scope of the claims.

1…減算器
2a,2b…異常判定処理部
3…故障停止処理部
4…デッドバンド
5…積分器
6…論理和回路
ABS1,ABS…第1,第2絶対値ブロック
LPF…ローパスフィルタ
DESCRIPTION OF SYMBOLS 1 ... Subtractor 2a, 2b ... Abnormality determination process part 3 ... Failure stop process part 4 ... Dead band 5 ... Integrator 6 ... OR circuit ABS1, ABS ... 1st, 2nd absolute value block LPF ... Low pass filter

Claims (3)

直流−交流変換または交流−直流変換を行う変換器と、前記変換器と交流系統との間に設けられた連系トランスと、前記変換器の制御を行う制御部と、を備えた電力変換装置において、
前記制御部は、
d軸,q軸系統電流検出値とd軸,q軸INV電流検出値との差分、または、d軸,q軸系統電流指令値とd軸,q軸INV電流指令値との差分を演算する減算器と、
差分の絶対値である第1絶対値を演算する第1絶対値ブロックと、
前記第1絶対値と第1閾値との比較により短絡異常の判定を行う異常判定部と、
前記異常判定部で短絡異常と判定された場合、故障停止処理を行う故障停止処理部と、
を備えたことを特徴とする電力変換装置。
A power conversion device comprising: a converter that performs DC-AC conversion or AC-DC conversion; an interconnection transformer provided between the converter and an AC system; and a control unit that controls the converter. In
The controller is
The difference between the d-axis / q-axis system current detection value and the d-axis / q-axis INV current detection value or the difference between the d-axis / q-axis system current command value and the d-axis / q-axis INV current command value is calculated. A subtractor,
A first absolute value block for calculating a first absolute value that is an absolute value of the difference;
An abnormality determination unit that determines a short-circuit abnormality by comparing the first absolute value and the first threshold;
When the abnormality determination unit determines that a short circuit abnormality has occurred, a failure stop processing unit that performs failure stop processing;
A power conversion device comprising:
直流−交流変換または交流−直流変換を行う変換器と、前記変換器と交流系統との間に設けられた連系トランスと、前記変換器の制御を行う制御部と、を備えた電力変換装置において、
前記制御部は、
d軸,q軸系統電流検出値とd軸,q軸INV電流検出値との差分、または、d軸,q軸系統電流指令値とd軸,q軸INV電流指令値との差分を演算する減算器と、
差分を積分する積分器と、
前記積分器の出力の絶対値である第2絶対値を演算する第2絶対値ブロックと、
前記第2絶対値と第2閾値との比較により短絡異常の判定を行う異常判定部と、
前記異常判定部で短絡異常と判定された場合、故障停止処理を行う故障停止処理部と、
を備えたことを特徴とする電力変換装置。
A power conversion device comprising: a converter that performs DC-AC conversion or AC-DC conversion; an interconnection transformer provided between the converter and an AC system; and a control unit that controls the converter. In
The controller is
The difference between the d-axis / q-axis system current detection value and the d-axis / q-axis INV current detection value or the difference between the d-axis / q-axis system current command value and the d-axis / q-axis INV current command value is calculated. A subtractor,
An integrator that integrates the difference;
A second absolute value block for calculating a second absolute value that is an absolute value of the output of the integrator;
An abnormality determination unit that determines a short-circuit abnormality by comparing the second absolute value and the second threshold;
When the abnormality determination unit determines that a short circuit abnormality has occurred, a failure stop processing unit that performs failure stop processing;
A power conversion device comprising:
直流−交流変換または交流−直流変換を行う変換器と、前記変換器と交流系統との間に設けられた連系トランスと、前記変換器の制御を行う制御部と、を備えた電力変換装置において、
前記制御部は、
d軸,q軸系統電流検出値とd軸,q軸INV電流検出値との差分、または、d軸,q軸系統電流指令値とd軸,q軸INV電流指令値との差分を演算する減算器と、
差分の絶対値である第1絶対値を演算する第1絶対値ブロックと、
前記第1絶対値と第1閾値との比較により短絡異常の判定を行う第1異常判定部と、
差分を積分する積分器と、
前記積分器の出力の絶対値である第2絶対値を演算する第2絶対値ブロックと、
前記第2絶対値と第2閾値との比較により短絡異常の判定を行う第2異常判定部と、
前記第1異常判定部および前記第2異常判定部のうち少なくとも何れか一方が短絡異常と判定した場合、故障停止処理を行う故障停止処理部と、
を備えたことを特徴とする電力変換装置。
A power conversion device comprising: a converter that performs DC-AC conversion or AC-DC conversion; an interconnection transformer provided between the converter and an AC system; and a control unit that controls the converter. In
The controller is
The difference between the d-axis / q-axis system current detection value and the d-axis / q-axis INV current detection value or the difference between the d-axis / q-axis system current command value and the d-axis / q-axis INV current command value is calculated. A subtractor,
A first absolute value block for calculating a first absolute value that is an absolute value of the difference;
A first abnormality determination unit that determines a short-circuit abnormality by comparing the first absolute value with a first threshold;
An integrator that integrates the difference;
A second absolute value block for calculating a second absolute value that is an absolute value of the output of the integrator;
A second abnormality determination unit that determines a short-circuit abnormality by comparing the second absolute value and a second threshold;
When at least one of the first abnormality determination unit and the second abnormality determination unit determines that a short circuit abnormality has occurred, a failure stop processing unit that performs a failure stop process;
A power conversion device comprising:
JP2018105748A 2018-06-01 2018-06-01 Electric power conversion device Pending JP2019213303A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220080580A (en) * 2020-12-07 2022-06-14 주식회사 현대케피코 Method and apparatus for detecting inverter fault

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20220080580A (en) * 2020-12-07 2022-06-14 주식회사 현대케피코 Method and apparatus for detecting inverter fault
KR102549166B1 (en) * 2020-12-07 2023-06-30 주식회사 현대케피코 Method and apparatus for detecting inverter fault

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