JP2019209575A - Image formation apparatus - Google Patents

Abstract

To detect the abnormality of a semiconductor laser with a simple configuration.MEANS FOR SOLVING THE PROBLEM: An image formation apparatus includes: an optical scan device 2 having a semiconductor laser 12 outputting a light beam of a light amount according to a drive current to be supplied, a photodiode 14 detecting the light amount of the light beam output from the semiconductor laser 12, a hold capacitor 38 holding the voltage for supplying the drive current, and a drive circuit 30 controlling the voltage held by the hold capacitor 38 so as to make the light amount of the light beam detected by the photodiode 14 match the target light amount, supplying the drive current according to the voltage held by the hold capacitor 38 to the semiconductor laser 12 and driving the semiconductor laser 12; and a CPU 503 controlling the optical scan device 2. The CPU 503 detects the abnormality of the optical scan device 2 on the basis of the voltage held by the hold capacitor 38 acquired at the timing T1 after starting-up the drive circuit 30 and specifies the cause of the detected abnormality.SELECTED DRAWING: Figure 6

Description

  The present invention relates to an image forming apparatus including an optical scanning device, and more particularly to abnormality detection in the optical scanning device.

  2. Description of the Related Art Conventionally, in an optical scanning device provided in an image forming apparatus, a method is known in which a light beam emitted from a semiconductor laser is deflected by a rotary polygon mirror and irradiated to a photosensitive drum through an f-θ lens. In this method, it is necessary to stably control the rotation of the scanner motor including the rotary polygon mirror. A beam detector (hereinafter referred to as BD) detects the raster-scanned light beam at a predetermined position, and outputs a beam detection signal (hereinafter referred to as BD signal). A rotation reference signal for the scanner motor is generated based on the BD signal, and each scanner motor is controlled to rotate at a constant speed based on the generated rotation reference signal. On the other hand, when the light beam does not reach the BD, the BD signal is not output, so the rotation reference signal of the scanner motor is not generated, and as a result, the rotation control of the scanner motor cannot be stably performed. In order to cope with this problem, there is a method of detecting a laser abnormality by checking a light emitting state of a laser diode using a photodiode. For example, in Patent Document 1, a warning is issued when the ratio between the monitor current value when a plurality of beams are simultaneously emitted from a laser diode and the monitor current value when only one beam is emitted is smaller than a specified value. A proposal has been made to notify and prohibit the light amount control.

Japanese Patent No. 4397240

  Causes of laser abnormalities include laser diodes, photodiodes, and parts such as drivers that control the laser diodes, as well as failure of the light quantity control signal due to cable disconnection or contact failure (the signal does not pass and is not received normally) Sometimes. When the light amount control signal is not transmitted, the light amount control signal cannot be received, so the light amount control cannot be performed, and the light emission state of the laser diode becomes unstable. In particular, as the number of semiconductor lasers mounted on the optical scanning device becomes multi-beam, the number of pins of the cable increases, and this type of failure increases. In the conventional example described above, when the light amount control signal is not passed, the light emission state becomes unstable, which affects the detection accuracy. In addition, since the detection timing for monitoring the photodiode is limited only to light emission, measures that are not limited to light emission are a problem.

  The present invention has been made under such circumstances, and an object thereof is to detect an abnormality of a semiconductor laser with a simple configuration.

  In order to solve the above-described problems, the present invention has the following configuration.

  (1) A light source that outputs a light beam having a light amount corresponding to the supplied drive current, a detection unit that detects the light amount of the light beam output from the light source, and a voltage for supplying the drive current are held. Voltage holding means for controlling the voltage held by the voltage holding means to match the light quantity of the light beam detected by the detection means to a target light quantity, and according to the voltage held by the voltage holding means An optical scanning device having a driving means for supplying a driving current to the light source and driving the light source; and a control means for controlling the optical scanning device, wherein the control means activates the driving means. An abnormality of the optical scanning device is detected based on a voltage held in the voltage holding unit acquired at a later first timing, and a factor of the detected abnormality is specified. An image forming apparatus.

  According to the present invention, an abnormality of a semiconductor laser can be detected with a simple configuration.

A circuit block diagram of a driving circuit and an image control unit of a conventional optical scanning device for comparison with the embodiment, and a timing chart explaining light amount control The figure explaining the leakage current of the conventional example Timing chart for explaining light quantity control when the light quantity control signal of the conventional example is not connected Sectional drawing which shows the structure of the image forming apparatus of Example 1,2. Schematic diagram illustrating the configuration of the optical scanning device of the first and second embodiments. FIG. 3 is a circuit block diagram of a drive circuit and an image control unit of the optical scanning device according to the first embodiment. The graph which shows the time transition of the charging voltage of the hold capacitor of Example 1 7 is a flowchart showing a control sequence for laser abnormality detection according to the first embodiment. FIG. 6 is a circuit block diagram of a drive circuit and an image control unit of the optical scanning device according to the second embodiment. Timing chart for explaining light amount control according to the second embodiment The graph which shows the time transition of the charging voltage of the hold capacitor of Example 2 7 is a flowchart illustrating a control sequence for laser abnormality detection according to the second embodiment.

  Embodiments of the present invention will be described below in detail with reference to the drawings.

[Control circuit of optical scanning device]
For comparison with the embodiments to be described later, a circuit of a conventional optical scanning device will be described below. FIG. 1A is a circuit block diagram illustrating a configuration of a conventional optical scanning device 2 that scans a photosensitive drum with a light beam emitted from a semiconductor laser and an image control unit 5 that controls the optical scanning device 2. . In FIG. 1A, the image control unit 5 includes a power source 502, an LS control unit 501 that controls the optical scanning device 2, and a CPU 503 that is a control unit that controls the LS control unit 501.

  The optical scanning device 2 has a semiconductor laser (hereinafter referred to as LD) 12 that is a light source having four laser diodes, and the LD 12 emits light beams from the four laser diodes (LD12a, LD12b, LD12c, LD12d). To do. The optical scanning device 2 is a light receiving element that receives the laser light emitted from the LD 12 and includes a photodiode (hereinafter referred to as PD) 14 that is a detection means. In the laser drive unit 11 disposed in the optical scanning device 2, drive circuits 30a to 30d for driving the LD 12 are provided corresponding to the LDs 12a to LD12d, and the circuit configurations of the drive circuits 30a to 30d are the same. is there. In FIG. 1A, only the drive circuit 30a corresponding to the LD 12a is shown, and the circuit configuration of the drive circuits 30b to 30d corresponding to the LD 12a to LD12d is the same as that of the drive circuit 30a, and thus the display is omitted. Hereinafter, the drive circuit 30a of the LD 12a will be described as an example.

  In order to drive the LD 12a, the laser drive unit 11 includes a drive circuit 30a that is a drive unit, resistors 37a and 39a, and a hold capacitor 38a that is a voltage holding unit. Further, the drive circuit 30a includes a reference voltage (shown as Vref in the figure) 32a, a comparator 31a, switches 33a and 36a, and a VI (voltage-current) conversion circuit (shown as VI conversion in the figure) 34a. And a transistor 35a. The drive circuit 30a receives the light beam from the LD 12a by the PD 14, and performs light amount control for determining the drive current supplied to the LD 12a so that the light amount is constant.

  The laser driving unit 11 and the image control unit 5 of the optical scanning device 2 are connected by a cable 60 composed of a plurality of signal lines. The cable 60 is composed of a wire rod, FFC, or the like. The cable connection signal 50 is used to detect connection between the image control unit 5 and the optical scanning device 2 by looping back the power line of the power source 502 of the image control unit 5 via the optical scanning device 2. The cable connection signal 50 is arranged on the signal lines at both ends of the cable 60, and the LS control unit 501 detects a connection failure due to an oblique insertion of the cable 60 based on the state of the cable connection signal 50.

  An enable signal (hereinafter referred to as an ENB signal) 22 controls the open / close state of the switch 36a in the drive circuit 30a, and closes the switch 36a when it is at a low level to completely discharge the charge of the hold capacitor 38a. A sample / hold signal S / H signal (hereinafter also referred to as a light quantity control signal) 27 operates the drive circuit 30 to perform light quantity control of the LD 12 when it is at a low level. On the other hand, when the S / H signal 27 is at a high level, the drive circuit 30 is operated so as to control the LD 12 according to image data (hereinafter, DATA) 24. The light amount control performed when the S / H signal is at the low level is APC control (Automatic Power Control), and is executed to control the light amount of the laser light emitted from the LD 12 to the target light amount.

  In the APC control, a current corresponding to a charging voltage (hereinafter also referred to as a hold voltage) of the hold capacitor 38a flows to the LD 12a by the VI conversion circuit 34a, and the LD 12a has a light amount corresponding to the current value. A laser beam is emitted. The PD 14 receives the laser beam from the LD 12a, and outputs a current corresponding to the light amount to the drive circuit 30a. The PD 14 is connected to the resistor 37a and the comparator 31a. The current output from the PD 14 flows to the ground via the resistor 37a, and the voltage generated in the resistor 37a is input to the comparator 31a.

  The comparator 31a compares the reference voltage (Vref) 32a with the voltage generated in the resistor 37a, and controls the charging voltage of the hold capacitor 38a based on the comparison result. That is, if the reference voltage 32a is larger than the voltage generated in the resistor 37a, the hold capacitor 38a is charged so that the charging voltage of the hold capacitor 38a increases. On the other hand, when the reference voltage 32a is smaller than the voltage generated in the resistor 37a, the charge is discharged from the hold capacitor 38a so that the charge voltage of the hold capacitor 38a is decreased. The comparator 31a maintains the charging voltage of the hold capacitor 38a when the reference voltage 32a and the voltage generated in the resistor 37a are equal. In this way, the hold capacitor 38a is charged with the hold voltage Vcha, which is a voltage corresponding to the result of the light amount control. The hold voltage Vcha is converted into a drive current for the LD 12a by the VI conversion circuit 34a.

[Timing chart of optical scanning device]
FIG. 1B is a timing chart for explaining the light amount control of the optical scanning device 2 described in FIG. The light beam emitted from the LD 12a is set to a light beam that is detected by the BD (beam detector) 20 (see FIG. 5) to output the BD signal 21. In FIG. 1B, the BD signal 21, ENB signal 22, light amount control signal 27 (S / Ha, S / Hb, S / Hc, S / Hd), image data 24 (DATAa) are sequentially displayed from the top in the vertical axis direction. , DATAb, DATAc, DATAd). Note that S / Ha, S / Hb, S / Hc, and S / Hd in the figure correspond to the light amount control signals 27a, 27b, 27c, and 27d in FIG. 1A, respectively. Further, FIG. 1B shows a voltage waveform of the hold voltage Vcha of the hold capacitor 38a corresponding to the LD 12a, and a light amount waveform indicating the light emission amount of the light beam output from the LD 12a (shown as LDa in the figure). ing. The voltage Vth indicates the light emission start voltage of the LD 12a, and the light amount Po indicates the target light amount. In addition, the horizontal axis indicates time, and TA and TB indicate timing (time). 1B, similarly to FIG. 1A, of the LDs 12a to 12d, the LD 12a will be described as an example.

  In the waveform of the BD signal 21, a period from when it falls to the low level until it falls to the next low level is one cycle in which the optical scanning device 2 scans the photosensitive drum 25 (see FIG. 4) described later. Also, the low level periods of S / Ha, S / Hb, S / Hc, and S / Hd of the light quantity control signal 27 are periods during which the light quantity control of the corresponding LD 12a, LD12b, LD12c, and LD12d is performed.

  In the period up to the timing TA point when the ENB signal 22 is at a low level, the hold capacitor 38a of the LD 12a is discharged, so the hold voltage Vcha is 0V and the LD 12a does not emit light. Subsequently, in a period between the timing TA and the timing TB, the image control unit 5 switches the ENB signal 22 from the low level to the high level. Further, the image control unit 5 sets S / Ha to the low level and DATAa to the low level, and starts the light amount control of the LD 12a. The drive circuit 30a increases the hold voltage Vcha of the hold capacitor 38a when the light amount control of the LD 12a is executed. When the hold voltage Vcha of the hold capacitor 38a exceeds the light emission start voltage Vth at timing TB, the LD 12a starts light emission. The drive circuit 30a controls the hold voltage Vcha of the hold capacitor 38a so that the output light amount of the LD 12a becomes the target light amount Po. When the BD 20 detects the light emission from the LD 12a and outputs the BD signal 21, the light quantity control of each light beam of the LD 12a to LD 12d is sequentially performed.

[Charge of hold capacitor by leakage current]
FIG. 2 is a schematic diagram for explaining the operation of the switch 33a in the drive circuit 30a of FIG. The state of the switch 33a is controlled by a light amount control signal (S / H signal) 27a. When the light quantity control signal 27a is at a low level, the switch 33a is short-circuited, and the hold circuit 38a is charged / discharged by the drive circuit 30a. On the other hand, when the light amount control signal 27a is at a high level, the switch 33a is in an open state, but a minute current flows through the hold capacitor 38a even in the open state. This current is called a leakage current Ileak, and its current value is 1/100 or less of the charge / discharge current. Therefore, in the case of the disconnection of the cable 60, the signal line for transmitting the light amount control signal 27a is not connected, but the hold voltage Vcha of the hold capacitor 38a increases due to the leak current Ileak.

[Abnormal light emission of laser diode due to leakage current]
FIG. 3 shows the light quantity of the LD 12a when one of the signal lines passing through the cable 60 shown in FIG. 1B is broken and the light quantity control signal 27a transmitted through the signal line is not input to the drive circuit 30a. It is a timing chart explaining control. The vertical and horizontal axes in FIG. 3 are the same as those in FIG. Note that TC indicates timing (time). In a section in which the ENB signal 22 up to the timing TA is at a low level, the hold voltage Vcha of the hold capacitor 38a corresponding to the LD 12a is 0 V, and the LD 12a does not emit light. After the timing TA, the image control unit 5 sets the ENB signal 22 to a high level, sets the light amount control signal 27a to a low level, and sets the image data 24 to a low level. However, since the signal line through which the light quantity control signal 27a passes is broken, the light quantity control signal 27a remains at the high level. On the other hand, the hold voltage Vcha of the hold capacitor 38a corresponding to the LD 12a increases due to the above-described leakage current Ileak. As a result, the hold voltage Vcha exceeds the light emission start voltage Vth, and the abnormal light emission of the LD 12a occurs between the timing TB and the timing TC when the image control by the LD 12a is performed based on the data DATAa. .

[Configuration of Image Forming Apparatus]
FIG. 4 is a cross-sectional view illustrating the overall configuration of the electrophotographic image forming apparatus 1 according to the first embodiment. The image forming apparatus 1 includes an optical scanning device 2Y, 2M, 2C, and 2K, an image control unit 5, an image reading unit 500, an image forming unit 506 including photosensitive drums 25Y, 25M, 25C, and 25K, a fixing unit 504, and a paper feed. / Conveyance unit 505. The image reading unit 500 optically reads an image of a document by illuminating the document placed on the document table, and converts the read image into image data (electrical signal) 24. The optical scanning device 2 (2Y, 2M, 2C, 2K) emits light according to the image data 24 and scans the photosensitive drum 25. The image control unit 5 receives the image data 24 from the image reading unit 500 and converts the received image data 24 into an image signal. The image control unit 5 transmits image signals to the optical scanning devices 2Y, 2M, 2C, and 2K, and performs light emission control of the optical scanning devices 2Y, 2M, 2C, and 2K. The subscripts Y, M, C, and K in FIG. 4 indicate configurations corresponding to yellow (Y), magenta (M), cyan (C), and black (K), respectively. In the following, reference numerals are omitted except when referring to a specific photosensitive drum or the like.

  The image forming unit 506 includes four image forming stations P (PY, PM, PC, PK). The four image forming stations P have the same configuration, and along the rotation direction (clockwise direction) of the endless intermediate transfer belt 511, yellow (Y), magenta (M), cyan (C), and black (K). It is arranged in the order. Each of the image forming stations P includes a photosensitive drum 25 that is a photosensitive member that rotates in an arrow direction (counterclockwise direction), and around the photosensitive drum 25 along a rotation direction (counterclockwise direction) A charger 3, a developing device 4, and a cleaning device 7 are arranged.

  The charger 3 uniformly charges the surface of the rotating photosensitive drum 25 with the same potential. The optical scanning device 2 emits a light beam modulated according to an image signal, and forms an electrostatic latent image on the surface of the photosensitive drum 25. The developing device 4 develops the electrostatic latent image formed on the photosensitive drum 25 (on the photosensitive member) by attaching each color toner (developer) to form a toner image. By the primary transfer member 6, the toner image on the photosensitive drum 25 is sequentially superimposed and transferred onto the intermediate transfer belt 511 to form a color image. The cleaning device 7 collects toner remaining on the photosensitive drum 25 without being transferred to the intermediate transfer belt 511.

  The sheet S as a recording medium is conveyed from the paper feed cassette 508 or the manual feed tray 509 of the paper feed / conveyance unit 505 to the secondary transfer roller 510. The secondary transfer roller 510 collectively transfers the toner images on the intermediate transfer belt 511 to the sheet S. The sheet S on which the toner image is transferred is conveyed to the fixing unit 504. The fixing unit 504 heats and pressurizes the sheet S to melt the toner, and fixes the toner image on the sheet S. The sheet S on which the toner image is fixed is discharged to a discharge tray 512.

  The optical scanning device 2 sequentially starts emitting light beams of magenta, cyan, and black images respectively from the emission start timing of the yellow image light beam. By controlling the emission start timing of the optical scanning device 2 in the sub-scanning direction (rotating direction of the photosensitive drum 25), a full-color toner image without color misregistration is formed on the intermediate transfer belt 511.

[Configuration of optical scanning device]
FIG. 5 is a diagram illustrating the configuration of the optical scanning device 2 according to the first embodiment. The optical scanning device 2 includes a laser drive unit 11, an LD 12 as a light source, a collimator lens 13, a PD 14, a cylindrical lens 15, a scanner motor 16, a rotary polygon mirror 16 a, an f-θ lens 17, a reflection mirror 18, and a BD 20. The laser light emitted from the LD 12 travels through the collimator lens 13 and the cylindrical lens 15 to the rotating polygon mirror 16a. In the non-image region, the laser beam L1 is deflected by the rotary polygon mirror 16a and is received by the BD 20 via the f-θ lens 17. When the BD 20 detects the laser light L1, the BD 20 outputs a BD signal 21 that determines the reference position of the image area. On the other hand, based on the BD signal 21, the optical scanning device 2 starts exposure. In the image area, the laser beam L2 is deflected by the rotating polygon mirror 16a, passes through the f-θ lens 17, is reflected by the reflecting mirror 18, and scans on the photosensitive drum 25. Thereby, an electrostatic latent image is formed on the photosensitive drum 25.

[Image control unit, control circuit of optical scanning device]
FIG. 6 is a circuit block diagram illustrating the configuration of the laser drive unit 11 disposed in the optical scanning device 2 of the present embodiment and the image control unit 5 that controls the laser drive unit 11. As in FIG. 1 (a), the LD 12 is a four-beam laser. Also, in FIG. 6, only the drive circuit 30a corresponding to the LD 12a is shown as in FIG. 1A, and the circuit configurations of the drive circuits 30b to 30d corresponding to the LD 12b to LD 12d are the same, and thus the display is omitted. . 6 is the same as the circuit shown in FIG. 1A except that a voltage switching circuit 53 as an output means is added to the optical scanning device 2. Here, the voltage switching circuit 53 will be described, and the description of the circuit configuration similar to that shown in FIG.

  In FIG. 6, a voltage switching circuit 53 is added to the optical scanning device 2. The voltage switching circuit 53 is supplied with charging voltages of the hold capacitors 38a to 38d of the LD 12a, LD 12b, LD 12c, and LD 12d through the buffers 52a to 52d. The LS control unit 501 outputs a switching signal 54 to the voltage switching circuit 53 via the signal line of the cable 60. When the switching signal 54 is input to the voltage switching circuit 53, the voltage switching circuit 53 sets the hold voltage Vch of the designated hold capacitor 38 as the charging voltage 51 in accordance with the switching signal 54 via the signal line and the image control unit 5. To the CPU 503. Thereby, the CPU 503 can detect the hold voltages Vcha, Vchb, Vchc, and Vchd of the hold capacitors 38a to 38d of the LD 12a, LD 12b, LD 12c, and LD 12d. FIG. 6 shows a connection in the case where the voltage switching circuit 53 selects the LD 12 a by the switching signal and outputs the hold voltage Vcha of the hold capacitor 38 a to the CPU 503. Further, it is assumed that the CPU 503 has a timer for measuring time.

  Table 1 is a table showing the relationship between the light amount control of the drive circuit 30 of FIG. 6 and each signal level. In Table 1, when the ENB signal 22 is at a low level (indicated by L in the table, the same applies hereinafter), the hold capacitor 38a is fully discharged. When the ENB signal 22 is at a high level (indicated by H in the table, hereinafter the same), the following control is performed according to the state of the light quantity control signal 27 and the image data (DATA) 24. When the light quantity control signal 27 is at a low level and the DATA 24 is at a low level, the light quantity control of the LD 12 is performed. When the light amount control signal 27 is at a low level and the DATA 24 is at a high level, the LD 12 is turned off. When the light amount control signal 27 is at a high level, the control of the LD 12 according to the low level of the DATA 24 or the high level, that is, data output (constant current) is performed.

[Hold voltage of hold capacitor and operating state of optical scanning device]
FIG. 7 is a graph showing the time transition of the hold voltage Vch of the hold capacitor 38 in the operating state of the LD 12. The horizontal axis in FIG. 7 indicates an elapsed time T after the scanner motor 16 is activated and the laser driving unit 11 starts operating. In the figure, T1, T1 ′, and T2 indicate timing (time), and details will be described later. The vertical axis in FIG. 7 indicates the hold voltage Vch of the hold capacitor 38. The target value shown on the vertical axis is the convergence value of the hold voltage Vch of the hold capacitor 38 with respect to the target light quantity at the time of light quantity control of the LD 12. The standard upper limit value and the standard lower limit value are the upper limit voltage value and the lower limit voltage value in the standard determined in consideration of the variation of the target value with respect to the target light amount, and indicate the voltage value within the allowable range. The standard upper limit value is a voltage value of the hold voltage Vch corresponding to the maximum light quantity at the time of light quantity control of the LD 12, and the standard lower limit value is also a voltage value of the hold voltage Vch corresponding to the minimum light quantity at the time of light quantity control of the LD 12. Good. The output limit value is the maximum value (limit value) of the hold voltage Vch determined by the characteristics of the drive circuit 30.

  In FIG. 7, a graph A indicated by a solid line is a graph showing a change in the hold voltage Vch of the hold capacitor 38 when the drive circuit 30a is normal. On the other hand, a graph A ′ indicated by a broken line is a graph showing a change in the hold voltage Vch of the hold capacitor 38 when the PD 14 that measures the amount of light when the LD 12 a emits light is abnormal. In the graph A and the graph A ′, the hold voltage Vch is charged with a predetermined current until the target value is reached. Therefore, the hold voltage Vch of the graph A and the graph A ′ increases with the same slope. However, in the normal graph A, when the hold voltage Vch increases to the target value, it does not increase any more and converges to the target value. On the other hand, in the case of the graph A ′, the output from the PD 14 is not fed back to the drive circuit 30 due to the abnormality of the PD 14, so the hold voltage Vch exceeds the target value and increases to the output limit value. Regarding the hold voltages Vchb to Vchd of the hold capacitors 38b to 38d of the LDs 12b to LD12d, a graph B indicated by a solid line is a graph showing changes in the hold voltages Vchb to Vchd when the drive circuits 30b to 30d are normal. On the other hand, a graph B ′ indicated by a broken line is a graph showing changes in the hold voltages Vchb to Vchd when the PD 14 is abnormal. By the way, the slope of the straight line (dV / dT) indicating the change rate of the hold voltage Vch in the graphs A and A ′ is larger than the slope of the straight line in the graphs B and B ′. This is because the LD 12a continuously controls the amount of light so that the BD 20 detects the light beam from the LD 12a and outputs the BD signal 21 (see FIG. 1B).

  On the other hand, as described with reference to FIG. 2, in the graph C showing the case where the signal line through which the light amount control signal 27 of the cable 60 passes is disconnected, the hold state of the hold capacitor 38 is held without performing the light amount control of the LD 12. . For this reason, the hold voltage Vch of the hold capacitor 38 gradually increases due to the leakage current Ileak described above. By the way, the current value of the leakage current Ileak is 1/100 or less of the charging current. Therefore, the change rate (dV / dT) of the hold voltage Vch in the graph C is significantly smaller than the change rate of the hold voltage Vch in the graphs A and A ′ and the graphs B and B ′. When the drive circuit 30 is abnormal, the hold voltage Vch of the hold capacitor 38 remains 0 V as shown in the graph D regardless of the control mode. Therefore, in the case of graphs C and D, changes (ΔVch1, ΔVchn in the figure) of the hold voltage Vch in a predetermined time (period) (T1 to T2, T1 ′ to T2) are calculated. The timing T2 is a timing at which the hold voltage Vch of the hold capacitor 38 becomes higher than the standard lower limit value due to the leak current Ileak. Based on the calculated voltage change of the hold voltage Vch, the disconnection of the signal line through which the light amount control signal 27 passes or the abnormality of the drive circuit 30 can be detected.

[Control sequence for optical scanning device abnormality detection]
FIG. 8 is a flowchart showing a control sequence for detecting an abnormality of the optical scanning device 2. The process shown in FIG. 8 is started when the laser driving unit 11 starts operating by the activation of the scanner motor 16 and is executed by the CPU 503 of the image control unit 5. Note that times T1, T1 ′, and T2 in the flowchart of FIG. 8 indicate the timings T1, T1 ′, and T2 shown in FIG. In FIG. 8, LD12a and LD12b to LD12d are denoted as LDa and LDb to LDd, respectively. Similarly, the charging voltages Vch of the hold capacitors 38a, 38b to 38d are described as Vcha and Vchb to Vchd, respectively.

  In step (hereinafter referred to as S) 101, the CPU 503 drives the scanner motor 16 in order to activate the laser driving unit 11 of the optical scanning device 2. Further, the CPU 503 resets and starts the timer. In S102, the CPU 503 refers to the timer and determines whether or not a time T1 (first timing) for acquiring the charging voltage Vcha of the hold capacitor 38a of the LD 12a has elapsed. If the CPU 503 determines that the time T1 has elapsed, it advances the process to S103, and if it determines that the time T1 has not elapsed, it returns the process to S102. The time T1 is a time (for example, approximately several tens of μsec to several hundreds of msec) exceeding the upper limit value when the hold voltage Vcha of the hold capacitor 38a increases at the rate of change shown in the graph A ′ of FIG. Shall be set. In S103, the CPU 503 outputs the switching signal 54 to the voltage switching circuit 53 of the laser driving unit 11 via the signal line of the cable 60, and the charging voltage Vcha of the hold capacitor 38a of the LD 12a is supplied from the voltage switching circuit 53 to the charging voltage. 51 is obtained via a signal line.

  In S104, the CPU 503 determines whether or not the acquired charging voltage Vcha of the hold capacitor 38a is higher than the standard upper limit value (see FIG. 7) (charging voltage Vcha> standard upper limit value). If the CPU 503 determines that the charging voltage Vcha is higher than the standard upper limit value, the process proceeds to S109, and if the CPU 503 determines that the charging voltage Vcha is lower than the standard upper limit value, the process proceeds to S105. In S105, the CPU 503 refers to the timer and determines whether or not a time T1 ′ (first timing) for acquiring the charging voltages Vchb to Vchd of the hold capacitors 38b to 38d of the LDs 12b to LD12d has elapsed. If the CPU 503 determines that the time T1 'has elapsed, it proceeds to S106, and if it determines that the time has not elapsed, it returns the process to S105. The time T1 ′ is set to a time exceeding the upper limit of the standard when the hold voltages Vchb to Vchd of the hold capacitors 38b to 38d rise at the rate of change shown in the graph B ′ of FIG. And the light amount control time for each cycle.

  In S <b> 106, the CPU 503 outputs the switching signal 54 to the voltage switching circuit 53 of the laser driving unit 11 via the signal line of the cable 60. Then, the CPU 503 sequentially acquires the charging voltages Vchb to Vchd of the hold capacitors 38b to 38d of the LD12b to LD12d as the charging voltage 51 from the voltage switching circuit 53 via the signal line. In S107, the CPU 503 determines whether or not the charging voltage Vcha of the hold capacitor 38a acquired at time T1 is within the standard, that is, whether or not the standard lower limit value or more. Further, the CPU 503 determines whether or not the charging voltages Vcha to Vchd of the hold capacitors 38b to 38d acquired at time T1 'are within the standard, that is, not less than the standard lower limit value and not more than the standard upper limit value (see FIG. 7). When the CPU 503 determines that the four charging voltages Vcha to Vchd are all within the standard, it determines that the cable 60 is normal and the optical scanning device 2 is also normal, and ends the process. On the other hand, if the CPU 503 determines that the acquired four charging voltages Vcha to Vchd include a charging voltage less than the standard lower limit value or a charge voltage exceeding the standard upper limit value, the process proceeds to S108. Proceed.

  In S <b> 108, the CPU 503 determines whether or not a charging voltage exceeding the standard upper limit value is acquired among the acquired charging voltages Vchb to Vchd of the hold capacitors 38 b to 38 d. If the CPU 503 determines that a charging voltage exceeding the standard upper limit value has been acquired, the process proceeds to S109. If the CPU 503 determines that a charging voltage exceeding the standard upper limit value has not been acquired, the process proceeds to S110. . In S109, the CPU 503 determines that the cause of the charge voltage Vch of the hold capacitor 38 exceeding the standard upper limit value is the abnormality of the PD 14. Then, the CPU 503 sets the LD 12 detected that the charging voltage Vch of the hold capacitor 38 exceeds the standard upper limit value as circuit abnormality information, and advances the process to S117.

  In S110, the CPU 503 stores, in the memory, the charge voltage value of the hold capacitor 38 of the LD 12 whose acquired charge voltage Vch is less than the standard lower limit value (non-standard) in the process of S107. In S111, the CPU 503 refers to the timer, and whether or not the time T2 (second timing) for acquiring again the charge voltage Vch of the hold capacitor 38 in which the charge voltage Vch was less than the standard lower limit has elapsed in the process of S107. to decide. If the CPU 503 determines that the time T2 has elapsed, it proceeds to S112, and if it determines that the time T2 has not elapsed, it returns the process to S111. The time T2 is generally in the range of several seconds to several tens of seconds, and is set according to the characteristics of the leakage current Ileak of the drive circuit 30. In S <b> 112, the CPU 503 outputs the switching signal 54 to the voltage switching circuit 53 of the laser driving unit 11 via the signal line of the cable 60. Then, the CPU 503 sequentially obtains the charging voltage Vch of the non-standard hold capacitor 38 stored in the memory as the charging voltage 51 through the signal line in the process of S110 sequentially from the voltage switching circuit 53.

  In S113, the CPU 503, for each non-standard hold capacitor 38, the charging voltage value stored in the memory (charging voltage value at time T1 or T1 ′) and the charging voltage value acquired in S112 (charging voltage at time T2). Value), a voltage rise value (voltage change) is calculated. In S114, the CPU 503 determines whether or not the voltage difference that is the voltage increase value (voltage change) calculated in S113 is equal to or higher than the error identification voltage Verr for identifying whether the voltage is increased due to the leakage current Ileak (calculated voltage change ≧ Verr). )to decide. If the CPU 503 determines that the voltage increase value is greater than or equal to the error identification voltage Verr (a predetermined voltage difference or more), the CPU 503 advances the process to S115 and determines that the voltage increase value is less than the error identification voltage Verr. Advances the process to S116.

  In S <b> 115, the CPU 503 determines that the cause of the charge voltage Vch of the hold capacitor 38 being less than the standard lower limit value is the disconnection of the signal line of the light quantity control signal 27. Then, the CPU 503 sets the LD 12 detected that the charging voltage Vch of the hold capacitor 38 is less than the standard lower limit value as circuit abnormality information, and advances the process to S117. In S <b> 116, the CPU 503 determines that the cause that the charging voltage Vch of the hold capacitor 38 is less than the standard lower limit value is an abnormality of the drive circuit 30. Then, the CPU 503 sets the LD 12 detected that the charging voltage Vch of the hold capacitor 38 is less than the standard lower limit value as circuit abnormality information, and advances the process to S117. In S117, the CPU 503 forcibly turns off the LDs 12a to LD12d by discharging the hold capacitors 38a to 38d of the LDs 12a to LD12d of the optical scanning device 2. Further, the CPU 503 notifies the occurrence of abnormality based on the information of the LD 12 set in the circuit abnormality information, and ends the process.

  As described above, in this embodiment, a circuit for acquiring the charging voltage Vch of the hold capacitor 38 corresponding to each LD 12 is added to the laser driving unit 11 of the optical scanning device 2. Thereby, based on the acquired charging voltage Vch, an abnormality in the laser drive unit 11 and the cable 60 is detected, and an abnormality factor such as an abnormality in the PD 14, a disconnection of the signal line, an abnormality in the drive circuit 30 that drives the LD 12 is specified. can do.

  As described above, according to this embodiment, it is possible to detect an abnormality of the semiconductor laser with a simple configuration.

  In the first embodiment, a semiconductor laser (LD) capable of emitting four beams is used. In the second embodiment, an embodiment using a semiconductor laser capable of emitting eight beams will be described. Further, in the second embodiment, in order to shorten the time required for charging the hold capacitor, a forced charging circuit that shortens the convergence time of the light amount control by applying a preset voltage to the hold capacitor is added to the optical scanning device. Examples will be described. The image forming apparatus according to the second embodiment is the same as the image forming apparatus 1 according to the first embodiment. The same reference numerals are used for the same components, and the description thereof is omitted here.

[Image control unit, control circuit of optical scanning device]
FIG. 9 is a circuit block diagram illustrating the configuration of the laser driving unit 11 disposed in the optical scanning device 2 of the present embodiment and the image control unit 5 that controls the laser driving unit 11. In this embodiment, unlike FIG. 6 of the first embodiment, the optical scanning device 2 is assumed to be equipped with an LD 12 (LD12a to LD12h) of an 8-beam laser. 9 also shows only the drive circuit 30a corresponding to the LD 12a and the circuit configurations of the drive circuits 30b to 30h corresponding to the LD 12b to LD 12h are the same as in FIG. 6 of the first embodiment. Omitted.

  In FIG. 9, the following circuit configuration is added compared to FIG. 6 of the first embodiment. That is, since an 8-beam laser is used for the semiconductor laser 12 (LD12), an APC CH (channel) control circuit 55 which is a circuit for designating a beam and a channel switching signal 29 which is a signal for designating a beam are provided. Have been added. The channel switching signal 29 is composed of three signals 29a (CHSELa), 29b (CHSELb), and 29c (CHSELc), and the laser beam to be emitted depends on the combination of the high level and low level of each signal. It is specified. The APC CH control circuit 55 outputs light amount control signals S / Ha to S / Hh according to the designated light beam.

  In addition, a forced charging circuit 57a (indicated as “forced charging” in the figure) is provided in order to perform forced charging to shorten the convergence time of light quantity control by applying a preset voltage to the hold capacitor 38a described above. . The forced charging circuit 57a, which is a voltage setting means, applies a preset charging voltage Vfchg (predetermined voltage) to the hold capacitor 38a. The LS control unit 501 of the image control unit 5 transmits the voltage value of the charging voltage Vfchg to the SIO (serial I / O) module 58 by the serial communication signal 59. The SIO module 58 sets the voltage value of the received charging voltage Vfchg in the forced charging circuit 57a. In FIG. 9, a switch 56a is added. The switch 56a is connected to the switch 36a when the ENB signal 22 is at a high level and the FCHG signal 28, which is a forcible charge signal, is at a high level. The connection state is set so that is connected.

  In addition, the LS control unit 501 of the image control unit 5 transmits a switching signal designating the target LD 12 to the SIO module 58 by the serial communication signal 59 in order to acquire the hold voltage Vch of the hold capacitor 38. The SIO module 58 switches the hold voltage Vch of the hold capacitor 38 output from the voltage switching circuit 53 according to the received switching signal. In FIG. 6 of the first embodiment, the resistor 37a is a variable resistor. However, in this embodiment, the resistor 37a is replaced with an electronic volume (EVR). The other circuit configuration of FIG. 9 is the same as that of FIG. 6 of the first embodiment, and the same reference numerals are given to the same circuit configuration to omit the description here.

[Control sequence for optical scanning device abnormality detection]
FIG. 10 is a timing chart for explaining the light amount control of the optical scanning device 2 shown in FIG. The optical scanning device 2 is equipped with an LD 12 that can emit 8 beams of laser light. In FIG. 10, the signal waveforms of the BD signal 21, the ENB signal 22, the channel switching signal 29 (CHSELa, CHSELb, and CHSELc) and the image data 24 (DATAa to DATAh) are shown in order from the top in the vertical axis direction. Note that CHSELa, CHSELb, and CHSELc correspond to channel switching signals 29a, 29b, and 29c, respectively. Further, FIG. 10 shows a voltage waveform of the hold voltage Vcha of the hold capacitor 38a corresponding to the LD 12a, and a light amount waveform indicating the light emission amount of the light beam output from the LD 12a (indicated as LDa in the figure). The voltage Vth indicates the light emission start voltage of the LD 12a, the voltage Vfchg indicates the above-described forced charging voltage, and the light amount Po indicates the target light amount. The horizontal axis indicates time, and TA, TB, and TC indicate timing (time). In FIG. 10 as well, similarly to FIG. 1A, the LD 12a among the LDs 12a to 12h will be described as an example.

  In the waveform of the BD signal 21, a period from when it falls to the low level until it falls to the next low level is one cycle in which the optical scanning device 2 scans the photosensitive drum 25. The ENB signal (enable signal) 22 closes the connected switch 36a and discharges the hold capacitor 38a completely. At this time, the switch 56a is connected to the ground side. When the light quantity control signal (S / H) 27 is at a low level, one of the LDs 12a to 12h is selected according to the channel switching signal 29 (CHSELa to CHSELc). Then, the drive circuit 30 selected from the drive circuits 30a to 30h operates so as to perform light amount control together with the image data 24 (DATAa to DATAh). In this embodiment, in order to suppress an increase in the number of signal lines due to the 8-beam laser, the configuration of the control signal is the ENB signal 22, the light amount control signal 27, and the three channel switching signals 29a to 29c.

  Table 2 is a table showing the relationship between the light amount control of the drive circuit 30 of FIG. 9 and each signal level. In Table 2, when the ENB signal 22 is at a low level (indicated by L in the table, the same applies hereinafter), the hold capacitor 38 is fully discharged. When the ENB signal 22 is at a high level (indicated by H in the table, the same applies hereinafter), the light quantity control signal 27, the channel switching signal 29 for designating the LD 12 to be controlled, and the state of the image data (DATA) 24 The following control is performed. When the light quantity control signal 27 is at a low level and the image data 24 is at a low level, the light quantity control of the LD 12 (LD 12a to LD 12h) is performed according to the channel switching signal 29. When the light amount control signal 27 is at a low level and the image data 24 is at a high level, the LD 12 is turned off. When the light quantity control signal 27 is at a high level, regardless of the low level or the high level of the channel switching signal 29, the LD 12 is controlled according to the low level or the high level of the image data 24, that is, data output (constant current). Is done.

  As shown in FIG. 10, the LD 12 a detects a BD 20 and emits a light beam for outputting a BD signal 21. In the period up to the point TA when the ENB signal 22 is at the low level, the hold voltage Vcha of the hold capacitor 38a of the LD 12a is 0V, and the LD 12a does not emit light. Subsequently, in a period between the timing TA and the timing TB, the image control unit 5 switches the ENB signal 22 from the low level to the high level. Further, when the image controller 5 sets the FCHG signal 28, which is a forced charging signal, from a low level to a high level, the voltage Vfchg from the forced charging circuit 57a is applied to the hold capacitor 38a of the LD 12a via the switch 36a. The

  At timing TB, the image control unit 5 sets the FCHG signal 28 from the high level to the low level, and sets the light amount control signal 27 from the high level to the low level while keeping the ENB signal 22 at the high level. As a result, the LD 12 that performs light amount control is selected according to the low level and high level states of the three signals CHSELa, CHSELb, and CHSELc of the channel switching signal 29, and the LD 12a is selected at the timing TB. At timing TB, the drive circuit 30a starts light amount control of the LD 12a, and raises the hold voltage Vcha of the hold capacitor 38a from the voltage Vfchg. When the hold voltage Vcha of the hold capacitor 38a exceeds the light emission start voltage Vth at timing TC, the LD 12a starts light emission. The drive circuit 30a controls the hold voltage Vcha of the hold capacitor 38a so that the output light amount of the LD 12a becomes the target light amount Po. When the BD 20 detects the light beam emitted from the LD 12a, the BD signal 21 is output, and the light amount control of each light beam of the LD 12a to LD 12h is sequentially performed.

[Hold voltage of hold capacitor and operating state of optical scanning device]
FIG. 11 is a graph showing the time transition of the hold voltage Vch of the hold capacitor 38 in the operating state of the LD 12. The horizontal axis in FIG. 11 indicates an elapsed time T after the scanner motor 16 is started and the laser driving unit 11 starts operating. In the figure, T1, T1 ′, T1 ″, and T2 indicate timing (time). The vertical axis in FIG. 11 indicates the hold voltage Vch of the hold capacitor 38. The target value, the standard upper limit value, the standard lower limit value, and the output limit value shown on the vertical axis are the same as those in FIG. 7 of the first embodiment, and a description thereof is omitted here. The forced charging voltage indicates the voltage Vfchg applied to the hold capacitor 38 by the forced charging circuit 57, and is a voltage value that is higher than the standard lower limit value and lower than the target value (standard lower limit value <forced charging voltage). <Target value).

  In FIG. 11, a graph A indicated by a solid line and a graph A ′ indicated by a broken line, a graph B indicated by a solid line and a graph B ′ indicated by a broken line, a graph C indicated by a solid line, and a graph D indicating that the hold voltage Vch of the hold capacitor 38 is 0V. These are the same as FIG. 7 of the first embodiment. Further, the method for detecting a failure of the optical scanning device 2 based on the graphs A, A ′, B, B ′, C, and D is the same as that in FIG. 7 of the first embodiment, and the description thereof is omitted here. .

  A graph C ′ indicated by a solid line indicates the charging voltage Vch of the hold capacitor 38 when the charging is not performed up to the forced charging voltage by the forced charging circuit 57. When the forced charging circuit 57 does not charge the battery to the forced charging voltage, the hold voltage Vch starts to increase from 0V. The timing T1 ″ is set to a timing (time) shorter than the time required for the hold voltage Vch to exceed the standard lower limit when charging is started from 0V. A timing T1 ″ illustrated in FIG. 11 indicates a timing at which the hold voltages Vchb to Vchh of the hold capacitors 38b to 38h corresponding to the LDs 12b to LD12h are acquired. As described above, the hold voltage Vcha of the hold capacitor 38a of the LD 12a rises faster than the hold voltages Vchb to Vchh of the hold capacitors 38b to 38h. Therefore, when acquiring the hold voltage Vcha of the hold capacitor 38a, it is necessary to acquire the hold voltage Vcha at a timing earlier than the timing T1. The forced charging failure state shown in the graph C ′ occurs, for example, when the FCHG signal 28 is not transmitted due to the disconnection of the cable 60 or the like, and as a result, forced charging is not performed. In such a case, charging of the hold capacitor 38 starts from 0 V, and the charging voltage Vch of the hold capacitor 38 is acquired during the time required to charge up to the standard lower limit value. If the acquired charging voltage Vch is lower than the standard lower limit voltage, it can be determined that the forced charging is defective.

[Control sequence for optical scanning device abnormality detection]
FIG. 12 is a flowchart showing a control sequence for detecting an abnormality in the optical scanning device 2. The process shown in FIG. 12 is started when the laser driving unit 11 starts operating by the activation of the scanner motor 16 and is executed by the CPU 503 of the image control unit 5. Note that times T1, T1 ′, T1 ″, and T2 in the flowchart of FIG. 12 indicate the timings T1, T1 ′, T1 ″, and T2 shown in FIG. In FIG. 12, LD12a and LD12b to LD12h are described as LDa and LDb to LDh, respectively. Furthermore, in FIG. 12, the charging voltages of the hold capacitors 38a, 38b to 38h are described as Vcha and Vchb to Vchh, respectively.

  The processes of S201 to S204 are the same as the processes of S101 to S104 of FIG. 8 of the first embodiment, and the description thereof is omitted here. In S205, the CPU 503 refers to the timer and determines whether or not a time T1 ″ (third timing) for acquiring the charging voltages Vchb to Vchh of the hold capacitors 38b to 38h of the LD12b to LD12h has elapsed. If the CPU 503 determines that the time T1 ″ has elapsed, the process proceeds to S206, and if it determines that the time has not elapsed, the CPU 503 returns the process to S205. The time T1 ″ is shorter than the time required for the hold voltages Vchb to Vchh of the hold capacitors 38b to 38h to exceed the standard lower limit value when charging is started from 0V, not from the forced charging voltage. Shall be set. The time T1 ″ is the timing for acquiring the hold voltages Vchb to Vchh of the hold capacitors 38b to 38h. Therefore, the time T1 ″ is a time later than the time T1, and is earlier than the times T1 ′ and T2 described later (time T1 <time T1 ″ <time T1 ′ <time T2). ). Although not executed in the process shown in FIG. 12, the time T1 ″ when acquiring the hold voltage Vcha of the hold capacitor 38a is earlier than the time T1. In S <b> 206, the CPU 503 transmits a switching signal using the serial communication signal 59 to the SIO module 58 via the signal line of the cable 60. The SIO module 58 outputs the received switching signal to the voltage switching circuit 53 of the laser driving unit 11. Then, the CPU 503 sequentially acquires the charging voltages Vchb to Vchh of the hold capacitors 38 b to 38 h of the LD 12 b to LD 12 h from the voltage switching circuit 53 as the charging voltage 51 via the signal line.

  The processes of S207 to S208 are the same as the processes of S105 to S106 of FIG. 8 of the first embodiment, and the description thereof is omitted here. In S209, the CPU 503 determines whether or not the charging voltage Vcha of the hold capacitor 38a acquired at time T1 is equal to or higher than the standard lower limit value. Further, the CPU 503 determines whether or not the charging voltages Vchb to Vchh of the hold capacitors 38b to 38h acquired at time T1 'are equal to or higher than the standard lower limit value and lower than the standard upper limit value (see FIG. 11). When the CPU 503 determines that the eight charging voltages Vcha to Vchh are within the standard, that is, the charging voltage Vcha is not less than the standard lower limit value and the charge voltages Vchb to Vchh are not less than the standard lower limit value and not more than the standard upper limit value, The process proceeds to S210. On the other hand, if the CPU 503 determines that a charging voltage less than the standard lower limit value or a charging voltage exceeding the standard upper limit value is acquired from the eight charging voltages Vcha to Vchh, the process proceeds to S211.

  In S210, the CPU 503 determines whether or not the charging voltages Vchb to Vchh of the hold capacitors 38b to 38h acquired at time T1 ″ are within the standard, that is, a voltage value equal to or higher than the standard lower limit value. If the CPU 503 determines that the charging voltages Vchb to Vchd are equal to or higher than the standard lower limit value, the CPU 503 determines that the cable 60 is normal and the optical scanning device 2 is also normal, and ends the process. . On the other hand, when the CPU 503 determines that the charging voltage Vchb to Vchd includes a voltage value less than the standard lower limit value, the cause of the fact that the charging voltage of the hold capacitor 38 is lower than the forced charging voltage is as follows. It is assumed that the signal line is disconnected, and the process proceeds to S218.

  The processes of S211 to S217, S219, and S220 are the same as the processes of S108 to S114, S116, and S117, respectively, and description thereof is omitted here. In S218, the CPU 503 determines that the cause that the charging voltage Vch of the hold capacitor 38 is lower than the forced charging voltage is the disconnection of the signal line of the FCHG signal 28 or the abnormality of the forced charging circuit 57. Then, the CPU 503 sets disconnection of the signal line of the FCHG signal 28 or abnormality of the forced charging circuit 57 as circuit abnormality information, and advances the processing to S220. Further, the CPU 503 determines that the cause of the charge voltage Vch of the hold capacitor 38 being less than the standard lower limit value is the disconnection of the signal line of the channel switching signal 29. Further, the CPU 503 specifies a signal line in which the channel switching signal 29 is disconnected based on the LD 12 whose charging voltage Vch of the hold capacitor 38 is less than the standard lower limit value. Then, the CPU 503 sets information on the identified signal line as circuit abnormality information, and advances the processing to S220. For example, if the LD 12 whose charging voltage Vch of the hold capacitor 38 is less than the standard lower limit is the LD 12a to LD 12d, the CPU 503 determines that the signal line of CHSELc is disconnected. Further, for example, when the LD 12 whose charge voltage Vch of the hold capacitor 38 is less than the standard lower limit value is the LD 12a, LD12b, LD12e, LD12f, the CPU 503 determines that the signal line of the CHSELb is disconnected. Further, for example, when the LD 12 whose charging voltage Vch of the hold capacitor 38 is less than the standard lower limit is the LD 12a, LD 12c, LD 12e, or LD 12g, the CPU 503 determines that the signal line of the CHSELc is disconnected.

  In the present embodiment, a forced charging circuit 57 is provided in the laser drive unit 11 of the optical scanning device 2 of the first embodiment in order to shorten the charging time of the hold capacitor 38. By measuring the charging voltage Vch of each hold capacitor 38 at a predetermined timing and judging whether it is lower than the standard lower limit value, the disconnection of the signal line through which the FCHG signal 28 instructing forced charging passes or the forced charging circuit 57 Abnormality can be detected. As described above, in the second embodiment, as in the first embodiment, the abnormality of the laser driving unit 11 and the cable 60 is detected based on the acquired charging voltage Vch, and the abnormality of the PD 14, the disconnection of the signal line, and the LD 12 are driven. It is possible to specify an abnormality factor of an abnormality such as the drive circuit 30 to be performed.

  As described above, according to this embodiment, it is possible to detect an abnormality of the semiconductor laser with a simple configuration.

2 Optical Scanning Device 12 Semiconductor Laser 14 Photodiode 30 Drive Circuit 38 Hold Capacitor 503 CPU

Claims (12)

A light source that outputs a light beam having a light amount corresponding to the supplied drive current;
Detecting means for detecting the light amount of the light beam output from the light source;
Voltage holding means for holding a voltage for supplying the driving current;
The voltage held by the voltage holding means is controlled to adjust the light quantity of the light beam detected by the detecting means to a target light quantity, and a driving current corresponding to the voltage held by the voltage holding means is applied to the light source. Driving means for supplying and driving the light source;
An optical scanning device having
Control means for controlling the optical scanning device;
With
The control means detects an abnormality of the optical scanning device based on the voltage held in the voltage holding means acquired at the first timing after starting the driving means, and detects the detected abnormality. An image forming apparatus characterized by identifying a factor.   The control means determines that the detection means is abnormal when the voltage held in the voltage holding means acquired at the first timing is larger than a voltage allowable range corresponding to the target light quantity. The image forming apparatus according to claim 1, wherein the image forming apparatus is detected.   The first timing is a timing that is later than a timing at which a light amount of the light beam output from the light source converges to the target light amount when the detection unit is normal. The image forming apparatus described.   When the voltage held in the voltage holding means acquired at the first timing is smaller than the allowable voltage range according to the target light amount, the control means outputs a second time later than the first timing. The image forming apparatus according to claim 3, wherein the voltage held by the voltage holding unit is acquired at a timing of 2.   The control means has a predetermined voltage difference between a voltage held in the voltage holding means acquired at the first timing and a voltage held in the voltage holding means acquired at the second timing. 5. The image forming apparatus according to claim 4, wherein the image forming apparatus detects that the driving unit is abnormal when the driving unit is smaller. The control means is connected to the optical scanning device via a cable, and outputs a first signal for starting the driving means to the optical scanning device via the cable,
When the voltage difference between the voltage held in the voltage holding means acquired at the first timing and the voltage held in the voltage holding means acquired at the second timing is greater than or equal to a predetermined voltage difference The image forming apparatus according to claim 4, wherein the disconnection of the cable is detected.   The image forming apparatus according to claim 6, wherein the voltage held by the voltage holding unit rises due to a leakage current when the driving unit is not activated.   8. The second timing according to claim 7, wherein the voltage held in the voltage holding means is a timing at which the voltage held by the leakage current has risen to an allowable voltage range corresponding to the target light amount. Image forming apparatus. The driving means has voltage setting means for setting the voltage held in the voltage holding means to a predetermined voltage in accordance with the second signal output from the control means,
The image forming apparatus according to claim 8, wherein the control unit outputs the second signal to the optical scanning device via the cable before outputting the first signal. The control means outputs the first signal after outputting the second signal, and then acquires the voltage held in the voltage holding means at a third timing earlier than the first timing. ,
The detected voltage held by the voltage holding means is smaller than the predetermined voltage, and it is detected that the voltage setting means is abnormal or the cable is disconnected. The image forming apparatus described in 1. The light source has a plurality of laser diodes that output the light beam,
The said 1st timing, the said 2nd timing, and the said 3rd timing are determined according to the timing at which the said light beam is output from each said laser diode. Image forming apparatus. The voltage holding means and the driving means are provided corresponding to a plurality of the laser diodes,
12. The image according to claim 11, wherein the optical scanning device includes an output unit that outputs a voltage held in the voltage holding unit designated by the control unit among the plurality of voltage holding units. Forming equipment.

Images