JP2019208976A - Game machine - Google Patents

Abstract

To simplify a device configuration as much as possible and reduce the control burden on a CPU.SOLUTION: A game machine includes a composite chip 40 in which a built-in host CPU 50, an image processor 51, and an audio processor 52 are housed. When the built-in host CPU 50 writes first information including the register number to a first relay register MCR and writes second information including the set value to a second relay register MCD, transfer data in which the register number and the set value are to be one set is stored in an audio command buffer 83. The audio processor 52 functions every predetermined operation cycle, reads the audio command buffer 83, and executes a setting operation based on an instruction from the built-in host CPU 50.SELECTED DRAWING: Figure 9

Description

  The present invention relates to a gaming machine that performs a lottery process resulting from a gaming operation and executes an image effect corresponding to the lottery result.

  A ball game machine such as a pachinko machine has a symbol start opening provided on the game board, a symbol display section for displaying a series of symbol variation patterns by a plurality of display symbols, and a big winning opening for opening and closing the opening and closing plate. Configured. When the detection switch provided at the symbol start port detects the passage of the game ball, the winning state is entered, and after the game ball is paid out as a prize ball, the display symbol is changed for a predetermined time in the symbol display section. Thereafter, when the symbol is stopped in a predetermined manner such as 7, 7, 7, etc., a big hit state is established, and the big winning opening is repeatedly opened to generate a gaming state advantageous to the player.

  Whether or not to generate such a gaming state is determined by a jackpot lottery executed on condition that a game ball wins at the symbol start opening, and the above symbol variation operation is based on the lottery result. It has become a thing. For example, when the lottery result is in a winning state, an effect operation called reach action or the like is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, a similar reach action may be executed even in the case of a lost state. In this case, the player pays close attention to the big hit state and pays close attention to the transition of the performance operation. When the predetermined symbols are aligned on the stop line at the end of the symbol variation operation, the player is guaranteed to be in the big hit state.

  In this type of gaming machine, there is a strong demand for simplifying the equipment configuration and reducing the control burden of the CPU while increasing the variety of effects.

  The present invention has been made in view of the above-described problems, and an object thereof is to provide a gaming machine in which the device configuration is extremely simplified and the control burden on the CPU is reduced.

  In order to achieve the above object, the present invention provides one or a plurality of effects based on an effect control means (50) having a host CPU for uniformly controlling image effects and sound effects, and a command list received from the effect control means. An image generation means (51) for generating image data for each frame of the display device and executing an image effect, and an audio signal is generated based on an instruction received from the effect control means, and a speaker is driven to generate an audio An audio control means (52) for executing an effect is a gaming machine configured to have a composite chip with a built-in instruction, and an instruction received from the effect control means specifies a built-in register of the sound control means A register number and a set value for the built-in register specified by the register number, and the effect control means transmits the first information including the register number to the first relay register. When the second information including the set value is written to the second relay register, a set of transfer data including the register number and the set value is stored in a predetermined voice command buffer. The voice control unit is configured to function every predetermined operation cycle, read the voice command buffer, and execute a setting operation based on an instruction received from the effect control unit.

  According to the above-described gaming machine of the present invention, since it has the composite chip that incorporates the effect control means, the image generation means, and the sound control means, the device configuration is simplified, and the CPU has the first and second relay registers. Since only access is required, the control burden on the CPU is greatly reduced.

It is a perspective view of the pachinko machine shown in an example. It is the front view which illustrated the game board of the pachinko machine of FIG. It is a block diagram which shows the whole structure of the pachinko machine of an Example. It is a block diagram illustrating a circuit configuration of an effect control unit. It is drawing explaining the internal structure of a composite chip | tip. It is a figure explaining issue and execution of a drawing command list. It is another drawing explaining issue and execution of a drawing command list. It is drawing explaining operation | movement of the sound engine (voice processor) built in the composite chip. It is a figure explaining the procedure in which a host CPU controls a sound engine. It is drawing explaining the operation | movement outline | summary of a host CPU, a DMA controller, and a serial port. It is drawing explaining the internal structure and operation | movement of a lamp driver. It is drawing explaining operation | movement of a motor driver and a signal acquisition circuit. It is drawing explaining the serial transmission operation | movement to a lamp driver. It is drawing explaining another serial transmission operation | movement to a lamp driver. It is a flowchart explaining the main operation | movement of an effect control part. It is a flowchart explaining a timer interruption operation of the effect control unit. It is a flowchart explaining generation and issue of an image command list. It is another flowchart explaining the production | generation and issue of an image command list. It is a flowchart explaining the production | generation and issue of a voice command list regarding control of a sound engine.

  Hereinafter, the present invention will be described in detail based on examples. FIG. 1 is a perspective view showing a pachinko machine GM of the present embodiment. This pachinko machine GM includes a rectangular frame-shaped wooden outer frame 1 that is detachably mounted on an island structure, and a front frame 3 that is pivotably mounted via a hinge 2 fixed to the outer frame 1. It is configured. A game board 5 is detachably attached to the front frame 3 not from the back side but from the front side, and a glass door 6 and a front plate 7 are pivotally attached to the front side so as to be freely opened and closed.

  On the outer periphery of the glass door 6, an electric lamp such as an LED lamp is arranged in a substantially C shape. On the other hand, at the upper left and right positions and the lower side of the glass door 6, all three speakers are arranged. The two speakers arranged in the upper part are each configured to output sound of the left and right channels R and L, and the lower speaker is configured to output heavy bass.

  The front plate 7 is provided with an upper plate 8 for storing game balls for launching, and a lower plate 9 for storing game balls overflowing or extracted from the upper plate 8 and a launch handle at the lower part of the front frame 3. 10 are provided. The launch handle 10 is interlocked with the launch motor, and a game ball is launched by a striking rod that operates according to the rotation angle of the launch handle 10.

  A chance button 11 is provided on the outer peripheral surface of the upper plate 8. The chance button 11 is provided at a position where it can be operated with the left hand of the player, and the player can operate the chance button 11 without releasing the right hand from the firing handle 10. The chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp is turned on and can be operated. The button chance state is a game state provided as necessary.

  On the right side of the upper plate 8, an operation panel 12 for ball lending operation with respect to the card-type ball lending machine is provided, a frequency display unit for displaying the remaining amount of the card with a three-digit number, and a ball of game balls for a predetermined amount A ball lending switch for instructing lending and a return switch for instructing to return the card at the end of the game are provided.

  As shown in FIG. 2, a guide rail 13 made of a metal outer rail and an inner rail is provided on the surface of the game board 5 in an annular shape, and a central opening HO is provided at the approximate center thereof. A movable effect body (not shown) is housed in a concealed state below the central opening HO, and at the time of a movable notice effect, the movable effect body rises into an exposed state so that a predetermined reliability can be obtained. The notice effect is realized. Here, the notice effect is an effect that informs indefinitely that a big hit state advantageous to the player will occur, and the reliability of the notice effect means the probability that the big hit state will result.

  A main display device DS1 composed of a large liquid crystal color display (LCD) is disposed in the central opening HO, and a movable sub display device composed of a small liquid crystal color display is disposed on the right side of the main display device DS1. DS2 is arranged. The main display device DS1 is a device that variably displays a specific symbol related to the big hit state and displays a background image and various characters in an animated manner. The display device DS1 has special symbol display portions Da to Dc in the center portion and a normal symbol display portion 19 in the upper right portion. In the special symbol display portions Da to Dc, there is a case where a reach effect that expects a big hit state is invited, and in the special symbol display portions Da to Dc and the surroundings, an appropriate notice effect is executed.

  In the game area in which the game ball falls and moves, the first symbol start port 15a, the second symbol start port 15b, the first big winning port 16a, the second big winning port 16b, the normal winning port 17, and the gate 18 are arranged. It is installed. Each of these winning openings 15 to 18 has a detection switch inside, and can detect the passage of a game ball.

  On the upper part of the first symbol starting port 15a, there is arranged an effect stage 14 configured to be able to win a prize in the first symbol starting port 15 after the game ball entering from the introduction port IN moves in a seesaw shape or a roulette shape. Yes. And when a game ball wins the 1st symbol starting port 15, it is comprised so that the fluctuation | variation operation | movement of the special symbol display parts Da-Dc will be started.

  The second symbol start port 15b is configured to be opened and closed by an electric tulip having a pair of left and right opening and closing claws. When the stop symbol after fluctuation of the normal symbol display unit 19 displays a winning symbol, a predetermined symbol is displayed. The opening / closing claw is opened only for a time or until a predetermined number of game balls are detected.

  The normal symbol display unit 19 displays a normal symbol. When a game ball that has passed through the gate 18 is detected, the normal symbol fluctuates for a predetermined time and is extracted when the game ball passes through the gate 18. The stop symbol determined by the selected lottery random value is displayed and stopped.

  The first big prize opening 16a is configured with a slide board that advances and retreats in the front-rear direction, and the second big prize opening 16b is configured with an opening / closing plate that is pivotally supported at the lower end and opens forward. . The operation of the first grand prize opening 16a and the second big prize opening 16b is not particularly limited. In this embodiment, the first big prize opening 16a corresponds to the first symbol start opening 15a, and the second big prize opening 16b is comprised corresponding to the 1st symbol starting port 15b.

  That is, when a game ball is won at the first symbol start opening 15a, the changing operation of the special symbol display portions Da to Dc is started. After that, when the predetermined big hit symbol is aligned with the special symbol display portions Da to Dc, the first big hit A special game is started, and the slide board of the first big winning opening 16a is opened forward to facilitate the winning of a game ball.

  On the other hand, when a predetermined big hit symbol is aligned with the special symbol display portions Da to Dc as a result of the fluctuating motion started by winning the game ball in the second symbol start opening 15b, a special game corresponding to the second big hit is started, The open / close plate of the two major winning openings 16b is opened to facilitate the winning of game balls. The game value of the special game (hit state) varies according to the jackpot symbols to be arranged, etc., but which game value is given is executed at the time of winning the game ball to the symbol start openings 15a, 15b. Determined in advance based on the lottery result of the big hit lottery.

  In a typical big hit state, the opening / closing plate closes when a predetermined time elapses after the opening / closing plate of the big winning opening 16 is opened or when a predetermined number (for example, 10) of game balls wins. Such an operation is continued up to 15 times, for example, and is controlled in a state advantageous to the player. In addition, when the stop symbol after the change of the special symbol display parts Da to Dc is a specific symbol among the special symbols, there is a privilege that the game after the end of the special game becomes a high probability state (probability variation state). Is granted.

  By the way, in the present embodiment, the big hit lottery for determining the big hit state and other lottery probabilities can be set in any of a plurality of stages based on the setting operation of the staff. The lottery probability setting operation by the staff is permitted only when the power is turned on by a special setting key SET (FIG. 3).

  FIG. 3 is a block diagram showing an overall circuit configuration of the pachinko machine GM that realizes the above-described operations, and FIG. 4 is a block diagram showing the production control board 22 in somewhat detail.

  As shown in FIG. 3, this pachinko machine GM receives AC 24V and outputs various DC voltages, power supply abnormality signals ABN1, ABN2, a system reset signal (power reset signal) SYS, etc., and a game control operation The main control board 21 that centrally handles the control, the effect control board 22 that executes various effect operations uniformly based on the control command CMD received from the main control board 21, and the control command received from the main control board 21 Based on CMD ′, the payout motor M is controlled to pay out a game ball, and a launch control board 24 that fires a game ball in response to a player's operation is mainly configured.

  Corresponding to the above configuration, the main control unit board 21 is connected to each game component of the game board 5 via the game board relay board 31. In response to the switch signals of the detection switches built in the winning holes 16 to 18 on the game board, necessary lottery processing is executed and solenoids such as electric tulips are appropriately driven.

  A liquid crystal interface board (liquid crystal IF board) 25 that relays image signals transmitted to the display devices DS1 and DS2 is directly connected to the effect control board 22 by male and female connectors without using a wiring cable. In addition, the liquid crystal IF board 25 includes a nonvolatile memory 26 (ferroelectric memory FeRAM: Ferroelectric Random Access Memory) that stores game performance information and the like, and a clock circuit 27 (RTC real time clock) that can measure the current time. ) And are installed.

  The control command CMD output from the main control board 21 is directly transmitted to the effect control board 22, but the control command CMD ′ is transmitted to the payout control board 23 via the main board relay board 32. Is done. These control commands CMD and CMD 'have a 16-bit length, but are transmitted in parallel every two 8-bit lengths.

  The main control board 21, the effect control board 22 and the payout control board 23 are equipped with a computer circuit using a one-chip microcomputer. On the other hand, the effect control board 22 is equipped with a computer circuit which is a single electronic element (composite chip 40) including an image processor 51, an audio processor 52, a host CPU 50, and the like. The lamp effect, the accessory effect, and the image effect are centrally controlled (see FIG. 4). Since the audio processor 52 is built in the composite chip 40, the audio processor 52 may be particularly referred to as a sound engine 52 in the following description. The image processor 51 is realized by a plurality of circuit blocks 60 to 63 that realize this function (see FIG. 5).

  In the following description, the functions mounted by the circuits mounted on the control boards 21 to 23 and the liquid crystal IF board 25 and the operations realized by the circuits are collectively referred to as a main control unit 21, an effect control unit 22, and This is called the payout control unit 23. Note that, with respect to the main control unit 21, all or part of the effect control unit 22 and the payout control unit 23 become sub-control units.

  By the way, the pachinko machine GM is roughly divided into a frame side member GM1 surrounded by a broken line in FIG. 3 and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes a front frame 3 on which a glass door 6 and a front plate 7 are pivotally attached, and a wooden outer frame 1 on the outside thereof. Is fixedly installed. On the other hand, the board side member GM2 is replaced in response to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. All except the frame side member 1 is the panel side member GM2.

  As shown in the broken line frame in FIG. 3, the frame-side member GM1 has a power supply board 20, a payout control board 23, a launch control board 24, a frame relay board 35, and a lamp drive that drives a C channel LED lamp group. A board 36 and a motor drive board 37 for driving an E channel accessory motor group are included, and these circuit boards are respectively fixed at appropriate positions of the front frame 3.

  On the other hand, a main control board 21, an effect control board 22, and a liquid crystal IF board 25 are fixed together with the display devices DS1, DS2 and other circuit boards as a board-side member GM2 on the back surface of the game board 5. Here, the other circuit boards include a lamp drive board 29 that drives the D-channel LED lamp group, a motor drive board 30 that drives the F-channel accessory motor group, and a frame relay board 34. ing.

  The motor drive board 37 on the frame side and the motor drive board 30 on the board side are provided with a plurality of motor drivers DVj for driving the accessory motor, and also receive a parallel signal of a plurality of bits and convert it into a serial signal. The signal acquisition circuits GET to be output are arranged. Then, the switch signal of the chance button 11 and the sensor signal of the origin sensor arranged for each accessory motor are supplied to the signal acquisition circuit GET of the motor drive board 37 as a parallel signal having a plurality of bits.

  The same applies to the motor drive board 30. The signal acquisition circuit GET of the motor drive board 30 is configured such that the sensor signal of the origin sensor arranged for each accessory motor is supplied as a parallel signal having a plurality of bits. ing.

  As will be described in detail later, in the case of this embodiment, the C channel LED lamp group, the D channel LED lamp group, the E channel accessory motor group, and the F channel accessory motor group are all effect control boards. It is driven based on drive data serially transmitted from 22 serial ports 55. Here, the names C channel to F channel correspond to the channel numbers #C to #F of the serial port 55 built in the composite chip 40.

  The frame side member GM1 including the drive boards 36 and 37 and the panel side member GM2 including the drive boards 29 and 30 are electrically connected by connection connectors C1 to C4 which are concentratedly arranged at one place. Yes. Therefore, the electrical connection between the frame side member GM1 and the panel side member GM2 is completed by one operation, and the electrical connection is interrupted by one operation.

  The power supply board 20 is connected to the main board relay board 32 through the connection connector C2, and is connected to the power supply relay board 33 through the connection connector C3. The power supply board 20 is provided with a power supply monitoring unit MNT that monitors whether AC power is turned on or off. When power supply monitoring unit MNT detects that AC power is turned on, it maintains system reset signal SYS at L level for a predetermined time, and then transitions it to H level.

  Further, when power supply monitoring unit MNT detects the interruption of the AC power supply, power supply abnormality signals ABN1 and ABN2 are immediately shifted to the L level. The power supply abnormality signals ABN1 and ABN2 quickly become H level after the power is turned on.

  The system reset signal of the present embodiment is generated by a DC power source based on an AC power source. For this reason, after detecting the turning-on of the AC power supply (usually turning on the power switch) and increasing it to the H level, the H level is maintained unless the DC power supply voltage drops to an abnormal level. Therefore, even if the AC power supply is in an instantaneous power interruption state while the DC power supply voltage is maintained, the system reset signal SYS does not reset the CPU. The power supply abnormality signals ABN1 and ABN2 are also output even when the AC power supply is instantaneously stopped.

  The main board relay board 32 outputs the power abnormality signal ABN1, the backup power supply BAK, and DC5V, DC12V, and DC32V output from the power board 20 to the main control unit 21 as they are. On the other hand, the power supply relay board 33 outputs the system reset signal SYS received from the power supply board 20 and the AC and DC power supply voltages to the effect control unit 22 as they are. And the production | presentation control part 22 resets the power supply of the electronic element arrange | positioned at each part of a board | substrate based on the received system reset signal SYS.

  On the other hand, the payout control board 24 is directly connected to the power supply board 20 without going through the relay board. When the main control unit 21 receives the same power supply abnormality signal ABN2 or backup power supply BAK together with other power supply voltages. Is receiving.

  The system reset signal SYS output from the power supply board 20 is a power supply reset signal indicating that the AC power supply 24V is supplied to the power supply board 20, and each circuit element constituting the effect control unit 22 based on the power supply reset signal. The power is reset.

  However, the system reset signal SYS is not supplied to the main control unit 21 and the payout control unit 23, and a power reset signal (CPU reset signal) is generated in the reset circuit RST of each of the circuit boards 21 and 24. ing. Therefore, for example, even if the connection connector C2 is rattled or noise is superimposed on the wiring cable, there is no possibility that the CPU of the main control unit 21 or the payout control unit 23 is abnormally reset.

  The reset circuits RST provided in the main control unit 21 and the payout control unit 23 each have a built-in watchdog timer, and each CPU is provided unless a regular clear pulse is received from the CPUs of the control units 21 and 24. Is forcibly reset.

  In this embodiment, the RAM clear signal CLR is generated by the main control unit 21 and transmitted to the one-chip microcomputer of the main control unit 21 and the payout control unit 23. Here, the RAM clear signal CLR is a signal for deciding whether or not to initialize all the areas of the built-in RAM of the one-chip microcomputer of each control unit 21 and 24. The initialization switch SW operated by the attendant is turned on. It has a value corresponding to the / OFF state.

  As shown in FIG. 3, the initialization switch SW is supplied to the main control unit 21 in the same manner as the setting key SET that defines the lottery probability and the like. The operations of the initialization switch SW and the setting key SET are recognized by the initial process of the main control unit 21 that is executed immediately after the power is turned on, and the setting process such as the lottery probability and the initialization process of the built-in RAM are executed.

  Thereafter, the set value such as the lottery probability is notified to the effect control unit 22 in the form of a predetermined control command in the steady process of the main control unit 21 started in the CPU interrupt permission state. It is stored in the nonvolatile memory 26 of the IF board 25. As described above, the setting key SET is used for setting a winning probability such as a big hit lottery in any of a plurality of stages. Then, the setting contents of the setting key SET are stored in the nonvolatile memory 26 together with the time information read from the clock circuit 27.

  As described above, the setting process such as the lottery probability and the initialization process of the built-in RAM are allowed only immediately after the power is turned on, and are not executed in a steady process started thereafter. However, when an attendant operates the setting key SET during the steady process of the main control unit 21, the fact is notified from the main control unit 21 to the effect control unit 22.

  Then, the production control unit 22 that has received the operation notification of the setting key SET reads out the stored content in the nonvolatile memory 26 and displays it on the display device DS1. The operation of the setting key SET during regular processing is an operation that the staff member wants to check the lottery probability setting history and game performance history before starting business, and wants to confirm that there is no trace of fraud To be used.

  When the initialization switch SW is operated in response to the operation of the setting key SET, the presentation control unit 22 that has received this notification erases all the contents stored in the nonvolatile memory 26. ing. This is because, for example, when the gaming machine is resold, the lottery probability setting history and the game performance history, which should be referred to as trade secrets, are deleted.

  The main control unit 21 and the payout control unit 23 receive the power supply abnormality signals ABN1 and ABN2 from the power supply board 20 to start necessary end processing prior to a power failure or business end. The backup power supply BAK is a DC5V DC power source that retains data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 23 even after the AC power supply 24V is cut off due to business termination or power failure. Therefore, the main control unit 21 and the payout control unit 23 can resume the game operation before power-off after power-on (power backup function). This pachinko machine is designed to retain the stored contents of the RAM of each one-chip microcomputer for at least several days.

  As described above, the effect control board 22 and the liquid crystal IF board 25 are integrated by connector connection, and the effect control unit 22 is connected to the DC voltage of each level from the power supply board 20 via the power relay board 33. (5V, 12V, 32V) and the system reset signal SYS are received (see FIGS. 3 and 4).

  The effect control unit 22 receives a control command CMD and a strobe signal STB from the main control unit 21. Then, the effect control unit 22 serially transmits the lamp drive data SPOc and SPCd to a large number of lamp drivers DR1 to DRn (see FIG. 10A) mounted on the lamp drive board 29 and the lamp drive board 36. The lamp effect based on the control command CMD is realized by driving the C channel lamp group and the D channel lamp group.

  The effect control unit 22 serially transmits the motor drive data SOe and SOf to a large number of motor drivers DV1 to DVm (see FIG. 11A) mounted on the motor drive board 30 and the motor drive board 37. , The E channel motor group and the F channel motor group are driven to realize the effect production based on the control command CMD.

  Although not particularly limited, the present embodiment employs a clock synchronous serial transmission method, and the lamp driver DRi of the lamp driving board 36 and the lamp driving board 29 is synchronized with the clock signals SPCKc and SPCKd. SPOc and SPOd are received. The motor driver DVj of the motor drive board 37 and the motor drive board 30 receives the motor drive signals SOe and SOf in synchronization with the serial clocks SCKE and SCKf (see FIG. 4).

  FIG. 4 is a block diagram showing the internal configuration of the effect control unit 22 in detail, and FIG. 5 is a block diagram showing the internal configuration of the composite chip. As shown in FIGS. 3 and 4, the effect control unit 22 includes a composite chip 40 that centrally controls an image effect, a sound effect, a lamp effect, and an accessory effect, and a work area for effect control operations performed by the composite chip 40. DDR3 SDRAM (Double-Data-Rate3 Synchronous Dynamic Random Access Memory) 41 that functions as a non-volatile memory, a control program that realizes a unified rendering operation, compressed audio data SND, compressed image data IMG, etc. A CGROM 42 to store, a digital amplifier 43 that amplifies an audio signal received from the composite chip 40 and drives the speaker SP, input buffers 44, 45A, 45B, output buffers 46A, 46B, signal switching units 47A, 47B, It is structured around.

  In the following description, for convenience, the DDR3 SDRAM 41 may be referred to as a DDR memory or an external RAM (Random Access Memory) 41, and the CGROM 42 may be referred to as an external ROM (Read Only Memory) 42.

  The DDR memory 41 that can be connected to the composite chip 40 of this embodiment has a maximum length of 8 Gbytes, but the area directly accessible from the composite chip 40 (host CPU 50) is 256 Mbytes. Therefore, in this embodiment, a frame buffer FB for temporarily storing image data for one frame of each of the display devices DS1 and DS2 is secured in the direct access area of the 256-Mbyte DDR memory 41. In this embodiment, the audio data SND stored in the external ROM 42 is copied to the directly accessible area of the DDR memory 41 when the power is turned on to enable high-speed access from the composite element 40.

  The external ROM 42 that can be connected to the composite chip 40 has a maximum length of 1 Tbyte (1,099,511,627,776 bytes = 1,024 Gbytes), but the area directly accessible from the composite chip 40 (host CPU 50) is 1 Gbyte. Therefore, in this embodiment, the direct access area of the external ROM 42 of 1 GM bytes is an effect control program for centrally controlling the effect operation, effect control data referred to by the effect control program, and basic data for audio effects. Audio data SND is stored in a nonvolatile manner. The effect control data includes drive data for realizing the lamp effect and the accessory effect. As described above, the audio data SND in the external ROM 42 is transferred from the external ROM 42 to the DDR memory 41 when the power is turned on.

  As shown in FIGS. 4 and 5, the composite chip 40 includes a host CPU 50, an image processor 51 that drives the display devices DS1 and DS2, and realizes an audio effect, and an audio processor 52 that drives a speaker and realizes an audio effect. A direct memory access (DMA) controller 53 that realizes direct data transmission without going through the host CPU 50, a parallel port (PIO) 54 that inputs and outputs parallel signals, and a serial port (SIO) that inputs and outputs serial signals 55, a main memory (M1) 56, a built-in DRAM (M2) 57, and the like. Although referred to as a parallel port for the sake of convenience, a parallel output port (PO) and a parallel input port (PI) are actually included.

  The serial port 55 of this embodiment has a total of six channels from channel #A to channel #F, but can function as a serial output port or a serial input port based on the setting of the operation mode. Therefore, in the present embodiment, channel #C and channel #D are used as serial output ports for lamp effects. On the other hand, channel #E and channel #F of serial port 55 are used as serial input ports for receiving serial signals by switching the operation mode after functioning as serial output ports for motor effects.

  Corresponding to the composite chip 40 having such an internal configuration, the input buffer 44 receives a control command CMD and a strobe signal STB from the main control unit 21 and a system reset signal SYS from the power supply board 20. Then, the control command CMD and the strobe signal STB are transmitted to the parallel port 54 of the composite chip 40, and the host CPU 50 obtains the control command CMD based on the interrupt processing caused by the strobe signal STB.

  The frame-side input buffer 45A receives the serial signal SNi of channel #E via the frame relay board 34, and the panel-side input buffer 45B receives the serial signal SNj of channel #F from the motor drive board 30. The input buffers 45A and 45B transmit the serial signals SNi and SNj to the serial port 55 of the composite chip 40. The serial signals SNi and SNj are serially transmitted in a clock synchronous manner in synchronization with the serial clocks SCKE and SCKf of the channel #E and the channel #F transmitted via the output buffers 46A and 46B.

  Here, the serial signal SNi includes an origin signal for specifying the rotation position of the accessory motor arranged on the frame side, and a switch signal indicating that the chance button 11 has been pressed. On the other hand, the serial signal SNj includes an origin signal for specifying the rotational position of the accessory motor arranged on the board side.

  Next, the frame side output buffer 46A and the panel side output buffer 46B output various signals received from the serial port 55 and the parallel port 54 of the composite chip 40 to the frame relay board 34 and the lamp driving board 29, respectively. .

  As shown in the figure, the frame-side output buffer 46A has a channel #C signal group SPOc, SPCKc, OEc transmitted from the serial port 55 to the lamp driving board 36, and a channel # transmitted from the serial port 55 to the motor driving board 37. The E signal group SOe, SCKE, SCKE and the latch pulse LTe of channel #E transmitted from the parallel port 54 to the motor drive board 37 are relayed.

  On the other hand, the panel-side output buffer 46B has a channel #D signal group SPOd, SPCKd, OEd transmitted from the serial port 55 to the lamp driving board 29 and a channel #F transmitted from the serial port 55 to the motor driving board 30. The signal groups SOf, SCKf, SCKf and the latch pulse LTf of channel #F transmitted from the parallel port 54 to the motor drive board 30 are relayed.

  The signal switching unit 47 includes a frame-side switching unit 47A that switches the final transmission destination of the serial clock SCKE of the channel #E transmitted to the motor driving board 37, and the serial clock SCKf of the channel #F transmitted to the motor driving board 30. It is divided into a panel side switch 47B for switching the final transmission destination. The frame side switching unit 47A and the panel side switching unit 47B receive the switching control signals CTLe and CTf from the parallel port 54, respectively, and switch the transmission destinations of the serial clocks SCKE and SCKf.

  In the present embodiment, the serial clocks SCKE and SCKf of the channel #E and the channel #F are transmitted to the motor drive board 37 and the motor drive board 30, respectively, but if the switching control signals CTLe and CTf are at the first level, In each motor drive board 37, 30, it is supplied to the motor driver DV, and if the switching control signals CTLe, CTf are at the second level, they are supplied to the signal acquisition circuit GET.

  Next, the liquid crystal IF substrate 25 will be described. In addition to the nonvolatile memory (FeRAM) 26 and the clock circuit 27, the liquid crystal IF substrate 25 receives a first LVDS (Low voltage differential signaling) signal from the image processor 51. A receiving signal distributor 28A and a signal converter 28B receiving the second LVDS signal from the image processor 51 are mounted. The first LVDS signal and the second LVDS signal are image signals for constructing each frame of the main display device DS1 and the sub display device DS2, and for each pixel, RGB 8-bit pixel data is horizontally converted. / A vertical synchronization signal and a pixel clock (dot clock) are included and output from the composite chip 40 to five pairs of differential signal lines.

  The signal distributor 28A receives the first LVDS signal LVDS1 to be transmitted to the main display device DS1, restores the RGB signal, and then distributes the image signal for the even pixel and the RGB signal for the odd pixel, respectively. Is converted into five pairs of LVDSo and LVDSe signals and output to the main display device DS1 (see FIG. 5).

  Based on the operation of the signal distributor 28A, the dot clock of the LVDS signal (LVDSo, LVDSe) transmitted to the main display device DS1 is greatly resistant to the dot clock frequency Fd of the original LVDS signal being halved. Since noise characteristics are improved, a large display device with high image quality (high resolution) can be driven stably. The main display device DS1 incorporates a first restoration circuit 38A that restores the RGB digital signal of the original dot clock frequency Fd based on the LVDSo and LVDSe signals, and the display screen of the main display device DS1 A high-quality one-frame image generated by the image processor 51 is displayed.

  On the other hand, the signal converter 28B is a circuit that receives the second LVDS signal LVDS2 to be transmitted to the sub display device DS2 by five pairs of differential signal lines, and outputs them together as a pair of differential signal lines. This is because the vertical and horizontal dimensions of the sub display device DS2 are significantly smaller than that of the main display device DS1, but the frequency of the vertical synchronizing signal (1/60 Hz) is the same, so that the pixel clock frequency is low. This is to greatly reduce the number of wires.

  In this embodiment, since RGB data constituting one pixel is specified by 8 bits each, the second LVDS signal of one cycle of the pixel clock includes 3 × 8 bits of RGB data, a vertical synchronization signal VS, and a horizontal synchronization signal. A total of 28 bits of data including HS, data enable signal DE, etc. are included. In signal converter 28B, a total of 36 bits obtained by adding control data for DC balance to these 28 bits is used as a pair of differences. Output to the dynamic signal line. In the present embodiment, by adopting such a configuration, the five pairs of signal lines can be significantly suppressed to a pair of signal lines.

  The composite image signal transmitted through the pair of signal lines is parallel-converted in the second restoration circuit 38B disposed close to the sub display device DS2, and then restored to the RGB digital signal and supplied to the sub display device DS2. Is done.

  FIG. 5 shows the internal structure of the composite chip 40 that centrally controls the image effect, the sound effect, the lamp effect, and the accessory effect together with the external ROM 42 and the DDR memory 41 related thereto. As described above, the frame buffer FB is secured in the directly accessible storage area of the DDR memory 41, and the audio data SND transferred from the external ROM 42 when the power is turned on is stored.

  Here, the frame buffer FB is a storage area in which image data in a completed state that specifies display screens of the display devices DS1 and DS2 is temporarily stored. The frame buffer FB of the present embodiment has a double buffer structure of a first buffer and a second buffer for each of the display devices DS1 and DS2, and each buffer is a predetermined specified based on a vertical synchronization signal 60 Hz. Are switched to a drawing bank and a display bank at every switching period (1/30 second).

  That is, the image data generated in the first buffer that functions as a drawing bank in a certain operation cycle is output to the display devices DS1 and DS2 from the first buffer that functions as a display bank in the next operation cycle. However, the arrangement position of the frame buffer FB having such a configuration is not limited to the DDR memory 41 and may be arranged in the main memory 56 or the built-in DRAM 57.

  Next, an effect control program, effect control data, image data IMG, and audio data SND are stored in the external ROM 42 in a nonvolatile manner. Note that the audio data SND includes a group of SEQ codes and a group of SAC codes shown in FIG. 8 in addition to a large number of audio phrase data for realizing an audio production of one unit. I will explain it.

  By the way, when the access speed of the external ROM 42 becomes a problem, a program ROM 58 may be separately arranged, and an effect control program and effect control data may be arranged here. In this case, the program ROM 58 is accessed via the CPU interface circuit 66 of the composite chip 40.

  Further, as an inexpensive element capable of storing more data, a SATA (Serial Advanced Technology Attachment) module (HSS device) 59 such as a flash SSD (solid state drive) composed of a NAND flash memory may be used. It is also preferable to adopt a configuration in which the HSS device 59 is accessed at a high speed by the HSS (High Speed Serial) method compliant with SerialATA. In this case, the HSS device 59 is accessed via the HSS controller 70 of the composite chip 40.

  As shown in FIG. 5, the composite chip 40 includes the internal circuit shown in FIG. 4, etc., and the host CPU 50 that centrally controls all the rendering operations and the units 60 to 60 that function as the image processor 51 as a whole. 63, a sound engine 52 that functions as a sound processor 52, a DMA controller 53 that realizes DMA transfer between external circuits such as the external ROM 42 and the DDR memory 41, and internal circuits, and parallel data, and parallel data Parallel input / output port (PIO) 54 that realizes transmission / reception of data, serial input / output port (SIO) 55 that realizes transmission / reception of serial data, main memory 56 having a storage capacity of about 3 MB, and storage of about 256 MB Built-in DRAM 57 having a capacity and dedicated as a destination for issuing the image command list LT A FIFO (First In First Out) structure image command buffer 71 that is used, such as command write register CMw is incorporated is a relay register to the image command buffer 71.

  These internal circuits of the composite chip 40 are each reset at the optimal timing based on the operation of the reset control circuit 67, and then operate at a speed based on the operation clock output by the clock control circuit 65. . Various interrupt processes are realized by the interrupt controller 64 that functions based on the setting of the host CPU 50. The DDR memory 41 is accessed via the DDR3 memory controller 68, and the external ROM 42 is accessed via the CG memory controller 69.

  The main memory 56 built in the composite chip 40 is capable of high-speed random access, and is used as a stack area required for program processing of the host CPU 50 and other work areas. A part of the storage area (3 Mbytes) of the main memory 56 can also be used as a command memory 56 capable of storing an image command list LT issued by the host CPU.

  Specifically, the image processor 51 built in the composite chip 40 includes a display controller 63 that outputs the first and second LDVS signals to the signal distributor 28A and the signal converter 28B, and the display devices DS1 and DS2. Based on a rendering engine 61 that generates image data for one frame, a CG data decoder 62 that reads and decodes compressed image data from the external ROM 42, and an operation instruction from the host CPU 50, controls each part of the image processor 51. And a VDP controller 60.

  The decoded output by the CG data decoder 62 is temporarily stored in the built-in DRAM 57. In addition, when the preloader built in the VDP controller functions to pre-read (preload) compressed image data (hereinafter referred to as CG data) from the external ROM 42, the pre-read CG data (preload data) ) Is temporarily stored in a preload buffer (see FIGS. 7 and 18) secured in the built-in DRAM 57.

As shown in FIG. 5, the VDP controller 60 includes various control registers CRG (R / W) that can be read / written from the host CPU 50, and receives an operation instruction received by the write control register (CRG _W ). It operates on the basis of the internal operation status as status information, and holds the control register for reading (CRG _R).

  In this embodiment, the issue destination of the image command list LT is basically the image command buffer 71. However, the image command list is additionally stored in the main memory (command memory) 56, the built-in DRAM 57, and the DDR memory 41. LT (auxiliary list LT ′ described later) can also be issued. Further, the standard image command list LT (auxiliary list LT ′) can be stored in the external ROM 42 in advance.

  However, in any case, the VDP controller 60 first reads the image command list LT from the image command buffer 71, and based on the JUMP instruction described therein, the main memory 56, the built-in DRAM 57, the DDR memory 41, Alternatively, the process proceeds to the processing of the image command list LT described in the external ROM 42.

  In any case, the image command list LT is an instruction list that lists a group of drawing commands and the like that specify each frame of each display device DS1, DS2. In this embodiment, the command sequence listed in the image command list LT includes (a) a control command related to VDP (Video Display Processor) control such as an interrupt operation of the VDP controller 60, and (b) a rendering operation of the rendering engine 61. And (c) decode commands related to the decoding operation of the CG data decoder 62. Hereinafter, these three types of commands (a) to (c) will be collectively referred to as image commands. To.

  Each of these image commands has a variable length that is an integer multiple of 32 bits, and the above three types of image commands (a) to (c) are listed in an appropriate order, and the image command list LT is completed. When the image command list LT completed by the host CPU 50 is issued, for example, to the image command buffer 71, the host CPU 50 sequentially sets the command write register for the command sequence constituting the image command list LT one by one for each image command. Write to CMw. Then, one image command of variable length written in the command write register CMw is automatically stored in the image command buffer 71 in the form of FIFO (First In First Out) based on the internal configuration. Yes.

Corresponding to such an internal operation, the VDP controller 6 has a management function of the image command buffer 71 (image command FIFO), and status information such as a use state of the image command buffer 71 is read control. register is configured to be held in the (CRG _R). Therefore, the host CPU writes the image command to the command write register CMw after confirming that the image command buffer 71 (image command FIFO) is not full.

  In this way, the image command sequence stored in the image command buffer 71 is automatically read out by the VDP controller 60 by the FIFO (First In First Out) method, and (a The control command is distributed to the VDP controller 60, (b) the drawing command is distributed to the rendering engine 61, and (c) the decoding command is distributed to the CG data decoder 62.

  Then, the VDP controller 60, the rendering engine 61, and the CG data decoder 62 start their respective operations based on the image commands described in the distributed image command list LT. That is, based on the control operation of the VDP controller 60, the CG data decoder 62 and the rendering engine 61 start the image data generation operation, and the final image data is completed in the frame buffer FB.

  As will be described later, the host CPU 50 of this embodiment operates intermittently at the same operation period Δ (= 1/30 seconds) as the bank switching period described above. It is executed in the operation cycle in which the image command list LT is issued to the command buffer 71.

  The case where the image command list LT is issued to the image command buffer 71 has been described above. As described above, the host CPU 50 stores the image command list in the main memory (command memory) 56, the built-in DRAM 57, or the DDR memory 41. LT can also be issued. However, in this case, the image command list LT issued in a certain operation cycle is validated in an operation cycle delayed by one or more.

  For example, when the command memory 56 is used, as shown in FIG. 6, it is necessary to secure a pair of list buffers BUFa and BUFb to be used by switching between writing and reading. Then, the image command list LT of the next cycle is issued to one list buffer BUFa / BUFb, and the usage of the pair of list buffers BUFa and BUFb is switched after one operation cycle.

  The switching operation of the list buffers BUFa and BUFb is executed by the control command list LTc issued to the image command buffer 71 by the host CPU 50. The control command list LTc issued in a certain operation cycle (T) is the first list buffer BUFa. The JUMP instruction (JUMP_BUFa) for specifying that the image command list LT should be executed and the bank flip wait instruction (WAIT_BANKFLIP) which is the last line of the control command list LTc. This JUMP instruction is the same as a so-called CALL instruction, and after execution of the JUMP instruction, a bank flip wait instruction (WAIT_BANKFLIP) is executed.

  Bank flip (Bank Flip) means switching between a drawing bank and a display bank in the frame buffer FB, and execution of the bank flip wait instruction causes the operation of the VDP controller 60 to be in a standby state until the next bank switching timing. The bank flip period (= bank switching period) may be 1/60 second corresponding to the frequency of 60 Hz of the vertical synchronization signal, but in this embodiment, sufficient operation time of each internal circuit of the composite chip 40 is ensured. Therefore, the bank flip cycle is dared to be 1/30 second (for two vertical synchronization signals). As described above, the bank flip period (bank switching period) is the same as the operation period Δ of the host CPU 50.

  In the present embodiment, since the above configuration is adopted, the next operation cycle (T + Δ) is 1/30 seconds later, but the control command list LTc issued in the next operation cycle (T + Δ) is the second list. It consists of a JUMP instruction (JUMP_BUFb) for instructing that the image command list LT of the buffer BUFa should be executed, and a bank flip wait instruction (WAIT_BANKFLIP) described in the last line of the control command list LTc. Therefore, in this operation cycle (T + Δ), the image command list LT of the second list buffer BUFb issued in the previous cycle is validated.

  The same applies hereinafter, and the image command list LT for the next cycle is issued to one of the list buffers BUFa and BUFb, and the control command list LTc for switching the list buffers BUFa and BUFb is issued to the image command buffer 71 to perform the image rendering operation. To make progress. According to this configuration, it is not necessary to complete the image command list LT issuance processing and the image data generation processing based on the image command list LT in one operation cycle (Δ), and the image data generation processing time is reduced. Since there is a time margin, it is possible to cope with an increase in the size of the display device and an increase in image quality.

  Note that at the end of the image command list LT, a JUMP instruction (JUMP_CFIFO) indicating a return to the bank flip wait instruction (WAIT_BANKFLIP) described in the image command buffer 71 is described, and is indicated by an arrow in FIG. Operation is realized.

  In order to effectively cope with an increase in the size and image quality of the display device, the preloader is made to function prior to the decoding operation, and the CG data (compressed image compression data) in the external ROM 42 is preloaded. Is also suitable. In order to realize the preload operation, it is necessary to set the VDP controller 60 to the pre-read operation mode after specifying a CG data transfer period (Δ to 3Δ) to be described later. In addition, it is necessary to describe a special decode command DCp instructing preload transfer in the image command list LT.

  In this pre-reading operation mode, the image command list LT is issued to a memory having a sufficient storage capacity, such as the DDR memory 41, and a plurality of N buffer areas must be secured. Hereinafter, a case where the issue destination of the image command list LT is, for example, the DDR memory 41 and the buffer area is three (triple buffers BUFa to BUFc) will be described with reference to FIG.

  In this case, the triple buffer BUFa to BUFc is used cyclically, and the image command list LT for the next cycle is issued to any of the areas (BUFa to BUFc), and the image command buffer 71 is in a bank flip wait state. A control command list LTc composed only of an instruction (WAIT_BANKFLIP) is issued.

  For example, in the operation cycle (T), the image command list LT that is activated one after another (T + 2Δ) is issued to the first buffer BUFa, and in the operation cycle (T + Δ), the image command list LT that is activated to T + 3Δ is the first one. In the operation cycle (T + 2Δ), an image command list LT that is activated to T + 4Δ is issued to the third buffer BUFb. The last line of the image command list LT is a jump instruction (JUMP_CFIFO) to the head address of the image command buffer 71.

  Further, the host CPU 50 needs to specify the head address of the image command list LT to be executed in each operation cycle to the VDP controller 60. Specifically, in the operation cycle (T), the image command list LT is required. Is specified in the first buffer BUFb, and in the operation cycle (T + Δ), the image command list LT is specified to exist in the third buffer BUFc. In the operation cycle (T + 2Δ), the image command list LT is specified in the first buffer BUFa. It is specified that it exists.

  As described above, the last line of any image command list LT is a jump instruction (JUMP_CFIFO) to the top address of the image command buffer 71. The image command buffer 71 is instructed to receive a bank flip wait instruction ( A control command list LTc composed only of WAIT_BANKFLIP) is issued. Therefore, the VDP controller 60 cyclically reads the triple buffers BUFa to BUFc, executes necessary processing, and then ends the processing by a bank flip wait instruction (WAIT_BANKFLIP). Since the control command list LTc always has the same contents, it is not always necessary to issue it every time, and it may be issued only once.

  By the way, as described above, the image command list LT may include a special decode command DCp that instructs preload transfer. In the pre-read operation mode, the newly written image command list LT is interpreted in the next operation cycle.

  Therefore, the image command list LT written in the operation cycle (T) is interpreted by the VDP controller 60 in the operation cycle (T + Δ), but the decode command DCp instructing the image command list LT to perform preload transfer is detected. In this case, the preloader built in the VDP controller 60 reads necessary CG data from the external ROM in the operation cycle (T + Δ), and reads the read CG data into the preload buffer BUFp secured in the built-in DRAM 57. Store (CG data transfer period Δ).

  When the CG data read to the preload buffer BUFp adopts the triple buffer (BUFa to BUFc) format, the CG data of the preload buffer BUFp is expanded by the CG data decoder 62 in the next operation cycle (T + 2Δ). , Used for image generation processing of the rendering engine 61.

  When four buffer areas (quadable buffers) are secured instead of three buffer areas (triple buffers), the CG data look-ahead period (T + Δ) extends from the operation period (T + Δ) to the operation period (T + 2Δ). In the transfer period 2Δ), when five buffer areas (quintable buffers) are secured, the pre-read period (transfer period 3Δ) is from the operation cycle (T + Δ) to the operation cycle (T + 3Δ).

  As described above, when the pre-reading operation mode is adopted, a CG data transfer time of one operation cycle or more can be ensured. Therefore, even when the external ROM 42 inferior in access speed is adopted, a large amount of CG data is used for one frame of the display device. Can be transferred, and the display device can be increased in size, image quality, and image production. It is also effective when the number of display devices is increased to three or more and different image effects are executed.

  Next, a sound engine (sound processor) 52 built in the composite chip 40 will be described with reference to FIG. 8. As shown in FIG. 8, the sound engine 52 has a plurality of accessible from the host CPU 50 and the VDP controller 60. A command register (RGi) 80, a sound control module 81 that operates intermittently to control internal operations, and compresses compressed audio phrase data read from the DDR memory 41 to generate one or more channels of digital audio ( PCM data), a multi-effector 85 that mixes and processes the multi-channel digital audio generated by the main generator 84, and an output from the multi-effector 85, which is necessary for the three transmission lines. Audio information is digital amplifier An audio interface 86 to be output to the 3, is configured with a, and is connected to such a host CPU50 via the relay register 82 and a command interface unit 83 relays the access operation to the command register RGi.

  Here, the sound control module SCM (hereinafter abbreviated as SCM81) includes a sequencer SEQj (Sequencer) for automatically executing a series of setting operations for a group of command registers RGi to RGj, and a simple access controller SACi. A plurality of (simple Access Controllers) are provided. All the operations are the same in that the set values in the group of command registers RGi to RGj are automatically set, but after finishing a set of setting operations (step operation), waiting for a predetermined time, The setting operation of the sequencer SEQ is more suitable for the sound control in that an intermittent setting operation that shifts to the next set of setting operations (step operation) or a repeated setting operation that repeats a series of setting operations as many times as possible is possible. Slightly more sophisticated than module SCM.

  However, the simple access controller SAC can periodically and repeatedly execute a predetermined periodic SAC operation defined in the external ROM 42 at a cycle that is an integral multiple of the operation cycle of the SCM 81. As will be described later, the operation content of the simple access controller SAC is specified by the SAC code number of 0 to N, but the regular SAC operation specified by the final SAC code number (N) is Internally controlled so that it is executed periodically and repeatedly.

  Therefore, in this embodiment, the equalizer function and the compressor function in the multi-effector 85 are repeatedly reset by this periodic SAC operation. Therefore, even if the setting content related to the sound quality changes due to the influence of noise or the like, the sound quality intended by the developer is surely restored based on the subsequent periodic SAC operation. As will be described later, in this embodiment, the operation cycle of the SCM 81 is 32/48 mS, and the periodic SAC operation is executed every 512 times of this operation cycle.

  In order to make each of the simple access controller SACi capable of such periodic SAC operation and the sequencer SEQj having a slightly advanced setting operation function effectively, the external ROM 42 has the operation of the simple access controller SAC (periodic SAC operation is performed). A plurality of types of SAC codes that define the operation of the sequencer SEQ are stored. Note that the same data as the external ROM 42 is copied to the DDR memory 41 by the DMA transfer operation when the power is turned on, and FIG. 8 shows this state.

  Each of the SEQ code and the SAC code is a series of 2-byte data strings that are a set of a 1-byte register number specifying the command register RGi and a 1-byte set value for the command register RGi. Yes, it is completed with a predetermined end code (FFFFh). However, the SEQ code includes an interruption code (FFFEh) indicating completion of a group of setting operations (step operations) in order to realize the above-described intermittent setting operation and repeated setting operation.

  The SEQ code is composed of a series of M SEQ data (SEQ code = M × SEQ data), and the SAC code is composed of a series of N SAC codes (SAC code = N × SAC data). Each of the SEQ data and SAC data, which is a unit of the SEQ code and SAC code, is a set of a 1-byte register number for specifying the command register RGi and a set value of 1-byte length for the command register RGi. It is. As described above, the external ROM 41 stores a plurality of types of SEQ codes and SAC codes each having such a configuration. In this specification, these are stored as SAC code groups (a group of SEQ codes). , And may be referred to as a SEQ code group (a group of SAC codes).

  As shown in FIG. 5, the audio data SND stored in the external ROM 42 includes the above-described SAC code group and SEQ code group in addition to the audio phrase data for realizing a unit of audio production. The voice phrase data that realizes one unit of sound production is specified by one phrase number, and one SAC code or one SEQ code that is completed with an end code (FFFFh) is also a single SAC code number, It is specified by one SEQ code number.

  The sequencer SEQj can be started by setting a SEQ code number and other operating conditions in a group of command registers RGj for starting SEQj. If a SAC code number and other operating conditions are set in a group of command registers RGi for starting SACi, the simple access controller SACi can be started. However, since the regular SAC operation is automatically activated, the SAC activation process is unnecessary.

  As described above, a large number of audio phrase data that realizes a single audio production is transferred from the external ROM 42 to the DDR memory 41 together with other SAC code groups and SEQ code groups when the power is turned on. In the case of this embodiment, the DDR memory 41 is composed of a DDR3 SDRAM capable of high-speed access, so that high-speed access of audio phrase data is possible, and a high-quality audio phrase with a sampling frequency of 48 kHz or higher. Can handle data.

  Based on the above, next, the sound control module 81 (SCM 81) will be described. The SCM 81 of the embodiment controls the internal operation of the sound engine 52 by starting operation intermittently. Specifically, the SCM 81 corresponds to the sampling frequency (48 kHz) of the voice phrase data, for example, at every sound engine operation cycle (32/48 mS) that is 32 times the sampling cycle (1/48 kHz). The setting value of RGi can be updated. If the setting value is updated, an internal operation based on the updated setting value of the command register RGi is started.

  The command registers RGi referred to by the SCM 81 are each configured to be specified by a 1-byte register number. Each command register RGi includes a sequencer SEQ and a simple access controller SAC. A setting value that defines the internal operation is set, or status information indicating the internal operation state of the sound engine 52 is stored. Note that the internal operation may be defined based on the set values in the plurality of command registers RGi to RGj, such as when the sequencer SEQ or the simple access controller SAC described above is started, The internal operation state is specified by a 1-bit or multi-bit flag value of the status information.

  Next, the main generator 84 receives a plurality of audio decoders that can independently decompress a plurality of compressed phrase data read from the DDR memory 41, and a plurality of channels decoded by the audio decoder. A tone generator that can perform volume setting, volume pan setting, etc. is included for each phrase data.

  The multi-effector 85 also has a mixer that mixes digital audio of multiple channels generated by the tone generator into digital audio of up to three channels (R0 / L1 + R1 / L1 + SUB0 / SUB1), and a desired frequency by digital filter processing. It includes an equalizer function that realizes the characteristics and an effector that realizes a compressor function that changes the input / output gain characteristics, and a total volume that defines the final volume.

  On the other hand, the audio interface 86 includes audio signal lines SD0 to SD2 in which the left and right channels (R / L) of each channel are collected and clock signals for digital audio of up to three channels (R0 / L1 + R1 / L1 + SUB0 / SUB1). The signal is output to three lines: a line SCLK and a control signal line LRO that specifies which of the left and right channels (R / L) is being transmitted. For example, if there are three digital amplifiers 43 that receive audio signals of the first channel (R0 / L0), the second channel (R1 / L1), and the third channel (SUB0 / SUB1), the audio interface The transmission paths between the face 86 and the digital amplifier 43 are each three lines. However, in the present embodiment, the audio signal of the third channel (SUB0 / SUB1) is not used, and the second channel is set to monaural audio (R1 = L1).

  Next, FIG. 9 is a diagram showing the configuration of the relay register 82 and the command interface unit (voice command FIFO) 83. In this embodiment, the host CPU 50 sets the relay register 82 in both cases where the predetermined command register RGi is WRITE accessed and the status information is READ-accessed from the command register RGi in order to define the internal operation of the sound engine 52. An indirect access method is used.

  At the time of WRITE access, except for the time of system control access to be described later, the write data (setting value) to the command register RGi is stored in the FIFO-structured voice command buffer 83 (voice command FIFO) controlled by the WR pointer and RD pointer. It is automatically accumulated.

  Hereinafter, this point will be further described with reference to FIG. 9A. More specifically, the relay register 82, in detail, the first relay register MCR for writing a 1-byte register number specifying the command register RGi to be accessed. A second relay register MCD that writes a setting value to be set in the command register RGi of the register number, and a transfer register to which the main data of each 1 byte of the first relay register MCR and the second relay register MCD is transferred And TRN.

  Here, the transfer register TRN is 2 bytes in length, and the first and second relay registers MCR and MCD are each 4 bytes in length. Each 1-byte portion (register number / setting value), which is a main part of each relay register MCR, MCD, is connected to a transfer register TRN having a length of 2 bytes as a whole, and a write signal to the relay registers MCR, MCD Based on (WR * CS), it is configured to be automatically transcribed. Note that WR * CS means the logical AND value of the write control signal WR output from the host CPU 50 and the internal chip select signal CS for selecting the relay registers MCR and MCD.

  FIG. 9B is a diagram for explaining the transfer operation, and shows the first write signal (WR * CS) indicating the WRITE access to the first relay register MCR and the WRITE access to the second relay register MCD. A second write signal (WR * CS) and a logical OR signal of the first write signal and the second write signal are shown. In this embodiment, one byte (register number or set value) of the transfer register TRN is based on the preceding write signal (WR * CS) generated first out of the first write signal and the second write signal. The WR pointer is updated as the transfer operation is executed.

  Then, based on the subsequent write signal (WR * CS) generated thereafter, the transfer operation of the remaining 1 byte (register number or set value) to the transfer register TRN is executed, and the subsequent write signal (WR * CS) In synchronization with the subsequent edge, 2-byte data (register number + setting value) of the transfer register TRN is written into the voice command buffer 83 having a ring buffer structure. The writing destination of the voice command buffer 83 is specified by the WR pointer, and the reading destination is specified by the RD pointer. The number of stages of the voice command buffer (voice command FIFO) 83 is, for example, 511 stages (2 bytes × 511).

  Since the present embodiment is configured as described above, whenever the host CPU 50 writes necessary information (register number and setting value) in the relay registers MCR and MCD, the necessary information is automatically stored in the voice command buffer. (Voice command FIFO) 83 is accumulated. Therefore, the host CPU 50 can repeat the write operation to the relay registers MCR and MCD at its own timing without particularly minding the internal operation of the sound engine 52. However, it should be considered that the number of stages of the voice command buffer 83 is 511, and that the readout period of the voice command buffer 83 is 32/48 mS corresponding to the sound engine operation period (32/48 mS). Is natural.

  Note that the host CPU not only performs direct WRITE access to write an arbitrary set value to an arbitrary command register RGi, but also sets a SAC code number and other operating conditions to a group of command registers RGi for starting SACi. A SEQ code number and other operating conditions are set in a group of command registers RGj for starting operation and SEQj starting, and a SEQ starting operation is also possible. However, in any case, in principle, it is necessary to adopt an indirect access method via the relay register 82 or the voice command buffer 83.

  As shown in FIG. 9C, the data group in units of 2 bytes (register number + setting value) accumulated in the voice command buffer 83 is read out by the SCM 81 in the sound engine operation cycle (32/48 mS), By setting a predetermined set value in a predetermined command register RGi specified by the number, the internal operation of the sound engine 52 changes.

  Specifically, for example, when a specific voice phrase number is set in a predetermined command register RGi, a specific unit of sound production is started. In addition, there are cases where the volume and volume balance of subsequent audio effects change due to setting values that define the audio volume and volume pan in the predetermined command register RGi.

  Furthermore, by setting a SAC code number, a SEQ code number, or the like in a predetermined command register RGi, the simple access controller SAC or the sequencer SEQ starts a setting operation based on a series of SAC data or a series of SEQ data. In some cases.

  As described above, the operation of writing the set value to the command register RGi is, as a rule, executed by the SCM 81 via the voice command buffer 83. However, since the SCM 81 operates intermittently at the sound engine operation cycle (32/48 mS), there is a problem in that it lacks rapidity. Therefore, the voice command buffer 83 and the SCM 81 are used for settings related to the sound engine control operation (system control access) such as an operation for reading out status information such as an internal error of the sound engine 52 (READ access) and interrupt control. Instead, the host CPU 50 uses a direct access method.

  That is, when the host CPU 50 writes the register number of the command register RGi related to the control operation of the sound engine in the first relay register MCR and writes the system control setting value in the second relay register MCD (system control access), The system control set value is immediately written into the corresponding command register RGi. When the host CPU 50 makes a READ access to a predetermined command register RGi, the status information read from the command register RGi written in the first relay register MCR is acquired in the second relay register MCD.

  Although the first operation mode (normal control mode) in which the SCM 81 functions and executes the setting operation of the command register RGi has been described above, in this embodiment, the second operation mode in which the VDP controller 60 substitutes the operation of the SCM 81 ( (Simple control mode) is also possible. In the second operation mode, with the sound engine 52 set to the second operation mode, the host CPU 50 issues a voice command list SLT defining the setting operation to the command register RGi to the voice list buffer LBUF. Become.

  The audio list buffer LBUF needs to be secured in advance in the main memory 56, the built-in DRAM 57, or the DDR memory 41. Also, the voice command list SLT is issued at a timing when setting operation to the command register RGi is required.

  As shown in the voice list buffer LBUF described at the top of FIG. 8, the voice command list SLT is a two-byte combination of the register number (1 byte) of the command register RGi and the set value (1 byte) in the command register RGi. This is a voice command sequence in which long voice commands are listed, and the number of voice commands listed is defined at the top thereof.

  In the second operation mode (simple control mode), the voice command list SLT issued to the voice list buffer LBUF is decoded by the VCP controller 60, and the voice command list SRG specified by each voice command is sent to the voice register RGi. The setting value specified by the command is set. That is, in the second operation mode, since the VDP controller 60 substitutes the operation of the SCM 81, the simple access controller SAC and the sequencer SEQ do not function.

  Therefore, the VCP controller 60 that has detected the voice command that defines the SAC activation operation or the voice command that defines the SEQ activation operation, the group of SAC data defined by the SAC code number, or the group of SAC data defined by the SEQ code number. The SEQ data is read from the DDR memory 41 and set in the corresponding command registers RGi to RGj. Note that the relay register 82 and the voice command buffer 83 are also used in the setting operation by the VCP controller 60.

  When using the second operation mode (simple control mode) described above, the host CPU 50 issues the voice command list SLT to the command list buffer LBUF in the same procedure as the issue of the image command list LT. . The issued voice command list is read by the VDP controller 60 after one operation cycle (Δ = 1/30 seconds) which is a bank flip cycle, and the setting operation to the command register RGi described above is executed. .

On the other hand, since the setting operation in the first operation mode is executed every sound engine operation cycle (32/48 mS), the setting operation in the second operation mode has a drawback that it is inferior in speed while being simple. Therefore, if this time delay becomes a problem, a group of voice command strings (voice command list SLT) is stored in the voice command list register CRG _WSL of the control register CRG built in the VDP controller 60 instead of the command list buffer LBUF. ) To execute the second operation mode.

The voice command list register CRG _WSL of the embodiment is 1040 bytes long, and about 511 voice commands (2 bytes) can be listed. As described above, since the number of stages of the voice command buffer (voice command FIFO) 83 built in the sound engine 52 is, for example, 511 stages (2 bytes × 511), it means the control burden for writing by the host CPU 50. The voice command list register CRG _WSL and the voice command buffer 83 are equivalent.

However, after the host CPU 50 issues the voice command list SLT to the voice command list register CRG _WSL , the VDP controller 60 only starts WRITE access to the sound engine 52. The WRITE access of the voice command buffer 83 is superior.

  Next, the DMA controller 53 will be described with reference to FIG. FIG. 10A shows the operation when the power is turned on, and FIG. 10B shows the operation when the drive data of the lamp effect and the accessory effect is updated. The DMA controller 53 of the embodiment has 14 channels (DMA channel # 0 to DMA channel # 13) that can operate independently, but in this embodiment, the channel # 0 is made to function when the power is turned on, The audio data SND in the external ROM 42 is DMA transferred to the DDR memory 41.

  Specifically, the host CPU 50 specifies (1) the start address of the transfer source in the state where the DMA channel # 0 is specified as the DMA use channel, and (2) the one-time read size (bytes) from the transfer source to the DMA controller 53. Length), (3) number of READ transfers to the DMA controller 53, (4) start address of the transfer destination, (5) one-time write size (byte length) from the DMA controller 53 to the transfer destination, and (6) to the transfer destination. First, the operation contents such as the number of WRITE transfers are specified in the corresponding register of the DMA controller 53.

  Next, when the host CPU 50 instructs the corresponding register (channel 0 control register) of the DMA controller 53 to start operation, DMA transfer is started under the above operating conditions (1) to (6), and the transfer source and transfer destination The transfer operation of the read size and the write size is repeated while appropriately updating the address, and when all the transfer operations are completed, the completion flag of the corresponding register (DMA interrupt status register) of the DMA controller 53 is set to the set state. It has become.

  Therefore, after instructing the operation contents such as (1) to (6) and instructing the start of operation, the host CPU 50 can leave the transfer operation to the DMA controller 53 and execute completely different processing. In this embodiment, the DMA controller 53 can be set with a single read size, a READ transfer count, a single write size, and a write transfer count, so that the difference in access speed between the transfer source and the transfer destination can be set. It can be absorbed smoothly, and an appropriate transfer operation is realized even when the transfer source read unit and the transfer destination write unit are limited.

  Next, FIG. 10B is a diagram for explaining the operation of the DMA controller 53 at the time of updating the drive data of the lamp effect and the accessory effect. In the present embodiment, the lamp effect is advanced by updating the lamp drive data every 3 mS, and the accessory effect is advanced by updating the motor drive data every 1 mS. The lamp drive data and the motor drive data are stored in a nonvolatile manner in the lamp drive data tables LMPc and LMPd of the external ROM 42 and the motor drive data tables MOTe and MOTf, respectively. , The transfer source of the DMA controller 53.

  As described above, in this embodiment, the channel #C to channel #F of the serial port 55 are set as serial output ports to realize the lamp effect and the effect effect. #C to #F are transfer destinations for the DMA controller 53.

  In addition, the channel #C to channel #F of the serial port 55 are provided with transmission FIFOc to transmission FIFOOf configured by 64 stages of storage areas in units of 16 bits, respectively, and the driving stored in the transmission FIFOc to transmission FIFOOf Data is automatically read out by a FIFO (First In First Out) method and serially transmitted from the serial output ports of channel #C to channel #F.

  Here, data accumulation in the transmission FIFOc to the transmission FIFOOf is via the relay register ITM (data register) arranged in the interface part of each channel #C to #F, and writing to the relay register The data is automatically stored in the transmission FIFO. Therefore, in this embodiment, for the DMA controller 53, the transfer destination of the WRITE transfer is the relay register ITM arranged in the channel #C to the channel #F of the serial port 55, and the transfer source of the READ transfer is the drive data table LMP. , MOT.

  The lamp drive data of the data table LMPc and the data table LMPd and the motor drive data of the data table MOTe and the data table MOTe are serially transmitted from the external ROM 42 via the DMA channel # 10 to the DMA channel # 13, respectively. DMA transfer is performed to the relay register ITM of channels #C to #F of the port 55.

  The transfer from the data tables LMP and MOT to the DMA controller 53 (# 10 to # 13) is executed every 32 bytes, while the DMA controller 53 (# 10 to # 13) transfers to the serial port 55 (#C to # 13). The transfer of #F) to the relay register ITM is executed every two bytes. That is, the DMA controller 53 (# 10 to # 13) transfers the 32 bytes received in one transfer divided into 16 times.

  In addition, a threshold value defining the execution timing of write transfer is set in advance in each serial port 55 (#C to #F) by the host CPU 50, and the accumulated data amount of the transmission FIFO (transmission FIFOc to transmission FIFOf) is predetermined. The DMA_Request signal is output from the serial port 55 to the DMA controller 53, and the DMA controller 53 returns a DMA_Acknowledge signal and executes a unit (2 byte length) write transfer. Since the host CPU 50 does not need to participate in these handshake operations, the host CPU 50 that has started the transfer operation of the DMA controller need only wait for the transfer operation.

  Next, serial transmission using the serial port 55 (#C to #F) and the serial port 55 (#C to #F) will be described with reference to FIGS. First, based on FIG. 11A showing the internal configuration of the serial port, channels #E and #F of the serial port 55 operate in the SPI communication mode, while channels #C and #D of the serial port 55 are operated. Is set to operate in the LED drive mode.

  Here, the SPI communication mode is an operation mode that enables serial communication between a master device and a slave device in conformity with the Motorola SPI. When the SPI module functions, the chip select (CS) and serial communication are performed. A clock (SCK), serial input data (SI), and serial output data (SO) can be used. However, in this embodiment, the chip select signal (CS) for selecting the slave device is not used. In the following description, a case where a serial transmission operation is executed in the SPI communication mode is referred to as an SPI transmission mode, and a case where a serial reception operation is executed in the SPI communication mode is referred to as an SPI reception mode.

  In channels #E and #F of the serial port 55 functioning in the SPI transmission mode, serial output data (motor drive data) accumulated in the transmission FIFO of each channel (#E, #F) is synchronized with the serial clock SCK. Serially transmitted. When all the motor drive data of the transmission FIFO is serially transmitted, the status register (not shown) of each channel (#E, #F) is set to the transmission complete state. As described with reference to FIG. 10, the motor drive data of the motor drive data tables MOTe and MOTf are automatically transferred to the transmission FIFO by the Handshake method.

  On the other hand, the LED drive mode is an operation mode in which an additional module for LED driver (denoted as DR IF Module) functions in addition to the above-described SPI module. In this LED drive mode, a serial clock (SPCK), serial output data (SPO), and an OE signal (output enable) are output. The OE signal is a signal indicating that a group of serial output data (lamp drive data SPO) is being serially transmitted. In this LED drive mode, an operation of outputting a latch signal (LD) every time data transmission of one block is completed is possible, but this embodiment does not adopt such an operation mode.

  In channels #C and #D of the serial port 55 functioning in the LED driving mode, serial output data (lamp driving data) accumulated in the transmission FIFO of each channel (#C, #D) is synchronized with the serial clock SCK. Thus, serial transmission is performed sequentially, and the OE signal maintains an active level during the serial transmission.

  Also in this LED drive mode operation mode, when all the motor drive data of the transmission FIFO has been serially transmitted, the status register (not shown) of each channel (#C, #D) is set to the transmission complete state. It is like that. Note that the lamp drive data of the lamp drive data tables LMPc and LMPd are automatically transferred to the transmission FIFOs of the channels #C and #D by the Handshake method.

  Based on the above, a description of serial transmission of motor drive data will be added. FIG. 11C illustrates the structure of the motor drive data tables MOTe and MOTf, and FIGS. 11D and 11E are diagrams for explaining motor drive.

  As described above, in this embodiment, motor drive data is serially transmitted to the motor driver DV (see FIG. 12A) disposed on the frame-side and board-side motor drive boards 37 and 30. A plurality of motor drivers DV1 to DVn are arranged on the motor drive boards 37 and 30, respectively. As shown in FIGS. 12 (a) to 12 (b), each motor driver DVi is connected in series. It has four shift registers SR1 to SRE4 and drivers OUT1 to OUT4 that drive the accessory motor Mi by receiving the output of each shift register.

  Therefore, when the motor drive data SO is output from the serial ports (#E, #F) in synchronization with the serial clock SCK, the motor drive data SO is sequentially transferred to the shift register SRi. In this embodiment, motor drive data corresponding to the number N of motor drivers DVi is stored in the motor drive table MOT, and latch pulses LTe and LTf are output from the parallel port 54 after transmission of all motor drive data is completed. By doing so, all the motor drivers DV are made to acquire motor drive data, and the accessory motors M1 to Mn are stepped up.

  The accessory motors M1 to Mn are constituted by, for example, stepping motors, and FIGS. 11D and 11E show a case where the unipolar stepping motor is excited, for example, in two phases. . In such a configuration, the motor drive data to be transmitted to one of the accessory motors Mi is 4 bits, and in this embodiment in which K accessory motors are arranged on the motor drive board 37 on the frame side, The total motor drive data is 4 × K bits. In this embodiment in which L accessory motors are arranged on the board-side motor drive board 30, the total motor drive data is 4 × L bits.

  By the way, in this embodiment, since DMA transfer is adopted, data transfer from the motor drive tables MOTe and MOTf to the DMA controller 63 (channels # 12 and # 13) and the DMA controller 63 (channels # 12 and # 13) are performed. Data transfer from the serial port 55 to the serial ports 55 (channels #E and #F) must be performed in units of a predetermined byte.

  In this embodiment, for example, DMA transfer is repeated in units of 2 bytes, and the total number of bits of motor drive data to be DMA transferred needs to be an integral multiple of 16 bits. Therefore, in this embodiment, by adding dummy data DUMMY of necessary bits (X, Y) to the head of the motor drive data tables MOTe, MOTf, the value of 4 × K + X or the value of 4 × L + Y is 16 bits. It is an integer multiple of.

  FIG. 11C illustrates this state, and the required number (X, Y) of dummy data DUMMY is added to the heads of the motor drive data tables MOTe and MOTf. Therefore, the number of serial clocks SCK output from the serial ports (#E, #F) is 4 × K + X or 4 × L + Y, but X or Y dummy data DUMMY transmitted at the head is No problem occurs because there is no motor driver to receive this and it disappears.

  Since the motor driving data of 4 × K + X bit or 4 × L + Y bit specifies one operation mode of the stepping motor, in the present embodiment in which the unipolar stepping motor is excited in two phases, at least the first operation is performed. There are four modes from the mode to the fourth operation mode (see FIG. 11E), and the motor drive data table MOT has at least the first segment data to the fourth segment data specifying these four modes. Are transmitted in order (see FIG. 11C).

  However, such an operation is merely a simple operation in which a plurality of accessory motors rotate regularly and synchronously, and in an actual accessory effect, only a specific accessory motor may move irregularly. Many. Therefore, in actuality, a large number of motor drive data tables MOTi are prepared for each type of accessory effect, and the host CPU 50 selects the motor drive table MOTi to be referenced in accordance with the accessory effect at that time. Then, the motor drive data (4 × K + X bit or 4 × L + Y bit) to be serially output is specified, and the DMA transfer operation and the serial transmission operation are started.

  Although the SPI transmission mode has been described above, the channels #E and #F of the serial port 55 also have a timing to function in the SPI reception mode. In this case, the operation in the reception mode is started with the number of serial data received set in advance in the corresponding registers of channels #E and #F. Then, since the serial clock SCK corresponding to the number of received data is transmitted, the serial data (sensor signal etc.) is received in synchronization with the serial clock SCK, and the host CPU 50 acquires the parallel data for each predetermined unit. Become.

  FIG. 11D is a diagram for explaining the serial reception operation, and also shows the circuit configuration of the signal acquisition circuit GET. Note that one or a plurality of signal acquisition circuits GET having the illustrated configuration are arranged in series on the frame side and the board side. In any case, one signal acquisition circuit GET includes eight shift registers, and 8-bit parallel signals (A to H) are supplied to the parallel terminals OD of the shift registers. . Each shift register receives the acquisition pulse LT (LTe, LTf) in common, so that an 8-bit parallel signal is acquired in the eight shift registers. As shown in the figure, since the eight shift registers are connected in series, each time the serial clock SCK is received, its own held data is transferred to the downstream shift register.

  Since both the frame-side and board-side signal acquisition circuits GET operate as described above, in this embodiment, all the signal acquisition circuits GET on the frame-side or board-side are first connected from the parallel port 54. The acquisition pulses LTe and LTf are output, and then the necessary number of serial clocks SCK are output, so that necessary data is serially received.

  In this embodiment, since the channels #E and #F of the serial port 55 are used in the SPI transmission mode and the SPI reception mode, from the parallel port 54 to the frame side and panel side switches 47A and 47B, Switching control signals CTLe and CTf are output to switch the transmission destinations of the serial clocks SCKE and SCKf.

  That is, by switching the internal circuits of the switching units 47A and 47B by the switching control signals CTLe and CTf, the serial clocks SCKE and SCKf of the channels #E and #F that function in the SPI transmission mode are transmitted to the motor driver DV. The serial clocks SCKE and SCKf of channels #E and #F that function in the SPI reception mode are transmitted to the frame side and board side signal acquisition circuits GET and GET.

  Next, channels #C and #D of the serial port 55 functioning in the LED drive mode will be described with reference to FIG. In this embodiment, a plurality of lamp drivers DR shown in FIG. 13B are mounted on the lamp driving boards 3629 on the frame side and the board side.

  The lamp driver DR is configured to be able to drive eight (three in total) RGB LED lamps of RGB three colors, and as shown in FIG. 13B, a total of 24 output terminals (LEDR_1-8, LEDG_1). -8, LEDB_1-8), a 5-bit address terminal (A0 to A4) that defines a unique slave address for each element, a clock terminal SCLK that receives the serial clock SPCKc / SPCKd, and lamp drive data SPOc / SPOd It has a serial terminal SDATA for receiving and a control terminal SDEN for receiving an operation control signal OEc / OEd.

  As shown in FIG. 13A, the clock terminal SCLK, the serial terminal SDATA, and the control terminal SDEN are commonly supplied to all the lamp drivers DR1 to DRn. In FIG. 13A, address signals 00000b to 11111b are supplied to address terminals (A0 to A4) of 32 lamp drivers DRi, and slave addresses of 32 lamp drivers DRi are 0. An example of ~ 31 is shown. Therefore, in this configuration, 256 (= 32 × 8) LED lamps for each color of RGB can be arranged.

  The lamp driver DR is configured to perform gradation control (Brightness Control) of light emission luminance for each of 24 LED lamps (eight RGB colors), and a duty ratio defined by 8 bits. A total of 30 built-in registers (R1 to R30) are built in, including 24 that can be set. Each built-in register (R1 to R30) needs to be set with 8-bit length setting data such as a duty ratio for defining a gradation, and each built-in register has an 8-bit register address (00h to 1Dh). ).

  Therefore, in order to control the light emission brightness of the 24 LED lamps to be driven by the lamp driver DR, a total of 30 built-in registers (R1 to R30) are specified with the slave address of the lamp driver DR specified. Necessary setting data must be transmitted.

  FIG. 13C is a time chart showing an operation procedure in the case where 8-bit length setting data is written in a predetermined built-in register of the lamp driver DR. As shown in the figure, the slave address is serially transmitted in synchronization with the serial clock supplied to the clock terminal SCLK while the control terminal SDEN is maintained at the active level, and then the register address for specifying the built-in register is serially transmitted. There is a need.

  After the above operation, the setting data to be set in the specified built-in register is serially transmitted. In this lamp driver DR, the control terminal SDEN is at the active level, and the 24th serial clock is changed. At the rising edge, the setting data transmitted third is written in the built-in register specified before (a three-wire transmission method that requires a signal to the control terminal SDEN).

  The case where setting data is set in a specific built-in register has been described above, but when setting data is set in all the built-in registers (R1 to R30), the operation shown in FIG. That is, with the control terminal SDEN set to the active level, the slave address is serially transmitted, and then the first register address (00h) is serially transmitted, and then the setting data to the built-in register is serially transmitted.

  With these operations, the setting operation to the first built-in register (R0) is completed, but if serial transmission is continued thereafter, the slave address is incremented by the internal operation, and then the serially transmitted setting data is changed to 8 bits. Each time it reaches, setting data is set in each of the built-in registers (R1 to R29).

  Since the lamp driver DR of the embodiment operates as described above, a total of 256 serial clocks should be transmitted in order to write setting data to one lamp driver DR. The number of 256 is the same as the number of bits of transmission data, and is the total number of 30 × 8 bits for 8 bits of slave addresses, 8 bits of register addresses, and 30 built-in registers. Corresponding to the above operation, channel #C and channel #D of the serial port 55 need to operate as shown in FIG.

  By the way, in the composite chip of the embodiment, the serial port 55 operating in the LED drive mode needs to define a bit length of one sample which is one unit of serial transmission. In the LED drive mode, the OEc / OEd signal is output as an Output Enable signal in units of one frame so as to correspond to the above-described three-wire transmission method. It is necessary to specify the number.

  As shown in FIG. 13A, the OEc / OEd signal is supplied to the control terminal SDEN of the lamp driver DR, and the operation condition of the lamp driver DR is that the SDEN terminal is at the H level. As described above, the total amount of data to be transmitted to one lamp driver DR is 256 bits.

  Therefore, in consideration of the above points, in this embodiment, one sample is 16 bits long and 16 samples (each 16 bits long) constitute one frame. FIG. 11B illustrates this relationship, and the lamp drive data tables LMPc and LMPd store lamp drive data to be transmitted to each lamp driver DR in units of 16 × 16 bits. . Since the lamp effect proceeds with time, lamp drive data tables LMPc and LMPd corresponding to the operation mode are prepared at the minimum.

  As in the case of the accessory effect, not all LED lamps are turned on / off synchronously in the lamp effect, and only a specific group of LED lamps may be turned on / off. Therefore, actually, a large number of lamp drive data tables LMPc and LMPd are prepared. However, in any of the lamp drive data tables LMPc and LMPd, the lamp drive data to be transmitted to one lamp driver DR is 16 × 16 bits (32 bytes), as in the case of the motor drive data tables MOTe and MOTf. Dummy data DUMMY is not required.

  That is, a DMA transfer operation is executed in units of 32 bytes from the motor drive data tables MOTe and MOTf to the DMA controller 63 (channels # 10 and # 11), and the serial port 55 is transferred from the DMA controller 63 (channels # 10 and # 11). For the transmission FIFO of (channel #C, #D), a DMA transfer operation is executed in units of 2 bytes. When serial transmission of the lamp driving data of the transmission FIFO is completed, the status register (not shown) of each channel (#C, #D) is set to the transmission complete state.

  Although the case where the number of transfer data to one motor driver is 16 × 16 bits has been described above, the data transfer unit from the motor drive data tables MOTe and MOTf to the DMA controller 63 and the DMA controller 63 to the transmission FIFO are described. If the data transfer unit does not match, appropriate dummy data DUMMY may be added to match the transfer unit.

  In FIG. 13, the three-wire transmission method is used. However, it is also preferable to adopt a two-wire transmission method that does not use the control terminal SDEN of the lamp driver. In this case, since the control terminal SDEN is not used, the OEc / OEd signal is not utilized as shown in FIG.

  In this two-wire transmission method, when the serial bit string to be transmitted satisfies the start condition of the bit mode shown in FIG. 14C, each lamp driver DRi becomes active. However, it is necessary to output the BLANK bit for each break of the start condition (9 bits), slave address (8 bits), register address (8 bits), and setting data (8 bits). Then, at the rising edge of the BLANK bit, each bit string is grasped by the lamp driver DRi, and setting data is acquired in any of the 30 built-in registers.

  Even in the operation mode of the two-wire transmission method, after transmitting the register address of the first built-in register, the register address is automatically incremented by the internal operation, so that all the built-in registers (30 pieces of one lamp driver DR) In order to set the setting data in (), it is necessary to transmit serial data of 10 + 9 + 9 + 9 × 30 = 298 bits. Thus, in the case of the two-wire transmission method, the number of transmission data to one lamp driver DR increases by the start bit (9 bits) and the BLANK bit, but for a plurality of lamp drivers, There is an advantage that serial data transmission can be completed at once.

  That is, in the case of the three-wire transmission method, it is necessary to output the OE signal again every 256-bit serial transmission to one lamp driver DR, but in the case of the two-wire transmission method, N lamp drivers DR1. With respect to .about.DRn, a total of 298.times.N bits of data can be output at once, so the control burden on the host CPU 50 is reduced.

  FIG. 14D shows a case where, for example, 32 lamp drivers DR1 to DR32 are driven in channels #C and #D of the serial port 55 functioning in the LED drive mode, and a total of 9536 bits of data is shown. Shows the state of serial transmission as 596 sample data for every 16 bits constituting one sample.

  In this embodiment, one sample corresponds to the transfer unit of DMA transfer (see FIG. 11A), and the number of transfers from the DMA controller 63 to the transmission FIFO of the serial port 55 is 596 times. In the two-wire transmission system, as described above, the OEc / OEd signal is not used.

  The case where the channels #C and #D of the serial port 55 are made to function in the LED drive mode has been described above, but is not particularly limited, and the SPI communication mode can also be used. FIG. 14E illustrates a case where the channels #C and #D of the serial port 55 are functioned in the SPI communication mode and, for example, ten lamp drivers DR1 to DR10 are driven.

  In this case, the total number of data to be serially transmitted is 298 × 10 bits, but since the transfer unit from the DMA controller 63 to the transmission FIFO of the serial port 55 is 16 bits, a 12-bit dummy bit DUMMY is set. In addition, the total is 2992 bits.

  Then, a total of 2992-bit serial transmission is executed at a time while the data transfer from the DMA controller 63 to the transmission FIFO of the serial port 55 is repeated 187 times (= 2992/16). As described above, by adding the dummy bit DUMMY, serial transmission utilizing DMA transfer to the transmission FIFO of the serial port 55 becomes possible regardless of the number of lamp drivers DR arranged. Note that this point does not matter whether the mode is the LED drive mode or the SPI communication mode. The dummy bit DUMMY is optional as long as it is a bit string that does not satisfy the start condition.

  As described above, the circuit configuration and the circuit operation of the effect control unit 22 have been mainly described. Next, the control operation of the effect control unit 22 will be described with reference to FIGS. The effect control unit 22 includes a main process (FIG. 15A) executed after power-on, a reception interrupt process (FIG. 15B) activated when receiving a control command CMD from the main control unit 21, and Timer interrupt processing (FIG. 6 (a)) that is repeatedly started every 1mS.

  FIG. 15A shows the operation of the host CPU 50 after the power is turned on. First, the initial setting process is executed for the built-in register of the composite chip 40, and the preparation for the subsequent production control is completed (ST10). FIG. 15B illustrates a part of the initial setting process. First, using the DMA controller 63 (channel # 0), the audio data SND stored in the external ROM 42 is converted into the DDR memory. 41 is DMA-transferred.

  Specifically, as described with reference to FIG. 10A, for the DMA transfer of the voice data SND, first, the DMA channel # 0 is specified as the DMA use channel, and the operation parameters necessary for the MDA transfer are set to DMA. The corresponding register of the controller 63 is set (ST1). The operation parameters to be set include (1) the leading address of the transfer source in the external ROM 42, (2) the size of reading once (byte length) from the transfer source to the DMA controller 53, and (3) the DMA controller from the external ROM 42. READ transfer count to 53, (4) start address of transfer destination in DDR memory 41, (5) one-time write size (byte length) from DMA controller 53 to transfer destination, (6) DMA controller 53 to DDR memory 41 The number of WRITE transfers to is included.

  Next, when the host CPU 50 instructs the corresponding register of the DMA controller 53 to start operation (ST2), DMA transfer is started under the operating conditions set in the processing of step ST1, and the transfer source and transfer destination addresses are set. While appropriately updating, the transfer operation of the read size and the write size is repeated.

  Since there is no need for the host CPU 50 to participate in this DMA transfer, the host CPU 50 subsequently stores the fact in the corresponding register of the VDP controller 60 when executing a pre-read operation (preload) of CG data from the external ROM. Is set (ST2). Next, the host CPU 50 instructs the sound engine 52 to perform a regular SAC operation (ST4).

  As described above, the periodic SAC operation executed in the present embodiment is an operation of repeatedly resetting the equalizer function and the compressor function in the multi-effector 85, and the sound engine 52 that has received the setting in step ST4 thereafter , The sound quality setting operation is repeated every 32/48 × 512 mS. Since the sound engine 52 includes a plurality of simple access controllers SAC, it is also preferable to set a plurality of types of regular SAC operations.

  In addition, the initial setting process (ST10) includes setting of operation parameters related to the VDP controller 60 (ST5) such as a bank flip period (1/30 second). These are shown in FIGS. This will be described later. Finally, an effect scenario for an initial effect that starts after the power is turned on is specified, and the initial process ends (ST6).

  When such an initial setting process (ST10) is completed, the processes of steps ST11 to ST20 are repeatedly executed in an infinite loop every bank flip period (1/30 second). During this infinite loop process (steps ST11 to ST20), the control command CMD may be received from the main control unit 21. In this case, the process of FIG. 15B is executed as the reception interrupt process. The

  In the reception interrupt process, the received control command CMD is first stored in the reception buffer (ST22). Then, the stored control command CMD is read out in the process of step ST19 of the infinite loop process, and the rendering operation based on the control command CMD is started. Further, when the control command CMD specifies the result of the lottery process as the winning state (ST23), the winning information is stored in the nonvolatile memory 26 disposed on the liquid crystal IF substrate 25 together with the time information ( ST24).

  When a control command CMD indicating that the setting key SET has been operated is received, a history display operation for displaying the game record history stored in the nonvolatile memory 26 on the display device DSP1 is started. Specifically, the history display command flag FG is set to 1 (ST25).

  This command flag FG is referred to in the process of step ST19, and a necessary image control operation is executed through the process of step ST20 and the like. In addition, when a control command CMD indicating that the initialization switch SW has been operated is received during the image control operation, the command flag FG is set to 2, and then, on condition that the chance button 11 is pressed. All the contents stored in the nonvolatile memory 26 are erased. Note that the pressing of the chance button is grasped in real time in the timer interrupt processing for every 1 mS (ST42 in FIG. 16).

  Subsequently, the infinite loop process of FIG. 15A will be described. In the infinite loop process, first, the image effect process (ST11) is executed based on the effect scenario specified in the process in step ST6 or the process in step ST19. This command list process is illustrated in FIG. Will be described later.

  Next, it is determined whether or not it is the update timing of the audio effect by comparing the elapsed time from the start of the effect and the effect scenario updated in the process of step ST20 (ST12), and the update timing of the audio effect is reached. If so, the voice command string is written into the relay buffer 82 shown in FIG. 5 or FIG. 9 (ST13). In this embodiment, since the voice command list SLT is not used, the host CPU 50 directly performs WRITE access to the relay buffer 82 (MCR, MCD).

  As described above, the voice command has a 2-byte length in which the register number (1 byte) of the command register RGi of the sound engine 52 and the set value (1 byte) in the register RGi are a set. Then, as described with reference to FIG. 9, the host CPU 50 writes a 4-byte length including the register number to the first relay register MCR and writes a 4-byte length including the set value to the second relay register MCD.

  Then, since the 2-byte length (register number + setting value) extracted from the relay register 82 is automatically accumulated in the voice command FIFO (see FIG. 9), the host CPU 50 has a group of voice commands (voice command sequence). ) May be repeatedly written to the same relay register 82. As described above, the voice command sequence stored in the voice command FIFO is read out by the SCM (sound control module) 81 shown in FIG. 8 by the FIFO method at every operation cycle (32/48 mS) of the sound engine 52. Then, the setting operation to the command register RGi is executed.

  After the sound effect is advanced as described above, it is determined whether or not it is the update timing of the lamp effect (ST14). If the update timing is reached, the host CPU 50 updates the reference positions of the lamp drive data tables LMPc and LMPd. (ST15). In addition, since the update timings of the lamp effects on the frame side and the board side do not necessarily match, only the reference position of the corresponding lamp drive data table LMPc / LMPd may be updated. Further, as described above, it is not limited to the regular update as shown in FIG. 11B, and only a specific LED lamp may be turned on / off.

  Next, the host CPU 50 controls each unit to serially transmit a group of data specified by the reference position of the lamp drive data table LMPc / LMPd from the channel # C / # D of the serial port 55 (ST16). The specific operation is as shown in FIG. 15 (d). For each lamp driver DR, the reference position of the lamp drive data table LMP is specified (ST33), and necessary operation parameters for the DMA transfer are set in the DMA controller. The corresponding register is set (ST34).

  As described with reference to FIG. 10B, the necessary operation parameters include (1) the leading address of the transfer source in the lamp drive data table LMPc / LMPd, and (2) the transfer source to the DMA controller 53 (# 10 / # 11). (3) The number of READ transfers from the lamp drive data table LMPc / LMPd to the DMA controller 53 (# 10 / # 11) (one time in FIG. 10B) ), (4) Address of transfer destination in channel # C / # D of serial port 55 (address of relay register ITM in the embodiment), (5) Once from DMA controller 53 (# 10 / # 11) to transfer destination (6) Channel #C from the DMA controller 53 to the serial port 55 WRITE transfer count to #D (Fig 10 (b) in 16 times) are included.

  Further, the operation parameters necessary for the DMA transfer of the lamp driving data include the transmission FIFO of the channel # C / # D of the serial port 55 described with reference to FIG. 10B and the DMA controller 53 (# 10 / # 11). Also included is a threshold value related to the amount of data stored in the transmission FIFO that realizes the hand shake operation during

  Then, a predetermined value is set in the corresponding register of the DMA controller to start the operation of the DMA controller 53 (# 10 / # 11) (ST34), and the corresponding register of the serial port 55 (channel # C / # D) is set. The serial transmission operation is started by setting a predetermined value (ST35). In the embodiment of FIG. 15D, the corresponding register needs to be set in advance so that the serial port 55 (channel # C / # D) is activated in the LED drive mode (ST35).

  The subsequent operation is as shown in FIGS. 13D and 14D, and serial transmission processing is executed until the transmission FIFO of the serial port 55 (channel # C / # D) becomes empty. . Since the host CPU 50 does not need to be involved in this serious transmission process at all, the host CPU 50 refers to a predetermined status register and waits for the end of transmission of the serial port 55 (channel # C / # D). (ST36).

  As described above, in the LED driving mode, the OE signal is output in units of one frame (16 samples = 256 bits in the embodiment), and one frame (256 bits) is processed to one lamp driver DR. The serial transmission process ends. Therefore, the host CPU determines whether or not all the processes have been completed (ST37), and executes the process of step ST33 if the process should shift to the serial transmission process to the next lamp driver DR.

  The LED driving mode in the three-wire transmission method has been described above, but when the two-wire transmission method is adopted, the serial port 55 (channel # C / # D) is used in the LED driving mode or in the SPI communication mode. Regardless of whether it is used or not, since the necessary serial data is serially transmitted to all the lamp drivers DR at once, the process of step ST37 is unnecessary.

  However, in this case, in the process of step ST34, (2) the size of one read from the transfer source to the DMA controller 53 (# 10 / # 11) or (5) the DMA controller 53 (# 10 / # 11) The one-time write size for the transfer destination is, for example, 2 bytes long (see FIG. 10C).

  Corresponding to this setting, in lamp driving in the LED driving mode shown in FIG. 14D, (3) READ transfer count from the lamp driving data table LMPc / LMPd to the DMA controller 53 (# 10 / # 11). (6) The number of times of WRITE transfer from the DMA controller 53 to the channel # C / # D of the serial port 55 is 596 times respectively, and the total becomes 2 × 596 × 8 = 9536 bits (FIG. 10 (c )reference).

  In the lamp driving in the SPI communication mode shown in FIG. 14E, (3) READ transfer count and (6) WRITE transfer count are each 187 times, and 2 × 187 × 8 = 2992 bits as a whole. (See FIG. 10C).

  As described above, when the processing of step ST16 is completed, it is next determined whether or not it is the update timing of the accessory effect (ST17). If the update timing has been reached, the reference position of the motor drive data table MOT is updated (ST18). However, since the progress of the effect production is executed by timer interruption every 1 mS (FIG. 16), the host CPU 50 next analyzes the control command received in the reception interruption processing (ST19).

  When a variation pattern command for specifying the result of the big hit lottery process is received, an effect scenario corresponding to the type of the variation pattern command is specified through an effect lottery (ST19). In addition, this effect scenario unifies all of the image effect, the lamp effect, the accessory effect, and the sound effect together with the time information of the effect progress.

  Next, the reference position of the effect scenario is updated based on the elapsed time from the start of the effect (ST20), and a bank flip is awaited (ST21). As described above, in this embodiment, the bump flip timing is set to twice the period of the vertical synchronizing signal of the display device, and the process until step ST20 is performed within 1/30 second from the start of execution of step ST11. Since the process only needs to be completed, the processes of steps ST11 to ST20 can be appropriately complicated. In this embodiment, since the command list process (ST11) is executed immediately after the bump flip and the image command list is issued, the processing time of about 1/30 second is secured in the VDP controller. Become.

  Next, timer interrupt processing will be described with reference to FIG. In the timer interruption process, various sensor signals are repeatedly acquired, and the accessory effect is advanced when necessary. Therefore, first, it is determined whether or not the motor drive data should be updated (ST30). And when it is not in effect production, the process of steps ST31-ST36 is skipped.

  On the other hand, if it is the timing to move any one or more accessory motors, first, the channels #E and #F of the serial port 55 are set to the SPI transmission mode. Actually, in many cases, only one of the frame-side motor drive board 37 and the board-side motor drive board 30 operates, and the processing of steps ST31 to ST37 described below is performed by the motor drive board 37. As for the motor drive board 30, it is executed only for one of them, or the processes of steps ST31 to ST37 are repeated twice.

  However, in the following description, for the sake of convenience, it is simplified if all the motor drivers DV to DV on the motor drive board 37 and the motor drive board 30 function synchronously, and a virtual case where all the motor drivers DV to DV are controlled collectively. I will continue to explain.

  In such a virtual case, the host CPU 50 next outputs the first level switching control signals CTLe and CTLf from the parallel port 54 (ST32). This is because the transmission destinations of serial clocks SCKE and SCKf that are output thereafter are the motor drivers DV mounted on the motor drive boards 37 and 30.

  Next, if it is time to advance the accessory motor, the reference positions of the motor drive data tables MOTe and MOTf are updated (ST33). Then, operation parameters necessary for the DMA transfer of the motor drive data are set in the corresponding register of the DMA controller 53 (# 12 / # 13) (ST34).

  The necessary operating parameters include (1) the start address of the transfer source in the motor drive data table MOTe / MOTf, and (2) the read size from the transfer source to the DMA controller 53 (# 12 / # 13) (for example, 2 bytes), (3) READ transfer count from motor drive data table MOTe / MOTf to DMA controller 53 (# 12 / # 13), (4) Address of transfer destination in channel # E / # F of serial port 55 (In the embodiment, the address of the relay register ITM), (5) One write size (for example, 2 bytes) from the DMA controller 53 (# 12 / # 13) to the transfer destination, (6) From the DMA controller 53 to the serial port 55 The number of WRITE transfers to channel # E / # F is included.

  The operation parameters necessary for the DMA transfer of the motor drive data include the transmission FIFO of the channel # E / # F of the serial port 55 described with reference to FIG. 10B, the DMA controller 53 (# 12 / # 13), and Also included is a threshold value related to the amount of data stored in the transmission FIFO that realizes the hand shake operation during

  After setting the above operation parameters, the host CPU 50 activates the DMA controller 53 (# 12 / # 13) (ST34) and starts serial transmission of the channel # E / # F of the serial port 55 (ST35). . Then, based on the hand shake operation of the DMA controller 53 (# 12 / # 13), the motor drive data is transferred to the transmission FIFO of the channel # E / # F, and the serial transmission operation is repeated.

  Therefore, the host CPU 50 refers to a predetermined status register and waits for all motor drive data to be transferred (ST36). Then, at the timing when transmission completion is confirmed, the host CPU 50 outputs latch pulses LTe and LTf to each motor driver through the parallel port 54 (ST37). The motor drivers DV1 to DVn receive the latch pulses LTe and LTf, and output the acquired motor drive data to the accessory motors M1 to Mn, so that the accessory motors M1 to Mn advance (see FIG. 12 (a) and FIG. 12 (b)).

  When the above processing is completed, the host CPU 50 sets the channels #E and #F of the serial port 55 to the SPI reception mode (ST38), and outputs the second level switching control signals CTLe and CTLf from the parallel port 54. (ST39). This is because the transmission destination of the clock signal output thereafter is the signal acquisition circuits GET and GET mounted on the motor drive boards 37 and 30.

  Unlike the case of the driving operation of the accessory motor (ST30 to ST37), the serial reception process described below is always executed every 1 mS regardless of whether or not the accessory effect is being performed. Therefore, in this embodiment, various sensor signals supplied to the signal acquisition circuits GET and GET can be grasped almost in real time.

  When the process of step ST39 is completed, the host CPU 50 outputs acquisition pulses LTe and LTf to the signal acquisition circuits GET and GET through the parallel port 54 (ST40). As described with reference to FIG. 12C, the signal acquisition circuits GET and GET acquire various sensor signals SNi and SNj based on the acquisition pulses LTe and LTf.

  Therefore, next, the host CPU 50 starts the serial input process of the serial port 55 (channels #E and #F) (ST41). Specifically, as shown in FIG. 16B, first, after identifying the number of serial clocks SCKE and SCKf to be output (ST43), 1-bit dummy data is transferred to the serial port 55 (channel # E and #F) are written in the transmission shift register (ST44).

  Then, triggered by this write operation, the output operation of the designated number of serial clocks SCKE and SCKf is started from the serial port 55 (channels #E and #F). As described with reference to FIG. 12D, since the signal acquisition circuits GET and GET transfer the sensor signals SNi and SNj bit by bit in synchronization with the serial clocks SCKE and SCKf, the serial ports 55 (channel #E and In #F), this is acquired. Note that serially received sensor signals are temporarily stored in the reception buffers of channels #E and #F in units of 1 byte or 2 bytes.

  The completion of the output processing of the specified number of serial clocks SCKE and SCKf is confirmed by the corresponding status register of the serial port 55 (channels #E and #F) (ST45), so that the completion of the serial reception processing is grasped. The host CPU 50 transfers the sensor signals SNi and SNj temporarily stored in the reception buffer to a predetermined buffer area (ST42). The sensor signals SNi and SNj transferred to the buffer area are appropriately used in the subsequent image effect, sound effect, and accessory effect.

  Next, the command list process (ST11) for image effect will be described based on FIG. FIG. 17A is a flowchart for explaining image control when a command list is issued to the DDR memory 41, and additionally describes an initial setting process (ST10) related to an image effect. In this embodiment, since no preloader is used, the process of step ST3 in FIG. 15C is not executed.

  To explain the above, the host CPU 50 writes a predetermined set value in the corresponding register of the VDP controller 60 so as to set the bank flip period to 1/30 seconds as an initial setting process (ST10) after power-on. (ST50). Also, the start address of the image command list LT is set (ST51).

  As described above, in this embodiment, the image command list LT can be issued to the command memory 56, the built-in DRAM 57, and the DDR memory 41. However, the basic issue destination is always the image command buffer 71. It is said.

  Therefore, the host CPU 50 sets CBA information and CBM information related to the head address of the image command buffer 71 in a corresponding register that defines the issue destination of the image command list LT (ST51), and subsequently starts processing of the command list. Is set to be permitted in the corresponding register (ST52). The CBM information indicates whether the image command list is issued to the image command buffer (built-in register) 71, or the main memory 56, built-in DRAM 57, DDR memory 41, or external ROM 42. This is memory information to be specified, and the CBA information is a relative address value in the specified memory.

  As a result of the above setting process (ST50 to ST52), each time a bank flip occurs, the operation of the VDP controller 60 and the like is initialized, and the CBA information on the image command list LT issued to the image command buffer 71 by the host CPU 50 is obtained. Based on the / CBM information, the read operation by the VDP controller 60 is repeated.

  Next, the host CPU 50 creates an image command list LT for the current cycle (ST53). The image command list LT changes variously according to the progress of the image effect. In any case, as shown in FIG. 17B, the image command list LT ends with a WAIT_BANKFLIP command meaning a bank flip wait.

  Incidentally, a JUMP_DDR instruction may be described in the middle of the image command list LT. Here, the JUMP_DDR instruction specifies the start address of the DDR memory 41 to which processing is to be subsequently transferred and the data size of the image command list LT ′ (hereinafter referred to as the auxiliary list LT ′) described after the start address. This is a JUMP instruction (see FIG. 17C) and substantially means a SUBROUTINE_CALL instruction that does not require the RETURN instruction to be described. The same applies to the JUMP_BUFa instruction, JUMP_BUFb instruction, and JUMP_CFIFO instruction described below, and the JUMP destination address is specifically specified by specifying the data size including the case of zero.

  This auxiliary list LT ′ describes a process that is repeated for a certain period regardless of the progress of the image effect. After being issued to the DDR memory 41 at a predetermined timing of the effect progress, it passes through the JUMP_DDR command. Thus, it is read repeatedly. Further, the auxiliary list LT ′ newly issued to the DDR memory 41 at the subsequent timing is also repeatedly read via the JUMP_DDR instruction.

  Accordingly, in the process of step ST53, in addition to the creation of the image command list LT, an auxiliary list LT 'may be created, or a JUMP_DDR instruction may be described in the created image command list LT. In any case, following step ST53, the host CPU 50 issues an image command list LT to the command buffer 71, and issues an auxiliary list LT ′ to the DDR memory 41 as necessary (ST54). This process is completed, and the next bank flip is awaited (ST21).

  On the other hand, the VDP controller 60 sequentially reads out the image command list LT issued in the current cycle from the image command buffer 71 and causes the CG data decoder 62 and the rendering engine 61 to function so that each frame of the display devices DS1 and DS2 Is completed in the drawing bank of the frame buffer FB. Based on the WAIT_BANKFLIP command, the next bank flip is awaited. As described above, in the next bank flip, since the drawing bank and the display bank of the frame buffer FB are switched, the image data completed this time is displayed on the display devices DS1 and DS2 after the next bank flip. Become.

  As described above, in the embodiment of FIG. 17 (a), the processing repeatedly used for a certain period of the image effect progress is described in the auxiliary list LT ′ and stored in the DDR memory 41, corresponding to the progress of the image effect. Thus, the control burden on the host CPU that creates the image command list LT is reduced. Although the DDR memory 41 is illustrated here, the command memory 56, the built-in DRAM 57, and the external ROM 42 may be used instead of the DDR memory 41 as described above. The external ROM 42 needs to store a fixed auxiliary list LT ′ in advance.

  The embodiment in which the issued image command list LT is read in the cycle has been described above. However, in order to secure the processing time for the VDP controller 60, the case where the operation shown in FIG. This will be explained based on.

  In this case, it is necessary to secure a pair of buffer areas (BUFa, BUFb) in the command memory 56 in the initial setting process (ST10) (ST51 '). Note that the bank flip period is set to 1/30 seconds (ST50), the head address of the image command buffer 71 is set as the issue destination of the image command list LT (ST51), and the processing of the command list is started. The permission setting (ST52) is the same as in the case of FIG.

  When the above processing is completed, the host CPU 50 first creates an image command list LT for the current cycle for the buffer area BUFa / BUFb referenced in the current cycle, and issues this to the image command buffer 71 (ST56). This image command list LT is referred to as a control command list LTc in the description of FIG. 6, and a JUMP instruction (JUMP_BUFa / JUMP_BUFb) specifying a buffer area of the command memory 56 to be referred to this time and a bank flip wait Only the instruction (WAIT_BANKFLIP) is described.

  The image command list LT (control command list LTc) issued to the image command buffer 71 by the process of step ST56 is immediately read out by the VDP controller 71, and the process of the image command list LT issued in the previous cycle is started. (See FIG. 5). Therefore, the process of FIG. 17B is superior to the process of FIG. 17A in the sense that a sufficient processing time is secured in the VDP controller 71.

  Next, the host CPU 50 creates an image command list LT to be processed in the next cycle (ST57). As described with reference to FIG. 5, the last line of the image command list LT is a JUMP instruction (JUMP_CFIFO) that means a return to the WAIT_BANKFLIP instruction of the image command buffer 71.

  Next, the host CPU 50 toggles the issue destination of the image command list LT (ST58), and issues the image command list LT created in the process of step ST57 to the issue destination (ST59). That is, either one of the head addresses of the pair of buffer areas (BUFa, BUFb) is selected as the issue destination of the current image command list LT (ST58), and the image command list LT is issued to the selected buffer area ( ST59).

  Note that the toggled buffer area is used in the process of step ST56 of the next cycle (see FIG. 5). In addition, the image command list LT issued in the process of step ST59 is activated in the next cycle. The subsequent processing is the same as in FIG. 17A, and after performing other necessary processing (ST12 to ST20), the next bank flip is awaited (ST21).

  Subsequently, a control operation for realizing the operation described above with reference to FIG. 7 will be described with reference to FIG. In this embodiment, since the preloader functions, the process of step ST3 in FIG. 15C is executed. The image command list LT described below describes a special decode command DCp for instructing preload transfer.

  As in the embodiment of FIG. 17, the bank flip period is set to 1/30 seconds (ST60), but an appropriate number of list buffers TG (# 0) for temporarily storing the image command list LT in the DDR memory 41. , # 1,..., #N) need to be secured (ST61). In FIG. 7, the list buffer TG is represented as BUFa, BUFb, and BUFc. However, in FIG. 18C, for the triple buffer TG in which the number N of list buffers TG is N = 2, # 0, It is illustrated as # 1, # 2. In this embodiment, the processes of step ST51 and step ST52 of FIG. 17 are not executed at the time of initial setting but are executed individually in the steady process.

  In the steady process, first, a control command list LTc, which is an image command list composed only of WAIT_BANKFLIP commands, is issued to the command buffer 71 (ST62). Next, the host CPU 50 sets a command list start address (that is, the head address of the image command list LT) for the image command list LT to be validated in the current cycle (ST63).

  Specifically, the DDR memory 41 is specified as the CBM information specifying the memory type, and the head address of the corresponding list buffer TG is specified as the CBA information specifying the relative address in the DDR memory 41. In order to facilitate the processing of step ST63, a head address buffer (see FIG. 18C) storing the head address of the list buffer TG (# 0, # 1,..., #N) is prepared. The CBA / CBM information is specified by sequentially reading out the head address buffer.

  Then, by permitting the start of processing of the image command list LT (ST64), the processing of the image command list LT after the head address specified in step ST63 is started (see FIG. 7). For example, when the list buffer TG # 1 is selected in the processing of step ST63, the VDP controller 71 performs decoding and drawing processing based on the image command list LT described in the list buffer TG # 1. After executing JUMP_CFIFO, WAIT_BANKFLIP in the control command list LTc stored in the command buffer 71 is executed to wait for a bank flip (see FIG. 18 (f)).

  Next, the host CPU 50 creates an image command list LT to be validated after N cycles (ST65). Note that at the end of the image command list LT, there is always a JUMP instruction (JUMP CFIFO) which means a return to the WAIT_BANKFLIP instruction of the control command list LTc of the command buffer 71.

  Next, the issue destination of the image command list LT is updated (ST65), and the image command list LT created by the process of step ST64 is issued to the list buffer TG (for example, TG # 0) (ST66). As described with reference to FIG. 7, in the process of step ST66, for example, the image command list LT issued to the list buffer TG # 0 is interpreted in the process of the next cycle after the bank flip, and the decode command DCp is detected. Preloads necessary CG data into a preload buffer secured in the built-in DRAM 57. The preloaded CG data is further decoded by the CG data decoder 62 in the processing of the next cycle, and used for the drawing operation by the rendering engine 61.

  Following the process of step ST66, the host CPU 50 creates an image command list LT that specifies the display screen of the next cycle, and issues it to the issue destination selected in the process of step ST66 (ST67). As described with reference to FIG. 7, a JUMP_CFIFO instruction is described at the end of the image command list LT. Therefore, after the execution of the JUMP_CFIFO instruction, the WAIT_BANKFLIP instruction described in the head address of the image command buffer 71 is executed to wait for the bank flip. As described above, in this embodiment, it is possible to effectively cope with an increase in the size and image quality of the display device by effectively utilizing the preload processing.

  Next, a case where the sound engine 52 is caused to function in the simple control mode (second operation mode) will be described with reference to FIG. As described above, in the simple control mode, the VDP controller 71 executes a setting operation for the command register RGi of the sound engine 52 based on the voice command list SLT.

  First, as an initial setting operation, the corresponding register of the VDP controller 71 is set to function the sound engine 52 in the simple control mode (second operation mode) (ST10), and the steady processing of steps ST11 to ST20 is repeated. It is.

  As shown in the figure, in the steady process, the host CPU 50 creates an appropriate image command list and issues it to an appropriate issue destination (ST11), and then determines whether or not it is the update timing of the audio effect (ST12). Then, when it is time to execute the setting operation to the command register RGi of the sound engine 52, a voice command list SLT for specifying the setting operation is created.

  As shown in the upper right part of FIG. 8, the voice command list SLT lists a series of voice commands, and each voice command includes a 1-byte register number and a 1-byte set value. . Then, at the top of the voice command list SLT, the number of voice commands listed thereafter is described.

After completing the voice command list SLT having such a configuration, the host CPU 50 issues this voice command list SLT to the voice command list register CRG _WSL of the VDP controller 71 (ST71). Then, as described above with reference to FIG. 8, the VDP controller 71 sets a predetermined set value in a predetermined voice register based on the voice command list SLT.

  When the SAC code number or the SEQ code number is recognized, the DDR memory 41 is accessed instead of the simple access controller SAC or the sequencer SEQ, and a series of setting operations are executed via the relay register 82. . Therefore, although somewhat lacking in speed, the host CPU 50 can easily control the sound effect.

  Although the embodiments have been described in detail above, the specific description does not particularly limit the present invention and is appropriately modified and changed. In each of the above-described embodiments, the bullet ball game machine has been described. However, it is needless to say that the game machine can also be suitably used in other game machines with image effects such as a revolving game machine.

GM gaming machine DS1, DS2 display device 50 image production control means 42 data storage means 51 image generation means 52 voice control means 40 composite chip MCR first relay register MCD second relay register 83 voice command buffer

Claims (9)

Based on an effect control means (50) having a host CPU for uniformly controlling image effects and sound effects, and a command list received from the effect control means, image data for each frame of one or a plurality of display devices is obtained. An image generation means (51) for generating and producing an image effect; an audio control means (52) for generating an audio signal and driving a speaker based on an instruction received from the effect control means; Is a gaming machine configured to have a composite chip with a built-in,
The instruction received from the effect control means is configured to have a register number for specifying the internal register of the sound control means, and a set value for the internal register specified by the register number,
When the production control means writes the first information including the register number to the first relay register and the second information including the setting value to the second relay register, the register number and the setting value Is configured so that a set of transfer data is stored in a predetermined voice command buffer,
The voice control means is configured to function every predetermined operation cycle, read the voice command buffer, and execute a setting operation based on an instruction received from the effect control means. Machine.   2. The gaming machine according to claim 1, wherein the setting operation based on an instruction received from the effect control means is an operation of writing a setting value to an internal register specified by a register number for each set of transfer data.   The gaming machine according to claim 1 or 2, wherein the predetermined operation cycle is defined corresponding to a sampling frequency of the audio signal. The built-in register is divided into a read register that can be read and a write register that can be written.
The gaming machine according to any one of claims 1 to 3, wherein a set value to the write register is stored in the voice command buffer as the transfer data together with a register number of the register.   5. The status information indicating the internal operation state of the voice control means is stored in a predetermined read register, and the status information is read and accessed via the first relay register and the second relay register. The gaming machine described in 1.   The gaming machine according to claim 5 or 6, wherein a predetermined write register is accessed for writing without going through the voice command buffer.   The volatile memory stores a series of data strings that consist of a register number that identifies the internal register and a set value for the internal register that is identified by the register number, and is completed with a predetermined end code. The gaming machine according to any one of claims 1 to 6. The voice control means is
A controller that reads the series of data strings and automatically writes the set value to the internal register specified by the register number based on the register number and the set value constituting each set; Item 8. The gaming machine according to Item 7. The controller is
The gaming machine according to claim 8, wherein the gaming machine functions by writing a predetermined set value to a predetermined internal register via the first relay register and the second relay register.

Images