JP2019208100A - Successive comparison a/d converter circuit - Google Patents

Abstract

To widen an input range while achieving high speed and downsizing.SOLUTION: An ADC 1 includes: samplers 3, 4 which sample and hold an analog signal input via switches S1 to S4; a comparator 6; a DAC5 in which a capacitor array is connected to an input terminal of the comparator 6; a SAR7; and a control circuit 8 for controlling operations of switches S1 to S4 and the samplers 3, 4. The control circuit 8 controls each operation so that another sampler different from a predetermined sampler circuit performs a hold operation during a period in which a given sampler performs a sample operation. The control circuit 8 controls each operation so that the analog signal is divided by a capacitance ratio between capacitors CS1, CS2 and capacitance of the D/A converter 5 when the hold operation is performed by connecting one terminal of the capacitors CS1, CS2 of the samplers 3, 4 to a reference voltage VRHP and connecting the other terminal of the capacitors CS1, CS2 to the input terminal of the comparator 6.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a successive approximation A / D conversion circuit.

  Conventionally, various configurations have been considered as successive approximation A / D conversion circuits. For example, in Patent Document 1, by attenuating an input signal, a MOS transistor having a relatively low withstand voltage can be used for a D / A converter, a comparator, and the like, which are internal components of an A / D converter circuit. A configuration for reducing the size is disclosed. Further, Patent Document 2 includes two A / D conversion units so that when one A / D conversion unit performs sample hold processing, the other A / D conversion unit performs A / D conversion processing. A configuration to control is disclosed.

JP 2010-166298 A JP 2007-288609 A

  In the conventional successive approximation A / D converter circuit including the configurations of Patent Document 1 and Patent Document 2 described above, there is no one that realizes all of high speed, downsizing, and wide input range. There was room for improvement in terms of improving the performance as.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a successive approximation A / D conversion circuit capable of widening an input range while realizing high speed and downsizing.

  The successive approximation A / D conversion circuit according to claim 1 includes a switch (S1 to S6) for selecting and inputting an arbitrary analog signal from a plurality of analog signals that are input signals, and a switch. A plurality of sample and hold circuits (3, 4, 22) for sampling and holding an input analog signal, a comparator (6, 32) for comparing the sampled and held analog signals between differential inputs, and a capacitor A D / A converter (5) having a configuration in which the array (10) is connected to an input terminal of the comparator, and a successive approximation register that holds a signal representing a comparison result by the comparator and outputs a digital value corresponding to the holding result (7) and an operation control unit (8) for controlling the operation of the switch and the sample hold circuit.

  In the above configuration, the sample hold circuit includes sampling capacitors (CS1, CS2, CS3) for sampling an analog signal. In addition, the operation control unit controls the operation of the sample and hold circuit so that another sample and hold circuit different from the predetermined sample and hold circuit performs the hold operation during a period in which the predetermined sample and hold circuit performs the sample operation.

  In a general successive approximation A / D conversion circuit, at least a sampling period for sampling an analog signal, an analog signal is held, and a comparison operation by a comparator is performed before the analog signal is converted into a digital value. A period in which the A / D conversion period to be added is added. On the other hand, in the above configuration, another sample-hold circuit performs a hold operation and a comparator performs a comparison operation during a period in which a predetermined analog signal is sampled by the predetermined sample-hold circuit.

  That is, according to the above configuration, a sampling period for a predetermined analog signal overlaps with an A / D conversion period for another analog signal. Therefore, according to the above-described configuration, the time required to convert one analog signal into a digital value is reduced by an amount corresponding to the overlap period as described above with respect to a general successive approximation A / D conversion circuit. be able to. In other words, according to the above configuration, the operation speed of the A / D conversion circuit can be increased as compared with a general successive approximation A / D conversion circuit.

  In this case, when the hold operation is performed, the operation control unit connects one terminal of the sampling capacitor to a reference voltage higher than the voltage of the analog signal and connects the other terminal of the sampling capacitor to the input terminal of the comparator. Thus, the operation of the sample and hold circuit is controlled so that the analog signal is divided by the capacity ratio between the sampling capacity and the capacity of the D / A converter.

  According to such a configuration, the divided voltage obtained by dividing the analog signal by the capacity ratio between the sampling capacitor and the D / A converter is applied to the input terminal of the comparator. Therefore, according to the above configuration, it is necessary to employ a sampling capacitor having a withstand voltage corresponding to the voltage value of the input analog signal, while the capacitance of the D / A converter is A voltage having a relatively low breakdown voltage according to the divided voltage having a voltage value lower than the voltage value can be employed.

  In this case, even when the voltage value of the analog signal is high, a divided voltage that is lower than the voltage value of the analog signal is applied to the input terminal of the comparator. Even if the range is expanded, the comparator can be composed of elements having a relatively low breakdown voltage. That is, in the above configuration, internal circuits such as a comparator and a D / A converter can be configured with low-breakdown-voltage elements, so that the circuit scale can be reduced accordingly. As described above, according to the successive approximation A / D conversion circuit having the above-described configuration, it is possible to obtain an excellent effect that the input range can be widened while realizing high speed and downsizing.

The figure which shows typically the structure of the successive approximation A / D conversion circuit which concerns on 1st Embodiment. The block diagram for demonstrating the on-off state of each switch in a 1st period The block diagram for demonstrating the on-off state of each switch in a 2nd period Timing chart for explaining the operation when the sampling is repeatedly performed in the order of the signals IN1 to IN4. Timing chart for explaining the dead time provided in the transition period FIG. 2 is a diagram in which changes are made to specifically represent the configuration of the D / A converter. FIG. 3 is a diagram in which changes are made to specifically represent the configuration of the D / A converter. Diagram showing input / output voltage of sampling circuit Timing chart showing the signal waveform of each part and the operating state of each channel FIG. 1 for explaining details of the operation including the operation in the transition period FIG. 2 for explaining details of the operation including the operation in the transition period FIG. 3 for explaining details of the operation including the operation in the transition period FIG. 4 for explaining details of the operation including the operation in the transition period FIG. 5 for explaining details of the operation including the operation in the transition period FIG. 6 for explaining details of the operation including the operation in the transition period FIG. 7 for explaining details of the operation including the operation in the transition period The figure which shows typically the structure of the successive approximation A / D conversion circuit which concerns on 2nd Embodiment. Timing chart for explaining the operation when the sampling is repeatedly performed in the order of the signals IN1 to IN6. The figure which shows the specific structure of the comparator with which the successive approximation A / D conversion circuit which concerns on 1st and 2nd embodiment is provided. Timing chart for explaining operations of the D / A converter and the comparator according to the first and second embodiments The figure which shows typically the structure of the successive approximation A / D conversion circuit which concerns on 3rd Embodiment. Timing chart for explaining operations of the D / A converter and the comparator according to the third embodiment The figure which shows typically the structure of the successive approximation A / D conversion circuit which concerns on 4th Embodiment. Timing chart for explaining the operation of the successive approximation A / D conversion circuit according to the fourth embodiment The figure which shows typically the structure of the successive approximation A / D conversion circuit which concerns on 5th Embodiment. Timing chart for explaining the operation of the successive approximation A / D conversion circuit according to the fifth embodiment

Hereinafter, a plurality of embodiments will be described with reference to the drawings. In each embodiment, substantially the same components are denoted by the same reference numerals and description thereof is omitted.
(First embodiment)
Hereinafter, a first embodiment will be described with reference to FIGS.

  An A / D conversion circuit 1 shown in FIG. 1 is used, for example, in an electronic control device mounted on a vehicle, and is configured as a semiconductor integrated circuit, that is, an IC. The A / D conversion circuit 1 includes switches S1 to S4, a buffer 2, sample hold circuits 3 and 4, a D / A converter 5, a comparator 6, a successive approximation register 7, a control circuit 8, and the like. Hereinafter, the A / D conversion circuit is also referred to as ADC, the D / A converter is also referred to as DAC, and the sample hold circuit is also referred to as sampler.

  The ADC 1 converts the input signals IN1 to IN4, which are a plurality of analog signals input via the terminals P1 to P4, into digital values Do corresponding to the input signals IN1 to IN4 and outputs them, and the successive approximation A / D conversion Circuit. In this case, the ADC 1 has a differential input configuration. In FIG. 1 and the like, only the configuration related to one (positive side) of the two inputs is illustrated, and the other of the two inputs (negative side). The illustration of the configuration related to) is omitted. In the following, the configuration related to the positive side of the ADC 1 will be described, but the configuration related to the negative side is the same as the configuration related to the positive side.

  The switches S1 to S4 are switches for selecting and inputting an arbitrary signal from the four signals IN1 to IN4, and open / close between each of the terminals P1 to P4 and the input terminal of the buffer 2. The buffer 2 is provided for performing level conversion and impedance conversion of the signals IN1 to IN4. In FIG. 1 and the like, the output voltage of the buffer 2 is expressed as a voltage VINP.

  The sampler 3 samples and holds signals IN1 to IN4 input via the switches S1 to S4, and includes switches SSH1, SHH1, SR1, SSL1, SHL1, SR and a capacitor CS1. Note that the switch SR is shared with a sampler 4 described later.

  The switch SSH1 opens and closes between the output terminal of the buffer 2 and the node N1. Capacitor CS1 corresponds to a sampling capacitor for sampling an analog signal, and one terminal thereof is connected to node N1, and the other terminal is connected to node N2.

  The switch SHH1 opens and closes between the node N1 and the reference voltage supply line L1 to which the reference voltage VRHP is supplied. The switch SR1 opens and closes between the node N1 and the reference voltage supply line L2 to which the reference voltage VRLM is supplied. The switch SSL1 opens and closes between the node N2 and the reference voltage supply line L3 to which the reference voltage VRHM is supplied. The switch SHL1 opens and closes between the node N2 and the common line L4 to which the output node of the DAC 5 is connected. The switch SR opens and closes between the reference voltage supply line L2 and the voltage supply line L4.

  The sampler 4 samples and holds signals IN1 to IN4 input via the switches S1 to S4, and includes switches SSH2, SHH2, SR2, SSL2, SHL2, SR and a capacitor CS2. The switch SSH2 opens and closes between the output terminal of the buffer 2 and the node N3. Capacitor CS2 corresponds to a sampling capacitor, and one terminal thereof is connected to node N3, and the other terminal is connected to node N4.

  The switch SHH2 opens and closes between the node N3 and the reference voltage supply line L1. The switch SR2 opens and closes between the node N3 and the reference voltage supply line L2. The switch SSL2 opens and closes between the node N4 and the reference voltage supply line L3. The switch SHL2 opens and closes between the node N4 and the voltage supply line L4.

  In the present embodiment, the reference voltages VRHP, VRLM, and VRHM are set to 4V, 0V, and 0V, respectively. In this case, the voltage value of the reference voltage VRHP is higher than the voltages of the signals IN1 to IN4. Therefore, in this embodiment, the reference voltage VRHP corresponds to a reference voltage that is higher than the voltages of the signals IN1 to IN4.

  The comparator 6 is for comparing the analog signals sampled and held by the samplers 3 and 4 between the differential inputs, and has a fully differential configuration. The positive input terminal of the comparator 6 is connected to the voltage supply line L4. The negative input terminal of the comparator 6 is connected to a negative voltage supply line L5 to which the voltage VINCM is applied. A switch SRPM is connected between the voltage supply lines L4 and L5. The output signal of the comparator 6 is given to the successive approximation register 7.

  The successive approximation register 7 is composed of a logic circuit and the like. The successive approximation register 7 holds a signal representing a comparison result by the comparator 6 and outputs a digital value Do corresponding to the holding result. The successive approximation register 7 outputs a signal for controlling the operation of the DAC 5 based on the digital value Do. Hereinafter, the successive approximation register is abbreviated as SAR.

  The control circuit 8 controls the overall operation of A / D conversion by the ADC 1. Each of the switches included in the above-described switches S1 to S4, SRPM, and samplers 3 and 4 is composed of an analog switch, for example, and is turned on / off by a signal from the control circuit 8. The control circuit 8 outputs a control signal for controlling the operation to the SAR 7. In the present embodiment, the control circuit 8 corresponds to an operation control unit that controls the operations of the switches S1 to S4 and the samplers 3 and 4.

  The control circuit 8 controls each switch so that one of the four signals IN1 to IN4 input via the four terminals P1 to P4 is given to one of the two samplers 3 and 4. Control can be performed. In addition, the control circuit 8 can control each switch so that the sampling voltage of one of the two samplers 3 and 4 is held and input to the comparator 6. Therefore, the control circuit 8 can control each switch so that one of the samplers 3 and 4 performs the sample operation, and the other of the samplers 3 and 4 performs the hold operation.

  The ADC 1 having the above configuration includes two samplers 3 and 4 as a configuration for sampling and holding the signals IN1 to IN4 and A / D conversion. In the above configuration, the sample or hold (A / D conversion) can be freely switched using any of these two samplers 3 and 4. Hereinafter, the system of the sampler 3 is referred to as channel CH1, and the system of the sampler 4 is referred to as channel CH2.

  In the present embodiment, the DAC 5 is configured such that the capacitor array is connected to the input terminal of the comparator 6. As shown in FIGS. 6 and 7, specifically, the DAC 5 includes a capacitor array 10 and switches SDM and SDP. The capacitance array 10 is composed of a plurality of capacitors CU each having a unit capacitance, and one terminal of each of the plurality of capacitors CU is commonly connected to the voltage supply line L4.

  The other terminals of the plurality of capacitors CU are selectively connected to the reference voltage supply line L2 or the reference voltage supply line L6 to which the reference voltage VRLP is supplied via the switches SDM and SDP, respectively. In the present embodiment, the reference voltage VRLP is set to 1.8V. The switches SDM and SDP are composed of analog switches, for example, and are turned on / off by a signal from the SAR 7. That is, the voltage value of the output node of the DAC 5 is controlled by the SAR 7.

Next, the operation of the above configuration will be described.
[1] General Operation The control circuit 8 controls the operations of the switches S1 to S4 and the samplers 3 and 4 as follows. That is, when any one of the signals IN1 to IN4 is supplied to one of the samplers 3 and 4, the control circuit 8 sets another sampler different from the one sampler, that is, the other sampling voltage of the samplers 3 and 4. Control is performed so that the signal is held and input to the comparator 6.

  With such control, the ADC 1 holds any one of the signals IN1 to IN4 using the channel CH2 when the sampling operation for sampling any one of the signals IN1 to IN4 is performed using the channel CH1. A hold operation is performed. When the hold operation is performed, an A / D conversion operation is also performed in which a digital value Do corresponding to the analog signal held from the successive approximation register 7 is generated.

  Hereinafter, a period in which such an operation is performed is referred to as a first period. Further, in the ADC1, when a sample operation is performed using the channel CH2, a hold operation is performed using the channel CH1. Hereinafter, a period in which such an operation is performed is referred to as a second period. And in ADC1, operation | movement of each part is performed so that these 1st periods and 2nd periods may be repeated alternately.

  As shown in FIG. 2, in the first period, the switch SSH1 is on, the switch SHH1 is off, the switch SR1 is off, the switch SSL1 is on, the switch SSH2 is off, the switch SHH2 is on, the switch SR2 is off, and the switch SSL2 is off Off, switch SHL1 is off, switch SHL2 is on, switch SR is off, and switch SRPM is off. Thereby, in the first period, the sample operation is performed using the channel CH1, and the hold operation (A / D conversion operation) is performed using the channel CH2.

  In the first period, among the switches S1 to S4, the switches corresponding to the signals IN1 to IN4 to be sampled using the channel CH1 are turned on and the other switches are turned off. In FIG. 2, the switch S1 is turned on and the other switches S2 to S4 are turned off, whereby the sampling operation for the signal IN1 is performed using the channel CH1.

  As shown in FIG. 3, in the second period, the switch SSH1 is off, the switch SHH1 is on, the switch SR1 is off, the switch SSL1 is off, the switch SSH2 is on, the switch SHH2 is off, the switch SR2 is off, and the switch SSL2 is off On, switch SHL1 is on, switch SHL2 is off, switch SR is off, and switch SRPM is off. Thereby, in the second period, the sample operation is performed using the channel CH2, and the hold operation (A / D conversion operation) is performed using the channel CH1.

  In the second period, among the switches S1 to S4, the switches corresponding to the signals IN1 to IN4 to be sampled using the channel CH2 are turned on and the other switches are turned off. In FIG. 3, the switch S2 is turned on and the other switches S1, S3, and S4 are turned off, whereby the sample operation for the signal IN2 is performed using the channel CH2.

  The control circuit 8 controls each switch so that an analog signal input through a predetermined terminal among the terminals P1 to P4, that is, any one of the signals IN1 to IN4 is sampled and held by the sampler of the same channel every time. Is supposed to do. Specifically, the control circuit 8 controls the operations of the switches S1 to S4 and the samplers 3 and 4 so that the signals IN1, IN2, IN3, and IN4 are sampled in this order. Thus, the signals IN1 and IN3 are always sampled and held using the channel CH1, and the signals IN2 and IN4 are always sampled and held using the channel CH2.

  As described above, the overall operation of the ADC 1 when the control of repeatedly sampling and holding the signals IN1 to IN4 is performed will be described with reference to FIG. In FIG. 4 and the like, the sample operation and hold operation (A / D conversion operation) for each of the signals IN1 to IN4 are represented as SP1 to SP4 and AD1 to AD4, and the digital value Do corresponding to each of the signals IN1 to IN4. Is represented as O1-O4.

  In the period T1, the switch S1 is turned on and the switches S2 to S4 are turned off, and the other switches are turned on and off in the same manner as in the first period described above. As a result, in the period T1, the sample operation for the signal IN1 is performed using the channel CH1, and the hold operation (A / D conversion operation) for the signal IN4 is performed using the channel CH2. Further, in the period T1, the output operation of the digital value O3 corresponding to the signal IN3 is performed.

  In the period T2, the switch S2 is turned on and the switches S1, S3, and S4 are turned off, and the other switches are turned on and off in the same manner as in the second period described above. As a result, in the period T2, the sample operation for the signal IN2 is performed using the channel CH2, and the hold operation (A / D conversion operation) for the signal IN1 is performed using the channel CH1. In the period T2, the output operation of the digital value O4 corresponding to the signal IN4 is performed.

  In the period T3, the switch S3 is turned on and the switches S1, S2, and S4 are turned off, and the other switches are turned on and off in the same manner as in the first period described above. Thus, in the period T3, the sampling operation for the signal IN3 is performed using the channel CH1, and the holding operation (A / D conversion operation) for the signal IN2 is performed using the channel CH2. In the period T3, an output operation of the digital value O1 corresponding to the signal IN1 is performed.

  In the period T4, the switch S4 is turned on and the switches S1 to S3 are turned off, and the other switches are turned on and off in the same manner as in the second period described above. Thereby, in the period T4, the sampling operation for the signal IN4 is performed using the channel CH2, and the holding operation (A / D conversion operation) for the signal IN3 is performed using the channel CH1. In the period T4, an output operation of the digital value O2 corresponding to the signal IN2 is performed.

  By repeating these periods T1 to T4, the signals IN1 and IN3 are always sampled and held using the channel CH1 and A / D converted, and the signals IN2 and IN4 are always sampled and held using the channel CH2. And A / D conversion.

  In this case, as shown in FIG. 5, the transition period from the period T1 to the period T2, the transition period from the period T2 to the period T3, the transition period from the period T3 to the period T4, and the transition from the period T4 to the period T1 In the period, a dead time Td that is a period in which all of the switches S1 to S4 are turned off is provided. By providing such a dead time Td, a short circuit of the input during each transition period is prevented.

[2] Voltage Dividing Function The ADC 1 having the above configuration has a configuration similar to a general charge redistribution successive approximation A / D converter circuit except that the ADC 1 has two samplers 3 and 4. The basic operation related to A / D conversion is similarly similar. However, in the ADC1, sampling capacitors for sampling the signals IN1 to IN4 are provided as capacitors CS1 and CS2 independently of the capacitor array 10 (a plurality of capacitors CU) included in the capacitor array type DAC5.

  In this case, the voltage dividing function for dividing the voltage applied to the input terminal of the comparator 6 is realized by controlling on / off of each switch as described above in the first period and the second period. It has become. Hereinafter, such a voltage dividing function will be described with reference to FIGS. 6 and 7 are diagrams in which changes are made to specifically represent the configuration of the DAC 5 with respect to FIGS. 2 and 3, respectively.

  In the first period in which the hold operation is performed using the channel CH2, as shown in FIG. 6, one terminal of the plurality of capacitors CU of the DAC 5 and the other terminal of the capacitor CS2 are connected in common and the comparator 6 is positively connected. Connected to the side input terminal. At this time, one terminal of the capacitor CS2 is connected to the reference voltage supply line L1 to which the reference voltage VRHP is supplied.

  In the second period in which the hold operation is performed using the channel CH1, as shown in FIG. 7, one terminal of the plurality of capacitors CU of the DAC 5 and the other terminal of the capacitor CS1 are connected in common and the comparator 6 is positively connected. Connected to the side input terminal. At this time, one terminal of the capacitor CS1 is connected to the reference voltage supply line L1 to which the reference voltage VRHP is supplied.

  In this case, in the DAC 5, the reference voltage VRLM is supplied to each other terminal of the capacitor CU constituting one capacitor group corresponding to a half capacity (= CD / 2) of the total capacity CD of the capacity array 10. The other terminal of the plurality of capacitors CU constituting the other capacitor group corresponding to the half capacity is connected to the reference voltage supply line L3 to which the reference voltage VRLP is supplied. Shall be.

  Here, the charge QS1 of the capacitor CS1 in the first period and the charge QH1 of the capacitor CS1 in the second period are expressed by the following expressions (1) and (2), respectively. However, the capacitances of the capacitors CS1 and CS2 are represented as Cs.

  Further, the voltage of the positive input terminal of the comparator 6 in the second period, that is, the voltage VINCP of the voltage supply line L4, and the voltage of the negative input terminal of the comparator 6 in the second period, that is, the voltage VINCM of the voltage supply line L5 Are represented by the following equations (3) and (4), respectively. However, the output voltage of the negative-side buffer (not shown) is expressed as voltage VINM.

  The following equation (5) can be derived from the above equations (3) and (4). However, a voltage obtained by subtracting the voltage VINCM from the voltage VINCP, that is, a differential voltage input to the comparator 6 is represented as VCPM, and a voltage obtained by subtracting the voltage VINM from the voltage VINP, that is, a differential voltage output from the buffer 2 or the like is represented as VINPM. .

  Thus, according to the above configuration, the divided voltage obtained by dividing the voltage input to the samplers 3 and 4 by the capacitance ratio between the sampling capacitor and the DAC 5 is applied to the input terminal of the comparator 6. In this case, the partial pressure ratio is “Cs / (Cs + CD)”. Therefore, when each capacitor is set so that the ratio of the capacitance Cs (for example, 3.2 pF) of the capacitors CS1 and CS2 and the total capacitance CD (for example, 3.2 pF) of the capacitance array 10 is “1: 1”, the voltage VINCP The voltage VINCM, the voltage VCPM, the voltage VINP, and the voltage VINM are as shown in FIG.

[3] Details of Operation Including Transition Period Next, detailed contents of the operation of the ADC 1 will be described with reference to FIGS. 9 to 16. In FIG. 9, binary signals for turning on / off each switch output from the control circuit 8 are shown with the same reference numerals as the corresponding switches. Each of these signals turns on the corresponding switch when it is at a high level, and turns off the corresponding switch when it is at a low level.

  These signals are generated based on a clock signal (not shown). 10 to 16 show only a portion of the configuration of the ADC 1 that is necessary for the operation description. 10 to 16, the reference voltage supply lines L <b> 2 and L <b> 3 are represented as a common line connected to a ground symbol that is a reference potential (0 V) of the circuit.

  In the present embodiment, the capacitors CS1 and CS2 are reset during a transition period in which the channel of the sampler is switched. Hereinafter, this point will be described by focusing on the transition period from the period T2 to the period T3. From time t1 to t2, the ADC 1 is in the circuit state shown in FIG. That is, from time t1 to t2, each switch is in an on / off state similar to the second period described above. At time t2, the ADC 1 enters the circuit state shown in FIG. That is, at time t2, the switch SSL2 turns from on to off.

  Between time t2 and time t3, ADC1 is in the circuit state shown in FIG. That is, the switches SSH2, SHH1, and SHL1 are turned from on to off between time t2 and time t3. At time t3, the ADC 1 enters the circuit state shown in FIG. That is, at time t3, the switches SSL1, SR1, SR, and SRPM are turned from off to on.

  As a result, both terminals of the capacitor CS1 are connected to the ground via SR1 and SSL1, and the charge is initialized (reset). At this time, the input terminals of the comparator 6 are short-circuited (short-circuited) via the switch SRPM and connected to the ground via the switch SR, thereby resetting the charge of the capacitor CU of the DAC 5 and the comparator 6. The input potential is reset.

  At time t4, the ADC 1 enters the circuit state shown in FIG. That is, at time t4, the switches SR1, SR, and SRPM are turned from on to off. Between time t4 and time t5, ADC1 is in the circuit state shown in FIG. That is, the switches SSH1 and SHL2 are turned from OFF to ON between time t4 and time t5. At time t5, the ADC 1 enters the circuit state shown in FIG. That is, at time t5, the switch SHH2 changes from off to on, and each switch is in the on / off state similar to the first period described above.

  As described above, in the present embodiment, the sampler 3 ends the sampling of the predetermined signal (for example, the signal IN1) and before the sampling of the next signal (for example, the signal IN3) before starting the sampling of the next signal (for example, the signal IN3). The capacitor CS1 is reset by connecting the child to the ground. Similarly to the sampler 3, the sampler 4 also resets the capacitor CS2 by connecting both terminals of the capacitor CS2 to the ground after completing the sampling of the predetermined signal and before starting the sampling of the next signal. It is supposed to be.

According to this embodiment described above, the following effects can be obtained.
In a general successive approximation A / D conversion circuit, before an analog signal is converted into a digital value, at least a sampling period for sampling the analog signal and an A / D conversion period in which a comparison operation by a comparator is performed A period of adding and is required. On the other hand, the ADC 1 of the present embodiment has two samplers 3 and 4 as a configuration for sampling and holding the signals IN1 to IN4 that are analog signals and for A / D conversion. The ADC 1 can freely switch which of the two systems of samplers 3 and 4 is used to perform sample or hold.

  In the ADC 1 having such a configuration, during the sampling operation for a predetermined analog signal (signals IN1 to IN4) using one of the samplers 3 and 4, the predetermined one is used using the other of the samplers 3 and 4. A hold operation and an A / D conversion operation for a signal other than the signal are performed. That is, according to the ADC 1 of the present embodiment, the sampling period for the predetermined signal and the A / D conversion period for another signal overlap.

  Therefore, according to the configuration of the present embodiment, the time required to convert one analog signal into a digital value for a general successive approximation A / D conversion circuit is as much as the occurrence of the overlap period as described above. Can be shortened. In other words, according to the configuration of the present embodiment, the operation speed as an A / D conversion circuit can be increased with respect to a general successive approximation A / D conversion circuit.

  In a general charge redistribution type successive approximation A / D converter circuit, a sampling capacitor for sampling an input signal is configured to be shared with a capacitor of the DAC. In such a configuration, all capacitors and switches constituting the DAC are required to have a breakdown voltage higher than the upper limit value of the input signal voltage. For this reason, in the above configuration, in applications where the upper limit value of the voltage of the input signal is relatively high, there is a possibility that the circuit scale of the DAC, and consequently the circuit scale of the entire A / D conversion circuit, may be increased.

  In contrast, in the ADC 1 of this embodiment, the sampling capacitors for sampling the signals IN1 to IN4 are independent of the capacitor array 10 (multiple capacitors CU) provided in the capacitor array type DAC 5 as the capacitors CS1 and CS2. Is provided. In the ADC 1, when the hold operation is performed, one terminal of the capacitor CS 1 or CS 2 is connected to the reference voltage VRHP higher than the voltage of the analog signal, and the other terminal of the capacitor CS 1 or CS 2 is input to the comparator 6. It is designed to be connected to the terminal. With this configuration, the ADC 1 realizes a voltage dividing function for dividing the voltage applied to the input terminal of the comparator 6.

  Therefore, in the ADC 1, a divided voltage obtained by dividing the voltage input to the sampler 3 or 4 by the capacitance ratio of the capacitor CS 1 or CS 2 and the total capacitance CD of the DAC 5 is applied to the input terminal of the comparator 6. Become. Therefore, according to the configuration of the present embodiment, as the capacitors CS1 and CS2, it is necessary to employ a capacitor having a withstand voltage corresponding to the voltage values of the input signals IN1 to IN4, but the capacitor CU of the DAC5, the switch SDP As the SDM, one having a relatively low breakdown voltage according to a divided voltage that becomes a voltage value lower than the voltage values of the signals IN1 to IN4 (for example, a voltage value of about ½) can be adopted.

  In addition, since it is necessary to use the same type of element as the capacitors CS1 and CS2 in order to eliminate the mismatch, the capacitor CU actually has a breakdown voltage similar to that of the capacitors CS1 and CS2. However, in this case, even when the voltage values of the signals IN1 to IN4 are high, the divided voltage that is lower than the voltage values of the signals IN1 to IN4 is applied to the input terminal of the comparator 6. Even if the input range of the signals IN1 to IN4 is expanded, the comparator 6 can be constituted by a relatively low withstand voltage element.

  In other words, in the configuration of the present embodiment, the internal circuit of the comparator 6 and the DAC 5 (for example, the switches SDP and SDM) can be configured with low-breakdown-voltage elements, and accordingly, the circuit scale of the entire ADC 1 is reduced to that extent. Can do. As described above, according to the ADC 1 of the present embodiment, it is possible to obtain an excellent effect that the input range can be widened while realizing high speed and downsizing.

  In the ADC1, the capacitors CS1 and CS2 corresponding to the sampling capacitors need to be reset after the sample is completed and before the next sample is started. In the configuration of the present embodiment, the capacitors CS1 and CS2 can be reset by connecting one terminal thereof to a reference voltage supply line L1 to which a reference voltage VRHP (for example, 4V) is supplied.

  However, in the reset by the reference voltage VRHP, when the next sample is started, the terminal voltages of the capacitors CS1 and CS2 change, and the change is performed using another channel via the switch. May affect the conversion behavior. That is, in the reset by the reference voltage VRHP, there is a possibility that interference between the channel CH1 and the channel CH2 occurs.

  Therefore, the ADC 1 of the present embodiment is provided with switches (SR1, SSL1, SR2, SSL2) for connecting both terminals of the capacitors CS1 and CS2 to the ground that is the reference potential of the circuit. In ADC1, after the sampling of a predetermined signal among the signals IN1 to IN4 is completed and before the sampling of the next signal is started, both terminals of the capacitors CS1 and CS2 are connected to the ground using the switch. The capacitors CS1 and CS2 are reset. According to such a configuration, it is possible to prevent the occurrence of interference between the channel CH1 and the channel CH2 as described above.

  Since the two channels CH1 and CH2 have different amounts of error between the differentials, even if the same input signal is used, the digital value Do obtained when sample hold and A / D conversion is performed using the channel CH1, The value may differ from the digital value Do obtained when the sample hold and A / D conversion is performed using the channel CH2.

  Therefore, the ADC 1 of the present embodiment has the above-described configuration, and the control circuit 8 is configured so that the signals IN1, IN2, IN3, and IN4 input via the terminals P1 to P4 are sampled and held in this order. Controls the operation of each switch. Thus, in this embodiment, the signals IN1 and IN3 are always sampled and held using the channel CH1, and the signals IN2 and IN4 are always sampled and held using the channel CH2. Therefore, according to the present embodiment, the occurrence of fluctuations in the output of the ADC 1 due to different offsets for the channels CH1 and CH2 can be suppressed.

  In addition, when the number of analog signals input to the ADC 1 is changed to two, when it is changed to six, when it is changed to eight, etc., the effect of suppressing the above-described output fluctuation by the same control method Can be obtained. That is, according to the ADC 1 including the two samplers 3 and 4 as in the present embodiment, if the number of input analog signals is a multiple of 2, the output variation described above is performed by the same control method. The effect of suppressing is acquired.

(Second Embodiment)
Hereinafter, the second embodiment will be described with reference to FIGS. 17 and 18.
As shown in FIG. 17, the ADC 21 of the present embodiment is different from the ADC 1 of the first embodiment in that switches S5 and S6 are added and a sampler 22 is added. The ADC 21 is a successive approximation A / D conversion circuit that converts the input signals IN1 to IN6 input via the terminals P1 to P6 into digital values Do corresponding to the input signals IN1 to IN6 and outputs them. Hereinafter, the input signals IN5 and IN6 are also simply referred to as signals IN5 and IN6.

  The switches S5 and S6 open and close between the terminals P5 and P6 and the input terminal of the buffer 2. The sampler 22 samples the signals IN1 to IN6, and has the same configuration as the other samplers 3 and 4. That is, the sampler 22 includes switches SSH3, SHH3, SR3, SSL3, SHL3, SR and a capacitor CS3. In this case, three switches SR are provided for each of the samplers 3, 4, and 22, that is, for each channel. However, a configuration in which one switch SR is shared by three channels may be used.

  The switch SSH3 opens and closes between the output terminal of the buffer 2 and the node N21. Capacitor CS3 corresponds to a sampling capacitor for sampling an analog signal, one terminal of which is connected to node N21 and the other terminal is connected to node N22.

  The switch SHH3 opens and closes between the node N21 and the reference voltage supply line L1 to which the reference voltage VRHP is supplied. The switch SR3 opens and closes between the node N21 and the reference voltage supply line L2 to which the reference voltage VRLM is supplied. The switch SSL3 opens and closes between the node N22 and the reference voltage supply line L3 to which the reference voltage VRHM is supplied. The switch SHL3 opens and closes between the node N22 and the voltage supply line L4. The switch SR opens and closes between the reference voltage supply line L2 and the voltage supply line L4.

  Each switch added in this embodiment is composed of, for example, an analog switch, like the switches S1 to S4, and is turned on and off by a signal from the control circuit 8. Therefore, in this case, the control circuit 8 controls the operations of the switches S1 to S6 and the samplers 3, 4, and 22.

  The control circuit 8 is configured so that any one of the six signals IN1 to IN6 input via the six terminals P1 to P6 is supplied to any one of the three samplers 3, 4, and 22. The switch can be controlled. Further, the control circuit 8 can control each switch so that the sampling voltage of any of the three samplers 3, 4, and 22 is held and input to the comparator 6.

  The ADC 21 having the above configuration includes three samplers 3, 4, and 22 as a configuration for sampling and holding the signals IN1 to IN6 and A / D conversion. In the above-described configuration, it is possible to freely switch which of the three systems of samplers 3, 4, and 22 is used to execute sample or hold (A / D conversion). Hereinafter, the system of the sampler 22 is referred to as channel CH3.

Next, the operation of the above configuration will be described.
In this case, the control circuit 8 controls the operations of the switches S1 to S6 and the samplers 3, 4, and 22 as follows. That is, when any one of the signals IN1 to IN6 is given to any one of the samplers 3, 4, and 22, the control circuit 8 holds a sampling voltage of another sampler different from the one sampler and holds it in the comparator 6. Control to input.

  By such control, the ADC 21 performs a hold operation using the channel CH2 or CH3 when the sample operation is performed using the channel CH1. Further, in the ADC 21, when a sample operation is performed using the channel CH2, a hold operation is performed using the channel CH1 or CH3. Further, in the ADC 21, when the sample operation is performed using the channel CH3, the hold operation is performed using the channel CH1 or CH2.

  Also, in this case, the control circuit 8 causes the analog signal input through a predetermined terminal among the terminals P1 to P6, that is, any one of the signals IN1 to IN6 to be sampled and held by the sampler of the same channel every time. Each switch is controlled. Specifically, the control circuit 8 controls the operations of the switches S1 to S6 and the samplers 3, 4, and 22 so that the signals IN1, IN2, IN3, IN4, IN5, and IN6 are sampled in this order.

  Thus, as shown in FIG. 18, signals IN1 and IN4 are always sampled and held using channel CH1, signals IN2 and IN5 are always sampled and held using channel CH2, and signals IN3 and IN6 are always channel CH3. Is used to sample and hold.

  In FIG. 18, the sample operation and hold operation (A / D conversion operation) for each of the signals IN5 and IN6 are represented as SP5, SP6 and AD5, AD6. In this case, a reset operation in which a capacitor or the like is reset is executed in a channel in which neither the sample operation nor the hold operation (A / D conversion operation) is executed. In FIG. 18, such a reset operation is represented by R.

  As described above, the ADC 21 of the present embodiment has the same configuration as the ADC 1 of the first embodiment, except that the number of samplers is increased from 2 to 3, and performs the same operation. be able to. Therefore, according to this embodiment, the same effect as that of the first embodiment can be obtained.

  In this case, the ADC 21 includes six switches S1 to S6 and three samplers 3, 4, and 22. In such a configuration, the control circuit 8 includes the switches S1 to S6 and the sampler so that the signals IN1, IN2, IN3, IN4, IN5, and IN6 input via the terminals P1 to P6 are sampled in this order. The operations of 3, 4, and 22 are controlled.

  Thus, in this embodiment, the signals IN1 and IN4 are always sampled and held using the channel CH1, the signals IN2 and IN5 are always sampled and held using the channel CH2, and the signals IN3 and IN6 are always sampled using the channel CH3. Hold. Therefore, according to the present embodiment, the occurrence of output fluctuation of the ADC 21 due to the offset that differs for each of the channels CH1, CH2, and CH3 can be suppressed.

  Even when the number of input analog signals is changed to three or nine with respect to the ADC 21, the effect of suppressing the above-described output fluctuation can be obtained by the same control method. That is, according to the ADC 21 including the three samplers 3, 4, and 22 as in the present embodiment, if the number of input analog signals is a multiple of 3, the above-described output is performed by the same control method. The effect of suppressing fluctuation is obtained.

(Third embodiment)
Hereinafter, a third embodiment will be described with reference to FIGS. 19 to 22.
The comparator 6 in each of the above embodiments is actually configured as shown in FIG. That is, as shown in FIG. 19, the comparator 6 includes a front stage section 6a and an output stage section 6b. The output stage unit 6b is a latch circuit, receives the output signal of the previous stage unit 6a, generates a digital value Do based on the output signal, and outputs the digital value Do. The SAR 7 generates and outputs a signal (command signal) for controlling the operation of the DAC 5 based on the digital value Do output from the output stage unit 6b.

  In this case, the clock signal MCLK is given to the SAR 7 and the comparator 6 as the operation clock. As shown in FIG. 20, the clock signal MCLK is a signal having a duty of 50%, like a general clock signal. The operation of the SAR 7 and the DAC 5 and the operation of the comparator 6 are executed in synchronization with the clock signal MCLK.

  That is, as shown in FIG. 20, the SAR 7 outputs a command signal so that the operation of the DAC 5 starts in synchronization with the rising edge of the clock signal MCLK. The comparator 6 starts operating in synchronization with the falling edge of the clock signal MCLK. In FIG. 20 and FIG. 22 described later, the comparator is referred to as Comp. Therefore, in each of the above embodiments, the time allocated to the operation of the DAC 5 and the time allocated to the operation of the comparator 6 are the same.

  However, the actual operation time of the comparator 6, that is, the settling time required for the output signal of the comparator 6 to converge to the final value, is required until the actual operation time of the DAC 5, that is, the output voltage of the DAC 5 converges to the target value. Compared to settling time, it is very short. This is because the DAC 5 includes a large number of capacitors CU. Accordingly, in the configuration shown in FIG. 19, the time allocated to the operation of the comparator 6 is longer than necessary, and there is room for improvement in terms of improving the operation speed of the A / D conversion circuit.

  In this embodiment, in order to improve such a point, a device is added to the configuration of the comparator. That is, as shown in FIG. 21, the comparator 32 included in the ADC 31 of this embodiment includes an EX-OR circuit 33 and an OR circuit 34 in addition to the configuration included in the comparator 6. The EX-OR circuit 33 inputs each output signal of the front stage section 6a and outputs a signal END representing their exclusive OR.

  The signal END is a signal corresponding to an end signal indicating that the operation of the comparator 32 has ended, and as shown in FIG. 22, a binary signal that changes from a low level to a high level at the timing when the operation of the comparator 32 ends. It becomes. In the present embodiment, the EX-OR circuit 33 corresponds to a signal generation circuit that generates an end signal indicating that the operation of the comparator 32 has ended.

  The OR circuit 34 receives the clock signal MCLK and the signal END, and outputs a clock signal CCLK representing the logical sum of them. Also in this case, the comparator 32 operates in synchronization with the clock signal MCLK. However, in this case, the SAR 7 operates in synchronization with the clock signal CCLK output from the OR circuit 34.

  That is, as shown in FIG. 22, the SAR 7 outputs a command signal so that the operation of the DAC 5 starts in synchronization with the rising edge of the clock signal CCLK. The comparator 32 starts operating in synchronization with the falling edge of the clock signal MCLK. Thus, in the present embodiment, the DAC 5 is configured to start operation based on the clock signal CCLK and the signal END.

  According to such a configuration, the time allocated to the operation of the comparator 32 is minimized, and accordingly, the time allocated to the operation of the DAC 5 is increased by the time ts shown in FIG. Therefore, according to the configuration of the present embodiment, the operation speed of the A / D conversion circuit can be further improved.

(Fourth embodiment)
The fourth embodiment will be described below with reference to FIGS. 23 and 24.
As shown in FIG. 23, the ADC 41 of the present embodiment is different from the ADC 1 of the first embodiment in that a switch SREF and a correction unit 42 are added and switches S3 and S4 are omitted. In FIG. 23, the configuration subsequent to the buffer 2 in the configuration of the ADC 1 is collectively represented as the A / D conversion unit 43.

  The switch SREF opens and closes between a terminal Pr for inputting a signal REF, which is a reference signal used for offset correction described later, and an input terminal of the buffer 2. The signal REF is a signal having a constant voltage level, for example, a signal of 0V. The switch SREF is provided to switch a signal input path so that a signal REF, which is a reference signal, is input to the sample hold circuit instead of the signals IN1, IN2 that are analog signals. It corresponds to.

  Since the two channels CH1 and CH2 included in the A / D conversion unit 43 have different samplers, the offset values of the digital values output from them are also different. The correction unit 42 corrects such a digital value, that is, the offset of the digital value output from the SAR 7, and outputs the corrected digital value as the digital value Do. The correction unit 42 includes correction memories 44 and 45, switches Sr11, Sr12, Sr21, Sr22, and a subtractor 46.

  The correction memory 44 is for storing a correction value REF1 for correcting the offset of the channel CH1. The input terminal of the correction memory 44 is connected to the output terminal of the A / D converter 43 via the switch Sr11. The output terminal of the correction memory 44 is connected to one input terminal (−) of the subtractor 46 via the switch Sr12.

  The correction memory 45 is for storing a correction value REF2 for correcting the offset of the channel CH2. The input terminal of the correction memory 45 is connected to the output terminal of the A / D converter 43 via the switch Sr21. The output terminal of the correction memory 45 is connected to one input terminal (−) of the subtractor 46 via the switch Sr22. The other input terminal of the subtractor 46 is connected to the output terminal of the A / D converter 43. The subtractor 46 subtracts a correction value, which is a digital value output from the correction memory 44 or 45, from the digital value output from the A / D conversion unit 43, and outputs the value after the subtraction as a digital value Do. .

  In the above configuration, the correction memories 44 and 45 are provided corresponding to the samplers 3 and 4 and correspond to a plurality of first memories for storing digital values output from the SAR 7. The switches Sr11 and Sr21 correspond to a second path changeover switch that switches a digital value writing path from the SAR 7 to the first memory. Further, the switches Sr12 and Sr22 correspond to a third path changeover switch for switching the reading path of the digital value from the first memory. The subtractor 46 corresponds to a first subtracter that subtracts and outputs a digital value read from the first memory via the third path changeover switch from the digital value output from the SAR 7.

  The switches SREF, Sr11, Sr12, Sr21, and Sr22 have the same configuration as the other switches, and are turned on / off by a signal from the control circuit 8 included in the A / D converter 43. The control circuit 8 causes the signal REF to be sampled and held by a predetermined sampler, and a digital value output from the SAR 7 accordingly is a first memory (correction memory 44 or 45) corresponding to the predetermined sampler. To control the operations of the switches SREF, Sr11, and Sr12.

  The control circuit 8 also includes a first memory (correction memory 44 or 45) corresponding to the predetermined sampler when a digital value is output from the SAR 7 as the analog signal is sampled and held by the predetermined sampler. The operations of the switches Sr12 and Sr22 are controlled so that the digital value read out from is supplied to the subtractor 46.

  Specifically, the switch Sr11 is turned on during a period in which an output operation corresponding to the signal REF sampled and held using the channel CH1 is performed, and is turned off in other periods. The switch Sr12 is turned on during a period in which an output operation corresponding to the signal IN1 sampled using the channel CH1 is performed, and is turned off during other periods.

  The switch Sr21 is turned on during an output operation corresponding to the signal REF sampled and held using the channel CH2, and is turned off during other periods. The switch Sr22 is turned on during a period in which an output operation corresponding to the signal IN2 sampled and held using the channel CH2 is performed, and is turned off during other periods.

  With such a configuration, the correction unit 42 acquires the correction values REF1 and REF2 corresponding to the channels CH1 and CH2, that is, the samplers 3 and 4, respectively, and the digital value output from the A / D conversion unit 43 is obtained. Offset correction is performed using a correction value corresponding to the sampler (3 or 4) that samples and holds the signal (IN1 or IN2) corresponding to the digital value. In this case, the correction values REF1 and REF2 are constantly updated, and the above correction is performed using the latest values. Further, in this case, noise is removed by a digital circuit such as a moving average filter at the time of updating.

Next, the operation of the above configuration will be described.
In the A / D converter 43, the signals IN1, IN2, REF, and REF are repeatedly sampled and held in this order. Thus, the signal IN1 is always sampled and held using the channel CH1, and the signal IN2 is always sampled and held using the channel CH2. The signal REF is sampled and held using both channels CH1 and CH2.

  As described above, the operation of the ADC 41 when the control of repeatedly holding the sample in the order of the signals IN1, IN2, REF, and REF is performed will be described with reference to FIG. In FIG. 24, the sample operation and hold operation (A / D conversion operation) for signal REF are represented as SPR and ADR. In FIG. 24, digital values output from the A / D converter 43 corresponding to the signals IN1, IN2, and REF are represented as O1, O2, and REF.

  In this case, the repetition cycle described above is one sequence, and the period during which the sample operation or hold operation (A / D conversion operation) corresponding to each signal is performed is one cycle. In the cycle C1, a sample operation for the signal IN1 is performed using the channel CH1, and a hold operation (A / D conversion operation) for the signal REF is performed using the channel CH2. Further, the digital value Do output in the cycle C1 is a value obtained by subtracting the correction value REF1 from the digital value REF.

  In the cycle C2, a sample operation for the signal IN2 is performed using the channel CH2, and a hold operation (A / D conversion operation) for the signal IN1 is performed using the channel CH1. Further, the digital value Do output in the cycle C2 is a value obtained by subtracting the correction value REF2 from the digital value REF.

  In the cycle C3, a sampling operation for the signal REF is performed using the channel CH1, and a holding operation (A / D conversion operation) for the signal IN2 is performed using the channel CH2. Further, the digital value Do output in the cycle C3 is a value obtained by subtracting the correction value REF1 from the digital value O1.

  In the cycle C4, a sampling operation for the signal REF is performed using the channel CH2, and a holding operation (A / D conversion operation) for the signal REF is performed using the channel CH1. Further, the digital value Do output in the cycle C4 is a value obtained by subtracting the correction value REF2 from the digital value O2.

  Also by this embodiment described above, the same effect as the first embodiment can be obtained. Furthermore, the ADC 41 according to the present embodiment includes a correction unit 42 that corrects an offset of a digital value output from the A / D conversion unit 43. The correction unit 42 acquires correction values REF1 and REF2 corresponding to the channels CH1 and CH2 of the A / D conversion unit 43, and converts the digital values output from the A / D conversion unit 43 into the digital values. Offset correction is performed using a correction value corresponding to a sampler that samples and holds the corresponding signal.

  In the above configuration, the two channels CH1 and CH2 included in the A / D conversion unit 43 have different samplers, so that the offset values of the digital values output from them are also different. According to this embodiment, the correction unit 42 described above performs offset correction using an optimal correction value for each of these channels, so that occurrence of output fluctuation of the ADC 41 due to the offset is reliably suppressed. The effect that it can do is acquired.

(Fifth embodiment)
The fifth embodiment will be described below with reference to FIGS. 25 and 26.
As shown in FIG. 25, the ADC 51 of the present embodiment is different from the fourth embodiment in that a terminal P3 and a switch S3 are added, a correction unit 52 is provided instead of the correction unit 42, and the like. . The correction unit 52 includes a subtractor 53, a correction memory 54, a subtractor 55, and switches Sr31 and Sr32 in addition to the configuration included in the correction unit 42.

  In this case, the ADC 51 is configured to execute an offset correction sequence for obtaining the correction values REF1 and REF2 for correcting the offset before the normal sequence in which the normal operation is performed is started. Correction values REF1 and REF2 obtained by executing such an offset correction sequence are stored in correction memories 44 and 45, respectively.

  One input terminal of the subtractor 53 is connected to the output terminal of the A / D conversion unit 43 via the switch Sr31. The other input terminal (−) of the subtractor 53 is connected to the output terminal of the correction memory 45. The subtractor 53 outputs a digital value obtained by subtracting the digital value read from the correction memory 45 from the digital value output from the A / D converter 43.

  The digital value output from the subtractor 53 is input to the correction memory 54 as a correction value ΔREF for correcting the offset of the channels CH1 and CH2. That is, the correction memory 54 calculates the difference between the digital value read from the correction memory 45, which is the first memory provided corresponding to the sampler 4, which is a specific sampler, and the digital value output from the SAR 7. It is held and corresponds to the second memory.

  The output terminal of the correction memory 54 is connected to one input terminal (−) of the subtractor 55 via the switch Sr32. The other input terminal of the subtractor 55 is connected to the output terminal of the subtractor 46. The subtractor 55 subtracts the correction value ΔREF, which is a digital value read from the correction memory 54, from the digital value output from the subtractor 46, and outputs the value after the subtraction as a digital value Do. That is, in this case, the subtractor 55 corresponds to a second subtracter.

  The switch Sr31 is turned on during a period in which an output operation corresponding to the signal REF sampled and held using the channel CH2 is performed, and is turned off during other periods. The switch Sr32 is turned on during a period in which an output operation corresponding to the signal IN1 sampled and held using the channel CH1 and an output operation corresponding to the signal IN2 sampled and held using the channel CH2 are performed. , Off in other periods.

  With such a configuration, the correction unit 52 acquires correction values REF1 and REF2 corresponding to the channels CH1 and CH2, that is, the samplers 3 and 4 in the offset correction sequence. Then, the correction unit 52 acquires the correction value ΔREF corresponding to the specific sampler 4 out of the channels CH1 and CH2, that is, the samplers 3 and 4 in the normal sequence, and converts the correction value ΔREF to the digital value output from the A / D conversion unit 43. On the other hand, the offset correction is performed using the correction value (REF1 or REF2) corresponding to the sampler (3 or 4) that samples and holds the signal (IN1 or IN2) corresponding to the digital value and the correction value ΔREF. .

Next, the operation of the above configuration will be described.
[1] Operation in Offset Correction Sequence In the offset correction sequence, the signal REF is repeatedly sampled and held. Thus, the signal REF is sampled and held using both channels CH1 and CH2.

  The operation of the ADC 51 in such an offset correction sequence will be described with reference to FIG. In FIG. 26, the sample operation and hold operation (A / D conversion operation) for signal REF are represented as SPR and ADR. In FIG. 26, digital values output from the A / D converter 43 corresponding to the signals IN1, IN2, IN3, and REF are represented as O1, O2, O3, and REF.

  In cycles C51 and C53, a sample operation for the signal REF is performed using the channel CH1, and a hold operation (A / D conversion operation) for the signal REF is performed using the channel CH2. The digital value Do output in cycles C51 and C53 is a value obtained by subtracting the correction value REF1 from the digital value REF.

  In cycles C52 and C54, a sample operation for the signal REF is performed using the channel CH2, and a hold operation (A / D conversion operation) for the signal REF is performed using the channel CH1. The digital value Do output in cycles C52 and C54 is a value obtained by subtracting the correction value REF2 from the digital value REF.

[2] Operation in Normal Sequence In the normal sequence, the signals IN1, IN2, IN3, and REF are repeatedly sampled and held in this order. Thus, the signals IN1 and IN3 are always sampled and held using the channel CH1, and the signals IN2 and REF are always sampled and held using the channel CH2.

  The operation of the ADC 51 in such a normal sequence will be described with reference to FIG. In the cycle C61, a sampling operation is performed on the signal IN1 using the channel CH1, and a hold operation (A / D conversion operation) is performed on the signal REF using the channel CH2. The digital value Do output in cycle C61 is a value obtained by subtracting the correction value REF1 from the digital value REF.

  In the cycle C62, the sampling operation for the signal IN2 is performed using the channel CH2, and the holding operation (A / D conversion operation) for the signal IN1 is performed using the channel CH1. Further, the digital value Do output in the cycle C62 is a value obtained by subtracting the correction value REF2 from the digital value REF.

  In the cycle C63, the sampling operation for the signal IN3 is performed using the channel CH1, and the holding operation (A / D conversion operation) for the signal IN2 is performed using the channel CH2. Further, the digital value Do output in the cycle C63 is a value obtained by subtracting the correction value REF1 from the digital value O1.

  In the cycle C64, a sampling operation for the signal REF is performed using the channel CH2, and a holding operation (A / D conversion operation) for the signal IN3 is performed using the channel CH1. Further, the digital value Do output in the cycle C64 is a value obtained by subtracting the correction value REF2 from the digital value O2.

  In the cycle C65, the sampling operation for the signal IN1 is performed using the channel CH1, and the holding operation (A / D conversion operation) for the signal REF is performed using the channel CH2. Further, the digital value Do output in the cycle C65 is a value obtained by subtracting the correction value REF1 from the digital value O3.

  In the cycle C66, the sample operation for the signal IN2 is performed using the channel CH2, and the hold operation (A / D conversion operation) for the signal IN1 is performed using the channel CH1. Further, the digital value Do output in the cycle C66 is a value obtained by subtracting the correction value REF2 from the digital value REF.

  In the cycle C67, the sampling operation for the signal IN3 is performed using the channel CH1, and the holding operation (A / D conversion operation) for the signal IN2 is performed using the channel CH2. Further, the digital value Do output in the cycle C67 is a value obtained by subtracting the correction value REF1 and the correction value ΔREF from the digital value O1.

  In the cycle C68, a sampling operation for the signal REF is performed using the channel CH2, and a holding operation (A / D conversion operation) for the signal IN3 is performed using the channel CH1. The digital value Do output in cycle C68 is a value obtained by subtracting the correction value REF2 and the correction value ΔREF from the digital value O2.

  Also by this embodiment described above, the same effect as the first embodiment can be obtained. Further, the ADC 51 of this embodiment includes a correction unit 52 that performs offset of the digital value output from the A / D conversion unit 43. In the ADC 51 of this embodiment, the correction value REF2 corresponding to the channel CH2 can be updated in the normal sequence, but the correction value REF1 corresponding to the channel CH1 cannot be updated (acquired).

  Therefore, the correction unit 52 acquires correction values REF1 and REF2 corresponding to the channels CH1 and CH2, respectively, in the offset correction sequence performed before the normal sequence. Then, the correction unit 52 acquires a correction value ΔREF corresponding to a specific channel CH2 out of the channels CH1 and CH2 in the normal sequence, and converts the digital value output from the A / D conversion unit 43 into the digital value. Offset correction is performed using the correction value corresponding to the sampler that samples and holds the corresponding signal and the correction value ΔREF.

  In this case, the correction value ΔREF is a difference between the correction value REF2 acquired in the offset correction sequence and the correction value REF2 acquired in the normal sequence, and corresponds to drift in the channel CH2. The drift caused by the operating state is considered to be approximately the same value for both channels CH1 and CH2. Therefore, in this embodiment, in addition to the correction values REF1 and REF2 acquired in advance in the offset correction sequence, the correction of the offset is performed using the correction value ΔREF corresponding to drift.

  In this way, offset correction is performed using the optimum correction value for each of the two channels CH1 and CH2, including the channel CH1 side where the correction value cannot be updated in the normal sequence. Therefore, according to this embodiment, the effect that the output fluctuation of the ADC 51 due to the offset can be reliably suppressed can be obtained.

(Other embodiments)
In addition, this invention is not limited to each embodiment described above and described in drawing, In the range which does not deviate from the summary, it can change, combine or expand arbitrarily.
The numerical values and the like shown in the above embodiments are examples and are not limited thereto.

The present invention is not limited to an A / D conversion circuit used in an electronic control device mounted on a vehicle, and can be applied to all successive comparison A / D conversion circuits.
The method of resetting the sampling capacitors (capacitors CS1, CS2, CS3) and the configuration therefor are not limited to those described in the above embodiment, and can be changed as appropriate.

  In each of the embodiments described above, control has been described in which predetermined analog signals (IN1 to IN6) are given to the same sample and hold circuit (channel) every time. In some cases, the control may be such that a predetermined analog signal is not applied to the same sample and hold circuit.

  The number of analog signals input to the A / D conversion circuit is not limited to the number exemplified in each of the above embodiments (for example, four in the first embodiment, six in the second embodiment, etc.) and may be appropriately selected. Can be changed. Note that when the number of input analog signals is changed, the number of switches corresponding to the switches S1 to S6 may be changed in accordance with the change.

  Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, as well as other combinations and forms including only one element, more or less, are within the scope and spirit of the present disclosure.

  1, 2, 31, 41, 51 ... A / D converter circuit, 3, 4, 22 ... sample hold circuit, 5 ... D / A converter, 6, 32 ... comparator, 7 ... successive approximation register, 8 ... control circuit DESCRIPTION OF SYMBOLS 10 ... Capacitance array, 33 ... EX-OR circuit, 42, 52 ... Correction | amendment part, 44, 45, 54 ... Memory for correction | amendment, 46, 55 ... Subtractor, CS1, CS2, CS3 ... Capacitor, CU ... Capacitor, S1 ~ S6, SREF, Sr11, Sr21, Sr31, Sr12, Sr22, Sr32 ... switches.

Claims (6)

Switches (S1 to S6) for selecting and inputting an arbitrary analog signal from a plurality of analog signals which are input signals;
A plurality of sample and hold circuits (3, 4, 22) for sampling and holding the analog signal input through the switch;
A comparator (6, 32) for comparing the sampled and held analog signal between the differential inputs;
A D / A converter (5) configured to connect a capacitor array (10) to an input terminal of the comparator;
A successive approximation register (7) that holds a signal representing a comparison result by the comparator and outputs a digital value corresponding to the holding result;
An operation control unit (8) for controlling the operation of the switch and the sample and hold circuit;
With
The sample hold circuit includes a sampling capacitor (CS1, CS2, CS3) for sampling the analog signal,
The operation controller is
Controlling the operation of the sample and hold circuit so that another sample and hold circuit different from the predetermined sample and hold circuit performs the hold operation during a period in which the predetermined sample and hold circuit performs the sample operation,
When the holding operation is performed, by connecting one terminal of the sampling capacitor to a reference voltage higher than the voltage of the analog signal and connecting the other terminal of the sampling capacitor to the input terminal of the comparator, A successive approximation A / D conversion circuit that controls the operation of the sample hold circuit so as to divide an analog signal by a capacity ratio between the sampling capacity and the capacity of the D / A converter.   The successive approximation A / D conversion circuit according to claim 1, wherein the operation control unit controls the predetermined analog signal to be sampled and held by the same sample and hold circuit every time. Further, a correction unit (42, 52) for correcting a digital value output from the successive approximation register is provided,
The correction unit is
A first path selector switch (SREF) that switches a signal input path so that a reference signal is input to the sample hold circuit instead of the analog signal;
A plurality of first memories (44, 45) provided corresponding to each of the sample-and-hold circuits and for storing digital values output from the successive approximation register;
A second path switch (Sr11, Sr21, Sr31) for switching a digital value writing path from the successive approximation register to the first memory;
A third path selector switch (Sr12, Sr22, Sr32) for switching a path for reading a digital value from the first memory;
A first subtractor (46) for subtracting and outputting a digital value read from the first memory via the third path selector switch from a digital value output from the successive approximation register;
With
The operation controller is
The reference signal is sampled and held by a predetermined sample-and-hold circuit, and a digital value output from the successive approximation register is stored in the first memory corresponding to the predetermined sample-and-hold circuit. Controlling the operation of the first path changeover switch and the second path changeover switch,
When the digital value is output from the successive approximation register as the analog signal is sampled and held by the predetermined sample-and-hold circuit, the digital read from the first memory corresponding to the predetermined sample-and-hold circuit The successive approximation A / D conversion circuit according to claim 1, wherein an operation of the third path changeover switch is controlled so that a value is given to the first subtracter. The correction unit further includes:
A second memory (54) for holding a difference between a digital value read from the first memory provided corresponding to the specific sample hold circuit and a digital value output from the successive approximation register;
A second subtracter (55) for subtracting and outputting a digital value read from the second memory from a digital value output from the first subtractor;
A successive approximation A / D conversion circuit according to claim 3.   The sample-and-hold circuit connects the two terminals of the sampling capacitor to the ground, which is the reference potential of the circuit, after finishing the sampling of the analog signal and before starting the next sampling of the analog signal. The successive approximation A / D conversion circuit according to claim 1, wherein the sampling capacitor is reset. And a signal generation circuit (33) for generating an end signal indicating that the operation of the comparator has ended.
The successive approximation A / D conversion circuit according to claim 1, wherein the D / A converter is configured to start an operation based on the end signal.

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