JP2019207978A - Printed wiring board - Google Patents

Abstract

To provide a printed wiring board for housing a plurality of types of electronic components in one opening.SOLUTION: In a printed wiring board 10, a plurality of types of electronic components 32 are built in one opening 31 formed in a core substrate 30. A first electronic component 32P and a second electronic component 32N are built in one opening 31. Size of a space between the first electronic component 32P and the second electronic component 32N adjacent to each other is 10 μm or more and 50 μm or less. The size of the space between the first electronic component 32P and the core substrate 30 is 15 μm or more and 50 μm or less. The size of the space between the second electronic component 32N and the core substrate 30 is 15 μm or more and 50 μm or less.SELECTED DRAWING: Figure 1

Description

The present invention relates to a printed wiring board in which a first electronic component and a second electronic component are accommodated in an opening.

Patent Document 1 discloses a metal substrate having a built-in Peltier element.

JP 2012-39050 A

[Problems of Patent Document 1]
In Patent Document 1, a through hole is formed in a metal substrate. In Patent Document 1, one semiconductor element is accommodated in each through hole. Therefore, according to Patent Document 1, it is expected that the substrate will increase as the number of semiconductor elements incorporated in the metal substrate increases.

A printed wiring board according to the present invention penetrates through a core material having a fifth surface and a sixth surface opposite to the fifth surface, and a plurality of first electronic components and a plurality of second electronic components. Formed in the opening, a core substrate having an opening for receiving the plurality of first electronic components housed in the opening, a plurality of second electronic components housed in the opening, And a resin for fixing the plurality of first electronic components and the plurality of second electronic components to the core substrate, and a first resin insulating layer formed on the fifth surface and the opening. A first buildup layer; and a second buildup layer including the sixth surface and a second resin insulating layer formed on the opening. The resin is derived from the first resin insulating layer, and the size of the space between the first electronic component and the second electronic component is 10 μm or more and 50 μm or less, from the opening. The size of the space between the exposed side wall of the core substrate and the first electronic component facing the side wall is 15 μm or more and 50 μm or less, and the side wall of the core substrate and the side wall exposed from the opening The size of the space between the second electronic component facing the surface is 15 μm or more and 50 μm or less.

[Effect of the embodiment]
According to the embodiment of the present invention, a plurality of first electronic components and a plurality of second electronic components are accommodated in one opening formed in the core substrate. Therefore, the core substrate may not be formed between the first electronic component and the second electronic component. Further, the size of the space between the first electronic component and the second electronic component is equal to or less than a predetermined value. The size of the space between the first electronic component and the core substrate is not more than a predetermined value. The size of the space between the second electronic component and the core substrate is not more than a predetermined value. Since the size of the space is equal to or less than a predetermined value, the size of the opening can be reduced. A printed wiring board can be made small.
The size of the space between the first electronic component and the second electronic component is greater than or equal to a predetermined value. The size of the space between the first electronic component and the core substrate is not less than a predetermined value. The size of the space between the second electronic component and the core substrate is not less than a predetermined value. Even if a plurality of types of electronic components are built in one opening, resin can be filled between different electronic components. Insulation reliability and connection reliability between different electronic components can be increased.

FIG. 1A is a cross-sectional view of a printed wiring board according to the first embodiment of the present invention, and FIGS. 1B and 1C are cross-sectional views of electronic components, and FIGS. ) Is a cross-sectional view of a via conductor. 2 (A) and 2 (B) are views showing the electronic component housing method of the first embodiment, and FIG. 2 (C) is a view showing the arrangement of the electronic components. Manufacturing process diagram of printed wiring board of first embodiment Manufacturing process diagram of printed wiring board of first embodiment Manufacturing process diagram of printed wiring board of first embodiment FIG. 6A is a cross-sectional view of a printed wiring board according to the second embodiment of the present invention, and FIG. 6B is a schematic view showing a part of the wiring for built-in components, and FIG. (D) is a figure which shows the position of an electronic component. FIG. 7A, FIG. 7B, and FIG. 7C are diagrams illustrating a method for housing electronic components according to the second embodiment. 8A and 8B are plan views showing wirings that connect electronic components.

[First embodiment]
FIG. 1A is a cross-sectional view of the printed wiring board 10 of the first embodiment. The printed wiring board 10 includes a core substrate 30 having a fifth surface F and a sixth surface S opposite to the fifth surface F, and a first buildup layer 55F formed on the fifth surface F of the core substrate 30. And a second buildup layer 55S formed on the sixth surface S of the core substrate.

The core substrate 30 includes a core material (insulating substrate) 20z having a fifth surface F and a sixth surface S opposite to the fifth surface F, and a fifth conductor layer formed on the fifth surface of the core material 20z. 34F and the 6th conductor layer 34S formed on the 6th surface S of the core material 20z, the 5th conductor layer 34F, and the through-hole conductor 36 which connects the 6th conductor layer 34S. The core substrate 30 further has an opening 31 extending from the fifth surface F to the sixth surface S. In the opening 31, a plurality of first electronic components 32P and a plurality of second electronic components 32N are accommodated. The space between the first electronic component 32P and the second electronic component 32N is filled with the resin 53. The space between the first electronic component 32P and the core substrate 30 is filled with a resin 53. The space between the second electronic component 32N and the core substrate 30 is filled with a resin 53. The first electronic component 32P and the second electronic component 32N are fixed to the core substrate 30 with a resin 53.

FIG. 1B shows a first electronic component 32P.
The first electronic component 32P has electrodes 32P1 and 32P2 at both ends. For example, the first electronic component 32P includes a P-type semiconductor element 321 having a first surface F1 and a second surface S1 opposite to the first surface F1, a first electrode 32P1 and a second surface on the first surface F1. It is formed by the second electrode 32P2 on S1. The P-type semiconductor element 321 is sandwiched between the first electrode 32P1 and the second electrode 32P2.
The first electrode 32P1 faces the fifth surface F of the core substrate 30 and the second electrode 32P2 faces the sixth surface S of the core substrate 30. The P-type semiconductor element is preferably a P-type thermoelectric element.
The first electronic component 32P is built in the opening 31 so that the first electrode 32P1 faces the fifth surface F.

FIG. 1C shows the second electronic component 32N.
The second electronic component 32N has electrodes 32P3 and 32P4 at both ends. For example, the second electronic component 32N includes an N-type semiconductor element 322 having a third surface F2 and a fourth surface S2 opposite to the third surface F2, a third electrode 32P3 on the third surface F2, and a fourth surface. A fourth electrode 32P4 on S2 is formed. The N-type semiconductor element 322 is sandwiched between the third electrode 32P3 and the fourth electrode 32P4.
The third electrode 32P3 faces the fifth surface F of the core substrate 30, and the fourth electrode 32P4 faces the sixth surface S of the core substrate 30. The N-type semiconductor element is preferably an N-type thermoelectric element. The second electronic component 32N is built in the opening 31 so that the third electrode 32P3 faces the fifth surface F.

The first buildup layer 55F includes a first resin insulating layer 50F formed on the fifth surface F of the core substrate 30 and the fifth conductor layer 34F, and a first resin formed on the first resin insulating layer 50F. A conductor layer (58F), a first conductor layer (58F), a third resin insulation layer (150F) formed on the first resin insulation layer (50F), a third conductor layer (158F) formed on the third resin insulation layer (150F), Have The first resin insulating layer 50 </ b> F covers the opening 31. The resin 53 and the first resin insulating layer 50F are integrally formed. The resin derived from the first resin insulating layer 50F fills the space between the first electronic component 32P and the side wall of the core substrate 30 exposed from the opening 31. The resin derived from the first resin insulation layer 50F fills the space between the second electronic component 32N and the side wall of the core substrate 30 exposed from the opening 31. The resin derived from the first resin insulation layer 50F fills the space between the first electronic component 32P and the second electronic component 32N. The component derived from the first resin insulation layer 50F forms the resin 53. The resin 53 can include a resin derived from the first resin insulating layer 50F and inorganic particles.

The first conductor layer 58F includes a first conductor circuit 58FW formed immediately above the opening 31 and a core material first conductor circuit 58FC formed immediately above the core material 20z. Adjacent first electronic component 32P and second electronic component 32N are connected by first conductor circuit 58FW.

FIG. 8A is a plan view showing the first conductor circuit 58FW. The first conductor circuit 58FW includes a first on-electrode first conductor circuit 58FW1 covering the first electrode 32P1, a third on-electrode first conductor circuit 58FW3 covering the third electrode 32P3, a first on-electrode first conductor circuit 58FW1, The first wiring 58fW that connects the first conductor circuit 58FW3 on the three electrodes is included. The first conductor circuit 58FW1 on the first electrode is located on the first electrode 32P1, and the size of the first conductor circuit 58FW1 on the first electrode is larger than the size of the first electrode 32P1. The first conductor circuit 58FW3 on the third electrode is located on the third electrode 32P3, and the size of the first conductor circuit 58FW3 on the third electrode is larger than the size of the third electrode 32P3. The width 58fWD of the first wiring 58fW is equal to the width 58FWD1 of the first on-electrode first conductor circuit 58FW1. Alternatively, the width 58fWD of the first wiring 58fW is smaller than the width 58FWD1 of the first on-electrode first conductor circuit 58FW1. The width 58fWD of the first wiring 58fW is equal to the width 58FWD3 of the first conductor circuit 58FW3 on the third electrode. Alternatively, the width 58fWD of the first wiring 58fW is smaller than the width 58FWD3 of the first conductive circuit 58FW3 on the third electrode.
A dotted line in the first conductor circuit 58FW1 on the first electrode indicates the outer periphery of the top portion of the first via conductor 60F1 for the first electrode. The first electrode first conductive circuit 58FW1 and the first electrode 32P1 are connected by a plurality of first electrode first via conductors 60F1.
The dotted line in the first conductor circuit 58FW3 on the third electrode indicates the outer periphery of the top of the first via conductor 60F3 for the third electrode. The first conductor circuit 58FW3 on the third electrode and the third electrode 32P3 are connected by a plurality of third electrode first via conductors 60F3.
One first electrode first conductor circuit 58FW1 is formed on one first electrode 32P1. One third electrode first conductor circuit 58FW3 is formed on one third electrode 32P3.

The first buildup layer 55F further includes a first via conductor 60F that penetrates the first resin insulation layer 50F and a third via conductor 160F that penetrates the third resin insulation layer 150F. The first via conductor 60F includes a via conductor (first conductor conductor for fifth conductor layer) 60F5 that connects the fifth conductor layer 34F and the first conductor circuit 58FC on the core material, the first electrode 32P1, and the first electrode first Via conductor (first via conductor for first electrode) 60F1, third electrode 32P3, and via conductor (first via for third electrode) connecting the first conductor circuit 58FW3 connecting the first conductor circuit 58FW1. Conductor) 60F3. There are a plurality of first electrode first via conductors 60F1 that connect one first electrode 32P1 and one first electrode first conductor circuit 58FW1 to each other. For example, the number of first via conductors 60F1 for the first electrode reaching one first electrode 32P1 is 20 or more. The effect of heat dissipation can be increased. Even if the electronic component 32 expands and contracts, connection reliability can be increased. There are a plurality of third electrode first via conductors 60F3 connecting one third electrode 32P3 and one third electrode first conductor circuit 58FW3. For example, the number of third electrode first via conductors 60F3 reaching one third electrode 32P3 is 20 or more. The effect of heat dissipation can be increased. Even if the electronic component 32 expands and contracts, connection reliability can be increased.

The first resin insulating layer 50F has a bottom surface BF facing the fifth surface F and a top surface TF opposite to the bottom surface BF. The first via conductor 60F5 for the fifth conductor layer, the first via conductor 60F1 for the first electrode, and the first via conductor 60F3 for the third electrode have the top diameter TDF at the position of the top surface TF. The top diameter TDF of the first via conductor 60F5 for the fifth conductor layer, the top diameter TDF of the first via conductor 60F1 for the first electrode, and the top diameter TDF of the first via conductor 60F3 for the third electrode are substantially equal. The top diameter TDF is shown in FIG.

The second buildup layer 55S includes a second resin insulation layer 50S formed on the sixth surface S of the core substrate 30 and the sixth conductor layer 34S, and a second resin insulation layer 50S formed on the second resin insulation layer 50S. A conductor layer 58S; a fourth resin insulation layer 150S formed on the second conductor layer 58S and the second resin insulation layer 50S; a fourth conductor layer 158S formed on the fourth resin insulation layer 150S; Have

The second conductor layer 58S includes a second conductor circuit 58SW formed immediately above the opening 31 and a second on-core material conductor circuit 58SC formed immediately above the core material 20z.
The adjacent first electronic component 32P and second electronic component 32N are connected by the second conductor circuit 58SW.

FIG. 8B is a plan view showing the second conductor circuit 58SW. The second conductor circuit 58SW includes a second on-electrode second conductor circuit 58SW2 that covers the second electrode 32P2, a fourth on-electrode second conductor circuit 58SW4 that covers the fourth electrode 32P4, a second on-electrode second conductor circuit 58SW2, and a second electrode circuit. A second wiring 58sW that connects the second conductor circuit 58SW4 on the four electrodes is included. The second conductor circuit 58SW2 on the second electrode is located on the second electrode 32P2, and the size of the second conductor circuit 58SW2 on the second electrode is larger than the size of the second electrode 32P2. The second conductor circuit 58SW4 on the fourth electrode is located on the fourth electrode 32P4, and the size of the second conductor circuit 58SW4 on the fourth electrode is larger than the size of the fourth electrode 32P4. The width 58sWD of the second wiring 58sW is equal to the width 58SWD2 of the second on-electrode second conductor circuit 58SW2. Alternatively, the width 58sWD of the second wiring 58sW is smaller than the width 58SWD2 of the second conductive circuit 58SW2 on the second electrode. The width 58sWD of the second wiring 58sW is equal to the width 58SWD4 of the second conductive circuit 58SW4 on the fourth electrode. Alternatively, the width 58sWD of the second wiring 58sW is smaller than the width 58SWD4 of the second conductive circuit 58SW4 on the fourth electrode.
The dotted line in the second conductor circuit 58SW2 on the second electrode indicates the outer periphery of the top of the second electrode second via conductor 60S2. The second electrode second conductive circuit 58SW2 and the second electrode 32P2 are connected by a plurality of second electrode second via conductors 60S2.
A dotted line in the second conductor circuit 58SW4 on the fourth electrode indicates the outer periphery of the top portion of the second via conductor 60S4 for the fourth electrode. The fourth electrode upper second conductor circuit 58SW4 and the fourth electrode 32P4 are connected by a plurality of fourth electrode second via conductors 60S4.
One second second electrode circuit 58SW2 is formed on one second electrode 32P2. One fourth on-electrode second conductor circuit 58SW4 is formed on one fourth electrode 32P4.

The second buildup layer 55S further includes a second via conductor 60S that penetrates the second resin insulation layer 50S and a fourth via conductor 160S that penetrates the fourth resin insulation layer 150S. The second via conductor 60S includes a via conductor (second via conductor for sixth conductor layer) 60S6 that connects the sixth conductor layer 34S and the second conductor circuit 58SC on the core material, the second electrode 32P2, and the second on-second electrode. Via conductor (second electrode second via conductor) 60S2 connecting the two-conductor circuit 58SW2, the fourth electrode 32P4, and a via conductor connecting the fourth electrode second conductor circuit 58SW4 (second via for second electrode) Conductor) 60S4. There are a plurality of second via conductors 60S2 for second electrodes that connect one second electrode 32P2 and one second electrode circuit on the second electrode 58SW2. For example, the number of second electrode second via conductors 60S2 reaching one second electrode 32P2 is 20 or more. The effect of heat dissipation can be increased. Even if the electronic component 32 expands and contracts, connection reliability can be increased. There are a plurality of fourth electrode second via conductors 60S4 that connect one fourth electrode 32P4 and one fourth electrode second conductor circuit 58SW4. For example, the number of the fourth electrode second via conductors 60S4 reaching one fourth electrode 32P4 is 20 or more. The effect of heat dissipation can be increased. Even if the electronic component 32 expands and contracts, connection reliability can be increased.

The second resin insulation layer 50S has a bottom surface BS facing the sixth surface S and a top surface TS opposite to the bottom surface BS. The second via conductor 60S6 for the sixth conductor layer, the second via conductor 60S2 for the second electrode, and the second via conductor 60S4 for the fourth electrode have a top diameter TDS at the position of the top surface TS. The top diameter TDS of the second via conductor 60S6 for the sixth conductor layer, the top diameter TDS of the second via conductor 60S2 for the second electrode, and the top diameter TDS of the second via conductor 60S4 for the fourth electrode are substantially equal. The top diameter TDS is shown in FIG.

A second solder resist layer 70S having an opening 71S can be formed on the fourth conductor layer 158S and the fourth resin insulation layer 150S. The fourth conductor layer 158S exposed from the opening 71S forms a second pad 73S for connecting to a wiring board such as a mother board.

A first solder resist layer 70F having an opening 71F can be formed on the third resin insulating layer 150F and the third conductor layer 158F. The third conductor layer 158F exposed from the opening 71F forms a first pad 73F for mounting an electronic component. Examples of electronic components mounted on the first pad 73F are LEDs and power semiconductors, and generate a large amount of heat during driving.

The first electronic component 32P, the second electronic component 32N, the first conductor circuit 58FW, the first electrode first via conductor 60F1, the third electrode first via conductor 60F3, the second conductor circuit 58SW, and the second electrode second. A connection method between the via conductor 60S2 and the second electrode second via conductor 60S4 is schematically shown in FIGS. 6B, 8A, and 8B. FIG. 6B is a cross-sectional view. As shown in these drawings, the first electronic component 32P and the second electronic component 32N include the first conductor circuit 58FW, the first electrode first via conductor 60F1, the third electrode first via conductor 60F3, and the second electrode. The conductor circuit 58SW, the second electrode second via conductor 60S2 and the fourth electrode second via conductor 60S4 are connected in series. The first electronic component 32P and the second electronic component 32N are alternately connected. The first electronic component 32P and the second electronic component 32N are alternately arranged, and both are connected in series. The connection in the first conductor circuit 58FW between the first electronic component 32P and the second electronic component 32N and the connection in the second conductor circuit 58SW between the first electronic component 32P and the second electronic component 32N are alternately repeated.

As shown in FIG. 1A, the second pad 73S includes a second pad (plus pad) 73SP having a plus potential and a second pad (minus pad) 73SN having a minus potential. The plurality of first electronic components 32P and the plurality of second electronic components 32N are disposed between the plus pad 73SP and the minus pad 73SN. Wiring (wiring for built-in components) from the plus pad 73SP to the minus pad 73SN via the first electronic component 32P and the second electronic component 32N is independent in the printed wiring board 10. The wiring for the built-in component includes the first conductor circuit 58FW, the first electrode first via conductor 60F1, the third electrode first via conductor 60F3, the second conductor circuit 58SW, the second electrode second via conductor 60S2, and the fourth. An electrode second via conductor 60S4 is included. The wiring for the built-in component is not connected to the conductor circuit in the printed wiring board other than the wiring for the built-in component. Data transmitted through the printed wiring board 10 is unlikely to deteriorate. The through-hole conductor 36S surrounding the opening 31 is included in the built-in component wiring. For example, the number of through-hole conductors 36S included in the internal component wiring is two. The first conductor circuit 58FWLU at the upper left in FIG. 8A extends from a position on the opening 31 to a position on the core material 20z, and is connected to the through-hole conductor 36S. The first conductor circuit 58FWLL at the lower left in FIG. 8A extends from the position on the opening 31 to the position on the core material 20z and is connected to the through-hole conductor 36S.
A second pad having a lower potential than the plus pad is included in the minus pad.

The first electronic component 32P and the second electronic component 32N are connected to the first conductor circuit 58FW via the first via conductor 60F. Therefore, even if the first electronic component 32P and the second electronic component 32N are built in the core substrate, heat can be transferred to the first electronic component 32P and the second electronic component 32N via the first conductor circuit 58FW. Heat can be efficiently transferred to the first electronic component 32P and the second electronic component 32N. The temperature rise of the electronic component mounted on the printed wiring board can be suppressed. For example, the heat is generated from an electronic component mounted on the first pad 73F. In the cross-sectional direction, the core substrate 30 is positioned substantially at the center of the printed wiring board. The cross-sectional direction is perpendicular to the fifth surface F.

The first electronic component 32P and the second electronic component 32N are connected to the second conductor circuit 58SW through the second via conductor 60S. Therefore, even if the first electronic component 32P and the second electronic component 32N are built in the core substrate, heat can be transmitted to the outside via the second conductor circuit 58SW. Heat can be efficiently transferred to the outside. For example, heat can be transferred to the motherboard. The temperature rise of the electronic component mounted on the printed wiring board can be suppressed.

The core material 20z is formed of a resin such as epoxy and a reinforcing material such as glass cloth. The core material 20z may further include inorganic particles such as silica. The first resin insulation layer 50F, the second resin insulation layer 50S, the third resin insulation layer 150F, and the fourth resin insulation layer 150S are formed of a resin such as epoxy and inorganic particles such as silica. The first resin insulating layer 50F, the second resin insulating layer 50S, the third resin insulating layer 150F, and the fourth resin insulating layer 150S may further include a reinforcing material such as glass cloth.

In the printed wiring board 10 of the first embodiment, the current from the electronic component mounted on the first pad 73F is passed through the second pad 73S by flowing current through the first electronic component 32P and the second electronic component 32N. Can be transmitted to the wiring board.

FIG. 2B shows the arrangement of the first electronic component 32P and the second electronic component 32N accommodated in the opening 31 of the core substrate 30. The first electronic component 32P and the second electronic component 32N are alternately arranged. The second electronic component 32N is located next to the first electronic component 32P. As shown in FIG. 2B, in the drawing, the electronic component located above the first electronic component 32P is the second electronic component 32N, and the electronic component located below the first electronic component 32P is the first. The second electronic component 32N is the second electronic component 32N, and the electronic component located to the left of the first electronic component 32P is the second electronic component 32N. The electronic component located above the second electronic component 32N is the first electronic component 32P, and the electronic component located below the second electronic component 32N is the first electronic component 32P, to the right of the second electronic component 32N. The electronic component located is the first electronic component 32P, and the electronic component located to the left of the second electronic component 32N is the first electronic component 32P.
The number of first electronic components 32P accommodated in one opening 31 is equal to the number of second electronic components 32N.

A plurality of types of electronic components are built in one opening 31. Examples of the electronic components are the first electronic component 32P and the second electronic component 32N. There are a plurality of various electronic components. There is no core substrate 30 between adjacent electronic components. There is no core material 20z between adjacent electronic components. Therefore, the size of the opening 31 for accommodating the electronic component can be reduced. The size of the printed wiring board 10 can be reduced. The number of first electronic components 32P is 10 or more, and the number of second electronic components 32N is 10 or more.

For example, the shape of the first electronic component 32P and the second electronic component 32N is a cube. An example of the length of each side is 1 mm.

As shown in FIG. 2B, a space se exists between the adjacent first electronic component 32P and second electronic component 32N. The width seD of the space se is 10 μm or more and 50 μm or less. Since the space se exists, interference between the first electronic component 32P and the second electronic component 32N can be suppressed.
As shown in FIG. 2B, a space sw exists between the core substrate 30 and the first electronic component 32P. A space sw exists between the core substrate 30 and the second electronic component 32N. The width swD of the space sw is 15 μm or more and 50 μm or less. Since the space sw exists, interference between the first electronic component 32P and the fifth conductor layer 34F can be suppressed. Interference between the second electronic component 32N and the fifth conductor layer 34F can be suppressed. Interference between the first electronic component 32P and the sixth conductor layer 34S can be suppressed. Interference between the second electronic component 32N and the sixth conductor layer 34S can be suppressed.

According to the printed wiring board 10 of the first embodiment, a plurality of electronic components (first electronic component 32P and second electronic component 32N) 32 are accommodated in one opening 31. Even if a large number of electronic components are incorporated in the printed wiring board 10, the size of the printed wiring board 10 can be reduced. Even if a plurality of electronic components are built in the printed wiring board, the printed wiring board 10 having a small and high cooling effect can be provided.

The space se and the space sw are filled with the resin 53 derived from the first resin insulating layer 50F. For this reason, the resin 53 and the first resin insulation layer 50F formed in the opening 31 are integrally formed. No interface is formed between the resin 53 and the first resin insulating layer 50F. Therefore, even if the electronic component 32 in the opening 31 repeats thermal expansion and thermal contraction, no separation occurs between the resin 53 and the first resin insulating layer 50F. The printed wiring board 10 having high reliability can be provided. Since the sizes seD and swD of the space se and the space sw are in an appropriate range, the resin 53 derived from the first resin insulating layer 50F can enter the spaces se and sw. The spaces se and sw can be filled with the resin 53 derived from the first resin insulation layer 50F.

The first wiring 58fW connects only different types of electronic components. The second wiring 58sW connects only different types of electronic components. Interference between electronic components of the same type can be suppressed. For example, individual electronic components can exert their maximum capabilities. The effect of heat dissipation can be increased.

[Production Method of First Embodiment]
3-5 shows the manufacturing method of the printed wiring board of 1st Embodiment.
A double-sided copper-clad laminate 20 is prepared (FIG. 3A). The double-sided copper-clad laminate 20 is formed of a core material 20z having a fifth surface F and a sixth surface S opposite to the fifth surface F, and a copper foil 22 laminated on both surfaces of the core material 20z. .

Through-holes for through-hole conductors are formed in the double-sided copper-clad laminate 20. A through hole conductor 36 is formed in the through hole for the through hole conductor. Thereafter, the fifth conductor layer 34F is formed on the fifth surface F of the core material 20z by a subtractive method. A sixth conductor layer 34S is formed on the sixth surface S of the core material 20z. The fifth conductor layer 34F and the sixth conductor layer 34S are connected by a through-hole conductor 36. The circuit board is completed. The fifth conductor layer 34F has an alignment mark TM. With reference to the alignment mark TM, an opening 31 penetrating the circuit board is formed at the center of the circuit board. The core substrate 30 having the fifth surface F and the sixth surface S opposite to the fifth surface F is completed (FIG. 3B). The core substrate 30 includes a fifth conductor layer 34F, a sixth conductor layer 34S, a through-hole conductor 36, and an opening 31. The fifth surface F of the core substrate 30 and the fifth surface F of the core material 20z are the same surface, and the sixth surface S of the core substrate 30 and the sixth surface S of the core material 20z are the same surface.

The tape 18 is stuck on the sixth surface S of the core substrate 30, and the opening 31 is closed (FIG. 3C). First, the first electronic components 32P are mounted one by one on the tape exposed from the opening 31 with the alignment mark TM as a reference. At this time, as shown in FIG. 2A, the first electronic component 32P is mounted on the tape 18 so that the space SP for mounting the first electronic component 32P and the second electronic component 32N is adjacent. (FIG. 3D). The first electronic components 32P are arranged in rows and columns, and the first electronic components 32P and the spaces SP are alternately arranged. The mounting of the first electronic component 32P is completed. All the first electronic components 32P accommodated in one opening 31 are mounted on the tape 18. Thereafter, the second electronic components are mounted one by one on the tape exposed from the opening 31 and the first electronic component 32P with the alignment mark TM as a reference. At this time, as shown in FIG. 2B, the second electronic component 32N is placed in the space SP. The first electronic component 32P and the second electronic component 32N are adjacent to each other. The second electronic components 32N are arranged in rows and columns, and the first electronic components 32P and the second electronic components 32N are alternately arranged (FIG. 4A). As shown in FIG. 2C, the first electronic component 32P and the second electronic component 32N are arranged at the intersection of the row and the column. The number of rows and the number of columns are the same. The number of rows is 4 or more and the number of columns is 4 or more. In the method for manufacturing a printed wiring board according to the first embodiment, first, all the first electronic components 32 </ b> P are accommodated in the openings 31. Thereafter, all the second electronic components 32N are accommodated in the opening 31. For this reason, two types of electronic components 32P and 32N can be accommodated in the correct position. The opening 31 is formed and the electronic components 32P and 32N are mounted using the same alignment mark TM as a reference. For this reason, the positional accuracy between the opening 31 and the electronic components 32P and 32N can be increased. The positional accuracy between the first electronic component 32P and the second electronic component 32N can be increased. The width seD of the space se can be set within a predetermined range (10 μm or more and 50 μm or less). The width swD of the space sw can be set within a predetermined range (15 μm or more and 50 μm or less).

The mounting order of the first electronic component 32P and the second electronic component 32N is arbitrary.

When the electronic components 32 </ b> P and 32 </ b> N are mounted on the tape 18, an uncured resin insulating layer forming film is laminated on the fifth surface F of the core substrate 30. At this time, the resin insulating layer forming film covers the opening 31. Thereafter, the resin insulating layer forming film is softened by heating press. Space se and space sw are filled with resin containing inorganic particles derived from the resin insulating layer forming film (FIG. 4B). The resin insulating layer forming film, the resin filling the space se, and the resin filling the space sw are cured. A first resin insulation layer 50 </ b> F is formed on core substrate 30 and opening 31. A resin 53 filling the space se and the space sw is formed. The first resin insulating layer 50F and the resin 53 are integrally formed.

The first resin insulating layer 50F has a bottom surface BF facing the fifth surface F and a top surface TF opposite to the bottom surface BF.

The tape 18 is removed from the core substrate 30. A second resin insulation layer 50S is formed on the sixth surface S and the opening 31 of the core substrate 30 (FIG. 4C).

The second resin insulation layer 50S has a bottom surface BS facing the sixth surface S and a top surface TS opposite to the bottom surface BS.

A first conductor layer (58F) is formed on first resin insulation layer (50F). At the same time, a first via conductor 60F that penetrates the first resin insulation layer 50F is formed. The first conductor layer 58F and the first via conductor 60F are formed by a semi-additive method. An opening for the first via conductor that penetrates through the first resin insulating layer 50F is formed. Then, the first via conductor 60F is formed by filling the opening. The opening for the first via conductor has a top diameter TDF at the position of the top surface TF of the first resin insulation layer 50F.
The first conductor layer 58F includes a first electrode-on-first conductor circuit 58FW1 formed on one first electronic component 32P and a third electrode-on-first conductor formed on one second electronic component 32N. Circuit 58FW3 is included. A plurality of first conductor circuits 58FW1 on the first electrode and first conductor circuits 58FW3 on the third electrode are formed. Adjacent first electronic component 32P and second electronic component 32N are connected by one first wiring 58fW. One first electronic component 32P and one second electronic component 32N are connected by one first wiring 58fW.
The first via conductor 60F is a first electrode first connection that connects the first conductor conductor 58F5, the first electrode 32P1, and the first conductor circuit 58FW that connects the first conductor layer 58F and the fifth conductor layer 34F. 1 via conductor 60F1, 3rd electrode 32P3, and 3rd electrode 1st via conductor 60F3 which connects 1st conductor circuit 58FW are provided. The first via conductor 60F5 for the fifth conductor layer has a top diameter TDF at the position of the top surface TF. The first electrode first via conductor 60F1 has a top diameter TDF at the position of the top surface TF. The first via conductor 60F3 for the third electrode has a top diameter TDF at the position of the top surface TF. The top diameter TDF of the first via conductor 60F5 for the fifth conductor layer, the top diameter TDF of the first via conductor 60F1 for the first electrode, and the top diameter TDF of the first via conductor 60F3 for the third electrode are substantially equal. The first electrode first via conductor 60F1 and the third electrode first via conductor 60F3 are formed with the alignment mark TM as a reference.
One first electrode 32P1 and the first conductor circuit 58FW are connected by a plurality of first electrode first via conductors 60F1. For example, the number of first via conductors 60F1 for the first electrode that connects one first electrode 32P1 and the first conductor circuit 58FW is 30 or more and 40 or less.
One third electrode 32P3 and the first conductor circuit 58FW are connected by a plurality of third electrode first via conductors 60F3. For example, the number of first via conductors 60F3 for third electrode connecting one third electrode 32P3 and the first conductor circuit 58FW is 30 or more and 40 or less.

A second conductor layer 58S is formed on the second resin insulation layer 50S. At the same time, a second via conductor 60S penetrating the second resin insulation layer 50S is formed. The second conductor layer 58S and the second via conductor 60S are formed by a semi-additive method. An opening for the second via conductor penetrating through the second resin insulating layer 50S is formed. Then, the second via conductor 60S is formed by filling the opening. The opening for the second via conductor has a top diameter TDS at the position of the top surface TS of the second resin insulation layer 50S.
The second conductor layer 58S is a second conductor on the second electrode 58SW2 formed on one first electronic component 32P and a second conductor on the fourth electrode formed on one second electronic component 32N. A circuit 58SW4 is included. A plurality of second conductor circuits 58SW2 on the second electrode and second conductor circuits 58SW4 on the fourth electrode are formed. Adjacent first electronic component 32P and second electronic component 32N are connected by one second wiring 58sW. One first electronic component 32P and one second electronic component 32N are connected by one second wiring 58sW.
The second via conductor 60S includes a second via conductor for second electrode 60S6 for connecting the second conductor layer 58S and the sixth conductor layer 34S, a second via conductor for the sixth conductor layer 60S6, the second electrode 32P2, and the second conductor circuit 58SW. A second via conductor 60S4 for the fourth electrode that connects the two via conductors 60S2, the fourth electrode 32P4, and the second conductor circuit 58SW; The second via conductor 60S6 for the sixth conductor layer has a top diameter TDS at the position of the top surface TS. The second electrode second via conductor 60S2 has a top diameter TDS at the position of the top surface TS. The fourth electrode second via conductor 60S4 has a top diameter TDS at the position of the top surface TS. The top diameter TDS of the second via conductor 60S6 for the sixth conductor layer, the top diameter TDS of the second via conductor 60S2 for the second electrode, and the top diameter TDS of the second via conductor 60S4 for the fourth electrode are substantially equal.
One second electrode 32P2 and the second conductor circuit 58SW are connected by a plurality of second via conductors 60S2 for the second electrode. For example, the number of second via conductors 60S2 for the second electrode connecting one second electrode 32P2 and the second conductor circuit 58SW is 30 or more and 40 or less.
One fourth electrode 32P4 and the second conductor circuit 58SW are connected by a plurality of fourth electrode second via conductors 60S4. For example, the number of the fourth electrode second via conductors 60S4 connecting one fourth electrode 32P4 and the second conductor circuit 58SW is 30 or more and 40 or less (FIG. 5A).

The third resin insulation layer 150F is formed on the first conductor layer 58F and the first resin insulation layer 50F. The third conductor layer 158F is formed on the third resin insulating layer 150F by a semi-additive method. At the same time, a third via conductor 160F that penetrates the third resin insulating layer 150F and connects the first conductor layer 58F and the third conductor layer 158F is formed (FIG. 5B). For example, there is no third via conductor 160F that connects the third conductor layer 158F and the first conductor circuit 58FW.

A fourth resin insulation layer 150S is formed on the second conductor layer 58S and the second resin insulation layer 50S. The fourth conductor layer 158S is formed on the fourth resin insulating layer 150S by a semi-additive method. At the same time, a fourth via conductor 160S that penetrates through the fourth resin insulating layer 150S and connects the second conductor layer 58S and the fourth conductor layer 158S is formed (FIG. 5B). For example, there is no fourth via conductor 160S connecting the fourth conductor layer 158S and the second conductor circuit 58SW.

A first solder resist layer (70F) having a first opening (71F) is formed on the third conductor layer (158F) and the third resin insulation layer (150F). A second solder resist layer 70S having a second opening 71S is formed on the fourth conductor layer 158S and the fourth resin insulation layer 150S. The printed wiring board 10 is completed (FIG. 1A). The third conductor layer 158F exposed from the first opening 71F functions as a pad for mounting an electronic component. The fourth conductor layer 158S exposed from the second opening 71S functions as a pad for connecting to the motherboard.

[Second Embodiment]
FIG. 6A is a cross-sectional view of the printed wiring board 110 according to the second embodiment. The printed wiring board 110 accommodates three types of electronic components 33 in the opening 31 of the core substrate 30. An example of the electronic component 33 accommodated in one opening 31 is a capacitor 33C, an inductor 33L, and a resistor 33R.

[Manufacturing Method of Second Embodiment]
FIG. 7 shows a part of the manufacturing method of the printed wiring board 110 of the second embodiment. FIG. 7 shows a method of mounting the electronic component 33 on the tape 18 closing the opening 31.
Similar to the first embodiment, first, the first electronic components such as the capacitor 33C are mounted on the tape 18 one by one in the opening 31 with the alignment mark TM as a reference. The housing of the first electronic component such as the capacitor 33C is completed. As shown in FIG. 7A, all the first electronic components such as the capacitors 33C are mounted on the tape 18 exposed from the openings 31. Thereafter, the second electronic components such as the inductor 33L are mounted on the tape 18 one by one with the alignment mark TM as a reference. The housing of the second electronic component such as the inductor 33L is completed. All the second electronic components such as the inductor 33 </ b> L are mounted on the tape 18 exposed from the opening 31. Finally, the third electronic components such as the resistor 33R are mounted on the tape 18 one by one using the alignment mark TM as a reference. The accommodation of the third electronic component such as the resistor 33R is completed. All the third electronic components such as the resistor 33R are mounted on the tape 18 exposed from the opening 31. Three types of electronic components 33 are arranged at the intersections of rows and columns.
The method for forming the core substrate 30 of the first embodiment is the same as the method for forming the core substrate 30 of the second embodiment. The method for forming the first buildup layer 55F in the first embodiment and the method for forming the first buildup layer 55F in the second embodiment are the same. The method for forming the second buildup layer 55S of the first embodiment and the method for forming the second buildup layer 55S of the second embodiment are the same. The method for forming the first solder resist layer 70F in the first embodiment and the method for forming the first solder resist layer 70F in the second embodiment are the same. The method for forming the second solder resist layer 70S of the first embodiment and the method for forming the second solder resist layer 70S of the second embodiment are the same.

The row is substantially parallel to the side wall of the core substrate exposed from the opening 31 for containing the electronic component 32. The row is substantially parallel to the side wall of the core substrate exposed from the opening 31 for containing the electronic component 32.

The first conductor circuit 58FW includes a first conductor circuit 58FWF1 and a first electronic component 32P that connect the second electronic component 32N and the through-hole conductor 36S (through-hole conductor in the wiring for built-in components) in FIG. A first conductor circuit 58FWF2 that connects the through-hole conductor 36S (through-hole conductor in the built-in component wiring) in FIG. 1A can be included.

The second conductor circuit 58SW is a second conductor circuit connecting the first electronic component 32P and the through-hole conductor in the built-in component wiring, the second conductor circuit 58N and the second electronic component 32N and the through-hole conductor 36S in the built-in component wiring. Conductor circuits can be included.

FIG. 6C shows two first electronic components 32P (32PI, 32PII) and two second electronic components 32N (32NI, 32NII) arranged in one row. As shown in FIG. 6C, the electronic components are arranged in the order of the first electronic component 32PI, the second electronic component 32NI, the first electronic component 32PII, and the second electronic component 32NII. A straight line L2 connecting the center of gravity of the first surface F1 of the first electronic component 32PI and the center of gravity of the first surface F1 of the first electronic component 32PII is shown in FIG. 6C. A straight line L1 connecting the center of gravity of the third surface F2 of the second electronic component 32NI and the center of gravity of the third surface F2 of the second electronic component 32NII is shown in FIG. 6C. The straight line L1 and the straight line L2 do not overlap. There is a gap between the straight line L1 and the straight line L2. Heat conduction can be increased.
A straight line connecting the centroid of the first surface of one first electronic component arranged on a specific row and the centroid of the first surface of another first electronic component and one arranged on the specific row A straight line connecting the center of gravity of the third surface of the second electronic component and the center of gravity of the third surface of another second electronic component does not overlap.

FIG. 6D shows two first electronic components 32P (32PI, 32PII) and two second electronic components 32N (32NI, 32NII) arranged in one column. As shown in FIG. 6D, the electronic components are arranged in the order of the first electronic component 32PI, the second electronic component 32NI, the first electronic component 32PII, and the second electronic component 32NII. A straight line L4 connecting the center of gravity of the first surface F1 of the first electronic component 32PI and the center of gravity of the first surface F1 of the first electronic component 32PII is shown in FIG. 6 (D). A straight line L3 connecting the center of gravity of the third surface F2 of the second electronic component 32NI and the center of gravity of the third surface F2 of the second electronic component 32NII is shown in FIG. 6 (D). The straight line L3 and the straight line L4 do not overlap. There is a gap between the straight line L3 and the straight line L4. Heat conduction can be increased.
A straight line connecting the centroid of the first surface of one first electronic component arranged on a specific row and the centroid of the first surface of another first electronic component and one arranged on the specific row A straight line connecting the center of gravity of the third surface of the second electronic component and the center of gravity of the third surface of another second electronic component does not overlap.

According to the embodiment, the temperature of the electronic component mounted on the printed wiring board can be controlled within a predetermined range.

30 Core substrate 31 Opening 32P First electronic component 32N Second electronic component 34F Fifth conductor layer 50F First resin insulation layer 60F First via conductor 60S Second via conductor 60F5 First via conductor for fifth conductor layer 60F1 First electrode First via conductor 60F3 first via conductor for third electrode 60S6 second via conductor for sixth conductor layer 60S2 second via conductor for second electrode 60S4 second via conductor for fourth electrode se, sw space

Claims (7)

A core member having a fifth surface and a sixth surface opposite to the fifth surface; and a plurality of first electronic components and openings for receiving the plurality of second electronic components through the core material. A core substrate;
A plurality of the first electronic components housed in the opening;
A plurality of the second electronic components housed in the opening;
A resin formed in the opening for fixing the plurality of first electronic components and the plurality of second electronic components to the core substrate;
A first buildup layer including a first resin insulating layer formed on the fifth surface and the opening;
A printed wiring board having the sixth surface and a second buildup layer including a second resin insulation layer formed on the opening,
The resin is derived from the first resin insulating layer, and the size of the space between the first electronic component and the second electronic component is 10 μm or more and 50 μm or less, and is exposed from the opening. The size of the space between the side wall of the core substrate and the first electronic component facing the side wall is 15 μm or more and 50 μm or less, and the side wall of the core substrate exposed from the opening and the surface facing the side wall The size of the space between the second electronic component is 15 μm or more and 50 μm or less. 2. The printed wiring board according to claim 1, wherein the first electronic component is a P-type thermoelectric element and the second electronic component is an N-type thermoelectric element. 2. The printed wiring board according to claim 1, wherein the first electronic component and the second electronic component are located at an intersection of a row and a column, and the two are alternately arranged. 4. The printed wiring board according to claim 3, wherein one of the first electronic component and the second electronic component is necessarily located on the intersection. 4. The printed wiring board according to claim 3, wherein the opening, the first electronic component, and the second electronic component have a rectangular parallelepiped shape, and a side wall of the core substrate exposed from the opening is formed of the first electronic component. The side wall of the core substrate that is substantially parallel to the side wall and exposed from the opening is substantially parallel to the side wall of the second electronic component. 4. The printed wiring board according to claim 3, wherein the number of rows and the number of columns are the same. 4. The printed wiring board according to claim 3, wherein the number of rows is four or more and the number of columns is four or more.

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