JP2019186817A - Solid state image sensor, imaging apparatus, and control method of solid state image sensor - Google Patents

Abstract

To reduce a calculation required for detecting a defective pixel.SOLUTION: A solid state image sensor comprises: a pixel (100) that outputs a signal based on a photo-electric conversion; a comparator (307) that compares a signal based on the photo-electric conversion with a first reference signal changing a level depending on a time in a first period, and compares a signal based on the photo-electric conversion with a fixed signal in a second period; a counter (310) that performs a count of a first count value in accordance with a comparison result of the comparator in the first period ; a first memory (312) that holds the first count value of the counter; and a second memory (313) that holds a value indicating a comparison result of the comparator in the second period.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a solid-state imaging device, an imaging apparatus, and a control method for a solid-state imaging device.

  In the imaging apparatus, a solid-state imaging device such as a CCD or a CMOS is used. In these solid-state imaging devices, defective pixels may occur due to local crystal defects existing on the semiconductor substrate. Since such a defective pixel cannot generate a correct pixel signal, it is necessary to detect the defective pixel and correct the output signal.

  As an example of a method for correcting an output signal of a defective pixel, a defective pixel included in a solid-state imaging device is detected in a manufacturing process, and defect information such as position data of the defective pixel is recorded in a nonvolatile memory of the imaging device. A method for correcting defective pixels based on the above is known. In this method, defect information can be obtained with high accuracy in the manufacturing process, and correction of defective pixels is performed based on defect information registered in advance, so that there are few false detections of defective pixels and high accuracy. On the other hand, it is not possible to correct defective pixels that could not be detected in the manufacturing process, such as late defective pixels that occurred after the shipment of the imaging device, and blinking defective pixels whose output level fluctuates with each shooting.

  On the other hand, a real-time defective pixel detection method is known in which a defective pixel is determined based on a level difference from a signal of a surrounding pixel every time an image is taken by an imaging device. For example, Patent Document 1 discloses a defective pixel correction device that detects a defective pixel by comparing a difference value between an average value of signals output from a pixel of interest and a plurality of pixels around the pixel of interest with a predetermined value. Yes. Real-time defective pixel detection is effective for correcting subsequent defective pixels or flashing defective pixels that are not recorded in advance in the nonvolatile memory or the like of the imaging apparatus, and suppressing image quality deterioration.

JP 2005-286825 A

  In Patent Document 1, the arithmetic circuit obtains an average value of luminance signals of peripheral pixels of the detection target pixel, further obtains a difference value from the luminance signal of the detection target pixel, and then uses the obtained difference value as a predetermined threshold value. Defect determination is performed by comparison. In order to detect a defect involving such a complicated operation, a large-scale arithmetic circuit is required.

  In addition, it is known that in the real-time defective pixel detection method, it is a serious problem to improve the accuracy of discrimination between defective pixels to be corrected and subject edges. If the area of the peripheral pixels used for obtaining the average value is narrow, the determination of the defective pixel and the subject edge may be erroneous for a subject including fine lines such as fireworks and characters, and fine patterns. It is possible to improve the determination accuracy of defective pixels and subject edges by enlarging the area of surrounding pixels to be used and adding direction determination such as comparison with upper and lower pixels and left and right pixels, but the pixels used for comparison By increasing the number, operations for defect detection are further increased and complicated. Therefore, in the real-time defective pixel detection method, it is difficult to enlarge the pixel area used for the calculation.

  An object of the present invention is to be able to reduce operations necessary for detecting defective pixels.

  The solid-state imaging device of the present invention compares a pixel that outputs a signal based on photoelectric conversion, a signal based on the photoelectric conversion in a first period, and a first reference signal whose level changes with time. A comparator that compares the signal based on the photoelectric conversion with a fixed signal in a period of 2, and a counter that counts a first count value according to a comparison result of the comparator in the first period; A first memory that holds a first count value of the counter, and a second memory that holds a value indicating a comparison result of the comparator in the second period.

  According to the present invention, it is possible to reduce the computation required for detecting defective pixels.

It is a block diagram which shows the structural example of an imaging device. It is a block diagram which shows the structural example of a solid-state image sensor. It is an equivalent circuit diagram which shows the structural example of a solid-state image sensor. It is a timing chart which shows the drive method of a solid-state image sensor. It is a schematic diagram which shows the image data read from the solid-state image sensor. It is a flowchart which shows the detection method of a defective pixel. It is an equivalent circuit diagram which shows the structural example of a solid-state image sensor. It is a timing chart which shows the drive method of a solid-state image sensor. It is a block diagram which shows the structural example of a solid-state image sensor. It is a block diagram which shows the structural example of a memory. It is a block diagram which shows the structural example of a solid-state image sensor.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
(First embodiment)
FIG. 1 is a block diagram illustrating a configuration example of the imaging apparatus 11 according to the first embodiment of the present invention. The photographing lens 1 forms an image of light on the solid-state image sensor 2. The solid-state imaging device 2 converts incident light into an image signal and outputs the image signal. The signal processing circuit 3 performs various corrections such as signal amplification and reference level adjustment, data rearrangement, and the like on the image signal output from the solid-state imaging device 2. The timing generation circuit 5 outputs a drive timing signal to the solid-state imaging device 2. The overall control / arithmetic circuit 4 performs overall driving / control of the entire imaging apparatus 11 such as the timing generation circuit 5 and the signal processing circuit 3 and predetermined image processing. The overall control / arithmetic circuit 4 performs defective pixel detection, defect correction, and the like as detection means and correction means. The memory circuit 6 includes a volatile memory that temporarily records and holds image signals and the like when the overall control / arithmetic circuit 4 performs arithmetic processing. The recording circuit 7 is a recording medium such as a memory card that records and holds an image signal and the like output from the overall control / arithmetic circuit 4. The display circuit 8 displays captured images, live view images, various setting screens, and the like. The operation circuit 9 outputs an operation member signal to the overall control / arithmetic circuit 4 as a user command.

  FIG. 2 is a block diagram illustrating a configuration example of the solid-state imaging device 2. The pixel unit 10 includes a plurality of pixels 100 arranged in a two-dimensional matrix. Each of the plurality of pixels 100 includes a color filter that transmits light in a predetermined wavelength range. The transmission wavelength of the color filter is not limited. For example, the color filter is a color filter that transmits red (R), green (G), and blue (B) light. The pixel unit 10 includes a plurality of pixels 100 arranged in a Bayer shape. The pixel unit 10 includes a pixel 100 provided with a red color filter, a pixel 100 provided with a green color filter, and a pixel 100 provided with a blue color filter.

  The vertical scanning circuit 20 supplies a control signal for controlling each pixel 100 to the pixel unit 10. The column circuit unit 30 includes a plurality of column circuits 300. The plurality of column circuits 300 are provided corresponding to the columns of the plurality of pixels 100. The reference signal generation circuit 40 generates a reference signal and supplies the reference signal to the column circuit 300. The clock generation circuit 50 supplies a clock signal to the column circuit 300. The horizontal scanning circuit 60 supplies a scanning signal for outputting a pixel signal to the column circuit 300. The arithmetic circuit 70 performs arithmetic processing on the pixel signal output from the column circuit unit 30 and outputs the arithmetically processed pixel signal.

  FIG. 3 is an equivalent circuit diagram illustrating a configuration example of the pixel 100, the column circuit 300, and the arithmetic circuit 70. First, the configuration of the pixel 100 will be described. The photodiode 101 is a photoelectric conversion unit that converts incident light into electric charges. The transfer switch 102 transfers the charge converted by the photodiode 101 to the floating diffusion unit 103. The transfer switch 102 is controlled by a transfer pulse PTX. The floating diffusion portion (hereinafter referred to as FD) 103 accumulates charges. The amplification MOS transistor 104 functions as a source follower and amplifies the voltage of the FD 103. The reset switch 105 resets the FD 103. The reset switch 105 is controlled by a reset pulse PRES and resets the FD 103 by the power supply voltage VDD. The selection switch 106 connects the output node of the amplification MOS transistor 104 to the output line 107. The selection switch 106 is controlled by a selection pulse PSEL. The output line 107 is provided for each column of the plurality of pixels 100. The pixel 100 in each column is connected to the output line 107 in each column. The above is the configuration of the pixel 100. Note that if a local crystal defect or the like occurs in a region where the pixel 100 is formed on the substrate of the solid-state imaging device 2, the pixel 100 may be a defective pixel that does not output a normal pixel signal.

  The plurality of output lines 107 are connected to the plurality of column circuits 300, respectively. Each column output line 107 outputs the analog signal output from the pixel 100 to the column circuit 300. A constant current source 108 as a load is connected to each of the plurality of output lines 107.

  Next, the configuration of the column circuit 300 will be described. The amplifier 302 is an amplifying unit and amplifies the signal output from the pixel 100. The amplification degree of the amplifier 302 is determined by the ratio between the capacitors 301 and 303. The amplifier 302 amplifies the analog signal on the output line 107. The reset switch 304 is controlled by a reset pulse PC0R and resets the capacitors 301 and 303. The capacitor 306 holds the output signal of the amplifier 302. The sampling switch 305 connects the output node of the amplifier 302 to the capacitor 306. The sampling switch 305 is driven by a sampling pulse PSH.

  The capacitor 306 outputs an input signal Vpixel. The reference signal generation circuit 40 generates and outputs the reference signal Vramp in FIG. The analog-digital converter (AD converter) includes a comparator 307 and a counter 310. The comparator 307 is a comparator, compares the input signal Vpixel and the reference signal Vramp, and outputs a comparison result. For example, the comparator 307 outputs a high level when the voltage of the reference signal Vramp is higher than the voltage of the input signal Vpixel, and outputs a low level when the voltage of the reference signal Vramp is lower than the voltage of the input signal Vpixel. The input signal Vpixel is an analog signal held in the capacitor 306. The reference signal Vramp is a signal generated by the reference signal generation circuit 40. As shown in FIG. 4, the reference signal Vramp has a period of the ramp signal V1 in which the voltage level changes linearly with time and a period of the fixed signal (fixed voltage) Vj. The fixed signal Vj is a determination threshold value for determining the level of the input signal Vpixel. The fixed signal Vj can be set to an arbitrary signal value (voltage value) suitable for determining a defective pixel. The reference signal generation circuit 40 may switch the fixed voltage Vj according to the shooting conditions such as the setting mode, sensitivity, and exposure time, and the luminance of the subject.

  The counter 310 is provided corresponding to the comparator 307, and starts the counting operation when the generation of the ramp signal V1 is started. The counter 310 performs a counting operation in synchronization with the clock signal CLK having a fixed period generated by the clock generation circuit 50, and stops the counting operation when the output signal COMP of the comparator 307 is inverted from a high level to a low level. The AD converter converts the analog input signal Vpixel into a digital signal, and outputs the digital signal to the line memory 311 or 312. The count value after the stop of the counter 310 corresponds to the digital signal converted by the AD converter.

  The line memories 311 and 312 hold the count value of the counter 310 as a digital signal converted by the AD converter. The number of bits of the line memories 311 and 312 is set according to the resolution desired for the image signal, and is 14 bits, for example. The line memory 311 holds a 14-bit count value N by the counter 310 corresponding to the output level of the pixel 100 in a state where the FD 103 is reset by the reset switch 105. The line memory 312 holds a 14-bit count value S by the counter 310 corresponding to the output level of the pixel 100 in a state where charge transfer is performed from the photodiode 101 to the FD 103. The line memory 313 is a 1-bit memory having a smaller number of bits than the line memories 311 and 312, for example, and holds a determination value J indicating the result of level determination by the comparator 307. The horizontal scanning circuit 60 reads the count value held in the line memories 311 and 312 and the determination value J held in the line memory 313 by the horizontal scanning signal PH. The above is the configuration of the column circuit 300.

  Next, the configuration of the arithmetic circuit 70 will be described. The subtraction circuit 702 is a difference circuit, and outputs a difference SN between the count value S read from the line memory 312 and the count value N read from the line memory 311. The bit addition circuit 703 adds the determination value J read from the line memory 313 to the difference SN, and outputs the difference SN with the determination value J added to the signal processing circuit 3. The above is the configuration of the arithmetic circuit 70.

  FIG. 4 is a timing chart showing a method for driving the solid-state imaging device 2. Hereinafter, the pixel signal reading operation for one row will be described with reference to FIG. The solid-state imaging device 2 resets the values of the line memories 311, 312, and 313 to 0 at a timing (not shown) before performing the reading operation.

  At time T401, the vertical scanning circuit 20 sets the selection pulse PSEL to a high level. Then, the selection switch 106 is turned on, and the output node of the amplification MOS transistor 104 is connected to the output line 107.

  At time T402, the vertical scanning circuit 20 sets the reset pulse PRES to low level. Then, the reset switch 105 is turned off and the reset of the FD 103 is released.

  At time T403, the reset pulse PC0R becomes low level. Then, the reset switch 304 is turned off, and the reset of the amplifier 302 and the capacitors 301 and 303 is released.

  At time T404, the sampling pulse PSH becomes high level. Then, the sampling switch 305 is turned on. The amplification MOS transistor 104 outputs a signal based on the reset release of the FD 103 to the output line 107. The amplifier 302 outputs a signal Vn obtained by amplifying a signal based on reset cancellation of the output line 107 to the capacitor 306.

  At time T405, the sampling pulse PSH becomes low level. Then, the sampling switch 305 is turned off, and the capacitor 306 holds the signal Vn and outputs the signal Vn as the input signal Vpixel.

  In the period from time T406 to T408, the reference signal generation circuit 40 generates the ramp signal V1 as the reference signal Vramp. The comparator 307 compares the signal Vn with the ramp signal V1. The comparator 307 outputs a high level comparison result signal COMP when the ramp signal V1 is higher than the signal Vn, and outputs a low level comparison result signal COMP when the ramp signal V1 is lower than the signal Vn.

  At time T406, the clock generation circuit 50 starts supplying the clock signal CLK to the counter 310, and the counter 310 starts a count value counting operation. At time T407, the voltage of the ramp signal V1 becomes lower than the voltage of the signal Vn, the comparison result signal COMP is inverted from the high level to the low level, and the counter 310 stops the count value counting operation.

  At time T408, the line memory 311 holds the count value N of the counter 310. Thereafter, the count value of the counter 310 is reset.

  At time T409, the vertical scanning circuit 20 sets the transfer pulse PTX to high level, and the sampling pulse PSH becomes high level. Then, the transfer switch 102 is turned on and the sampling switch 305 is turned on. In the exposure period, the photodiode 101 converts light into electric charge and accumulates the electric charge. When the transfer pulse PTX becomes high level, the transfer switch 102 transfers the charge of the photodiode 101 to the FD 103.

  At time T410, the vertical scanning circuit 20 sets the transfer pulse PTX to low level. Then, the transfer switch 102 ends the charge transfer from the photodiode 101 to the FD 103. The amplification MOS transistor 104 outputs a signal based on the charge of the FD 103 to the output line 107. That is, the amplification MOS transistor 104 outputs a signal based on the photoelectric conversion of the photodiode 101 to the output line 107. The amplifier 302 outputs a signal Vs obtained by amplifying the signal on the output line 107 to the capacitor 306.

  At time T411, the sampling pulse PSH becomes low level. Then, the sampling switch 305 is turned off, the capacitor 306 holds the signal Vs, and outputs the signal Vs as the input signal Vpixel.

  In the period from time T412 to T414, the reference signal generation circuit 40 generates the ramp signal V1 as the reference signal Vramp. The comparator 307 compares the signal Vs with the ramp signal V1. The comparator 307 outputs a high-level comparison result signal COMP when the ramp signal V1 is higher than the signal Vs, and the low-level comparison result signal COMP when the ramp signal V1 is lower than the signal Vs. Is output.

  At time T412, the clock generation circuit 50 starts supplying the clock signal CLK to the counter 310, and the counter 310 starts counting operation of the count value. Further, the vertical scanning circuit 20 sets the selection pulse PSEL to a low level, the selection switch 106 is turned off, and the output node of the amplification MOS transistor 104 and the output line 107 are disconnected. Further, the reset pulse PC0R becomes high level, the reset switch 304 is turned on, and the amplifier 302 and the capacitors 301 and 303 are reset.

  At time T413, the voltage of the ramp signal V1 becomes lower than the voltage of the signal Vs, the comparison result signal COMP is inverted from the high level to the low level, and the counter 310 stops the count value counting operation.

  At time T414, the line memory 312 holds the count value S of the counter 310. Thereafter, before the time T415, the count value of the counter 310 is reset.

  In the period from time T415 to T417, the reference signal generation circuit 40 generates the fixed signal Vj as the reference signal Vramp. The comparator 307 compares the signal Vs with the fixed signal Vj. The comparator 307 outputs a high level comparison result signal COMP when the voltage of the signal Vs is lower than the voltage of the fixed signal Vj, and compares it at a low level when the voltage of the signal Vs is equal to or higher than the voltage of the fixed signal Vj. The result signal COMP is output.

  At time T416, the line memory 313 holds the comparison result signal COMP of the comparator 307 as the level determination value J. When the voltage of the signal Vs is lower than the voltage of the fixed signal Vj, the signal Vs is a high luminance signal, and the comparison result signal COMP and the determination value J are at a high level “1”. When the voltage of the signal Vs is equal to or higher than the voltage of the fixed signal Vj, the signal Vs is a low luminance signal, and the comparison result signal COMP and the determination value J are at the low level “0”. At time T417, the reference signal generation circuit 40 resets the reference signal Vramp.

  Note that the level determination operation from time T415 to time T417 may be performed from time T410 to time T412 after the charge transfer from the photodiode 101 to the FD 103 is completed.

  At time T418, the horizontal scanning circuit 60 starts supplying the horizontal scanning signal PH. Then, the line memory 311 outputs the count value N, the line memory 312 outputs the count value S, and the line memory 313 outputs the determination value J. The subtraction circuit 702 subtracts the count value N from the count value S and outputs a subtraction value SN. The bit addition circuit 703 adds a 1-bit judgment value J to the subtraction value SN input from the subtraction circuit 702 and outputs the result. The subtraction value SN is pixel data. The above is the reading operation of the pixel signals for one row. This is repeated for the desired number of rows, and image data for one frame is read out.

  As described above, a method for detecting a defective pixel using the image data read from the solid-state imaging device 2 will be described with reference to FIGS. The overall control / arithmetic circuit 4 writes the image data and the determination value J input from the solid-state imaging device 2 into the memory circuit 6 via the signal processing circuit 3. Then, the overall control / arithmetic circuit 4 compares the determination value J of the area of the wide range of pixels 100 and detects the pixel 100 with the determination value J isolated from the surrounding pixels 100 as a defective pixel.

  FIGS. 5A to 5D are schematic diagrams illustrating image data read from the solid-state imaging device 2. FIG. 5A shows image data separated for each color and a luminance signal of image data for one color as an image. 5B, 5C, and 5D show determination values J of pixel data corresponding to a part of the image data shown in FIG. FIG. 5B shows the determination value J of the image data corresponding to the area 1001 in FIG. FIG. 5C shows the determination value J of the image data corresponding to the area 1002 in FIG. FIG. 5D shows the determination value J of the image data corresponding to the area 1003 in FIG. The sizes of the regions 1001 to 1003 are the sizes of the comparison regions used for comparison for detecting defective pixels, respectively. In the example of FIGS. 5B to 5D, the areas 1001 to 1003 are areas around the horizontal X = 11 pixels and the vertical Y = 11 pixels centered on the target pixel, but the number of pixels is limited to this. Not. The regions 1001 to 1003 may be pixel regions around the target pixel having the same color as the target pixel. Focusing on the pixels indicated by diagonal lines in each of the areas 1001 to 1003, a method for detecting a defective pixel when each of the areas 1001 to 1003 is used as a comparison area for detecting defective pixels will be described.

  FIG. 6 is a flowchart illustrating a method for detecting a defective pixel of the imaging apparatus 11. In step S1, the overall control / arithmetic circuit 4 acquires the determination value J of the pixel in the comparison area centered on the pixel of interest from the memory circuit 6, and proceeds to step S2.

  In step S <b> 2, the overall control / arithmetic circuit 4 determines whether or not the determination value J of the pixel of interest is 1. The overall control / arithmetic circuit 4 proceeds to step S3 if the determination value J is 1, and proceeds to step S4 if the determination value J is 0.

  In step S3, the overall control / arithmetic circuit 4 counts the number J1 of pixels in which the determination value J is 1 in the pixels in the comparison area, and proceeds to step S5. In step S5, the overall control / arithmetic circuit 4 determines whether or not the number of pixels J1 having the determination value J of 1 is less than the threshold value D1. The overall control / arithmetic circuit 4 proceeds to step S7 when the pixel number J1 is less than the threshold value D1, and proceeds to step S8 when the pixel number J1 is equal to or greater than the threshold value D1.

  In step S7, the overall control / arithmetic circuit 4 determines that the pixel of interest is a defective pixel, sets the correction flag C of the pixel of interest to 1, and writes the correction flag C to the memory circuit 6. In step S8, the overall control / arithmetic circuit 4 determines that the target pixel is not a defective pixel, sets the correction flag C of the target pixel to 0, and writes the correction flag C in the memory circuit 6.

  In step S4, the overall control / arithmetic circuit 4 counts the number J0 of pixels in which the determination value J is 0 in the pixels in the comparison area, and proceeds to step S6. In step S6, the overall control / arithmetic circuit 4 determines whether or not the number of pixels J0 having the determination value J of 0 is less than the threshold value D2. The overall control / arithmetic circuit 4 proceeds to step S9 when the pixel number J0 is less than the threshold value D2, and proceeds to step S10 when the pixel number J0 is equal to or greater than the threshold value D2.

  In step S9, the overall control / arithmetic circuit 4 determines that the pixel of interest is a defective pixel, sets the correction flag C of the pixel of interest to 1, and writes the correction flag C to the memory circuit 6. In step S <b> 10, the overall control / arithmetic circuit 4 determines that the target pixel is not a defective pixel, sets the correction flag C of the target pixel to 0, and writes the correction flag C in the memory circuit 6.

  The above is the defective pixel detection method of the imaging device 11. The case where this defective pixel detection method is applied to the areas 1001, 1002, and 1003 in FIGS. 5B to 5D will be described. For example, the threshold values D1 and D2 are 2. In FIG. 5B, the determination value J of the target pixel in the region 1001 is 1, and the region 1001 includes two or more pixels having the determination value J of 1. Therefore, the target pixel is determined not to be a defective pixel. The correction flag C becomes 0. In FIG. 5C, the determination value J of the target pixel in the region 1002 is 1, and since the region 1002 does not include a pixel having the determination value J other than the target pixel, the target pixel is a defective pixel. And the correction flag C becomes 1. In FIG. 5D, the determination value J of the target pixel in the region 1003 is 0, and the region 1003 does not include any pixel having the determination value J of 0 other than the target pixel. Therefore, the target pixel is a defective pixel. And the correction flag C becomes 1.

  The overall control / arithmetic circuit 4 is a defect detection unit, and when the number of determination values that are the same as the determination value J of the target pixel among the determination values J of the pixels in the regions 1001 to 1003 is less than the threshold value, It is detected as a defective pixel.

  The above defective pixel detection method is applied to each pixel of one frame of image data to detect defective pixels in the entire image data. The threshold values D1 and D2 may be different values. The threshold values D1 and D2 may be varied according to the setting of the imaging device 11 such as the charge accumulation time, sensitivity, and shooting mode.

  As described above, since the overall control / arithmetic circuit 4 detects a defective pixel using the determination value J obtained inside the solid-state imaging device 2, a binary calculation for determining the level of the luminance signal, a plurality of pixels There is no need to perform an average calculation of the luminance signal and a difference calculation with the luminance signal of the pixel of interest. In other words, the overall control / arithmetic circuit 4 does not need to include an arithmetic circuit for performing an averaging calculation and a difference calculation as in the prior art. Further, since the comparator 307 inside the solid-state imaging device 2 calculates the determination value J, it is not necessary to add a binarization arithmetic circuit. Furthermore, since complicated calculations such as average calculation and difference calculation of multi-bit luminance signals are not required, the number of pixels used for detection of defective pixels can be easily increased as compared with conventional real-time defect correction.

  Therefore, according to the present embodiment, it is possible to enlarge the comparison area of the pixel signal used for defective pixel detection while reducing the scale of the arithmetic circuit necessary for defective pixel detection provided in the overall control / arithmetic circuit 4. It is possible to improve pixel detection accuracy.

  The comparator 307 compares the signal Vs with the fixed signal Vj. The determination value is determined based on the comparison result of the comparator 307. Therefore, the solid-state imaging device 2 may improve the detection accuracy of the defective pixel by performing level determination a plurality of times while detecting the defective pixel while switching the level of the fixed signal Vj. Note that the amount of light incident on each pixel 100 varies depending on the color of the subject, the type of light source, and the type of color filter provided on each pixel, and therefore depends on the color of light transmitted through the color filter of each pixel 100. Thus, the level of the fixed signal Vj may be varied. Further, the detection accuracy of defective pixels may be improved by using a plurality of types of defective pixel detection operations in combination. For example, the defective pixel detection method according to the present embodiment may be used in combination with the real-time defective pixel detection method such as comparing luminance signals of adjacent pixels of the same color to perform two types of defective pixel detection operations. In the case of a defective pixel candidate detected by the real-time defect detection method, if the defective pixel candidate and its adjacent pixel of the same color include both of the determination values J = 0 and J = 1, the defect according to the present embodiment Apply the pixel detection method. On the other hand, a pixel for which the correction flag C is determined to be 0 may be excluded from the defective pixel determination. As described above, the defective pixel detection method of the present embodiment using a wide range of pixel signals and a known defective pixel detection method are used to detect a plurality of types of defective pixels. As a result, the overall control / arithmetic circuit 4 can improve the detection accuracy of defective pixels, although it is necessary to provide an arithmetic circuit that performs an average calculation or a difference calculation.

  The overall control / arithmetic circuit 4 is a difference correction unit that corrects the pixel signal (difference) SN of the defective pixel having the correction flag C of 1 by interpolating with the average value of the signals of adjacent pixels of the same color. Then, the corrected image data is recorded in the recording circuit 7. The overall control / arithmetic circuit 4 may discard the information of the determination value J after correcting the defective pixel data.

  According to this embodiment, the solid-state imaging device 2 obtains the determination value J by comparing the input signal Vs and the fixed signal Vj. The overall control / arithmetic circuit 4 detects a defective pixel using the determination value J. As a result, the overall control / arithmetic circuit 4 can reduce the calculation for performing defect detection. In addition, the overall control / arithmetic circuit 4 can increase the number of pixels in the comparison region used for defect detection and improve the detection accuracy of the defective pixels.

(Second Embodiment)
FIG. 7 is an equivalent circuit diagram showing a configuration example of the pixel 100, the column circuit 300a, and the arithmetic circuit 70a according to the second embodiment of the present invention. FIG. 7 is different from FIG. 3 in that a reference signal generation circuit 40a, a column circuit 300a, and an arithmetic circuit 70a are provided instead of the reference signal generation circuit 40, the column circuit 300, and the arithmetic circuit 70. In the column circuit 300a, selection switches 308 and 309 and a pulse generation circuit 314 are added to the column circuit 300 of FIG. In the arithmetic circuit 70a, a bit shift circuit 701 is added to the arithmetic circuit 70 of FIG. Hereinafter, the points of the present embodiment different from the first embodiment will be described.

  The line memories 311 and 312 are each a 13-bit memory, for example. The line memory 311 holds a 13-bit count value N by the counter 310. The line memory 312 holds a 13-bit count value S from the counter 310. The pulse generation circuit 314 generates the selection pulse PRAMP based on the determination value J held in the line memory 313. The pulse generation circuit 314 generates a low level selection pulse PRAMP when the determination value J is 0, and generates a high level selection pulse PRAMP when the determination value J is 1. The pulse generation circuit 314 supplies the selection pulse PRAMP to the selection switches 308 and 309.

  The reference signal generation circuit 40a outputs the ramp signals V1 and V2 as the reference signal Vramp. When the selection pulse PRAMP is at a low level, the selection switch 308 is turned on, the selection switch 309 is turned off, and the comparator 307 compares the ramp signal V1 with the input signal Vpixel. When the selection pulse PRAMP is at a high level, the selection switch 308 is turned off, the selection switch 309 is turned on, and the comparator 307 compares the ramp signal V2 with the input signal Vpixel.

  The reference signal generation circuit 40a generates, as the reference signal Vramp, ramp signals V1 and V2 whose voltage levels change linearly with time, and a fixed signal Vj. As shown in FIG. 8, the ramp signal V2 has a different slope from the ramp signal V1. The ramp signal V1 has a smaller slope than the ramp signal V2. For example, the slope of the ramp signal V2 is twice that of the ramp signal V1. When the input signal Vpixel has a luminance lower than the threshold value, the AD converter can perform high-precision AD conversion on the low-luminance input signal Vpixel by selecting the ramp signal V1. When the input signal Vpixel has a luminance higher than the threshold value, the AD converter can perform high-speed AD conversion on the high luminance input signal Vpixel by selecting the ramp signal V2. Specifically, when the ramp signal V2 is selected, the AD conversion speed is doubled.

  When the determination value J of the memory 313 is 0, the pulse generation circuit 314 has a low level selection pulse PRAMP because the voltage of the signal Vs is equal to or higher than the voltage of the fixed signal Vj and the signal Vs is a low luminance signal. Is output. Then, the selection switch 308 is turned on, and the comparator 307 compares the ramp signal V1 with the signal Vs. Thereby, highly accurate AD conversion can be performed.

  When the determination value J of the memory 313 is 1, the pulse generation circuit 314 has a high-level selection pulse because the voltage of the signal Vs is lower than the voltage of the fixed signal Vj and the signal Vs is a high luminance signal. Outputs PRAMP. Then, the selection switch 309 is turned on, and the comparator 307 compares the ramp signal V2 with the signal Vs. Thereby, high-speed AD conversion can be performed.

  The bit shift circuit 701 bit shifts the 13-bit count value S of the line memory 312 based on the determination value J of the line memory 313. When the determination value J is 1, the bit shift circuit 701 performs a bit shift that adds a predetermined number of bits (eg, 1 bit) of 0 to the 13-bit count value S of the line memory 312. And output to the subtraction circuit 702 as a 14-bit signal S. By adding 1 bit to the lower order, the signal S can be doubled. Further, when the determination value J is 0, the bit shift circuit 701 adds a predetermined number of bits (for example, 1 bit) of 0 to the 13-bit count value S of the line memory 312. Shifting is performed, and a 14-bit signal S is output to the subtraction circuit 702. By adding 1 bit to the upper order, the signal S can be doubled. Thereby, the signal S can be corrected according to the difference in slope between the ramp signals V1 and V2. Further, the bit shift circuit 701 performs a bit shift to add a 0 bit of a predetermined number of bits (for example, 1 bit) to the 13-bit count value N of the line memory 311 as a 14-bit signal N. The result is output to the subtraction circuit 702. The bit shift circuit 701 is a count value correction unit, and corrects the count value S of the line memory 312 according to the slope of the reference signal Vramp (ramp signal V1 or V2).

  The subtraction circuit 702 outputs a difference SN between the 14-bit count value S and the 14-bit count value N. The bit addition circuit 703 adds the determination value J read from the line memory 313 to the difference SN, and outputs the difference SN with the determination value J added to the signal processing circuit 3.

  As described above, the comparator 307 determines whether or not the voltage of the signal Vs is lower than the voltage of the fixed signal Vj before performing AD conversion of the signal Vs. The line memory 313 holds this determination result as a determination value J. The selection switches 308 and 309 select the ramp signal V2 having a large slope when the voltage of the signal Vs is lower than the voltage of the fixed signal Vj, and when the voltage of the signal Vs is equal to or higher than the voltage of the fixed signal Vj, A ramp signal V1 having a small inclination is selected. The comparator 307 compares the signal Vs with the ramp signal V1 or V2, and performs AD conversion.

  FIG. 8 is a timing chart showing a method for driving the solid-state imaging device 2. Hereinafter, the points of FIG. 8 different from FIG. 4 will be described. The operations at times T401 to T408 are the same as the operations in FIG. The initial value of the memory 313 is 0, and the pulse generation circuit 314 outputs a low level selection pulse PRAMP.

  At time T409, the vertical scanning circuit 20 sets the transfer pulse PTX to high level. Then, the transfer switch 102 transfers the charge of the photodiode 101 to the FD 103. At time T409, the sampling pulse PSH goes high and the sampling switch 305 is turned on. The amplification MOS transistor 104 outputs a signal based on the charge of the FD 103 to the output line 107. The amplifier 302 outputs a signal Vs obtained by amplifying the signal on the output line 107 to the capacitor 306.

  At time T410, the vertical scanning circuit 20 sets the transfer pulse PTX to low level. Then, the transfer switch 102 ends the charge transfer from the photodiode 101 to the FD 103.

  At time T411, the sampling pulse PSH becomes low level, and the sampling switch 305 is turned off. The capacitor 306 holds the signal Vs output from the amplifier 302.

  At time T412a, the reference signal generation circuit 40 outputs the fixed signal Vj to the selection switch 308 as the reference signal Vramp. Since the selection pulse PRAMP is at a low level, the selection switch 308 outputs the fixed signal Vj to the comparator 307. The comparator 307 compares the signal Vs held in the capacitor 306 with the fixed signal Vj. The comparator 307 outputs a high-level comparison result signal COMP when the voltage of the signal Vs is lower than the voltage of the fixed signal Vj, and low level when the voltage of the signal Vs is equal to or higher than the voltage of the fixed signal Vj. The comparison result signal COMP is output.

  At time T412a, the vertical scanning circuit 20 sets the selection pulse PSEL to a low level. Then, the selection switch 106 is turned off, and the output node of the amplification MOS transistor 104 and the output line 107 are disconnected. Further, the reset pulse PC0R becomes high level, the reset switch 304 is turned on, and the amplifier 302 and the capacitors 301 and 303 are reset.

  At time T413a, the line memory 313 holds the comparison result signal COMP value of the comparator 307 as the determination value J. The determination value J is 1 when the comparison result signal COMP is at a high level, and is 0 when the comparison result signal COMP is at a low level. The pulse generation circuit 314 outputs a high-level selection pulse PRAMP when the determination value J is 1, and outputs a low-level selection pulse PRAMP when the determination value J is 0. When the selection pulse PRAMP is at a low level, the selection switch 308 is turned on and the selection switch 309 is turned off. When the selection pulse PRAMP is at a high level, the selection switch 308 is turned off and the selection switch 309 is turned on.

  Note that since the comparator 307 performs a low-resolution determination as to whether or not the voltage of the signal Vs is lower than the voltage of the fixed signal Vj, high-precision determination such as signal level AD conversion is not necessarily required. Therefore, the determination value J of the line memory 313 may be determined without waiting for the voltage fluctuation of the signal Vs to settle.

  At time T414a, the reference signal generation circuit 40a resets the ramp signals V1 and V2. At times T415a to T417a, the reference signal generation circuit 40a generates a ramp signal V1 having a small inclination and a ramp signal V2 having a large inclination. When the selection pulse PRAMP is at a low level, the comparator 307 compares the signal Vs with the ramp signal V1. When the selection pulse PRAMP is at a high level, the comparator 307 compares the signal Vs with the ramp signal V2.

  At time T415a, the clock generation circuit 50 starts supplying the clock signal CLK to the counter 310. Then, the counter 310 starts a count value counting operation.

  For example, when the selection pulse PRAMP is at a high level, the comparator 307 compares the signal Vs with the ramp signal V2. At time T416a, the voltage of the signal Vs becomes equal to or higher than the voltage of the ramp signal V2, and the comparator 307 inverts the comparison result signal COMP from the high level to the low level. Similarly, when the selection pulse PRAMP is at a low level, when the voltage of the signal Vs becomes equal to or higher than the voltage of the ramp signal V1, the comparator 307 inverts the comparison result signal COMP from the high level to the low level. When the comparison result signal COMP changes from the high level to the low level, the counter 310 stops the count value counting operation.

  At time T417a, the line memory 312 holds the count value S of the counter 310. Thereafter, until the time T418, the count value of the counter 310 is reset.

  At time T418, the horizontal scanning circuit 60 starts supplying the horizontal scanning signal PH. Then, the line memory 311 outputs the count value N, the line memory 312 outputs the count value S, and the line memory 313 outputs the determination value J. The bit shift circuit 701 adds 1 bit of 0 to the higher order to the 13-bit count value N of the line memory 311 and outputs it to the subtraction circuit 702 as a 14-bit signal N. Further, when the judgment value J is 1, the bit shift circuit 701 adds 1 bit of 0 to the lower order to the 13-bit count value S of the line memory 312 and subtracts it as a 14-bit signal S. Output to the circuit 702. Further, when the determination value J is 0, the bit shift circuit 701 performs a bit shift by adding 1 bit of 0 to the higher order with respect to the 13-bit count value S of the line memory 312, and 14 bits The signal S is output to the subtraction circuit 702. The subtraction circuit 702 subtracts the 14-bit count value N from the 14-bit count value S, and outputs a subtraction value SN. The bit addition circuit 703 adds a 1-bit judgment value J to the subtraction value SN input from the subtraction circuit 702 and outputs the result. The above is the reading operation of the pixel signals for one row. This is repeated for the desired number of rows, and image data for one frame is read out.

(Third embodiment)
FIG. 9 is a block diagram illustrating a configuration example of the solid-state imaging device 2 excluding the pixel unit 10 and the vertical scanning circuit 20 according to the third embodiment of the present invention. Hereinafter, the points of FIG. 9 different from FIG. 3 will be described. The column circuit 300b is provided instead of the column circuit 300 in FIG. The arithmetic circuit 70b is provided instead of the arithmetic circuit 70 in FIG. The solid-state imaging device 2 further includes a defect detection unit 80.

  In the column circuit 300b, the line memory 313b is provided instead of the line memory 313 in FIG. The line memory 313 b outputs the determination value J to the defect detection unit 80 instead of outputting the determination value J to the bit addition circuit 703. The defect detection unit 80 detects defective pixels based on the determination value J by the same processing as in FIG. 6, generates a correction flag C, and outputs the correction flag C to the signal processing circuit 3. The arithmetic circuit 70b has a subtracting circuit 702 from which the bit adding circuit 703 in FIG. The subtraction circuit 702 subtracts the count value N of the line memory 311 from the count value S of the line memory 312 and outputs the subtraction value S−N to the signal processing circuit 3 as a pixel signal.

  FIG. 10 is a block diagram illustrating a configuration example of the line memory 313b of FIG. The line memory 313b is a memory having the number of bits corresponding to the number of rows in the pixel area used by the defect detection unit 80. For example, the line memory 313b is 11 line memories, and holds a determination value J of 11 × 11 pixels, for example, as shown in FIGS. When the pixel signal of the n-th row is read, determination values J_n, J_n-1,..., J_n-10 from the n-10th row to the nth row are stored in the line memory 313b. The defect detection unit 80 performs defective pixel detection using the determination values J_n, J_n−1,. C is output separately from the difference signal S-N as defect information of the pixels in the n-5th row. The defective pixel detection method is the same as the method described with reference to FIGS. 5 and 6 of the first embodiment.

  When known real-time flaw detection is performed inside the solid-state imaging device 2, it is necessary to provide a line memory of the number of rows × 14 bits used for defective pixel detection inside the solid-state imaging device 2. On the other hand, in the present embodiment, the line memory 313b having the number of rows × 1 bit used in the defect detection unit 80 may be provided inside the solid-state imaging device 2, and the necessary line memory compared with the known real-time scratch detection. Can be reduced.

  In the present embodiment, since the defect detection unit 80 detects defective pixels inside the solid-state imaging device 2, the overall control / arithmetic circuit 4 does not detect defective pixels using the determination value J. Therefore, the determination value J is not output to the outside of the solid-state image sensor 2, and the solid-state image sensor 2 outputs a correction flag C as a detection result of the defective pixel. Further, the overall control / arithmetic circuit 4 does not need to be provided with a detection circuit for detecting defective pixels. The overall control / arithmetic circuit 4 is a difference correction unit, and when the correction flag C output from the solid-state imaging device 2 is 1, since the target pixel is a defective pixel, the pixel signal (difference) S− of the target pixel. N is corrected. As a method for correcting a pixel signal of a defective pixel, a known defect correction method may be used, such as complementing with an average value of signals of adjacent pixels of the same color. Moreover, this embodiment can also be applied to the second embodiment.

  As described above, the defect detection unit 80 detects a defective pixel inside the solid-state image sensor 2 using the determination value J generated inside the solid-state image sensor 2. Therefore, in this embodiment, the defect detection circuit can be reduced from the overall control / arithmetic circuit 4.

(Fourth embodiment)
FIG. 11A is a block diagram illustrating a configuration example of the solid-state imaging device 2 according to the fourth embodiment of the present invention. The solid-state imaging device 2 is configured by a stacked structure including a plurality of substrates 1101 to 1103. For example, the solid-state imaging device 2 is a stacked solid-state imaging device including three layers of first to third substrates 1101 to 1103. Hereinafter, differences of the present embodiment from the third embodiment will be described.

  FIG. 11B is a block diagram illustrating a configuration example of the first to third substrates 1101 to 1103. The first substrate 1101 includes a pixel unit 10 and a pixel driving unit 21 that drives the pixel unit 10. The pixel unit 10 includes a plurality of pixels 100 arranged in a two-dimensional matrix. The pixel drive unit 21 corresponds to the vertical scanning circuit 20 in FIG. 2 and supplies a control signal to each pixel 100 of the pixel unit 10.

  The second substrate 1102 includes a read circuit unit 31, a reference signal generation circuit 40, and a clock generation circuit 50. The read circuit unit 31 corresponds to the column circuit unit 30 in FIG. 2 and includes a plurality of column circuits 300b. Each of the plurality of column circuits 300b performs level determination and AD conversion of the analog signal from the corresponding pixel 100, and holds the count values S and N and the determination value J.

  The third substrate 1103 includes a control unit 61, an arithmetic circuit 71, a defect detection unit 80, and an output unit 90. The control unit 61 generates control signals for the reference signal generation circuit 40 and the clock generation circuit 50, and controls level determination and AD conversion operation in the read circuit unit 31. The control unit 61 corresponds to the horizontal scanning circuit 60 in FIG. 2, generates a control signal for the readout circuit unit 31, and transfers the count values S and N and the determination value J from the readout circuit unit 31 to the arithmetic circuit 71. And the transfer of the determination value J from the readout circuit unit 31 to the defect detection unit 80 is controlled. The defect detection unit 80 detects a defective pixel using the determination value J transferred from the readout circuit unit 31. The method for detecting defective pixels is the same as the method described with reference to FIGS. The defect detection unit 80 outputs the detection result to the arithmetic circuit 71.

  The arithmetic circuit 71 corresponds to the arithmetic circuit 70b of FIG. 9 and performs a subtraction process on the count values S and N output from the readout circuit unit 31 to obtain a pixel signal SN. The arithmetic circuit 71 has a correction circuit 711. The correction circuit 711 is a difference correction circuit, and when the correction flag C output from the defect detection unit 80 is 1, since the target pixel is a defective pixel, the pixel signal (difference) SN of the target pixel. Is corrected and output. On the other hand, when the correction flag C output from the defect detection unit 80 is 0, the correction circuit 711 outputs the pixel signal SN of the target pixel because the target pixel is not a defective pixel. The correction method of the pixel signal of the defective pixel is, for example, a method of interpolating with an average value of signals of adjacent pixels of the same color. The output unit 90 outputs the pixel signal output from the arithmetic circuit 71 from the solid-state imaging device 2.

  In the present embodiment, the defect detection unit 80 detects a defective pixel inside the solid-state imaging device 2, and the correction circuit 711 corrects the defective pixel. The overall control / arithmetic circuit 4 does not detect and correct defective pixels using the determination value J. Therefore, the determination value J does not have to be output to the outside of the solid-state image sensor 2. Further, it is not necessary to provide the overall control / arithmetic circuit 4 with a detection circuit for detecting defective pixels and a correction circuit for correcting defective pixels.

  According to the present embodiment, the defect detection unit 80 and the correction circuit 711 detect and detect a defective pixel inside the solid-state imaging device 2 using the determination value J obtained inside the solid-state imaging device. The defective pixel is corrected. Therefore, the overall control / arithmetic circuit 4 can reduce the defect detection circuit and the defect correction circuit.

  As mentioned above, although preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary. The imaging device 11 can be applied to a smartphone, a tablet, an industrial camera, a medical camera, and the like in addition to a digital camera and a video camera.

2 solid-state imaging device, 4 overall control / arithmetic circuit, 100 pixels, 101 photodiode, 307 comparator, 310 counter

Claims (14)

A pixel that outputs a signal based on photoelectric conversion;
In the first period, the signal based on the photoelectric conversion is compared with the first reference signal whose level changes with time, and in the second period, the signal based on the photoelectric conversion is compared with the fixed signal. A comparator;
In the first period, a counter that counts a first count value according to a comparison result of the comparator;
A first memory for holding a first count value of the counter;
A solid-state imaging device comprising: a second memory that holds a value indicating a comparison result of the comparator in the second period. The pixel outputs a signal based on reset cancellation in the third period,
In the third period, the comparator compares the signal based on the reset release with a second reference signal whose level changes with time,
The counter counts a second count value according to the comparison result of the comparator in the third period,
The solid-state imaging device according to claim 1, further comprising a third memory that holds a second count value of the counter.   The difference means for outputting the difference between the first count value held in the first memory and the second count value held in the third memory is further provided. The solid-state imaging device described.   The solid-state imaging device according to claim 3, further comprising an adding unit that adds a value held in the second memory to the difference output by the difference unit. The first period is a period after the second period;
5. The solid-state imaging device according to claim 1, wherein the first reference signal has a different slope according to a value held in the second memory.   The first reference signal has a first slope when the signal based on the photoelectric conversion has a higher luminance than the first threshold, and the signal based on the photoelectric conversion has a lower luminance than the first threshold. The solid-state imaging device according to claim 5, wherein in some cases, the second inclination is smaller than the first inclination.   The count value correcting means for correcting the first count value held in the first memory in accordance with the slope of the first reference signal. Solid-state image sensor.   The defect detection unit for detecting whether or not the pixel is a defective pixel based on a value held in the second memory, according to any one of claims 1 to 7, The solid-state imaging device described. The pixels are a plurality of pixels arranged in a matrix,
The defect detection means has the same number of values as the values held in the second memory for the pixel of interest among the values held in the second memory for pixels around the pixel of interest. The solid-state imaging device according to claim 8, wherein the pixel of interest is detected as a defective pixel when the threshold is less than 2.   The defect detection means includes: a value held in the second memory for the pixel of interest among values held in the second memory for pixels around the pixel of interest of the same color as the pixel of interest; 10. The solid-state imaging device according to claim 8, wherein when the number of the same values is smaller than a second threshold, the target pixel is detected as a defective pixel. Defect detection means for detecting whether or not the pixel is a defective pixel based on a value held in the second memory;
The solid-state imaging device according to claim 3, further comprising a difference correction unit that corrects a difference output by the difference unit for the defective pixel detected by the defect detection unit. A solid-state imaging device according to any one of claims 1 to 7,
An image pickup apparatus comprising: defect detection means for detecting whether or not the pixel is a defective pixel based on a value held in the second memory of the solid-state image pickup element. A solid-state imaging device according to claim 3;
Defect detection means for detecting whether or not the pixel is a defective pixel based on a value held in the second memory of the solid-state imaging device;
An image pickup apparatus comprising: a difference correction unit that corrects a difference output by the difference unit of the solid-state image sensor for the defective pixel detected by the defect detection unit. Outputting a signal based on photoelectric conversion by a pixel;
In the first period, the comparator compares the signal based on the photoelectric conversion with the first reference signal whose level changes with time, and in the second period, the signal based on the photoelectric conversion and the fixed signal And a step of comparing
Counting a first count value according to a comparison result of the comparator in the first period by a counter; and
Holding a first count value of the counter by a first memory;
And a step of holding a value indicating a comparison result of the comparator in the second period by a second memory.

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