JP2019178066A - METHOD OF MANUFACTURING n-TYPE SILICON SINGLE CRYSTAL INGOT, METHOD OF MANUFACTURING n-TYPE SILICON WAFER, AND n-TYPE SILICON WAFER - Google Patents

Abstract

To provide a method of manufacturing an n-type silicon single crystal in which variance in in-plane resistance of an n-type silicon wafer whose plane orientation is (111) can be suppressed and the n-type silicon wafer can be obtained in a high yield.SOLUTION: A method of manufacturing an n-type silicon single crystal ingot comprises a lifting process of an n-type silicon single crystal ingot 6 whose crystal orientation is <111> from a dopant added melt 41 prepared by adding a dopant to a silicon melt by a Czochralski method in which a magnetic field is not applied, the n-type silicon single crystal ingot 6 being lifted in the lifting process so that a solid-liquid boundary surface S between the n-type silicon single crystal ingot 6 being lifted and the dopant-added melt 41 is downward convex. The lifting process includes lifting the n-type silicon single crystal ingot 6 at a lifting rate of 0.35-0.45 m/min so that the solid-liquid boundary surface between the n-type silicon single crystal ingot 6 being lifted and the dopant-added melt 4 is downward convex.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a method for manufacturing an n-type silicon single crystal ingot, a method for manufacturing an n-type silicon wafer, and an n-type silicon wafer.

  For the manufacture of a Zener diode, an n-type silicon wafer doped with a dopant at a high concentration is used. As such an n-type silicon wafer, one having a (111) plane orientation is usually used in order to maintain the lattice uniformity of the crystal due to the high concentration diffusion of the dopant.

One of the characteristics of a Zener diode is that the operating voltage division is finely divided and the individual operating voltage range is very narrow. In order to manufacture a Zener diode having such characteristics with a high yield, it is necessary to suppress variations in in-plane resistance of one n-type silicon wafer.
However, an n-type silicon wafer having a (111) plane orientation has a problem that it is difficult to make the in-plane resistance distribution uniform.

On the other hand, in a silicon wafer having a (100) plane orientation, a technique for increasing the number of crystal rotations when pulling up a silicon single crystal ingot is known for the purpose of improving variation in in-plane resistance.
Therefore, it is conceivable to improve the in-plane resistance variation by applying the technique of the silicon single crystal ingot having a crystal orientation of <100> to the pulling of the silicon single crystal ingot of <111>.
However, when the silicon single crystal ingot with a crystal orientation of <111> is pulled, the in-plane resistance variation can be improved to a certain level by making the crystal rotation speed higher than usual. It is impossible to achieve in-plane resistance variation at a level that satisfies the required level from
In order to satisfy the demand level from the semiconductor device manufacturer, it is necessary to make the crystal rotation speed higher, but since it exceeds the specifications of the manufacturing apparatus, it is necessary to modify the manufacturing apparatus. In addition, if the rotation speed of the crystal is higher than usual, crystal deformation (loss of roundness of the crystal and deformation into petals) occurs during pulling of the silicon single crystal ingot, and high quality silicon single crystal There also arises a problem that the crystal ingot cannot be manufactured.

On the other hand, a method for improving in-plane resistance variation of an n-type silicon wafer having a (111) plane orientation is disclosed (for example, see Patent Document 1).
In the method of Patent Document 1, a silicon single crystal ingot whose center axis is inclined by 1 to 6 ° with respect to the <111> crystal axis is grown, and when the silicon wafer is cut out from the silicon single crystal ingot, the above inclination angle is supported. By cutting at an angle, the in-plane resistance variation of the silicon wafer is improved.

Japanese Patent Laid-Open No. 11-186121

  However, in the method described in Patent Document 1, since the cut silicon wafer has an elliptical plate shape, an extra outer diameter processing step is required to obtain a perfect circular silicon wafer. Further, since the single crystal is cut obliquely, the number of silicon wafers obtained from one single crystal is reduced, which causes a reduction in production yield.

  An object of the present invention is to provide n-type silicon capable of suppressing variations in in-plane resistance of an n-type silicon wafer having a (111) plane orientation and capable of obtaining such an n-type silicon wafer with a high yield. The object is to provide a method for producing a single crystal ingot, a method for producing an n-type silicon wafer, and an n-type silicon wafer.

  As a result of diligent investigations on suppressing variation in the in-plane resistance of an n-type silicon wafer having a (111) plane orientation, the present inventors have found that the variation in in-plane resistance of an n-type silicon wafer and the pulling of a single crystal. The present invention was completed by finding that there is a correlation with the shape of the solid-liquid interface at the time.

  The method for producing an n-type silicon single crystal ingot according to the present invention comprises an n-type silicon single crystal having a crystal orientation of <111> from a dopant-added melt obtained by adding a dopant to a silicon melt by the Czochralski method without applying a magnetic field. A pulling step for pulling up the crystal ingot, wherein the pulling step includes forming the n-type silicon single crystal so that a solid-liquid interface between the n-type silicon single crystal ingot being pulled and the dopant-added melt has a downward convex shape. It is characterized by raising the ingot.

According to the present invention, in the pulling step, the diameter of the n-type silicon single crystal ingot is controlled by controlling the solid-liquid interface between the n-type silicon single crystal ingot being pulled and the dopant-added melt to have a downward convex shape. Variation in in-plane resistance in the direction can be suppressed.
The mechanism that can suppress this variation in in-plane resistance is not clear, but can be estimated as follows.
(1) In an n-type silicon single crystal ingot having a crystal orientation of <111>, facet growth occurs at the center of the single crystal (silicon wafer), so that a large amount of dopant is taken in and the resistivity decreases.
(2) When pulling up a silicon single crystal ingot by the Czochralski method, if the solid-liquid interface is made downwardly convex, the resistivity at the center of the single crystal increases, and the resistivity tends to increase particularly when no magnetic field is applied. .
From the above, when pulling up an n-type silicon single crystal ingot having a crystal orientation of <111>, the solid-liquid interface has a downwardly convex shape, thereby canceling the actions shown in (1) and (2). It can be estimated that variation in in-plane resistance of the silicon single crystal ingot can be suppressed.
Therefore, by cutting an n-type silicon single crystal ingot having the above characteristics in a direction perpendicular to the central axis, an n-type silicon wafer having a small in-plane resistance variation and a (111) plane orientation is obtained. In addition, the number of n-type silicon wafers obtained from one n-type silicon single crystal ingot can be increased as compared with the method described in Patent Document 1.

  The method for producing an n-type silicon single crystal ingot of the present invention includes a pulling step of pulling up an n-type silicon single crystal ingot having a crystal orientation of <111> from a dopant-added melt obtained by adding a dopant to a silicon melt by the Czochralski method. In the pulling step, the pulling speed is 0.35 m / min to 0.45 m / min, and the solid-liquid interface between the n-type silicon single crystal ingot being pulled and the dopant-added melt is downwardly convex. Thus, the n-type silicon single crystal ingot is pulled up.

In the method of manufacturing an n-type silicon single crystal ingot according to the present invention, the pulling step includes the diameter of the straight body portion of the n-type silicon single crystal ingot being D, the position of the outer edge of the solid-liquid interface being 0, and the pulling direction being normal. It is preferable that the n-type silicon single crystal ingot is pulled up so that the height H at the center of the solid-liquid interface has a downward convex shape of -0.0933D or more and -0.02D or less.
According to this invention, by controlling the pulling process so that the height of the center of the solid-liquid interface becomes a downward convex shape satisfying the above range, variation in the in-plane resistance in the radial direction in the n-type silicon single crystal ingot can be achieved. It can be suppressed more. As a result, an n-type silicon wafer having a smaller in-plane resistance variation can be obtained.

In the method for producing an n-type silicon single crystal ingot according to the present invention, in the pulling step, the n-type silicon single crystal ingot is cooled by a water-cooled body disposed so as to surround the n-type silicon single crystal ingot being pulled. It is preferable to do.
According to the present invention, the temperature gradient in the pulling direction of the n-type silicon single crystal ingot is increased by simply cooling the n-type silicon single crystal ingot being pulled up with a water-cooled body, and the solid-liquid interface is projected downward. The shape can be controlled.

In the method for producing an n-type silicon single crystal ingot according to the present invention, the pulling step is performed by assuming that the inner diameter of the crucible at the liquid surface position of the dopant-added melt is A, and the depth of the crucible from the liquid surface is B. It is preferable that the dopant-added melt with an amount of / A of 0.5 or less is accommodated in the crucible and the n-type silicon single crystal ingot is pulled up from the dopant-added melt.
According to the present invention, by pulling up the n-type silicon single crystal ingot from a small amount of dopant-added melt, convection in which the solid-liquid interface can easily form a downward convex shape can be formed in the dopant-added melt being pulled up. . Therefore, the solid-liquid interface can be controlled to a downwardly convex shape by a simple method that only adjusts the amount of the dopant-added melt.

In the method for producing an n-type silicon single crystal ingot according to the present invention, it is preferable to perform the pulling step so that the variation Δρ in the in-plane resistance in the radial direction of the n-type silicon single crystal ingot is 8% or less.
According to the present invention, by using an n-type silicon wafer cut out from an n-type silicon single crystal ingot having the above characteristics for the manufacture of a Zener diode, variations in the quality of the Zener diode can be suppressed.
In addition, RRG (Radial Resistivity Gradient) is mainly used for the variation evaluation of in-plane resistance. RRG is a percentage obtained by dividing the difference between the maximum value and the minimum value of resistivity measured at an arbitrary position in the surface of a single silicon wafer by the minimum value. That is, when the maximum value of resistivity is ρmax and the minimum value is ρmin, RRG is expressed by the following formula (1).
RRG = (ρmax−ρmin) / ρmin × 100 (%) (1)

The method for producing an n-type silicon wafer of the present invention includes cutting the n-type silicon single crystal ingot produced by the above-described method for producing an n-type silicon single crystal ingot in a direction perpendicular to the central axis thereof. A slicing step of cutting out an n-type silicon wafer having a (111) plane is provided.
The n-type silicon wafer of the present invention is an n-type silicon wafer having a plane orientation of (111), the variation in in-plane resistance Δρ in the radial direction is 8% or less, and the resistivity is 0.001 Ω · cm or more. If the center is 0% position and the outer edge is 100% position, the area from 0% position to 20% position is the first area and 20% position. The region from the position of 80% to 80% is the second region, the region from the position of 60% to the position of 100% is the third region, and the average value of the resistivity of the third region is the resistivity of the second region. It is smaller than the maximum value of the first region and larger than the minimum value of the resistivity of the first region.

The schematic diagram which shows schematic structure of the single crystal pulling apparatus which concerns on one Embodiment of this invention. Explanatory drawing of the solid-liquid interface shape of the n-type silicon single crystal ingot being pulled up, and a dopant addition melt. The graph which shows the relationship between the straight body position of the n-type silicon single crystal ingot in Example 1 of this invention, and the raising speed. The graph which shows the relationship between the straight body position in the said Example 1, the convex shape height of a solid-liquid interface, and RRG. The graph which shows the relationship between the convex shape height of the solid-liquid interface in the said Example 1, and RRG. The graph which shows resistance distribution of the n-type silicon wafer obtained from the upward convex part and the downward convex part in Example 3 of this invention.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[Configuration of single crystal pulling device]
First, the configuration of the single crystal pulling apparatus will be described.
As shown in FIG. 1, the single crystal pulling apparatus 1 includes a single crystal pulling apparatus main body 3, a doping apparatus (not shown), and a control unit (not shown).
The single crystal pulling apparatus main body 3 includes a chamber 30, a crucible 31 disposed in the chamber 30, a heating unit 32 that radiates and heats the crucible 31, a pulling cable 33 as a pulling unit, and heat insulation. A tube 34 and a shield 36 are provided.

  In the chamber 30, an inert gas, for example, argon gas, is introduced at a predetermined gas flow rate from the upper side to the lower side through the introduction unit 30 </ b> A provided at the upper part under the control of the control unit. The pressure in the chamber 30 (furnace pressure) can be controlled by the control unit.

The crucible 31 melts polycrystalline silicon, which is a raw material for a silicon wafer, to form a silicon melt 4. The crucible 31 includes a bottomed cylindrical quartz crucible 311 and a graphite crucible 312 which is disposed outside the quartz crucible 311 and accommodates the quartz crucible 311. The crucible 31 is supported by a support shaft 37 that rotates at a predetermined speed.
The heating unit 32 is disposed outside the crucible 31 and heats the crucible 31 to melt the silicon in the crucible 31.
One end of the pulling cable 33 is connected to, for example, a pulling drive unit (not shown) disposed on the crucible 31. Further, the pulling cable 33 is appropriately attached to the other end with a seed holder 38 for holding a seed crystal or a doping device (not shown). The pulling cable 33 is configured to be rotatable by driving a pulling drive unit. The pull-up cable 33 is raised at a predetermined pull-up speed under the control of the pull-up drive unit by the control unit.
The heat insulating cylinder 34 is disposed so as to surround the crucible 31 and the heating unit 32.
The shield 36 is a heat shielding shield that blocks radiant heat radiated upward from the heating unit 32. The shield 36 is installed so as to cover the surface of the silicon melt 4. The shield 36 has a conical shape in which the opening on the lower end side is smaller than the opening on the upper end side.

The doping apparatus is for volatilizing a volatile dopant in a solid state and doping the silicon melt 4 in the crucible 31 to generate a dopant added melt 41. Red dopant is mentioned as a dopant of this embodiment. As a doping apparatus, a configuration in which the lower end portion of the cylindrical portion is immersed in the silicon melt 4 and red phosphorus is added to the silicon melt 4, or a lower end portion of the cylindrical portion is separated from the silicon melt 4. Thus, a configuration in which red phosphorus is added to the silicon melt 4 by blowing the volatilized red phosphorus onto the silicon melt 4 can be applied.
The control unit appropriately controls the gas flow rate in the chamber 30, the pressure in the furnace, and the pulling speed of the pulling cable 33 based on the setting input by the operator, thereby controlling the n-type silicon single crystal ingot 6 during manufacture.

[Method of manufacturing n-type silicon wafer]
Next, a method of manufacturing an n-type silicon wafer having a (111) plane orientation using the single crystal pulling apparatus 1 will be described.
The manufacturing process of the n-type silicon wafer includes a pulling process for pulling up an n-type silicon single crystal ingot having a crystal orientation <111> by the Czochralski method, and a direction perpendicular to the central axis of the n-type silicon single crystal ingot. And a slicing step of cutting an n-type silicon wafer having a plane orientation of (111) by cutting.
Hereinafter, each step will be described in detail.

<Pulling process>
First, a quartz crucible 311 containing a polysilicon material is installed in the chamber 30 of the single crystal pulling apparatus 1. After that, after the polysilicon material is heated and melted under the control of the control unit, the gas flow rate in the chamber 30 and the furnace pressure are set to a predetermined state, and red phosphorus as an n-type dopant is added to the silicon melt 4. In addition, the silicon melt 4 contains red phosphorus. Thereby, the dopant addition melt 41 is produced | generated. At this time, the amount of red phosphorus added is such that the resistivity of the n-type silicon wafer cut out from the n-type silicon single crystal ingot 6 is 0.001 Ω · cm to 3.5 Ω · cm.

  Thereafter, the control unit of the single crystal pulling apparatus 1 immerses the seed crystal in the melt based on the operator's setting input, and then pulls it up at a predetermined pulling speed to manufacture the n-type silicon single crystal ingot 6. . The seed crystal at this time is cut from an n-type silicon single crystal ingot having a crystal orientation of <111>.

  In the present embodiment, the n-type silicon single crystal ingot 6 is pulled up at a lower pulling speed than the general manufacturing conditions. By lowering the pulling speed in this way, the crystal growth rate is lowered, and as shown in FIG. 1, the solid-liquid interface S between the n-type silicon single crystal ingot 6 being pulled and the dopant-added melt 41 is convex. The n-type silicon single crystal ingot 6 can be pulled up in the form. The pulling speed for making the solid-liquid interface S into a downward convex shape is preferably 0.35 mm / min or more and 0.60 mm / min or less, more preferably 0.35 mm / min or more and 0.45 mm / min or less.

  As shown in FIG. 2, the n-type silicon single crystal ingot 6 has a diameter of the straight body portion of the n-type silicon single crystal ingot 6 as D, the position of the outer edge S1 of the solid-liquid interface S is 0, and the pulling direction is the positive direction. N-type silicon single crystal ingot 6 may be pulled up so that the center height H of the solid-liquid interface S between 6 and dopant-added melt 41 has a downwardly convex shape of −0.0933D or more and −0.02D or less. preferable. In particular, it is preferable to pull up so as to satisfy the above conditions in the entire area of the straight body.

  By performing a pulling process that satisfies the above conditions, an n-type silicon single crystal ingot having a variation in in-plane resistance Δρ (RRG) in the radial direction of 8% or less and a crystal orientation of <111> can be obtained.

<Slicing process>
Next, using a wire saw (not shown), an n-type silicon wafer having a (111) plane orientation is cut out from the n-type silicon single crystal ingot.
At the time of this cutting, the n-type silicon single crystal ingot is cut in a direction orthogonal to the central axis. Thereby, an n-type silicon wafer having a small RRG of 8% or less and a plane orientation of (111) plane can be obtained. In addition, the n-type silicon wafer whose plane orientation is (111) plane has a first region from 0% to 20% when the center is 0% and the outer edge is 100%. The region, the region from the 20% position to the 80% position is the second region, the region from the 60% position to the 100% position is the third region, and the average value of the resistivity of the third region is the second It has characteristics that are smaller than the maximum resistivity of the region and larger than the minimum resistivity of the first region.

[Other Embodiments]
Note that the present invention is not limited to the above embodiment, and various improvements and design changes can be made without departing from the scope of the present invention.
In the above embodiment, the solid-liquid interface is controlled to have a downward convex shape by slowing the pulling speed, but the present invention is not limited to this.
For example, the n-type silicon single crystal ingot 6 being pulled is cooled by a water-cooled body 50 disposed so as to surround the n-type silicon single crystal ingot 6 as shown by a two-dot chain line in FIG. The shape may be controlled.
Alternatively, the solid-liquid interface S may be controlled to have a downward convex shape by pulling up the n-type silicon single crystal ingot 6 by a so-called multi-pull method. Specifically, as indicated by a two-dot chain line in FIG. 1, the inner diameter of the crucible 31 at the position of the liquid surface 41A of the dopant-added melt 41 is A, and the depth of the crucible 31 from the liquid surface 41A is B. The dopant-added melt 41 with an amount of / A of 0.5 or less may be accommodated, and the n-type silicon single crystal ingot 6 may be pulled up from the dopant-added melt 41. Thereafter, each time one n-type silicon single crystal ingot 6 is manufactured, a silicon polycrystalline material and a dopant may be added to the crucible 31 to manufacture the next n-type silicon single crystal ingot 6.
Moreover, you may control so that the solid-liquid interface S may become a downward convex shape by combining said method.

Moreover, although the example which used red phosphorus as an n-type dopant was demonstrated in the said embodiment, a dopant is not limited to this. For example, antimony or arsenic can be used as a dopant.
In addition, specific procedures, structures, and the like in carrying out the present invention may be other structures or the like as long as the object of the present invention can be achieved.

  EXAMPLES Next, although an Example and a comparative example demonstrate this invention further in detail, this invention is not limited at all by these examples. In the following description, an n-type silicon single crystal ingot and an n-type silicon wafer are simply referred to as a silicon single crystal ingot and a silicon wafer.

[Example 1: Correlation investigation between solid-liquid interface shape and variation in in-plane resistance of silicon wafer]
First, a silicon single crystal ingot having a shoulder portion, a straight body portion, and a tail portion was manufactured by the Czochralski method.
In this production, as shown in FIG. 3, the pulling speed was controlled according to the position of the straight body portion. In this control, the pulling speed is decreased almost linearly from the position of 0 mm (upper end of the straight body) to the position of 200 mm of the straight body, and the lifting speed is increased from the position of 200 mm to the position of the lower end of the straight body. It was made constant at 0.4 mm / min, which is slower than the general speed. The reason for controlling in this way is that by changing the pulling speed, the convection of the dopant-added melt is changed, and the shape of the solid-liquid interface can be controlled.
Other manufacturing conditions are as follows.
Dopant: Red phosphorus Red phosphorus concentration: Resistivity of silicon wafer cut out from ingot
Concentration of 0.7 mΩ · cm to 2.0 mΩ · cm Ingot diameter: 150 mm
Straight body length: 1000 mm
Application of magnetic field: None

Next, the straight body part of the silicon single crystal ingot manufactured on the said conditions was cut | disconnected in the direction orthogonal to a central axis, and the some cylindrical block was created. And this cylindrical block was cut | disconnected in the vertical direction (center-axis direction) in the position which passes along a center axis | shaft, and the shape of the solid-liquid interface was confirmed by image | photographing the cut surface with an X-ray. The result is shown in FIG. The “convex shape height of the solid-liquid interface” shown in FIG. 4 means the height of the center of the solid-liquid interface when the position of the outer edge of the solid-liquid interface is 0 and the pulling direction is the positive direction.
As shown in FIG. 4, the shape of the solid-liquid interface is horizontal (height 0 mm) at a position of 400 mm of the straight body part, is an upward convex shape at the upper end side from 400 mm, and is a downward convex shape at the lower end side from 400 mm. Met.
From this, it was confirmed that the shape of the solid-liquid interface can be controlled to a downward convex shape by slowing the pulling speed.

Next, a plurality of round disk-shaped silicon wafers were cut out from the straight body portion of another silicon single crystal ingot manufactured under the above conditions, and RRG was evaluated. The RRG was evaluated based on the measurement results obtained by measuring resistance values at a plurality of positions on a straight line passing through the center of the silicon wafer. The result is shown in FIG.
As shown in FIG. 4, it was found that the RRG when the solid-liquid interface has a downward convex shape is smaller than the RRG when the solid-liquid interface has an upward convex shape.
Further, when the correlation between the convex shape height of the solid-liquid interface and the RRG was examined using the result shown in FIG. 4, the result shown in FIG. 5 was obtained. From the results of FIG. 5, it can be seen that the RRG is 8% or less when the height of the downward convex shape of the solid-liquid interface is −4 mm or less.

Here, it can be inferred from the results of FIG. 5 that the RRG decreases as the height of the downward convex shape increases, but another problem may occur when the height is increased. Then, in order to investigate the lower limit of the height of the downward convex shape, when samples having heights of −15 mm and −16 mm were prepared and evaluated, it was found that dislocations occurred.
From the above, when manufacturing a silicon single crystal ingot having a diameter of 150 mm, the RRG may be 8% or less by setting the height of the downward convex shape of the solid-liquid interface to -14 mm or more and -4 mm or less. It could be confirmed.

The above results are obtained when the silicon single crystal ingot has a diameter of 150 mm, but it is considered that there is a similar correlation between the convex shape height of the solid-liquid interface and the RRG even in the case of other diameters. .
Therefore, when the diameter of the silicon single crystal ingot is Dmm, the height of the downward convex shape of the solid-liquid interface is set to −0.0933D (−14 mm / 150 mm) or more and −0.02D (−4 mm / 150 mm) or less. Therefore, the RRG is considered to be 8% or less.

[Example 2: Verification of results obtained in investigation of Example 1]
First, the silicon single crystal ingot of Experimental Example 1 was manufactured under the conditions shown in Table 1. In this production, the pulling speed was controlled so that the shape of the solid-liquid interface in the upper end region, the central region, and the lower end region of the straight body portion became the shape shown in Table 1. Further, red phosphorus was added as a dopant, and no magnetic field was applied.
And the height of the center of the solid-liquid interface in the upper end region, the central region, and the lower end region, the shape of the solid-liquid interface, the convex shape ratio, and RRG were examined by the same method as in Example 1.
The results are shown in Table 1.
In Table 1, “the upper end region of the straight body portion” is a region of 5% or more and less than 30% when the upper end of the straight body portion is 0% and the lower end is 100%. Further, the “center region” and the “lower end region” are a region of 30% to 60% and a region of 60% to 90%, respectively. The “convex shape ratio” is a value obtained by dividing the height H at the center of the solid-liquid interface by the diameter D of the straight body portion.

  From the result of Experimental Example 1, in the lower end region where the convex shape ratio satisfies the condition of −0.0933 or more and −0.02 or less, the RRG is 8% or less, and in the upper end region and the center region that do not satisfy the above condition, the RRG is It exceeded 8%. That is, the correlation between the convex shape ratio and RRG was the same as the result of Example 1.

In addition, experimental examples 2 and 3 were performed under the same conditions as in experimental example 1 except that the resistivity at the upper end of the straight body was 0.02 Ω · cm, 0.5 Ω · cm, 4 Ω · cm, and the pulling speed was changed. , 4 silicon single crystal ingots were manufactured and evaluated in the same manner as in Experimental Example 1.
As shown in Table 1, in the range where the resistivity at the upper end of the straight body portion is 0.02 Ω · cm (2 mΩ · cm) to 4 Ω · cm, even if the resistivity changes, the correlation between the convex shape ratio and RRG is The result was the same as in Example 1. Moreover, it can be estimated from this result that the same result can be obtained even when the resistivity at the upper end of the straight body portion is less than 2 mΩ · cm or more than 4 Ω · cm.

Moreover, the silicon single crystal ingot of Experimental Example 5 was manufactured under the same conditions as Experimental Example 1 except that the length of the straight body portion was 600 mm and the pulling speed was changed, and the same evaluation as in Experimental Example 1 was performed. It was.
As shown in Table 1, even if the length of the straight body portion was changed, the correlation between the convex shape ratio and the RRG was the same as the result of Example 1. Moreover, it can be estimated from this result that the same result can be obtained even when the length of the straight body portion is less than 600 mm or more than 1000 mm.

In addition, the silicon single crystal ingots of Experimental Examples 6, 7, 8, and 9 were formed under the same conditions as Experimental Example 1, except that the diameters of the straight body portions were 200 mm, 200 mm, 100 mm, and 100 mm, respectively, and the pulling speed was changed. The same evaluation as in Experimental Example 1 was performed.
As shown in Table 1, the correlation between the convex shape ratio and the RRG was the same as the result of Example 1 regardless of the diameter of the straight body portion. Moreover, it can be estimated from this result that the same result can be obtained even when the diameter of the straight body portion is less than 100 mm or more than 200 mm.

  From the above, regardless of the diameter of the straight body part, the length of the straight body part, and the resistivity of the upper end of the straight body part, the convex shape ratio H / D is −0.0933 or more and −0.02 or less. It was found that a silicon wafer having an RRG of 8% or less can be obtained by controlling the solid-liquid interface shape.

[Example 3: Correlation investigation between solid-liquid interface shape and in-plane resistance distribution of silicon wafer]
Of the silicon wafers used in the RRG evaluation of Example 1, a silicon wafer (Experimental Example 10) in which the solid-liquid interface is cut out from a portion having an upward convex shape (the convex shape height is 5 mm), and a downward convex shape (convex shape) FIG. 6 shows the resistance distribution of a silicon wafer (Experimental Example 11) cut out from a portion having a height of −5 mm. In the following, when the center of the silicon wafer is at 0% position and the outer edge is at 100% position, the area from 0% position to 20% position is the first area, and the position from 20% position to 80% position. The region up to the second region and the region from the 60% position to the 100% position will be referred to as the third region.

As shown in FIG. 6, in Experimental Example 10 obtained from the upwardly convex portion, the average value of the resistivity in the third region is greater than the maximum value of the resistivity in the second region and the minimum value of the resistivity in the first region. It was also found to be big.
On the other hand, Experimental Example 11 obtained from the downwardly convex portion has a characteristic resistance distribution in which the average value of the third region is smaller than the maximum value of the second region and larger than the minimum value of the first region. I found out.
As described above, it was found that the characteristic resistance distribution shown in Experimental Example 11 gave good results to RRG, and the RRG could be 8% or less. That is, the crystal orientation is <111> and the height H of the solid-liquid interface center with respect to the diameter D is a downward convex shape having a certain size or more. It was found that a resistivity distribution was formed, and as a result, the RRG could be 8% or less.

  4 ... silicon melt, 6 ... n-type silicon single crystal ingot, 31 ... crucible, 41 ... dopant-added melt, 41A ... liquid surface, 50 ... water-cooled body, S ... solid-liquid interface.

Claims (8)

With a Czochralski method that does not apply a magnetic field, a pulling step of pulling up an n-type silicon single crystal ingot having a crystal orientation <111> from a dopant-added melt obtained by adding a dopant to a silicon melt,
In the pulling step, the n-type silicon single crystal ingot is pulled up so that a solid-liquid interface between the n-type silicon single crystal ingot being pulled and the dopant-added melt has a downward convex shape. Type silicon single crystal ingot manufacturing method. The Czochralski method includes a pulling step of pulling up an n-type silicon single crystal ingot having a crystal orientation of <111> from a dopant-added melt obtained by adding a dopant to a silicon melt,
In the pulling process, the pulling speed is set to 0.35 m / min or more and 0.45 m / min or less so that the solid-liquid interface between the n-type silicon single crystal ingot being pulled and the dopant-added melt has a downward convex shape. And a method for producing an n-type silicon single crystal ingot, wherein the n-type silicon single crystal ingot is pulled up. In the manufacturing method of the n-type silicon single crystal ingot according to claim 1 or 2,
The pulling step is
The diameter of the straight body portion of the n-type silicon single crystal ingot is D,
The position of the outer edge of the solid-liquid interface is 0,
With the pulling direction as the positive direction,
An n-type silicon single crystal ingot, wherein the n-type silicon single crystal ingot is pulled up so that a height H at the center of the solid-liquid interface has a downward convex shape of −0.0933D or more and −0.02D or less. Production method. In the manufacturing method of the n-type silicon single crystal ingot according to any one of claims 1 to 3,
In the pulling step, the n-type silicon single crystal ingot is cooled by a water-cooled body disposed so as to surround the n-type silicon single crystal ingot being pulled. Method. In the manufacturing method of the n-type silicon single crystal ingot according to claim 1 or 2,
The pulling step is
The inner diameter of the crucible at the liquid surface position of the dopant added melt is A,
The depth of the crucible from the liquid level is B,
An n-type silicon single crystal ingot characterized by containing the dopant-added melt in an amount of B / A of 0.5 or less in the crucible and pulling up the n-type silicon single crystal ingot from the dopant-added melt. Manufacturing method. In the manufacturing method of the n-type silicon single crystal ingot according to any one of claims 1 to 5,
A method for producing an n-type silicon single crystal ingot, wherein the pulling step is performed so that a variation Δρ in in-plane resistance in the radial direction of the n-type silicon single crystal ingot is 8% or less.   By cutting the n-type silicon single crystal ingot produced by the method for producing an n-type silicon single crystal ingot according to any one of claims 1 to 6 in a direction perpendicular to the central axis. A method for producing an n-type silicon wafer comprising a slicing step of cutting out an n-type silicon wafer having a (111) plane orientation. An n-type silicon wafer having a (111) plane orientation,
The in-plane resistance variation Δρ in the radial direction is 8% or less,
The resistivity is 0.001 Ω · cm to 3.5 Ω · cm,
When the center is 0% position and the outer edge is 100% position,
The area from the 0% position to the 20% position is the first area,
The area from the 20% position to the 80% position is the second area,
The area from the 60% position to the 100% position is the third area.
An n-type silicon wafer, wherein an average value of resistivity of the third region is smaller than a maximum value of resistivity of the second region and larger than a minimum value of resistivity of the first region.

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