JP2019162844A - Liquid discharge device and driving signal generating circuit - Google Patents

Abstract

To provide a liquid discharge device which can reduce occurrence of unintended displacement of a piezoelectric element.SOLUTION: A liquid discharge device comprises: a driving circuit outputting a driving signal; a piezoelectric element having a first electrode supplied with the driving signal and a second electrode supplied with a reference voltage signal and being displaced by a potential difference between the first electrode and the second electrode; a cavity filled with liquid discharged from a nozzle in association with displacement of the piezoelectric element; a diaphragm provided between the cavity and the piezoelectric element; a detection circuit detecting whether or not voltage variations of the driving signal are within a predetermined range; and a determination circuit determining whether or not the driving signal is normal on the basis of a detection result of the detection circuit.SELECTED DRAWING: Figure 23

Description

  The present invention relates to a liquid ejection device and a drive signal generation circuit.

  As an ink jet printer (liquid ejecting apparatus) that ejects a liquid such as ink to print an image or a document, a printer using a piezoelectric element such as a piezoelectric element is known. Piezoelectric elements are provided in a print head corresponding to a plurality of nozzles that eject ink and cavities that store ink ejected from the nozzles. Then, when the piezoelectric element is displaced according to the drive signal, the diaphragm provided between the piezoelectric element and the cavity is bent, and the volume of the cavity is changed. As a result, a predetermined amount of ink is ejected from the nozzles at a predetermined timing, and dots are formed on the medium.

  In Patent Document 1, a drive signal generated based on print data is supplied to the upper electrode and a reference voltage is supplied to the lower electrode for a piezoelectric element that is displaced based on a potential difference between the upper electrode and the lower electrode. A liquid ejecting apparatus is disclosed that ejects ink by controlling the displacement of a piezoelectric element by controlling whether or not a drive signal is supplied by a selection circuit (switch circuit).

JP 2017-43007 A

  In a liquid ejecting apparatus that ejects ink based on displacement of a piezoelectric element as described in Patent Document 1, when an unintended DC voltage is supplied to the piezoelectric element, unintended displacement is continuously generated in the piezoelectric element. . When an unintended displacement occurs in the piezoelectric element, the diaphragm is also displaced based on the displacement. As a result, a larger deflection than expected occurs in the diaphragm, and an unintended stress is applied to the diaphragm.

  When such unintentional stress generated in the diaphragm is continuously applied for a long time, the stress concentrates around the contact point between the diaphragm and the cavity, and there is a possibility that a crack or the like is generated in the diaphragm.

  Furthermore, when a transition is made from a state where unintentional bending has occurred to the diaphragm to a discharge operation, an unnecessary load is applied to the diaphragm, which may cause cracks or the like in the diaphragm.

  If a crack occurs in the diaphragm, the ink stored in the cavity leaks from the crack, and the amount of ink ejected varies with the change in the volume of the cavity. As a result, the ink ejection accuracy deteriorates.

  Further, when ink leaking from the crack adheres to both the upper electrode and the lower electrode of the piezoelectric element, a current path through the ink is formed between the upper electrode and the lower electrode. As a result, the potential of the reference voltage signal supplied to the lower electrode varies. In the case where the reference voltage signal is supplied in common to the plurality of piezoelectric elements, the fluctuation of the potential of the reference voltage signal affects the displacement of the plurality of piezoelectric elements. That is, not only the ejection accuracy from the nozzle corresponding to the vibration plate in which the crack has occurred, but also the ink ejection accuracy in the entire liquid ejection apparatus may be affected.

  The problem with respect to the displacement generated in the piezoelectric element and the diaphragm due to such unintentional voltage being continuously applied to the piezoelectric element for a long time is a new problem that is not disclosed in Patent Document 1.

  One aspect of the liquid ejection apparatus according to the present invention includes a drive circuit that outputs a drive signal, a first electrode that is supplied with the drive signal, and a second electrode that is supplied with a reference voltage signal. A piezoelectric element that is displaced by a potential difference between the electrode and the second electrode; a cavity that is filled with a liquid ejected from a nozzle in accordance with the displacement of the piezoelectric element; and a space between the cavity and the piezoelectric element. And a detection circuit for detecting whether or not a voltage fluctuation of the drive signal is within a predetermined range, and determining whether or not the drive signal is normal based on a detection result of the detection circuit And a determination circuit.

  In one aspect of the liquid ejecting apparatus, when the voltage fluctuation of the drive signal is detected to be within the predetermined range in the detection circuit for a predetermined period, the determination circuit You may determine that it is not normal.

  In one aspect of the liquid ejection apparatus, when the determination circuit determines that the drive signal is not normal, the drive circuit controls the voltage value of the drive signal so as to approach the voltage value of the reference voltage signal. May be.

  In one aspect of the liquid ejecting apparatus, when the determination circuit determines that the drive signal is not normal, the determination circuit releases the charge of at least one of the first electrode and the second electrode. May be output.

  In one aspect of the liquid ejection apparatus, the detection circuit may detect whether the voltage fluctuation of the drive signal is within the predetermined range based on an original drive signal that is an origin of the drive signal. Good.

  In one aspect of the liquid ejection apparatus, the detection circuit may detect whether or not the voltage fluctuation of the drive signal is within the predetermined range based on the drive signal.

  One aspect of a drive signal generation circuit provided in a liquid ejection apparatus according to the present invention is a piezoelectric element that is displaced by a potential difference generated between a first electrode and a second electrode, and is ejected from a nozzle in accordance with the displacement of the piezoelectric element. A drive signal generation circuit for use in a liquid ejection apparatus having a cavity filled with a liquid to be filled and a diaphragm provided between the cavity and the piezoelectric element. A drive circuit that outputs a drive signal supplied to one electrode; a detection circuit that detects whether or not a voltage fluctuation of the drive signal is within a predetermined range; and the drive signal based on a detection result of the detection circuit And a determination circuit for determining whether or not is normal.

It is a perspective view which shows schematic structure of a liquid discharge apparatus. It is a block diagram which shows the electrical structure of a liquid discharge apparatus. FIG. 10 is a flowchart for explaining mode transition in each operation mode of the liquid ejection apparatus. It is a block diagram which shows the circuit structure of a drive signal generation circuit. It is a circuit diagram which shows the circuit structure of a reference voltage signal generation circuit. It is a circuit diagram which shows the electric constitution of a feed switching circuit. It is a figure which shows an example of the drive signal COM in printing mode. It is a block diagram which shows the electrical structure of a discharge module and drive IC. It is a circuit diagram which shows the electric constitution of a selection circuit. It is a figure which shows the decoding content in a decoder. It is a figure for demonstrating operation | movement of the drive IC in print mode. It is a disassembled perspective view of a discharge module. It is sectional drawing which shows schematic structure of a discharge part. It is a figure which shows an example of arrangement | positioning of the several nozzle provided in the discharge module and the discharge module. It is a figure for demonstrating the relationship between the displacement of a piezoelectric element and a diaphragm, and discharge. It is a figure which shows typically the displacement of a piezoelectric element and a diaphragm when the voltage value of the electrode of a piezoelectric element rises. FIG. 6 is a plan view when the diaphragm is viewed from a direction Z. It is the figure which illustrated the case where the primary natural vibration arose in a diaphragm. It is the figure which illustrated the case where the tertiary natural vibration arose in a diaphragm. It is a figure for demonstrating the discharge means for discharging the electric charge of a piezoelectric element. It is sectional drawing which shows typically the transistor which comprises a transfer gate. It is a flowchart figure for demonstrating operation | movement of transfer mode. It is a block diagram which shows the electrical structure of a DAC circuit, a detection circuit, and a determination circuit. It is a timing chart for demonstrating operation | movement of the detection circuit in case the original drive signal dA is updated. It is a timing chart for demonstrating operation | movement of the detection circuit when the original drive signal dA is not updated. It is a timing chart for demonstrating operation | movement of the detection circuit in case the clock signal (phi) 2 is supplied. FIG. 6 is a timing chart for explaining the operation of the detection circuit 320 when the clock signal φ2 is not supplied. FIG. 10 is a timing chart illustrating an operation of a determination circuit associated with an operation of detecting an original drive signal dA in an update detection circuit. FIG. 10 is a timing chart showing the operation of the determination circuit associated with the detection operation of the clock signal φ2 in the clock detection circuit. It is a block diagram which shows the electric constitution of the DAC circuit in 2nd Embodiment, a detection circuit, and the determination circuit. It is a timing chart for demonstrating operation | movement of the detection circuit when the original drive signal dA in 2nd Embodiment is updated. It is a timing chart for demonstrating operation | movement of the detection circuit in case the original drive signal dA in 2nd Embodiment is not updated. It is a block diagram which shows the circuit structure of the drive signal generation circuit in 3rd Embodiment. It is a circuit diagram which shows the electric constitution of the detection circuit in 3rd Embodiment.

  Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings. The drawings used are for convenience of explanation. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

  Hereinafter, the liquid ejection apparatus according to the present invention will be described by taking an inkjet printer as an example of a printing apparatus that ejects ink as a liquid.

As the liquid ejection device, for example, a printing device such as an ink jet printer, a color material ejection device used for manufacturing a color filter such as a liquid crystal display, an electrode material ejection used for forming an electrode such as an organic EL display or a surface emitting display. Examples thereof include a device and a bio-organic discharge device used for biochip production.

1 First Embodiment 1.1 Configuration of Liquid Ejecting Apparatus A printing apparatus as an example of a liquid ejecting apparatus according to a first embodiment ejects ink according to image data supplied from an external host computer, This is an inkjet printer that forms dots on a print medium such as paper and prints an image including characters, graphics, and the like according to the image data.

  FIG. 1 is a perspective view illustrating a schematic configuration of the liquid ejection apparatus 1. FIG. 1 illustrates a direction X in which the medium P is transported, a direction Y in which the moving body 2 reciprocates across the direction X, and a direction Z in which ink is ejected. In the first embodiment, the direction X, the direction Y, and the direction Z are described as axes that are orthogonal to each other.

  As shown in FIG. 1, the liquid ejection apparatus 1 includes a moving body 2 and a moving mechanism 3 that reciprocates the moving body 2 along the direction Y.

  The moving mechanism 3 includes a carriage motor 31 that is a driving source of the moving body 2, a carriage guide shaft 32 that is fixed at both ends, and a timing belt 33 that extends substantially parallel to the carriage guide shaft 32 and is driven by the carriage motor 31. And having.

  The carriage 24 included in the moving body 2 is supported by the carriage guide shaft 32 so as to be reciprocally movable, and is fixed to a part of the timing belt 33. Therefore, by driving the timing belt 33 by the carriage motor 31, the movable body 2 is guided by the carriage guide shaft 32 and reciprocates along the direction Y.

  A head unit 20 is provided in a portion of the moving body 2 that faces the medium P. The head unit 20 has a large number of nozzles, and ink is ejected along the direction Z from each of the nozzles. Further, a control signal or the like is supplied to the head unit 20 via the flexible cable 190.

  The liquid ejection apparatus 1 includes a transport mechanism 4 that transports the medium P on the platen 40 along the direction X. The transport mechanism 4 includes a transport motor 41 that is a driving source, and a transport roller 42 that is rotated by the transport motor 41 and transports the medium P along the direction X.

  Then, at the timing when the medium P is transported by the transport mechanism 4, the head unit 20 ejects ink onto the medium P, whereby an image is formed on the surface of the medium P.

  FIG. 2 is a block diagram showing an electrical configuration of the liquid ejection apparatus 1.

  As shown in FIG. 2, the liquid ejection apparatus 1 includes a control unit 10 and a head unit 20. The control unit 10 and the head unit 20 are connected via a flexible cable 190.

  The control unit 10 includes a control circuit 100, a carriage motor driver 35, a transport motor driver 45, and a voltage generation circuit 90.

The control circuit 100 supplies a plurality of control signals and the like for controlling various configurations based on image data supplied from the host computer.

  Specifically, the control circuit 100 supplies a control signal CTR1 to the carriage motor driver 35. The carriage motor driver 35 drives the carriage motor 31 according to the control signal CTR1. Thereby, the movement in the direction Y of the carriage 24 shown in FIG. 1 is controlled.

  Further, the control circuit 100 supplies a control signal CTR2 to the transport motor driver 45. The transport motor driver 45 drives the transport motor 41 in accordance with the control signal CTR2. Thereby, the movement of the medium P in the direction X by the transport mechanism 4 shown in FIG. 1 is controlled.

  Further, the control circuit 100 supplies the head unit 20 with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, an operation mode signal MC, a drive data signal DRV, and a select signal EN.

  The voltage generation circuit 90 generates a voltage VHV of, for example, DC42V and supplies it to the head unit 20. The voltage VHV may also be supplied to various components included in the control unit 10.

  The head unit 20 includes a drive signal generation circuit 50, a power supply switching circuit 70, a drive IC 80, and a discharge module 21.

  The drive signal generation circuit 50 is supplied with a voltage VHV, a drive data signal DRV, and a select signal EN.

  The drive signal generation circuit 50 amplifies a signal based on the drive data signal DRV into a voltage based on the voltage VHV, thereby generating a drive signal COM and supplying the drive signal COM to the drive IC 80. In addition, the drive signal generation circuit 50 generates a reference voltage signal VBS of, for example, DC5V obtained by stepping down the voltage VHV, and supplies it to the ejection module 21. The drive signal generation circuit 50 generates a power supply control signal CTVHV based on the drive data signal DRV and supplies the power supply control signal CTVHV to the power supply switching circuit 70. Here, the select signal EN indicates whether the drive data signal DRV supplied to the drive signal generation circuit 50 is a data signal for generating the drive signal COM or a data signal for generating the power supply control signal CTVHV. It is a signal for instructing.

  Further, the drive signal generation circuit 50 supplies an error signal ERR to the control circuit 100 when the generated drive signal COM is not normal.

  The power supply switching circuit 70 is supplied with a voltage VHV and a power supply control signal CTVHV. The power supply switching circuit 70 switches whether the potential of the voltage VHV-TG supplied to the drive IC 80 is a potential based on the voltage VHV or a ground potential in accordance with the power supply control signal CTVHV.

  The drive IC 80 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, an operation mode signal MC, a voltage VHV-TG, and a drive signal COM.

  The drive IC 80 switches whether the drive signal COM is selected or not selected in a predetermined period based on the clock signal SCK, the print data signal SI, the operation mode signal MC, the latch signal LAT, and the change signal CH. Then, the drive signal COM selected by the drive IC 80 is supplied to the ejection module 21 as the drive signal VOUT. The voltage VHV-TG is used, for example, to generate a high voltage logic signal for selecting the drive signal COM.

  The discharge module 21 includes a plurality of discharge units 600 including the piezoelectric element 60.

  The drive signal VOUT supplied to the ejection module 21 is supplied to one end of the piezoelectric element 60. The reference voltage signal VBS is supplied to the other end of the piezoelectric element 60. The piezoelectric element 60 is displaced according to the potential difference between the drive signal VOUT and the reference voltage signal VBS. Then, an amount of ink corresponding to the displacement is ejected from the ejection unit 600.

  The details of the drive signal generation circuit 50, the power supply switching circuit 70, the drive IC 80, and the ejection module 21 described above will be described later. In FIG. 2, the description has been made assuming that the liquid ejection apparatus 1 has one head unit 20, but a plurality of head units 20 may be provided. Further, in FIG. 2, the head unit 20 has been described as having one ejection module 21, but a plurality of ejection modules 21 may be provided.

  The liquid ejection apparatus 1 as described above has a plurality of operation modes including a print mode, a standby mode, a transition mode, and a sleep mode.

  The print mode is an operation mode in which printing can be executed by ejecting ink to the medium P based on supplied image data. The standby mode is an operation mode in which printing can be executed in a short time when image data is supplied while reducing power consumption with respect to the printing mode. The transition mode is an operation mode during transition from the standby mode to the sleep mode. The sleep mode is an operation mode that can further reduce power consumption compared to the standby mode.

  Here, the relationship of each operation mode which the liquid discharge apparatus 1 has is demonstrated using FIG. FIG. 3 is a flowchart for explaining mode transition in each operation mode of the liquid ejection apparatus 1.

  As shown in FIG. 3, when power is supplied to the liquid ejection apparatus 1, the control circuit 100 controls the operation mode to the standby mode (S110). Then, the control circuit 100 determines whether or not a predetermined time has elapsed after shifting to the standby mode (S120).

  If the predetermined time has not elapsed (N in S120), the control circuit 100 determines whether image data is supplied to the liquid ejection apparatus 1 (S130).

  When the image data is not supplied (N in S130), the standby mode is continued. On the other hand, when the image data is supplied (Y in S130), the control circuit 100 controls the operation mode to the print mode (S140).

  In the print mode, the drive signal generation circuit 50 determines whether or not the drive signal COM is normal (S150). If the drive signal COM is normal (Y in S150), it is determined whether printing corresponding to the supplied image data has been completed (S160). If printing has not ended (N in S160), the drive signal generation circuit 50 determines whether or not the drive signal COM is normal (S150).

  In the printing mode, when printing corresponding to the supplied image data is completed (Y in S160), the control circuit 100 controls the operation mode to the standby mode (S110).

  When the predetermined time has elapsed (Y in S120) and when the drive signal COM is not normal (N in S150), the control circuit 100 controls the operation mode to the transition mode (S170). After the transition mode ends, the control circuit 100 controls the operation mode to the sleep mode (S180).

  After the transition to the sleep mode, the control circuit 100 determines whether image data is supplied to the liquid ejection apparatus 1 (S190).

  When the image data is not supplied (N in S190), the sleep mode is continued. On the other hand, when image data is supplied (Y in S190), the control circuit 100 controls the operation mode to the print mode (S140).

  The liquid ejection apparatus 1 may include an operation mode other than the operation modes described above as a plurality of operation modes. For example, the liquid ejection apparatus 1 may include an operation mode such as a test printing mode for performing test printing on the medium P, a stop mode for stopping operation due to running out of ink, a conveyance failure of the medium P, or the like.

1.2 Configuration and Operation of Drive Signal Generation Circuit Next, the drive signal generation circuit 50 will be described with reference to FIG. FIG. 4 is a block diagram showing a circuit configuration of the drive signal generation circuit 50. As shown in FIG. 4, the drive signal generation circuit 50 includes an integrated circuit 500, an output circuit 550, a first feedback circuit 570, a second feedback circuit 580, and a plurality of other circuit elements.

  Further, the drive signal generation circuit 50 is electrically connected to various external components such as terminals Drv-In, En-In, Err-Out, Vhv-In, Vbs-Out, Ctvh-Out, and Com-Out. , Gnd-In. Among these, the ground potential (for example, 0 V) of the liquid ejection apparatus 1 is supplied to the terminal Gnd-In.

  The integrated circuit 500 includes a GVDD generation circuit 410, a signal selection circuit 420, a power supply control signal generation circuit 430, a reference voltage signal generation circuit 450, a DAC (Digital to Analog Converter) circuit 310, a detection circuit 320, a determination circuit 350, and a modulation circuit 510. A gate drive circuit 520 and an LC discharge circuit 530.

  Further, the integrated circuit 500 has terminals Drv, En, Err, Vhv, Vfb, Vbs, Ctvh, Bst, Hdr, Sw, Gvd, Ldr, Gnd for electrically connecting with various components of the drive signal generation circuit 50. Having a plurality of terminals.

  The voltage VHV is supplied to the GVDD generation circuit 410 via the terminal Vhv-In and the terminal Vhv. The GVDD generation circuit 410 transforms the voltage VHV to generate the voltage GVDD and supplies it to the reference voltage signal generation circuit 450 and the gate drive circuit 520.

  The GVDD generation circuit 410 is configured by, for example, a linear regulator circuit or a switching regulator circuit. Note that the GVDD generation circuit 410 may be provided outside the integrated circuit 500.

The signal selection circuit 420 is supplied with the drive data signal DRV via the terminal Drv-In and the terminal Drv terminal, and with the select signal EN via the terminal En-In and the terminal En terminal. In the signal selection circuit 420, the drive data signal DRV is a signal to be supplied to the DAC circuit 310, or a signal to be supplied to each of the reference voltage signal generation circuit 450, the power supply control signal generation circuit 430, and the LC discharge circuit 530. Is determined based on the select signal EN and supplied to each of the components.

  Specifically, the signal selection circuit 420 includes a plurality of registers (not shown). When the drive data signal DRV is a signal to be supplied to the DAC circuit 310, the signal selection circuit 420 holds the drive data signal DRV in a plurality of registers corresponding to the DAC circuit 310 according to the select signal EN. Then, the signal selection circuit 420 supplies the held signal to the DAC circuit 310 as a digital original drive signal dA.

  On the other hand, when the drive data signal DRV is a signal supplied to each of the reference voltage signal generation circuit 450, the power supply control signal generation circuit 430, and the LC discharge circuit 530, the signal selection circuit 420 generates the drive data signal DRV according to the select signal EN. Among them, data corresponding to each of the reference voltage signal generation circuit 450, the power supply control signal generation circuit 430, and the LC discharge circuit 530 is held in a predetermined register. Then, the signal selection circuit 420 supplies the held signal as the discharge control signals DIS1, DIS2, and DIS3 to the power supply control signal generation circuit 430, the LC discharge circuit 530, and the reference voltage signal generation circuit 450, respectively.

  The power supply control signal generation circuit 430 is supplied with the discharge control signal DIS1. The power supply control signal generation circuit 430 includes an open drain circuit (not shown). Then, when the supplied discharge control signal DIS1 is an active signal, the power supply control signal generation circuit 430 controls the open drain circuit to turn off and sets the terminal Ctvh to high impedance.

  On the other hand, when the discharge control signal DIS1 is a signal indicating inactivity, the power supply control signal generation circuit 430 controls the open drain circuit to be on and sets the terminal Ctvh to the ground potential. At this time, the L level power supply control signal CTVHV is supplied to the power supply switching circuit 70 shown in FIG. 2 via the terminal Ctvh and the terminal Ctvh-Out.

  In the description of FIG. 20 and the like to be described later, the open drain circuit included in the power supply control signal generation circuit 430 will be described as being configured by an NMOS transistor. In the following description, it is assumed that the discharge control signal DIS1 is supplied to the gate terminal of the NMOS transistor via the inverter circuit. Therefore, in the first embodiment, the signal indicating that the discharge control signal DIS1 is active is an H level signal, and the signal indicating that the discharge control signal DIS1 is inactive is an L level signal. Note that the power supply control signal generation circuit 430 is not limited to an open drain circuit, and may be configured by a push-pull circuit, for example.

  The reference voltage signal generation circuit 450 is supplied with the voltage GVDD. The reference voltage signal generation circuit 450 reduces the supplied voltage GVDD to generate a reference voltage signal VBS.

  FIG. 5 is a circuit diagram showing a circuit configuration of the reference voltage signal generation circuit 450. The reference voltage signal generation circuit 450 includes a comparator 451, transistors 452, 453, and resistors 454, 455, 456. In the following description, the transistor 452 is described as a PMOS transistor, and the transistor 453 is described as an NMOS transistor.

  The voltage Vref <b> 1 is supplied to the input terminal (−) of the comparator 451. The input terminal (+) of the comparator 451 is connected in common with one end of the resistor 454 and one end of the resistor 455. The output terminal of the comparator 451 is connected to the gate terminal of the transistor 452.

  The voltage GVDD is supplied to the source terminal of the transistor 452. The drain terminal of the transistor 452 is connected in common with the other end of the resistor 454, one end of the resistor 456, and a terminal Vbs from which the reference voltage signal VBS is output.

  The other end of the resistor 456 is connected to the drain terminal of the transistor 453.

  A discharge control signal DIS3 is supplied to the gate terminal of the transistor 453. A ground potential is supplied to the source terminal of the transistor 453.

  A ground potential is supplied to the other end of the resistor 455.

  As described above, the reference voltage signal generation circuit 450 constitutes a series regulator circuit.

  A voltage obtained by dividing the reference voltage signal VBS by the resistor 454 and the resistor 455 is supplied to the input terminal (+) of the comparator 451. When the voltage supplied to the input terminal (+) of the comparator 451 is higher than the voltage Vref1 supplied to the input terminal (−) of the comparator 451, the comparator 451 outputs an H level signal. At this time, the transistor 452 is controlled to be off. Therefore, the voltage GVDD is not supplied to the terminal Vbs.

  On the other hand, when the voltage supplied to the input terminal (+) of the comparator 451 is smaller than the voltage Vref1 supplied to the input terminal (−) of the comparator 451, the comparator 451 outputs an L level signal. At this time, the transistor 452 is controlled to be on. Therefore, the voltage GVDD is supplied to the terminal Vbs.

  As described above, the reference voltage signal generation circuit 450 compares the signal based on the reference voltage signal VBS with the voltage Vref1 in the comparator 451 and controls the transistor 452, thereby stepping down the voltage GVDD and becoming a target. A reference voltage signal VBS having a voltage value is generated.

  In addition, when the discharge control signal DIS3 supplied to the gate terminal of the transistor 453 is an H level signal, the transistor 453 is controlled to be on. At this time, the ground potential is supplied to the terminal Vbs via the resistor 456. In other words, the transistor 453 is provided so that the electrical connection between the terminal Vbs and the terminal Vbs-Out and the ground potential can be switched.

  Returning to FIG. 4, the reference voltage signal VBS generated by the reference voltage signal generation circuit 450 is supplied to the ejection module 21 shown in FIG. 2 via the terminal Vbs and the terminal Vbs-Out. The reference voltage signal VBS functions as a reference voltage that serves as a reference for displacing the piezoelectric element 60.

  Note that the reference voltage signal generation circuit 450 may be provided outside the integrated circuit 500, and may be further provided outside the drive signal generation circuit 50.

  The DAC circuit 310 converts the original drive signal dA into an analog original drive signal aA and supplies it to the modulation circuit 510. Further, the DAC circuit 310 supplies a digital signal based on the original drive signal dA to the detection circuit 320.

  The detection circuit 320 detects whether or not a signal based on the original drive signal dA supplied from the DAC circuit 310 is within a predetermined range.

  The determination circuit 350 determines whether or not the original drive signal dA is normal according to the detection result of the detection circuit 320. If it is determined that the original drive signal dA is not normal, the determination circuit 350 generates an error signal ERR and supplies the error signal ERR to the control circuit 100 illustrated in FIG. 2 via the terminal Err and the terminal Err-Out.

  Details of the operations and configurations of the DAC circuit 310, the detection circuit 320, and the determination circuit 350 described above will be described later.

  The modulation circuit 510 includes an adder 512, an adder 513, a comparator 514, an inverter 515, an integral attenuator 516 and an attenuator 517.

  The integral attenuator 516 attenuates and integrates the voltage signal of the drive signal COM supplied via the terminal Vfb, and supplies the voltage signal to the input terminal (−) of the adder 512.

  The original drive signal aA is supplied to the input terminal (+) of the adder 512. The adder 512 subtracts and integrates the voltage signal supplied from the integration attenuator 516 to the input terminal (−) of the adder 512 from the original drive signal aA supplied to the input terminal (+). Then, the subtracted and integrated voltage signal is supplied to the input terminal (+) of the adder 513.

  Here, the maximum voltage of the original drive signal aA is a low voltage of about 2V, for example, whereas the maximum voltage of the drive signal COM may be a high voltage of about 40V, for example. For this reason, the integral attenuator 516 attenuates the voltage of the drive signal COM in order to match the amplitude range of both voltages when obtaining the deviation.

  The attenuator 517 attenuates the high frequency component of the voltage signal of the drive signal COM input via the terminal Ifb, and supplies the voltage to the input terminal (−) of the adder 513.

  The adder 513 outputs to the comparator 514 a voltage signal As obtained by subtracting the voltage supplied from the attenuator 517 to the input terminal (−) from the voltage supplied from the adder 512 to the input terminal (+).

  The voltage signal As output from the adder 513 is a voltage obtained by subtracting the voltage supplied to the terminal Vfb from the voltage of the original drive signal aA and further subtracting the voltage supplied to the terminal Ifb. That is, the voltage signal As is a voltage signal obtained by correcting a deviation obtained by subtracting the attenuation voltage of the output drive signal COM from the target voltage of the original drive signal aA with the high frequency component of the drive signal COM.

  The comparator 514 generates a modulation signal Ms based on the voltage signal As supplied from the adder 513. Specifically, the comparator 514 generates an H-level modulation signal Ms when the voltage of the voltage signal As supplied from the adder 513 is rising and when the voltage becomes equal to or higher than a predetermined threshold Vth1. Further, the comparator 514 generates the L-level modulation signal Ms when the voltage of the voltage signal As is decreasing and when the voltage signal As is below a predetermined threshold value Vth2. Note that the threshold value Vth1 and the threshold value Vth2 are set such that threshold value Vth1> threshold value Vth2.

The comparator 514 supplies the generated modulation signal Ms to the first gate driver 521 included in the gate drive circuit 520. The comparator 514 supplies the generated modulation signal Ms to the second gate driver 522 included in the gate drive circuit 520 via the inverter 515. Accordingly, the signal supplied from the comparator 514 to the first gate driver 521 and the signal supplied to the second gate driver 522 are in an exclusive relationship with each other.

  Here, the logic levels of the signals supplied to the first gate driver 521 and the second gate driver 522 are in an exclusive relationship. The logic of the signals supplied to the first gate driver 521 and the second gate driver 522 is the same. It includes the concept that the timing is controlled so that the level does not simultaneously become the H level.

  The gate drive circuit 520 includes a first gate driver 521 and a second gate driver 522.

  The first gate driver 521 level-shifts the voltage value of the modulation signal Ms output from the comparator 514, and outputs the result as the first amplification control signal Hgd from the terminal Hdr.

  Specifically, of the power supply voltage of the first gate driver 521, a voltage is supplied to the high potential side via the terminal Bst and to the low potential side via the terminal Sw. The terminal Bst is connected in common with one end of a capacitor 541 provided outside the integrated circuit 500 and a cathode terminal of a backflow preventing diode 542. The other end of the capacitor 541 is connected to the terminal Sw. The anode terminal of the diode 542 is connected to the terminal Gvd to which the voltage GVDD is supplied. Therefore, the potential difference between the terminal Bst and the terminal Sw is approximately equal to the potential difference between both ends of the capacitor 541, that is, the voltage GVDD. The first gate driver 521 generates a first amplification control signal Hgd having a voltage larger than the terminal Sw by the voltage GVDD according to the input modulation signal Ms, and outputs the first amplification control signal Hgd from the terminal Hdr.

  The second gate driver 522 operates on the lower potential side than the first gate driver 521. The second gate driver 522 level-shifts the voltage value of the signal obtained by inverting the modulation signal Ms output from the comparator 514 by the inverter 515, and outputs the result as the second amplification control signal Lgd from the terminal Ldr.

  Specifically, the voltage GVDD is supplied to the high potential side of the power supply voltage of the second gate driver 522, and the ground potential is supplied to the low potential side. The second gate driver 522 generates a second amplification control signal Lgd having a voltage larger than the terminal Gnd by the voltage GVDD in accordance with the inverted signal of the modulation signal Ms supplied, and outputs the second amplification control signal Lgd from the terminal Ldr.

  The LC discharge circuit 530 includes a resistor 531 and a transistor 532. In the following description, the transistor 532 is described as an NMOS transistor.

  One end of the resistor 531 is connected to the terminal Vfb. The other end of the resistor 531 is connected to the drain terminal of the transistor 532.

  A discharge control signal DIS2 is supplied to the gate terminal of the transistor 532. A ground potential is supplied to the source terminal of the transistor 532.

  When the H level discharge control signal DIS2 is supplied to the gate terminal of the transistor 532, the transistor 532 is controlled to be turned on. At this time, the ground potential is supplied to the terminal Com-Out from which the drive signal COM is output via the resistors 531 and 571 and the transistor 532. In other words, the transistor 532 is provided so that the electrical connection between the terminal Com-Out and the ground potential can be switched.

The output circuit 550 includes transistors 551 and 552, resistors 553 and 554, and a low pass filter 560 (Low Pass Filter). In the following description, the transistors 551 and 552 are described as NMOS transistors.

  A voltage VHV is supplied to the drain terminal of the transistor 551. The gate terminal of the transistor 551 is connected to one end of the resistor 553. The source terminal of the transistor 551 is connected to the terminal Sw. The other end of the resistor 553 is connected to the terminal Hdr. Therefore, the first amplification control signal Hgd is supplied to the gate terminal of the transistor 551.

  A drain terminal of the transistor 552 is connected to a source terminal of the transistor 551. The gate terminal of the transistor 552 is connected to one end of the resistor 554. A ground potential is supplied to the source terminal of the transistor 552. The other end of the resistor 554 is connected to the terminal Ldr. Therefore, the second amplification control signal Lgd is supplied to the gate terminal of the transistor 552.

  In the transistors 551 and 552 connected as described above, when the transistor 551 is controlled to be turned off and the transistor 552 is controlled to be turned on, a connection point to which the terminal Sw is connected is a ground potential, and a voltage is applied to the terminal Bst. GVDD is supplied. On the other hand, when the transistor 551 is controlled to be on and the transistor 552 is controlled to be off, the voltage VHV is supplied to the connection point to which the terminal Sw is connected. Therefore, the voltage VHV + voltage GVDD is supplied to the terminal Bst. In other words, the first gate driver 521 that drives the transistor 551 uses the capacitor 541 as a floating power supply, and the voltage of the terminal Sw changes to the ground potential or the voltage VHV according to the operation of the transistors 551 and 552. A first amplification control signal Hgd having an L level of voltage VHV and an H level of voltage VHV + voltage GVDD is supplied to the gate terminal. The transistor 551 performs a switching operation based on the first amplification control signal Hgd.

  The second gate driver 522 for driving the transistor 552 outputs the second amplification control signal Lgd whose L level is the ground potential and H level is the voltage GVDD regardless of the operation of the transistors 551 and 552. The transistor 552 performs a switching operation based on the second amplification control signal Lgd.

  As described above, an amplified modulated signal obtained by amplifying the modulated signal Ms based on the voltage VHV is generated at the connection point between the source terminal of the transistor 551 and the drain terminal of the transistor 552. That is, the transistors 551 and 552 function as an amplifier circuit that amplifies the voltage of the modulation signal Ms. As described above, the first amplification control signal Hgd and the second amplification control signal Lgd that drive the transistors 551 and 552 are in an exclusive relationship. That is, the transistor 551 and the transistor 552 are controlled so as not to be turned on simultaneously.

  Low pass filter 560 includes an inductor 561 and a capacitor 562.

  One end of the inductor 561 is connected in common with the source terminal of the transistor 551 and the drain terminal of the transistor 552. The other end of the inductor 561 is connected in common with a terminal Com-Out from which the drive signal COM is output and one end of the capacitor 562. A ground potential is supplied to the other end of the capacitor 562.

  As described above, the inductor 561 and the capacitor 562 smooth the amplified modulation signal supplied to the connection point between the transistor 551 and the transistor 552. As a result, the amplified modulation signal is demodulated to generate the drive signal COM.

  The first feedback circuit 570 includes a resistor 571 and a resistor 572. One end of the resistor 571 is connected to the terminal Com-Out. The other end of the resistor 571 is connected in common with the terminal Vfb and one end of the resistor 572. A voltage VHV is supplied to the other end of the resistor 572. As a result, the drive signal COM that has passed through the first feedback circuit 570 is pulled up and fed back to the terminal Vfb from the terminal Com-Out.

  Second feedback circuit 580 includes resistors 581, 582 and capacitors 583, 584, 585.

  One end of the capacitor 583 is connected to the terminal Com-Out. The other end of the capacitor 583 is connected in common with one end of the resistor 581 and one end of the resistor 582. A ground potential is supplied to the other end of the resistor 581. Thereby, the capacitor 583 and the resistor 581 function as a high pass filter. Note that the cutoff frequency of the high-pass filter including the capacitor 583 and the resistor 581 is set to, for example, about 9 MHz.

  The other end of the resistor 582 is connected in common with one end of the capacitor 584 and one end of the capacitor 585. A ground potential is supplied to the other end of the capacitor 584. Thereby, the resistor 582 and the capacitor 584 function as a low pass filter. Note that the cutoff frequency of the low-pass filter including the resistor 582 and the capacitor 584 is set to, for example, about 160 MHz.

  Thus, since the second feedback circuit 580 is composed of a high-pass filter and a low-pass filter, the second feedback circuit 580 functions as a band pass filter that passes a predetermined frequency range of the drive signal COM. To do.

  The other end of the capacitor 585 is connected to the terminal Ifb. As a result, the DC component of the high frequency component of the drive signal COM that has passed through the second feedback circuit 580 is cut back to the terminal Ifb.

  By the way, the drive signal COM is a signal obtained by smoothing the amplified modulation signal by the low-pass filter 560. This drive signal COM is integrated / subtracted via the terminal Vfb and then fed back to the adder 512. Therefore, self-excited oscillation occurs at a frequency determined by the feedback delay and the transfer function of the feedback. However, since the delay amount of the feedback path via the terminal Vfb is large, there is a case where the frequency of the self-oscillation cannot be made high enough to ensure the accuracy of the drive signal COM only by the feedback via the terminal Vfb. . Therefore, by providing a path for feeding back the high-frequency component of the drive signal COM via the terminal Ifb in addition to the path via the terminal Vfb, the delay when viewed from the entire circuit can be reduced. As a result, the frequency of the voltage signal As becomes high enough to ensure the accuracy of the drive signal COM as compared to the case where there is no path through the terminal Ifb.

  Of the drive signal generation circuit 50 described above, the configuration including the modulation circuit 510, the gate drive circuit 520, the LC discharge circuit 530, the output circuit 550, the capacitor 541, and the diode 542 generates the drive signal COM described above. 3 is an example of a drive circuit 51.

1.3 Configuration and Operation of Power Supply Switching Circuit Next, the configuration and operation of the power supply switching circuit 70 will be described with reference to FIG. FIG. 6 is a circuit diagram illustrating an electrical configuration of the power supply switching circuit 70.

  The power supply switching circuit 70 includes transistors 471, 472, 473 and resistors 474, 475. In the following description, the transistor 471 is described as a PMOS transistor, and the transistors 472 and 473 are described as NMOS transistors.

  The source terminal of the transistor 471 is connected to one end of the resistor 474 and supplied with the voltage VHV. The gate terminal of the transistor 471 is connected in common with the other end of the resistor 474 and the drain terminal of the transistor 472. Further, the drain terminal of the transistor 471 is connected to one end of the resistor 475.

  A voltage Vdd1 is supplied to a gate terminal of the transistor 472. The source terminal of the transistor 472 is connected to the gate terminal of the transistor 473 and is supplied with a power supply control signal CTVHV. Here, the voltage Vdd1 is a DC voltage signal having an arbitrary voltage value.

  A drain terminal of the transistor 473 is connected to the other end of the resistor 475. A ground potential is supplied to the source terminal of the transistor 473.

  The power supply switching circuit 70 configured as described above switches whether to supply the voltage VHV to the drive IC 80 as the voltage VHV-TG in accordance with the power supply control signal CTVHV supplied from the drive signal generation circuit 50.

  Specifically, when the discharge control signal DIS1 indicating inactivity is supplied to the power supply control signal generation circuit 430, the power supply control signal generation circuit 430 sets the terminal Ctvh-Out to the ground potential. Therefore, the power supply control signal CTVHV is an L level signal. Accordingly, the transistor 473 is controlled to be off and the transistor 472 is controlled to be on. Therefore, the ground potential is supplied to the gate terminal of the transistor 471 through the transistor 472. Accordingly, the transistor 471 is controlled to be on.

  As described above, when the power supply control signal CTVHV is an L level signal, the transistor 471 is controlled to be on and the transistor 473 is controlled to be off. Therefore, the power supply switching circuit 70 supplies the voltage VHV supplied via the transistor 471 to the drive IC 80 as the voltage VHV-TG.

  On the other hand, when the discharge control signal DIS1 indicating active is supplied to the power supply control signal generation circuit 430, the power supply control signal generation circuit 430 sets the terminal Ctvh-Out to high impedance. At this time, the voltage at the terminal Ctvh-Out becomes the voltage Vdd1 supplied via the transistor 472. In other words, the power supply control signal CTVHV is an H level signal. Accordingly, the transistor 473 is controlled to be on. At this time, the voltage VHV is supplied to the drain terminal of the transistor 472 and the gate terminal of the transistor 471 through the resistor 474. Accordingly, the transistor 471 is controlled to be turned off.

  As described above, when the power supply control signal CTVHV is an H level signal, the transistor 471 is controlled to be off and the transistor 473 is controlled to be on. Accordingly, the power supply switching circuit 70 supplies the ground potential supplied via the resistor 475 and the transistor 472 to the drive IC 80 as the voltage VHV-TG.

1.4 Configuration and Operation of Drive IC Next, the configuration and operation of the drive IC 80 will be described.

First, an example of the drive signal COM supplied to the drive IC 80 will be described with reference to FIG. Thereafter, the configuration and operation of the drive IC 80 will be described with reference to FIGS.

  FIG. 7 is a diagram illustrating an example of the drive signal COM in the print mode. FIG. 7 shows the period T1 from the rise of the latch signal LAT to the rise of the change signal CH, the period T2 after the period T1, until the next rise of the change signal CH, and after the period T2, the latch signal LAT is A period T3 until rising is shown. Note that the period formed by the periods T1, T2, and T3 is a period Ta for forming a new dot on the medium P.

  As shown in FIG. 7, in the print mode, the drive signal generation circuit 50 generates the voltage waveform Adp in the period T1. When the voltage waveform Adp1 is supplied to the piezoelectric element 60, a predetermined amount, specifically, a medium amount of ink is ejected from the corresponding ejection unit 600.

  Further, the drive signal generation circuit 50 generates the voltage waveform Bdp in the period T2. When the voltage waveform Bdp is supplied to the piezoelectric element 60, a small amount of ink smaller than the predetermined amount is ejected from the corresponding ejection unit 600.

  Further, the drive signal generation circuit 50 generates the voltage waveform Cdp in the period T3. When the voltage waveform Cdp is supplied to the piezoelectric element 60, the piezoelectric element 60 is displaced to the extent that ink is not ejected from the corresponding ejection unit 600. Accordingly, no dots are formed on the medium P. This voltage waveform Cdp is a voltage waveform for preventing the viscosity of the ink from increasing by causing the ink in the vicinity of the nozzle opening of the ejection unit 600 to vibrate. In the following description, in order to prevent the viscosity of ink from increasing, displacing the piezoelectric element 60 to the extent that ink is not ejected from the ejection unit 600 is referred to as “microvibration”.

  Here, the voltage value at the start timing and the voltage value at the end timing of the voltage waveform Adp, the voltage waveform Bdp, and the voltage waveform Cdp are all common to the voltage Vc. That is, the voltage waveforms Adp, Bdp, and Cdp are voltage waveforms that start with the voltage Vc and end with the voltage Vc. Therefore, in the print mode, the drive signal generation circuit 50 outputs the drive signal COM having a voltage waveform in which the voltage waveforms Adp, Bdp, and Cdp are continuous in the period Ta.

  Then, the voltage waveform Adp is supplied to the piezoelectric element 60 in the period T1, and the voltage waveform Bdp is supplied in the period T2, so that a medium amount of ink and a small amount of ink are discharged from the ejection unit 600 in the period Ta. And are discharged. As a result, “large dots” are formed on the medium P. In addition, since the voltage waveform Adp is supplied to the piezoelectric element 60 in the period T1 and the voltage waveform Bdp is not supplied in the period T2, a medium amount of ink is ejected from the ejection unit 600 in the period Ta. As a result, “medium dots” are formed on the medium P. In addition, since the voltage waveform Adp is not supplied to the piezoelectric element 60 in the period T1, and the voltage waveform Bdp is supplied in the period T2, a small amount of ink is ejected from the ejection unit 600 in the period Ta. As a result, “small dots” are formed on the medium P. Further, since the voltage waveforms Adp and Bdp are not supplied to the piezoelectric element 60 in the periods T1 and T2, and the voltage waveform Cdp is supplied in the period T3, the ink is not ejected from the ejection unit 600 in the period Ta, and the micro vibration is generated. To do. In this case, no dots are formed on the medium P.

  Next, an example of the drive signal COM in the standby mode, the transition mode, and the sleep mode will be described. Illustration of an example of the drive signal COM in the standby mode, the transition mode, and the sleep mode is omitted.

In the standby mode, transition mode, and sleep mode, ink is not ejected onto the medium P. Therefore, the periods T1, T2, and T3 are not defined. Therefore, in the standby mode, the transition mode, and the sleep mode, the latch signal LAT and the change signal CH are L level signals.

  In the standby mode, the drive signal generation circuit 50 performs control so that the voltage value of the drive signal COM approaches the voltage value of the reference voltage signal VBS.

  In the sleep mode, the drive signal generation circuit 50 stops operating. Here, the operation of the drive signal generation circuit 50 is stopped when the drive data signal DRV for stopping the generation of the drive signal COM is supplied to the drive signal generation circuit 50, specifically, the drive The signal generation circuit 50 includes outputting the ground potential as the drive signal COM.

  The transition mode is an operation mode during the transition from the standby mode to the sleep mode as described above. In the present embodiment, the drive signal generation circuit 50 controls the voltage value of the drive signal COM to approach the voltage value of the reference voltage signal VBS before transition to the transition mode, and stops operation after transition to the transition mode.

  FIG. 8 is a block diagram showing an electrical configuration of the discharge module 21 and the drive IC 80. As shown in FIG. 8, the drive IC 80 includes a selection control circuit 210 and a plurality of selection circuits 230.

  The selection control circuit 210 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, an operation mode signal MC, and a voltage VHV-TG. The selection control circuit 210 is provided with a set of a shift register 212 (S / R), a latch circuit 214, and a decoder 216 corresponding to each of the ejection units 600. That is, the head unit 20 is provided with a set of shift registers 212, latch circuits 214, and decoders 216 as many as the total number n of the ejection units 600.

  The shift register 212 temporarily holds 2-bit print data [SIH, SIL] included in the print data signal SI for each corresponding ejection unit 600.

  Specifically, the number of stages of shift registers 212 corresponding to the ejection unit 600 are connected in cascade, and the serially supplied print data signal SI is sequentially transferred to the subsequent stage according to the clock signal SCK. In FIG. 8, in order to distinguish the shift register 212, the first stage, the second stage,..., And the nth stage are shown in order from the upstream side to which the print data signal SI is supplied.

  Each of the n latch circuits 214 latches the print data [SIH, SIL] held in the corresponding shift register 212 at the rising edge of the latch signal LAT.

  Each of the n decoders 216 decodes the 2-bit print data [SIH, SIL] latched by the corresponding latch circuit 214 and the 2-bit operation mode data [MCH, MCL] included in the operation mode signal MC. The selection signal S is generated and supplied to the selection circuit 230.

  The selection circuit 230 is provided corresponding to each of the ejection units 600. That is, the number of selection circuits 230 included in one head unit 20 is the same as the total number n of ejection units 600 included in the head unit 20. The selection circuit 230 controls the supply of the drive signal COM to the piezoelectric element 60 based on the selection signal S supplied from the decoder 216.

  FIG. 9 is a circuit diagram showing an electrical configuration of the selection circuit 230 corresponding to one ejection unit 600.

  As illustrated in FIG. 9, the selection circuit 230 includes an inverter 232 (NOT circuit) and a transfer gate 234. The transfer gate 234 includes a transistor 235 that is an NMOS transistor and a transistor 236 that is a PMOS transistor.

  The selection signal S is supplied from the decoder 216 to the gate terminal of the transistor 235. The selection signal S is logically inverted by the inverter 232 and is also supplied to the gate terminal of the transistor 236.

  The drain terminal of the transistor 235 and the source terminal of the transistor 236 are connected to the terminal TG-In. A drive signal COM is supplied to the terminal TG-In. Then, the transistor 235 and the transistor 236 are controlled to be turned on or off according to the selection signal S, so that the drive signal VOUT is output from the terminal TG-Out to which the source terminal of the transistor 235 and the drain terminal of the transistor 236 are connected in common. And supplied to the discharge module 21. In the following description, the case where the transistor 235 and the transistor 236 of the transfer gate 234 are controlled to be in a conductive state is referred to as controlling the transfer gate 234 to be on, and the transistor 235 and the transistor 236 are in a non-conductive state. The controlled case may be referred to as controlling the transfer gate 234 off.

  Next, the decoding contents of the decoder 216 will be described with reference to FIG. FIG. 10 is a diagram showing the decoding contents in the decoder 216.

  The decoder 216 receives 2-bit print data [SIH, SIL], 2-bit operation mode data [MCH, MCL], a latch signal LAT, and a change signal CH.

  When the operation mode data [MCH, MCL] is in the print mode [1, 1], the decoder 216 outputs the print data [SIH, M2] in each of the periods T1, T2, T3 defined by the latch signal LAT and the change signal CH. A selection signal S having a logic level based on SIL] is output.

  Specifically, when the print data [SIH, SIL] is [1, 1] that defines “large dots” in the print mode, the decoder 216 sets the H level in the period T1, the H level in the period T2, and the period T3. The selection signal S which becomes L level is output.

  Further, when the print data [SIH, SIL] is [1, 0] that defines “medium dot” in the print mode, the decoder 216 is at the H level in the period T1, the L level in the period T2, and the L level in the period T3. A selection signal S is output.

  Further, when the print data [SIH, SIL] is [0, 1] defining “small dots” in the print mode, the decoder 216 is at the L level in the period T1, the H level in the period T2, and the L level in the period T3. A selection signal S is output.

  Further, when the print data [SIH, SIL] is [0, 0] that defines “fine vibration” in the print mode, the decoder 216 is at the L level in the period T1, the L level in the period T2, and the H level in the period T3. A selection signal S is output.

  The decoder 216 determines the logic level of the selection signal S regardless of the print data [SIH, SIL] and the periods T1, T2, and T3 in the standby mode, the transition mode, and the sleep mode.

  Specifically, the decoder 216 outputs an H level selection signal S in the standby mode in which the operation mode data [MCH, MCL] is [1, 0].

  The decoder 216 outputs an L level selection signal S when the operation mode data [MCH, MCL] is in the transition mode [0, 0].

  The decoder 216 outputs an L level selection signal S in the sleep mode in which the operation mode data [MCH, MCL] is [0, 1].

  Here, the logic level of the selection signal S is level-shifted to a high amplitude logic based on the voltage VHV-TG by a level shifter (not shown).

  An operation in which the drive signal VOUT based on the drive signal COM is generated in the drive IC 80 described above and supplied to the ejection unit 600 included in the ejection module 21 will be described with reference to FIG.

  FIG. 11 is a diagram for explaining the operation of the drive IC 80 in the print mode.

  In the print mode, the print data signal SI is serially supplied in synchronization with the clock signal SCK and sequentially transferred in the shift register 212 corresponding to the ejection unit 600. When the supply of the clock signal SCK is stopped, the print data [SIH, SIL] corresponding to the ejection unit 600 is held in each of the shift registers 212. The print data signal SI is supplied in the order corresponding to the last n stages,..., 2 stages, and 1 stage of the ejection unit 600 in the shift register 212.

  Here, when the latch signal LAT rises, each of the latch circuits 214 latches the print data [SIH, SIL] held in the corresponding shift register 212 at the same time. In FIG. 11, LT1, LT2,..., LTn indicate print data [SIH, SIL] latched by the latch circuit 214 corresponding to the first, second,.

  The decoder 216 outputs a logic level selection signal S according to the contents shown in FIG. 10 in each of the periods T1, T2, and T3 in accordance with the dot size defined by the latched print data [SIH, SIL]. To do.

  When the print data [SIH, SIL] is [1, 1], the selection circuit 230 selects the voltage waveform Adp in the period T1, selects the voltage waveform Bdp in the period T2, and selects the voltage waveform Bdp in the period T3. The voltage waveform Cdp is not selected. As a result, the drive signal VOUT corresponding to the large dot shown in FIG.

  When the print data [SIH, SIL] is [1, 0], the selection circuit 230 selects the voltage waveform Adp in the period T1 according to the selection signal S, does not select the voltage waveform Bdp in the period T2, and The voltage waveform Cdp is not selected at T3. As a result, the drive signal VOUT corresponding to the medium dot shown in FIG.

  When the print data [SIH, SIL] is [0, 1], the selection circuit 230 does not select the voltage waveform Adp in the period T1 and selects the voltage waveform Bdp in the period T2 according to the selection signal S. The voltage waveform Cdp is not selected at T3. As a result, the drive signal VOUT corresponding to the small dots shown in FIG.

  When the print data [SIH, SIL] is [0, 0], the selection circuit 230 does not select the voltage waveform Adp in the period T1 and selects the voltage waveform Bdp in the period T2, according to the selection signal S. The voltage waveform Cdp is not selected at T3. As a result, the drive signal VOUT corresponding to the slight vibration shown in FIG.

  Printing is not performed in the standby mode, transition mode, and sleep mode. Therefore, in the standby mode, transition mode, and sleep mode in the first embodiment, in addition to the latch signal LAT and the change signal CH described above, the clock signal SCK and the print data signal SI are also L level signals. Therefore, the shift register 212 and the latch circuit 214 do not operate. Accordingly, in the standby mode, the transition mode, and the sleep mode, as described above, the decoder 216 determines the logic level of the selection signal S according to the operation mode signal MC.

  In the standby mode in which the operation mode data [MCH, MCL] is [1, 0], the selection circuit 230 generates a drive signal COM having a voltage value equivalent to the reference voltage signal VBS according to the supplied H level selection signal S. select. As a result, a drive signal VOUT having a voltage value equivalent to the reference voltage signal VBS is supplied to the ejection unit 600.

  In the transition mode in which the operation mode data [MCH, MCL] is [0, 0], the selection circuit 230 makes the transfer gate 234 nonconductive according to the L level selection signal S supplied. As a result, the drive signal COM is not supplied to the ejection unit 600 as the drive signal VOUT.

  In the sleep mode in which the operation mode data [MCH, MCL] is [0, 1], the selection circuit 230 does not select the drive signal COM as the drive signal VOUT according to the L level selection signal S supplied. As a result, the voltage previously supplied to the piezoelectric element 60 is held.

1.5 Configuration and Operation of Discharge Unit Next, the configuration and operation of the discharge module 21 and the discharge unit 600 will be described. FIG. 12 is an exploded perspective view of the discharge module 21. FIG. 13 is a cross-sectional view taken along the line III-III in FIG.

  As shown in FIGS. 12 and 13, the discharge module 21 includes a substantially rectangular channel substrate 670 elongated in the direction X. On one surface side in the direction Z of the flow path substrate 670, a pressure chamber substrate 630, a vibration plate 621, a plurality of piezoelectric elements 60, a housing portion 640, and a sealing body 610 are provided. A nozzle plate 632 and a vibration absorber 633 are provided on the other surface side in the direction Z of the flow path substrate 670. Each configuration of the discharge module 21 is a substantially rectangular member that is long in the direction X like the flow path substrate 670, and is bonded to each other using an adhesive or the like.

  As shown in FIG. 12, the nozzle plate 632 is a plate-like member on which a plurality of nozzles 651 arranged in the direction X are formed. Such a nozzle 651 is provided in the nozzle plate 632 and is an opening portion communicating with a cavity 631 described later.

  The flow path substrate 670 is a plate-like member for forming an ink flow path. As shown in FIGS. 12 and 13, the channel substrate 670 is formed with an opening 671, a supply channel 672, and a communication channel 673. The opening 671 is a long through hole extending along the direction X that penetrates in the direction Z and is formed in common in the plurality of nozzles 651. The supply flow path 672 and the communication flow path 673 are through holes formed corresponding to the plurality of nozzles 651. Further, as shown in FIG. 13, a relay channel 674 formed in common in the plurality of supply channels 672 is provided on one surface in the direction Z of the channel substrate 670. The relay channel 674 communicates the opening 671 and the plurality of supply channels 672.

  The housing portion 640 is a structure manufactured by, for example, injection molding of a resin material, and is fixed to the other surface in the direction Z of the flow path substrate 670. As shown in FIG. 13, a supply channel 641 and a supply port 661 are formed in the housing portion 640. The supply channel 641 is a recess corresponding to the opening 671 of the channel substrate 670, and the supply port 661 is a through hole communicating with the supply channel 641. A space in which the opening 671 of the flow path substrate 670 and the supply flow path 641 of the casing 640 communicate with each other functions as a reservoir that stores ink supplied from the supply port 661.

  The vibration absorber 633 is configured to absorb pressure fluctuations that occur inside the reservoir. Specifically, the vibration absorber 633 is configured so that the opening 671, the relay flow path 674, and the plurality of supply flow paths 672 formed in the flow path substrate 670 are closed to form the bottom surface of the reservoir. It is fixed to one surface side in the direction Z of 670. Such a vibration absorber 633 includes, for example, a compliance substrate that is a flexible sheet member capable of elastic deformation.

  As shown in FIGS. 12 and 13, the pressure chamber substrate 630 is a plate-like member in which a plurality of cavities 631 corresponding to the plurality of nozzles 651 are formed. The plurality of cavities 631 have a long shape along the direction Y, and are provided side by side along the direction X. One end portion in the direction Y of the cavity 631 communicates with the supply flow path 672, and the other end portion in the direction Y of the cavity 631 communicates with the communication flow path 673.

  As shown in FIGS. 12 and 13, a diaphragm 621 is fixed to the surface of the pressure chamber substrate 630 opposite to the surface to which the flow path substrate 670 is connected. The diaphragm 621 is an elastically deformable plate member. Specifically, as shown in FIG. 13, the flow path substrate 670 and the vibration plate 621 face each other with an interval inside each cavity 631. That is, the diaphragm 621 constitutes an upper surface that is a part of the wall surface of the cavity 631.

  The cavity 631 is located between the flow path substrate 670 and the vibration plate 621 and functions as a pressure chamber that applies pressure to the ink filled in the cavity 631.

  As shown in FIGS. 12 and 13, a plurality of piezoelectric elements 60 are provided on the surface of the diaphragm 621 opposite to the cavity 631. In other words, the diaphragm 621 is provided between the cavity 631 and the piezoelectric element 60. The plurality of piezoelectric elements 60 are provided side by side in the direction X so as to correspond to the plurality of cavities 631. Then, the diaphragm 621 vibrates in conjunction with the deformation of the piezoelectric element 60, whereby the pressure inside the cavity 631 fluctuates and ink is ejected from the nozzles 651. Specifically, the piezoelectric element 60 is an actuator that is deformed by the supply of the drive signal VOUT, and the piezoelectric element 60 has a structure in which the piezoelectric body 601 is sandwiched between a pair of electrodes 611 and 612 as shown in FIG. . Then, the drive signal VOUT is supplied to the electrode 611, and the reference voltage signal VBS is supplied to the electrode 612. In this case, in the piezoelectric element 60, the central portion of the piezoelectric body 601 is deformed in the vertical direction with respect to both end portions together with the diaphragm 621 in accordance with the potential difference between the electrode 611 and the electrode 612. Then, ink is ejected from the nozzle 651 as the piezoelectric element 60 is deformed. Here, the diaphragm 621 functions as a diaphragm that is displaced by the piezoelectric element 60 and expands / reduces the internal volume of the cavity 631 filled with ink. The electrode 611 included in the piezoelectric element 60 is an example of the first electrode, and the electrode 612 is an example of the second electrode.

12 and 13 is a structure that protects the plurality of piezoelectric elements 60 and reinforces the mechanical strength of the pressure chamber substrate 630 and the vibration plate 621. For example, the sealing member 610 is bonded to the vibration plate 621 with an adhesive. Fixed. A plurality of piezoelectric elements 60 are housed inside a recess formed in a surface of the sealing body 610 facing the diaphragm 621.

  In the discharge module 21 configured as described above, a configuration including the piezoelectric element 60, the cavity 631, the diaphragm 621, and the nozzle 651 is the discharge unit 600.

  FIG. 14 is a diagram illustrating an example of an arrangement of the discharge module 21 and a plurality of nozzles 651 provided in the discharge module 21 when the liquid discharge apparatus 1 is viewed in plan along the direction Z. In FIG. 14, the head unit 20 will be described as including four ejection modules 21.

  As shown in FIG. 14, each ejection module 21 is formed with a nozzle row L composed of a plurality of nozzles 651 provided in a row in a predetermined direction. Each nozzle row L is formed by n nozzles 651 arranged in a row along the direction X.

  The nozzle row L shown in FIG. 14 is an example and may have a different configuration. For example, in each nozzle row L, n nozzles 651 may be arranged in a staggered manner so that the even-numbered nozzles 651 and odd-numbered nozzles 651 from the end have different positions in the direction Y. Further, each nozzle row L may be formed in a direction different from the direction X. In the first embodiment, the number of nozzle rows L provided in each ejection module 21 is exemplified as “1”, but each ejection module 21 is formed with nozzle rows L of “2” or more. May be.

  Here, in the first embodiment, the n nozzles 651 forming the nozzle row L are provided at a high density of 300 or more per inch in the discharge module 21. Therefore, in the ejection module 21, n piezoelectric elements 60 are also provided with high density corresponding to the n nozzles 651.

  In the first embodiment, the piezoelectric body 601 used for the piezoelectric element 60 is preferably a thin film having a thickness of, for example, 1 μm or less. Thereby, the displacement amount of the piezoelectric element 60 with respect to the potential difference between the electrode 611 and the electrode 612 can be increased.

  Here, the operation of discharging ink discharged from the nozzles 651 will be described with reference to FIG. FIG. 15 is a diagram for explaining the relationship between displacement and ejection of the piezoelectric element 60 and the diaphragm 621 when the drive signal VOUT is supplied to the piezoelectric element 60. FIG. 15 is a cross-sectional view when two of the plurality of piezoelectric elements 60, the cavity 631, and the nozzle 651 included in the discharge module 21 are viewed from the direction Y. FIG. 15 (1) schematically shows displacement of the piezoelectric element 60 and the diaphragm 621 when the voltage Vc is supplied as the drive signal VOUT. FIG. 15B shows the piezoelectric element 60 and the diaphragm 621 when the voltage value of the drive signal VOUT supplied to the piezoelectric element 60 is controlled so as to approach the reference voltage signal VBS from the voltage Vc. The displacement is schematically shown. Further, (3) in FIG. 15 shows the piezoelectric element 60 and the diaphragm when the voltage value of the drive signal VOUT supplied to the piezoelectric element 60 is controlled to be farther from the reference voltage signal VBS than the voltage Vc. A displacement of 621 is schematically shown.

In the state shown in FIG. 15A, the piezoelectric element 60 and the diaphragm 621 are moved in the direction Z according to the potential difference between the drive signal VOUT supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612. It is bent. At this time, the voltage Vc is supplied to the electrode 611 as the drive signal VOUT. The voltage Vc is a voltage value at the start timing and end timing of the voltage waveforms Adp, Bdp, Cdp as described above. That is, the state of the piezoelectric element 60 and the diaphragm 621 shown in (1) of FIG. 15 becomes the reference state of the piezoelectric element 60 in the printing mode.

  When the voltage value of the drive signal VOUT is controlled so as to approach the voltage value of the reference voltage signal VBS, as shown in (2) of FIG. 15, along the direction Z of the piezoelectric element 60 and the diaphragm 621. The resulting displacement is reduced. At this time, the internal volume of the cavity 631 increases, and ink is supplied to the cavity 631 from the reservoir.

  Thereafter, the voltage value of the drive signal VOUT is controlled so as to be separated from the voltage value of the reference voltage signal VBS. At this time, as shown in (3) of FIG. 15, the displacement along the direction Z of the piezoelectric element 60 and the diaphragm 621 increases. At this time, the internal volume of the cavity 631 is reduced, and the ink filled in the cavity 631 is ejected from the nozzle 651.

  In the first embodiment, when the drive signal VOUT is supplied to the piezoelectric element 60, the states (1) to (3) in FIG. 15 are repeated. As a result, ink is ejected from the nozzles 651 and dots are formed on the medium P. Note that the displacement of the piezoelectric element 60 and the diaphragm 621 shown in (1) to (3) of FIG. 15 is caused by a potential difference between the drive signal VOUT supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612. As it increases, it increases along the direction Z. In other words, the ejection amount of ink ejected from the nozzles 651 is controlled according to the potential difference between the drive signal VOUT and the reference voltage signal VBS.

  Note that the displacement of the piezoelectric element 60 and the diaphragm 621 with respect to the drive signal VOUT shown in FIG. 15 is merely an example. For example, when the potential difference between the drive signal VOUT and the reference voltage signal VBS is large, ink is supplied to the cavity 631. Is drawn, and ink filled in the cavity 631 may be ejected from the nozzle 651 when the potential difference between the drive signal VOUT and the reference voltage signal VBS becomes small.

1.6 Details of Transition Mode and Discharge of Piezoelectric Element As described above, in the sleep mode, the transfer gate 234 included in the selection circuit 230 is controlled to be off. Ideally, the voltage and current supplied to the electrode 611 in the sleep mode are blocked by the transfer gate 234. Accordingly, the electrode 611 holds the voltage immediately before the transfer gate 234 is controlled to be turned off. Accordingly, the piezoelectric element 60 is displaced in the sleep mode by bringing the voltage supplied to the electrode 611 immediately before the transfer gate 234 is controlled to be off to the voltage of the reference voltage signal VBS supplied to the electrode 612. Can be reduced.

  However, the transfer gate 234 and the piezoelectric element 60 have a resistance component. Therefore, even when the transfer gate 234 is controlled to be turned off, a leak current is supplied to the electrode 611 via the resistance components of the transfer gate 234 and the piezoelectric element 60. Therefore, charges caused by the leakage current are accumulated in the electrode 611. Therefore, the voltage value of the electrode 611 increases, and there is a possibility that unintended displacement occurs in the piezoelectric element 60.

  FIG. 16 is a diagram schematically showing displacement of the piezoelectric element 60 and the diaphragm 621 when the voltage value of the electrode 611 is increased by a leakage current. FIG. 16 is a cross-sectional view of two of the plurality of piezoelectric elements 60, the cavities 631, and the nozzles 651 included in the discharge module 21 when viewed from the direction Y. FIG. 16A shows the displacement of the piezoelectric element 60 and the diaphragm 621 immediately after the transition to the sleep mode. FIG. 16B shows the displacement of the piezoelectric element 60 and the diaphragm 621 when electric charges are accumulated in the electrode 611 due to leakage current generated in the transfer gate 234 and the piezoelectric element 60. Yes.

  As shown in FIG. 16 (1), the piezoelectric element 60 immediately after transitioning to the sleep mode is displaced based on the potential difference between the voltage of the electrode 611 and the voltage of the electrode 612. At this time, the electrode 611 holds the voltage immediately before the transition to the sleep mode. That is, the voltage of the electrode 611 immediately after the transition to the sleep mode is a voltage assumed to be held by the electrode 611. Therefore, the piezoelectric element 60 is displaced within the assumed range, and the diaphragm 621 is similarly displaced within the assumed range. At this time, a stress F1 within an assumed range is generated at the contact α between the diaphragm 621 and the cavity 631.

  Note that FIG. 16 (1) illustrates a case where the voltage of the electrode 611 and the voltage of the electrode 612 immediately before the transition to the sleep mode are different, but the voltage of the electrode 611 and the voltage of the electrode 612 are equivalent. Preferably, the voltage value is In this case, the piezoelectric element 60 and the diaphragm 621 are not displaced.

  When charges due to leakage current or the like are accumulated in the electrode 611, the potential difference between the voltage of the electrode 611 and the voltage of the electrode 612 becomes large, and as shown in (2) of FIG. Displacement increases. Therefore, the displacement of the diaphragm 621 also increases. At this time, a larger stress F2 than expected may occur at the contact α between the diaphragm 621 and the cavity 631.

  Further, the stress generated at the contact point between the diaphragm 621 and the cavity 631 may vary depending on the position of the contact point between the diaphragm 621 and the cavity 631 in the direction Y. Specifically, the stress generated at the contact point between the vibration plate 621 and the cavity 631 is a contact point between the vibration plate 621 and the cavity 631, and is larger at a point where the displacement in the direction Z of the vibration plate 621 becomes maximum. Stress is generated.

  As a factor of the displacement that occurs in the diaphragm 621, for example, natural vibration that occurs in the diaphragm 621 can be cited. FIG. 17 is a plan view when the diaphragm 621 is viewed from the direction Z. FIG. As shown in FIG. 17, the cavity 631 in the present embodiment has a long shape along the direction Y, and the vibration plate 621 may generate a natural vibration along the direction Y. Such natural vibration occurs in a vibration region D between the first contact DL where the diaphragm 621 and the cavity 631 are in contact with the second contact DR.

  FIG. 18 is a diagram illustrating a case where primary natural vibration is generated in the diaphragm 621. As shown in FIG. 18, when primary natural vibration occurs in the vibration plate 621, the displacement ΔD of the vibration plate 621 caused by the natural vibration becomes maximum at the central portion of the vibration region D. Specifically, in the vibration region D, when the distance from the first contact DL to the second contact DR is d, the distance from the first contact DL is d / 2 and the distance from the second contact DR is The displacement ΔD of the diaphragm 621 is maximized at a point where d / 2.

  FIG. 19 is a diagram illustrating a case where tertiary natural vibration is generated in the diaphragm 621. As shown in FIG. 19, when tertiary natural vibration is generated in the diaphragm 621, the displacement ΔD of the diaphragm 621 caused by the natural vibration is a distance d / 2 from the first contact DL and is second. It becomes the maximum at a point where the contact DR is d / 2, a point where the distance from the first contact DL is d / 6, and a distance where the distance from the second contact DR is d / 6.

  As described above, in the direction Y, a larger stress F2 may be applied to the contact α between the diaphragm 621 and the cavity 631 at the point where the displacement ΔD of the diaphragm 621 becomes maximum.

  Further, in an operation mode that continues for a long time such as a sleep mode, the stress F2 may be continuously applied to the contact α of the diaphragm 621 for a long time, and as a result, the diaphragm 621 may crack. In addition, when the vibration plate 621 is shifted to the printing mode in a state where a larger displacement than expected is generated, there is a possibility that an unnecessary load is applied to the vibration plate 621 due to the displacement of the piezoelectric element 60 during ink ejection. As a result, the diaphragm 621 may be cracked.

  If a crack occurs in the vibration plate 621, ink filled in the cavity 631 leaks from the crack. For this reason, there is a possibility that variations in the amount of ink ejected with respect to changes in the internal volume of the cavity 631 occur. As a result, the ink ejection accuracy deteriorates.

  Further, when the ink leaking from the crack adheres to both the electrodes 611 and 612, a current path through the ink is formed between the electrode 611 and the electrode 612. As a result, the voltage value of the reference voltage signal VBS supplied to the electrode 612 may vary. In the liquid ejection device 1 shown in the first embodiment, the reference voltage signal VBS is supplied to the plurality of electrodes 612 in common. Therefore, when the voltage value of the reference voltage signal VBS varies, the displacement of the plurality of piezoelectric elements 60 is affected. As a result, the discharge accuracy of the entire liquid discharge apparatus 1 may be affected.

  Therefore, in the first embodiment, an unintended potential difference is generated in the electrodes 611 and 612 of the piezoelectric element 60, so that unintended displacements in the piezoelectric element 60 and the diaphragm 621 are continuously generated for a long time. Three discharge means for discharging the charges of the electrodes 611 and 612 are provided.

  FIG. 20 is a view for explaining a discharging means for discharging the electric charge of the piezoelectric element 60.

  In FIG. 20, the parasitic diodes 241, 242, 243, and 244 formed on the transfer gate 234 are indicated by broken lines.

  The first discharge means discharges electric charge through the first discharge path A shown in FIG. Specifically, in the first discharging means, the electric charge stored between the terminal TG-Out and the electrode 611 through the plurality of parasitic diodes formed in the transfer gate 234, and the terminal Com-Out and the terminal TG -Releases the charge stored between In.

  Here, the details of the parasitic diodes 241, 242, 243, and 244 formed in the transfer gate 234 will be specifically described with reference to FIG.

  FIG. 21 is a cross-sectional view schematically showing the transistors 235 and 236 constituting the transfer gate 234.

  As shown in FIG. 21, the transistor 235 includes polysilicon 252, N-type diffusion layers 253 and 254, and a plurality of electrodes.

  N-type diffusion layers 253 and 254 are formed on P substrate 251 so as to be separated from each other. The polysilicon 252 is formed between the N-type diffusion layer 253 and the N-type diffusion layer 254 via an insulating layer (not shown).

  An electrode 255 is formed on the polysilicon 252. An electrode 256 is formed on the N-type diffusion layer 253. An electrode 257 is formed on the N-type diffusion layer 254.

  The electrode 255 functions as a gate terminal, one of the electrodes 256 and 257 functions as a drain terminal, and the other functions as a source terminal. In the first embodiment, the electrode 256 is described as a drain terminal, and the electrode 257 is described as a source terminal.

  In the transistor 235 configured as described above, a PN junction is formed on each of the contact surface between the P substrate 251 and the N type diffusion layer 253 and the contact surface between the P substrate 251 and the N type diffusion layer 254. Therefore, the transistor 235 is formed with a parasitic diode 243 having the P substrate 251 as an anode and the N-type diffusion layer 253 as a cathode, and a parasitic diode 244 having the P substrate 251 as an anode and the N-type diffusion layer 254 as a cathode. .

  An electrode 258 is formed on the P substrate 251. Since the transistor 235 is formed on the P substrate 251, the electrode 258 functions as a back gate terminal of the transistor 235. Note that a ground potential is supplied to the electrode 258.

  The transistor 236 includes an N-well 261, polysilicon 262, P-type diffusion layers 263 and 264, and a plurality of electrodes.

  The P-type diffusion layers 263 and 264 are formed on the N well 261 formed on the P substrate 251 so as to be separated from each other. The polysilicon 262 is formed between the P-type diffusion layer 263 and the P-type diffusion layer 264 with an insulating layer (not shown) interposed therebetween.

  An electrode 265 is formed on the polysilicon 262. An electrode 266 is formed on the P-type diffusion layer 263. An electrode 267 is formed on the P-type diffusion layer 264.

  The electrode 265 functions as a gate terminal, one of the electrodes 266 and 267 functions as a drain terminal, and the other functions as a source terminal. In the first embodiment, the electrode 266 is described as a drain terminal, and the electrode 267 is described as a source terminal.

  In the transistor 236 configured as described above, a PN junction is formed on each of the contact surface between the N well 261 and the P type diffusion layer 263 and the contact surface between the N well 261 and the P type diffusion layer 264. Therefore, the transistor 236 is formed with a parasitic diode 242 having the P-type diffusion layer 263 as an anode and the N-well 261 as a cathode, and a parasitic diode 241 having the P-type diffusion layer 264 as an anode and the N-well 261 as a cathode. .

  An electrode 268 is formed in the N well 261. Since the transistor 236 is formed in the N well 261, the electrode 268 functions as a back gate terminal of the transistor 236. Note that the voltage VHV-TG is supplied to the electrode 268.

  Returning to FIG. 20, the first discharging means through the first discharging path A including the parasitic diodes 241, 242, 243, and 244 described above will be described.

  In the first discharging means, first, the H level discharge control signal DIS 1 is supplied to the power supply control signal generation circuit 430.

  The discharge control signal DIS1 supplied to the power supply control signal generation circuit 430 is supplied to the transistor 432 via the inverter 431. Thereby, the transistor 432 is controlled to be turned off.

As described above, when the transistor 432 is controlled to be turned off, the transistor 473 of the power supply switching circuit 70 is controlled to be turned on. When the transistor 473 is controlled to be on, the voltage VHV-TG becomes a ground potential supplied through the resistor 475. As a result, the electrode 268 of the transistor 236 constituting the transfer gate 234 becomes the ground potential. Therefore, the potential of the node a to which the terminal COM-Out and the terminal TG-In are connected becomes the ground potential via the parasitic diode 241. Similarly, the potential of the node b where the terminal TG-Out and the electrode 611 are connected becomes the ground potential via the parasitic diode 242.

  In other words, the electric charge stored in the node a is discharged through the parasitic diode 241, the resistor 475, and the transistor 473. Similarly, the electric charge stored in the node b passes through the parasitic diode 242, the resistor 475, and the transistor 473. Is released through.

  As described above, in the first discharging means, the power supply switching circuit 70 sets the potential of the voltage VHV-TG to the ground potential based on the discharge control signal DIS1. Thereby, the electric charge stored in the node a and the node b is discharged through the parasitic diodes 241 and 242. Therefore, accumulation of unintended charges on the electrode 611 is reduced.

  Further, the charges at the node a and the node b released by the first discharge means are the charges at the terminals TG-In and TG-Out of the transfer gate 234. Therefore, the discharge of electric charge by the first discharge means is possible regardless of whether the transfer gate 234 is controlled to be on or off. For this reason, the possibility that unintended charges are stored in the electrode 611 can be further reduced.

  Note that the configuration of the power supply switching circuit 70 is not limited to the above-described configuration, and may be any configuration that can switch the potential of the electrode 268 of the transistor 236 to the ground potential.

  Next, the second discharging means will be described. In the second discharge means, the electric charge stored in the node a is discharged through the second discharge path B including the LC discharge circuit 530.

  When discharging electric charges by the second discharge means, first, the H level discharge control signal DIS2 is supplied to the transistor 532 of the LC discharge circuit 530. Thereby, the transistor 532 is controlled to be turned on. Therefore, the potential of the node a becomes a ground potential supplied through the resistors 571 and 531 and the transistor 532. In other words, the electric charge stored in the node a is discharged through the resistors 571 and 531 and the transistor 532.

  When the operation of the drive signal generation circuit 50 is stopped, the voltage VHV may be supplied to the node a via the resistors 572 and 571. In the second discharge means, the charge of the node a can be released, so that the charge caused by the voltage VHV can be reduced in the node a.

  As described above, since the second discharging means can discharge the charge of the node a, the potential of the node a can be lowered. Therefore, leakage current generated from the terminal TG-In of the transfer gate 234 to the terminal TG-Out is reduced. That is, an increase in the voltage at the node b due to the leakage current can be reduced. Therefore, the possibility that unintended charges are stored in the electrode 611 can be further reduced.

  Note that the LC discharge circuit 530 may have any structure that can discharge the charge of the node a. For example, the LC discharge circuit 530 is provided at a connection point where the source terminal of the transistor 551 and the drain terminal of the transistor 552 are connected in common. Also good.

  Next, the third discharging means will be described. In the third discharge means, the charge stored in the node c to which the electrode 612 and the terminal Vbs-Out are connected is discharged through the third discharge path C including the transistor 453 of the reference voltage signal generation circuit 450.

  When discharging the charge by the third discharging means, first, the H level discharge control signal DIS3 is supplied to the transistor 453 of the reference voltage signal generation circuit 450. Thus, the transistor 453 is controlled to be on. Therefore, the potential of the node c becomes a ground potential supplied through the resistor 456 and the transistor 453. In other words, the electric charge stored in the node c is discharged through the resistor 456 and the transistor 453.

  As described above, the piezoelectric element 60 is displaced by the potential difference between the voltage of the electrode 611 and the voltage of the electrode 612. By discharging the charge stored in the node c by the third discharging means, it is possible to reduce the supply of an unintended voltage to the electrode 612. Therefore, it is possible to further reduce the occurrence of unintended displacement in the piezoelectric element 60.

  In the first embodiment, the discharge of electric charges by the first discharge means, the second discharge means, and the third discharge means described above is executed in the transition mode. Therefore, a method for discharging charges by the first discharge means, the second discharge means, and the third discharge means in the first embodiment will be described with reference to FIG.

  FIG. 22 is a flowchart for explaining the operation in the transition mode.

  First, the control circuit 100 performs control so that the voltage value of the drive signal COM approaches the voltage value of the reference voltage signal VBS before the operation mode transitions to the transition mode (S171). Specifically, the control circuit 100 supplies the drive data generation circuit 50 with the drive data signal DRV in which the voltage value of the drive signal COM is the voltage value of the reference voltage signal VBS. Then, the drive signal generation circuit 50 controls the voltage value of the drive signal COM so as to approach the voltage value of the reference voltage signal VBS based on the supplied drive data signal DRV.

  In the transition mode, the voltage values of both the drive signal COM and the reference voltage signal VBS may fluctuate in the process in which the operation mode transitions to the sleep mode. Therefore, by controlling the voltage value of the drive signal COM to approach the voltage value of the reference voltage signal VBS before shifting to the transition mode, the possibility that an unintended potential difference occurs in the piezoelectric element 60 in the transition mode is reduced. be able to.

  Note that the control so that the voltage value of the drive signal COM approaches the voltage value of the reference voltage signal VBS preferably means that the voltage value of the drive signal COM and the voltage value of the reference voltage signal VBS are the same. In a broad sense, the voltage value may be controlled so as to approach the piezoelectric element 60 so as not to cause an unintended displacement due to the potential difference between the drive signal COM and the reference voltage signal VBS. Specifically, it is preferable to control the potential difference between the drive signal COM and the reference voltage signal VBS to be 2V or less.

  When the voltage value of the drive signal COM and the voltage value of the reference voltage signal VBS are sufficiently close, the control circuit 100 controls the operation mode to the transition mode (S172).

  After the operation mode transitions to the transition mode, the control circuit 100 controls to turn off the transfer gate 234 (S173). As a result, the voltage supplied to the electrode 611 is held at the voltage immediately before the transition to the transition mode, that is, the voltage sufficiently close to the voltage of the reference voltage signal VBS.

  When a predetermined time has elapsed after the transfer gate 234 is controlled to be turned off, the control circuit 100 controls the discharge of electric charges by the second discharge means (S174). Specifically, the control circuit 100 supplies the drive signal generation circuit 50 with the drive data signal DRV for generating the H level discharge control signal DIS2.

  After the transfer gate 234 is controlled to be turned off, the charge stored in the node a is released by the second discharging means, so that the voltage of the node a is lowered. Therefore, leakage current generated in the transfer gate 234 is reduced, and voltage increase of the electrode 611 due to the leakage current is reduced. Note that the discharge of electric charge by the second discharging means may be continuously performed until the mode is changed to the printing mode or the standby mode.

  When a predetermined time has elapsed after the start of the discharge of the charge by the second discharge means, the control circuit 100 controls the discharge of the charge by the third discharge means (S175). Specifically, the control circuit 100 supplies the drive signal generation circuit 50 with a drive data signal DRV for generating the H level discharge control signal DIS3. Before the charge stored in the node b is released by the first discharge means, the voltage supplied to the electrode 612 is discharged to the electrode 611 by releasing the charge stored in the node c by the third discharge means. The increase with respect to the supplied voltage is reduced. That is, it is possible to reduce the occurrence of displacement in the piezoelectric element 60 that is opposite to the displacement that occurs in the piezoelectric element 60 during the printing operation. As a result, the stress generated in the piezoelectric element 60 and the diaphragm 621 can be reduced.

  Note that the discharge of electric charge by the second discharge unit and the discharge of electric charge by the third discharge unit may be performed simultaneously by the control circuit 100, for example, and the discharge of the electric charge by the third discharge unit is first performed. After being executed, the discharge of electric charge by the second discharging means may be executed. Further, the discharge of electric charges by the third discharging means may be continuously performed until the mode is changed to the printing mode or the standby mode.

  Then, when a predetermined time has elapsed after the start of the discharge of charges by the second discharge means and the third discharge means, the control circuit 100 controls the discharge of charges by the first discharge means (S176). Specifically, the control circuit 100 supplies a drive data signal DRV for generating the H level discharge control signal DIS1 to the drive signal generation circuit 50. Thereby, the electric charge stored in the electrode 611 is released. Therefore, the possibility that an unintended voltage is generated in the piezoelectric element 60 is reduced, and the occurrence of an unintended displacement in the piezoelectric element 60 and the diaphragm 621 is reduced. Note that the discharge of electric charge by the first discharging means may be continuously performed until the mode is changed to the printing mode or the standby mode.

  When a predetermined time has elapsed after the discharge of electric charges by the first discharge means, the second discharge means, and the third discharge means described above has started, the control circuit 100 switches the operation mode as shown in FIG. Transition to sleep mode. Note that the discharge of electric charges by the first discharge unit, the second discharge unit, and the third discharge unit may be continuously performed in the sleep mode.

1.7 Anomaly Detection of Drive Signal As described above, in the sleep mode, as described above, the unintended displacement of the piezoelectric element 60 due to the potential difference caused by the accumulation of unintended charges in the piezoelectric element 60 may occur. For example, unintended charges are accumulated in the piezoelectric element 60. Another factor is that the drive signal COM is not normally output in the print mode, and a constant voltage value is continuously output.

Therefore, the liquid ejection apparatus 1 includes a detection circuit 320 that detects whether or not the output of the drive signal COM is within a predetermined range and detects whether or not the drive signal COM is outputting a constant voltage. Further, the liquid ejecting apparatus 1 continuously outputs a constant voltage based on the detection result of the detection circuit 320 as to whether or not the drive signal COM is normal. A determination circuit 350 for determining whether or not

  The factors that cause the drive signal COM to continuously output a constant voltage are that the original drive signal dA supplied to the drive signal generation circuit 50 has not been updated and that the clock signal for updating the original drive signal dA is It is mentioned that it is not supplied. Therefore, in the liquid ejection apparatus 1 according to the first embodiment, the detection circuit 320 detects whether or not the original drive signal dA is updated and whether or not a clock signal for updating the original drive signal dA is supplied. The determination circuit 350 determines whether or not the drive signal COM continuously outputs a constant voltage based on the detection result of the detection circuit 320.

  Details of configurations and operations of the detection circuit 320 and the determination circuit 350 in the first embodiment will be described with reference to FIGS. FIG. 23 is a block diagram showing an electrical configuration of the DAC circuit 310, the detection circuit 320, and the determination circuit 350.

  The DAC circuit 310 includes a DAC interface (I / F) 311, a comparator 312, a latch circuit 313, and a DAC 314.

  The DAC interface 311 is supplied with the clock signal φ1 and the original drive signal dA. Then, the DAC interface 311 takes in the original drive signal dA according to the clock signal φ1 and outputs a signal S1 based on the original drive signal dA to the comparator 312.

  The comparator 312 compares the signal S1 as a data signal supplied this time, and a signal S2 supplied from a latch circuit 313 described later as a data signal supplied last time. Specifically, the comparator 312 outputs the signal S1 to the latch circuit 313 when the comparison result between the signal S1 and the signal S2 is within a predetermined range. On the other hand, the comparator 312 outputs a predetermined data signal to the latch circuit 313 when the comparison result between the signal S1 and the signal S2 is outside the predetermined range.

  The latch circuit 313 latches the data signal input from the comparator 312 at the falling edge of the clock signal φ2. The latch circuit 313 outputs the latched data signal as a signal S2 to the DAC 314, the comparator 312 and the detection circuit 320.

  The DAC 314 converts the signal S2 from digital to analog and outputs the signal S2 to the drive circuit 51 shown in FIG. 4 as an analog original drive signal aA.

  The detection circuit 320 includes an update detection circuit 321, a clock detection circuit 322, a NAND circuit 323, and an oscillation circuit 330.

  The update detection circuit 321 includes latch circuits 324 and 326 and a comparator 325.

  The latch circuit 324 latches the signal S2 at the rising edge of the clock signal φ2 and outputs the signal S2 to the comparator 325 as the signal S3.

  The comparator 325 receives the signal S2 and the signal S3. Then, the comparator 325 compares the signal S2 and the signal S3. Specifically, the comparator 325 outputs an L level signal as the signal S4 when the signals S2 and S3 are the same, and outputs an H level signal as the signal S4 when they are different.

The latch circuit 326 latches the signal S4 at the rising edge of the clock signal φ2. Then, the latch circuit 326 outputs the latched signal S4 to the NAND circuit 323 as a signal S5 that is an output signal of the update detection circuit 321.

  Note that the comparator 325 may compare all the data bits of the input data signal and compare whether the input data signal is the same or different. For example, only the specific data bit may be compared. The comparison may be made to compare whether the input data signals are the same or different. Specifically, only the upper few bits or the lower few bits of the input data signal may be compared.

  The clock detection circuit 322 includes a frequency dividing circuit 327, a latch circuit 328, and a differentiating circuit 329.

  The frequency dividing circuit 327 outputs a signal S6 obtained by dividing the clock signal φ2.

  The latch circuit 328 latches the signal S6 at the rising edge of the clock signal CLK supplied from the oscillation circuit 330 and outputs it as the signal S7.

  The differentiation circuit 329 receives the signal S6 output from the frequency dividing circuit 327 and the signal S7 output from the latch circuit 328. The differentiating circuit 329 calculates and outputs an exclusive OR of the input data signal. That is, the differentiating circuit 329 outputs an H level signal as the signal S8 when the logic level of the signal S6 and the logic level of the signal S7 are different, and outputs an L level signal as the signal S8 in the same case. Then, the differentiation circuit 329 outputs the signal S8 as an output signal of the clock detection circuit 322 to the NAND circuit 323.

  The NAND circuit 323 outputs an L level reset signal RST when both the logic level of the signal S5 output from the update detection circuit 321 and the signal S8 output from the clock detection circuit 322 are H level. The NAND circuit 323 outputs an H level reset signal RST when the logic level of at least one of the signal S5 and the signal S8 is L level. This reset signal RST is supplied to the determination circuit 350 as an output signal of the detection circuit 320.

  The determination circuit 350 includes a counter 351 and a decoder 352.

  When the H level reset signal RST is input, the counter 351 increments the count value at the falling edge of the clock signal CLK and outputs the count value to the decoder 352. In addition, when the L level reset signal RST is input, the counter 351 resets the count value to 0 and outputs the count value to the decoder 352.

  When the count value input from the counter 351 exceeds a predetermined value, that is, when an H level signal is continuously input to the determination circuit 350 for a predetermined period, the decoder 352 generates a constant voltage. Is output, and an error signal ERR is output.

  Here, a method for detecting whether or not the original drive signal dA in the detection circuit 320 is updated and a method for detecting whether or not the clock signal φ2 is supplied will be specifically described with reference to FIGS.

  FIG. 24 is a timing chart for explaining the operation of the detection circuit 320 when the original drive signal dA is updated.

  The DAC interface 311 generates the signal S1 by taking in the supplied original drive signal dA based on the clock signal φ1. Then, the signal S1 is supplied to the comparator 312. Specifically, the DAC interface 311 sequentially receives the 5-bit data signal Da [9-5] and the 5-bit data signal Da [4-0] supplied as the original drive signal dA based on the clock signal φ1. The signal S1 is generated by capturing and combining.

  The comparator 312 compares the signal S1 with the signal S2 input from the latch circuit 313. Then, the comparator 312 outputs the data signal Da based on the comparison result.

  The latch circuit 313 latches the data signal Da output from the comparator 312 as the signal S2 at the falling edge of the clock signal φ2.

  The latch circuit 324 latches the data signal Da latched by the latch circuit 313 at the rising edge of the clock signal φ2 as the signal S3.

  The comparator 325 receives the signal S2 and the signal S3, outputs an L level signal when the input signals are the same, and outputs an H level signal when they are different.

  Specifically, the latch circuit 324 latches the data signal Da as the signal S3 at the rising edge of the clock signal φ2. At this time, the latch circuit 313 holds the data signal Da as the signal S2. Therefore, the same data signal Da is supplied to the comparator 325. As a result, the comparator 325 outputs an L level signal as the signal S4.

  Latch circuit 313 latches data signal Db as signal S2 at the fall of the next clock signal φ2. At this time, the latch circuit 324 holds the data signal Da as the signal S3. Therefore, the comparator 325 receives the data signal Da and the data signal Db that are different data signals. As a result, the comparator 325 outputs an H level signal.

  The latch circuit 326 latches the signal S4 at the rising edge of the clock signal φ2 and before the latch circuit 324 latches the signal S2. Therefore, the latch circuit 326 latches an H level signal as the signal S5 and outputs it to the NAND circuit 323 as an output signal of the update detection circuit 321.

  Next, the operation of the detection circuit 320 when the original drive signal dA is not updated will be described with reference to FIG. FIG. 25 is a timing chart for explaining the operation of the detection circuit 320 when the original drive signal dA is not updated.

  As in the case where the original drive signal dA is updated, the DAC interface 311 sequentially takes and supplies the supplied original drive signal dA based on the clock signal φ1 to generate the signal S1.

  The comparator 312 compares the signal S1 with the signal S2 input from the latch circuit 313. Then, the comparator 312 outputs the data signal Da based on the comparison result.

  The latch circuit 313 latches the data signal Da output from the comparator 312 as the signal S2 at the falling edge of the clock signal φ2.

The latch circuit 324 outputs the data signal Da to the signal S at the rising edge of the clock signal φ2.
Latch as 3. At this time, the latch circuit 313 holds the data signal Da as the signal S2. Therefore, the same data signal Da is supplied to the comparator 325. As a result, the comparator 325 outputs an L level signal as the signal S4.

  When the original drive signal dA is not updated, the latch circuit 313 latches the data signal Da again as the signal S2 at the next falling edge of the clock signal φ2. At this time, the latch circuit 324 holds the data signal Da as the signal S3. Therefore, the same data signal Da is input to the comparator 325. As a result, the comparator 325 outputs an L level signal.

  The latch circuit 326 latches the signal S4 at the rising edge of the clock signal φ2 and before the latch circuit 324 latches the signal S2. Therefore, the latch circuit 326 latches an L level signal as the signal S5 and supplies it to the NAND circuit 323 as an output signal of the update detection circuit 321.

  As described above, the update detection circuit 321 outputs an H level signal as the signal S5 to the NAND circuit 323 when the original drive signal dA is updated, and as the signal S5 when the original drive signal dA is not updated. An L level signal is output to the NAND circuit 323.

  Next, details of a method for detecting whether or not the clock signal φ2 is supplied will be described with reference to FIGS. FIG. 26 is a timing chart for explaining the operation of the detection circuit 320 when the clock signal φ2 is supplied.

  The frequency dividing circuit 327 outputs a signal S6 obtained by dividing the clock signal φ2.

  The latch circuit 328 latches the signal S6 as the signal S7 at the rising edge of the clock signal CLK.

  In the first embodiment, the clock signal CLK has a different period from the clock signal φ2. That is, when the clock signal φ2 is normally input, a timing at which the logic levels of the signal S6 and the signal S7 are different occurs.

  Therefore, when the logic level of the signal S6 changes based on the clock signal φ2 in the period after the latch circuit 328 latches the signal S6 at the rise of the clock signal CLK and until the next rise of the clock signal CLK, the differential circuit 329 The input signal S6 and the signal S7 have different logic levels.

  Differentiating circuit 329 outputs L level signal S8 to NAND circuit 323 as an output signal of clock detection circuit 322 when signal S6 and signal S7 have the same logic level. Further, the differentiating circuit 329 outputs an H level signal S8 to the NAND circuit 323 as an output signal of the clock detection circuit 322 when the signal S6 and the signal S7 have different logic levels. That is, when the clock signal φ2 is supplied, the clock detection circuit 322 outputs an H level signal and an L level signal alternately as the signal S8.

  Next, the operation of the detection circuit 320 when the clock signal φ2 is not supplied will be described with reference to FIG. FIG. 27 is a timing chart for explaining the operation of the detection circuit 320 when the clock signal φ2 is not supplied.

When the clock signal φ2 is not supplied, the frequency dividing circuit 327 continuously outputs the H level or L level signal S6. In the description of FIG. 27, it is assumed that an H level signal is output as the signal S6, but an L level signal may be used.

  The latch circuit 328 latches the signal S6 as the signal S7 at the rising edge of the clock signal CLK.

  The differentiation circuit 329 receives an H level signal S6 and an H level signal S7. Therefore, the L level signal S8 is supplied to the NAND circuit 323 as an output signal of the clock detection circuit 322.

  As described above, when the clock signal φ2 is supplied, the clock detection circuit 322 outputs an output signal in which H level and L level are alternately generated to the NAND circuit 323 as the signal S8. Further, when the clock signal φ2 is not supplied, the clock detection circuit 322 continues to output the L level output signal to the NAND circuit 323 as the signal S8.

  The NAND circuit 323 receives the signal S5 output from the update detection circuit 321 and the signal S8 output from the clock detection circuit 322. The NAND circuit 323 outputs an L level reset signal RST when both the output of the update detection circuit 321 and the output of the clock detection circuit 322 are H level signals.

  As described above, the update detection circuit 321 outputs an H level output signal to the NAND circuit 323 as the signal S5 when the original drive signal dA is updated, and as the signal S5 when the original drive signal dA is not updated. The L level output signal is output to the NAND circuit 323. Further, when the clock signal φ2 is supplied, the clock detection circuit 322 alternately outputs the H level output signal and the L level output signal to the NAND circuit 323 as the signal S8, and the clock signal φ2 is supplied. If not, the L level output signal is continuously output to the NAND circuit 323 as the signal S8.

  Therefore, when the original drive signal dA is updated and the clock signal φ2 is supplied and the NAND circuit 323 outputs the H level signal, the NAND circuit 323 outputs the L level reset signal RST, In other states, an H level reset signal RST is output.

  Next, the operation of the determination circuit 350 will be described with reference to FIGS. FIG. 28 is a timing chart showing the operation of the determination circuit 350 associated with the detection operation of the original drive signal dA in the update detection circuit 321.

  As described above, the update detection circuit 321 outputs an H level signal as the signal S5 when the original drive signal dA is updated.

  The NAND circuit 323 outputs an L level signal when the input signal S5 is at an H level and the signal S8 is at an H level. At this time, the count value output from the counter 351 is reset to zero.

  The update detection circuit 321 outputs an L level signal as the signal S5 when the original drive signal dA is not updated.

  When the input signal S5 is at L level, the NAND circuit 323 outputs a signal at H level regardless of the logic level of the signal S8. At this time, the count value output from the counter 351 is incremented at the falling edge of the clock signal CLK.

  The count value output from the counter 351 is output to the decoder 352. When the count value exceeds a predetermined value, the decoder 352 outputs an error signal ERR.

  Next, the operation of the determination circuit 350 corresponding to the detection operation of the clock signal φ2 in the clock detection circuit 322 will be described with reference to FIG. FIG. 29 is a timing chart showing the operation of determination circuit 350 associated with the detection operation of clock signal φ2 in clock detection circuit 322.

  As described above, when the clock signal φ2 is supplied, the clock detection circuit 322 alternately outputs the signal S8 having a logic level of H level or L level at the timing described above. The NAND circuit 323 outputs an L level signal when the logic level of the signal S8 is an H level and when the signal S5 outputs an H level signal. As a result, the count value output from the counter 351 is reset to zero.

  Further, when the clock signal φ2 is not supplied, the clock detection circuit 322 continuously outputs an L level signal as the signal S8.

  When the logic level of the signal S8 is L level, the NAND circuit 323 outputs an H level signal regardless of the logic level of the signal S5. At this time, the count value output from the counter 351 is incremented at the falling edge of the clock signal CLK.

  The count value output from the counter 351 is input to the decoder 352. The decoder 352 outputs an error signal ERR when the count value exceeds a predetermined value.

  As described above, the determination circuit 350 outputs the error signal ERR when at least one of the update of the original drive signal dA and the supply of the clock signal φ2 is not performed. Thereby, the determination circuit 350 determines whether or not the drive signal COM continuously outputs a constant voltage signal in the print mode. Accordingly, it is possible to detect / determine that the drive signal COM is continuously output as a constant voltage signal in the print mode, and therefore, it can be reduced based on the detection / determination result. Therefore, by continuously supplying an unintended DC voltage to the piezoelectric element 60, it is possible to reduce the unintentional displacement continuously applied to the piezoelectric element 60 and the diaphragm 621.

  Further, as shown in FIG. 2, the error signal ERR is supplied to the control circuit 100. For example, the control circuit 100 changes the operation mode to the transition mode based on the error signal ERR. At this time, as shown in FIG. 22, the voltage value of the drive signal COM is controlled so as to approach the voltage value of the reference voltage signal VBS. Then, the charge of at least one of the electrode 611 and the electrode 612 of the piezoelectric element 60 is released. Thereby, it is possible to further reduce the continuous supply of unintended voltage to the piezoelectric element 60 and the continuous application of unintended displacement to the piezoelectric element 60 and the diaphragm 621.

  Here, the voltage waveforms Adp, Bdp, Cdp of the drive signal COM have a period during which a constant voltage value is generated as shown in FIG. Therefore, the voltage waveform Adp, Bdp, Cdp of the drive signal COM outputs a constant voltage during the time from when the count value is reset to 0 until the decoder 352 outputs the error signal ERR after reaching the predetermined count value. Long enough for the time to do.

1.8 Effects As described above, in the liquid ejection apparatus 1 according to the first embodiment, the detection circuit 320 compares the supplied original drive signal dA with the previous original drive signal dA to perform the original drive. It is detected whether or not the signal dA is updated, and whether or not the clock signal φ2 is supplied is also detected. Thereby, the detection circuit 320 can detect whether or not the drive signal COM is outputting a constant voltage.

  Based on the detection result of the detection circuit 320, the determination circuit 350 measures the period during which the drive signal COM outputs a constant voltage based on the clock signal CLK. Therefore, it is possible to reduce the drive signal COM from outputting a constant voltage for a long time.

  Accordingly, it is possible to reduce the continuous application of the drive signal COM having a constant voltage as the unintended DC voltage to the piezoelectric element 60 for a long time. Therefore, the occurrence of unintended displacement in the piezoelectric element 60 and the diaphragm 621 is reduced.

  In the first embodiment, the detection circuit 320 detects whether or not the voltage of the drive signal COM is outputting a constant voltage based on the digital original drive signal dA. As a result, the influence of noise or the like generated in the drive signal generation circuit 50 is reduced, and the detection accuracy can be increased.

  In the liquid ejection device 1 of the first embodiment, when the drive signal COM supplied to the piezoelectric element 60 outputs a constant voltage for a long time, the voltage value of the drive signal COM supplied to the electrode 611 is The reference voltage signal VBS supplied to the electrode 612 is controlled to approach the voltage value. Therefore, the occurrence of an unintended potential difference between the electrodes 611 and 612 of the piezoelectric element 60 is further reduced, and the possibility of an unintended displacement occurring in the piezoelectric element 60 and the diaphragm 621 is further reduced.

  Furthermore, in the liquid ejection device 1 of the first embodiment, when the drive signal COM supplied to the piezoelectric element 60 continues to output a constant voltage for a long time, the liquid ejection device 1 transits to the transition mode based on the error signal ERR. Accordingly, electric charges of the electrode 611 and the electrode 612 are released. Therefore, the occurrence of an unintended potential difference between the electrodes 611 and 612 of the piezoelectric element 60 is reduced, and the possibility of an unintended displacement occurring in the piezoelectric element 60 and the diaphragm 621 can be further reduced.

  In the first embodiment, the drive circuit 51 that generates the drive signal COM, the detection circuit 320 that detects whether the drive signal COM outputs a constant voltage, and the detection result of the detection circuit 320 are used. A determination circuit that determines whether or not the drive signal COM continuously outputs a constant voltage is provided in the drive signal generation circuit 50. Therefore, generation, detection and determination of the drive signal COM can be detected without depending on the control unit. Therefore, it is possible to reduce the possibility of delays in generation, detection, and determination.

2 Second Embodiment Next, a liquid ejection apparatus 1 according to a second embodiment will be described with reference to FIGS. 30 to 32.

  The liquid ejection apparatus 1 according to the second embodiment is different from the liquid ejection apparatus 1 according to the first embodiment in the configuration of the detection circuit 320. In the following description, descriptions overlapping with the first embodiment are omitted or simplified, and contents different from the first embodiment will be mainly described.

  FIG. 30 is a block diagram showing an electrical configuration of the DAC circuit 310, the detection circuit 320, and the determination circuit 350 in the second embodiment.

  As in the first embodiment, the DAC circuit 310 includes a DAC interface (I / F) 311, a comparator 312, a latch circuit 313, and a DAC 314. The DAC circuit 310 generates an analog original drive signal aA based on the supplied original drive signal dA, and outputs the signal S2 latched by the latch circuit 313 to the detection circuit 320.

  The detection circuit 320 includes a DATA update detection circuit 331, an inverter 335, and an oscillation circuit 330.

  The DATA update detection circuit 331 includes latch circuits 332 and 334 and a comparator 333.

  The latch circuit 332 latches the signal S2 as the signal S11 at the falling edge of the clock signal CLK output from the oscillation circuit 330. In the second embodiment, the clock signal CLK has a different period from the clock signal φ2.

  The comparator S333 receives the signal S2 and the signal S11. Then, the comparator 333 compares whether or not the signal S2 and the signal S11 are the same, and outputs a signal S12 based on the comparison result. Specifically, the comparator 333 outputs an L level signal as the signal S12 when the signal S2 and the signal S11 are the same, and outputs an H level signal as the signal S12 when they are different.

  The latch circuit 334 latches the signal S12 at the rising edge of the clock signal CLK. Then, the latch circuit 334 outputs the signal S13 to the inverter 335 as an output signal of the DATA update detection circuit 331.

  Inverter 335 inverts the logic level of signal S13 and outputs the inverted signal to determination circuit 350 as reset signal RST.

  The determination circuit 350 includes a counter 351 and a decoder 352 as in the first embodiment.

  When the reset signal RST is at the H level, the counter 351 increments the count value and outputs the count value to the decoder 352. When the reset signal RST is at L level, the count value is reset to 0 and output to the decoder 352.

  When the count value input from the counter 351 exceeds a predetermined value, the decoder 352 generates an error signal ERR and outputs the error signal ERR.

  Here, the details of a method for detecting whether or not the original drive signal dA has been updated will be described with reference to FIGS. 31 and 32. FIG. 31 is a timing chart for explaining the operation of the detection circuit 320 when the original drive signal dA is updated.

  The operation of each component included in the DAC circuit 310 is the same as that of the first embodiment, and the description of the operation is omitted.

  The latch circuit 332 latches the data signal Da held as the signal S2 by the latch circuit 313 at the falling edge of the clock signal CLK generated by the oscillation circuit 330, and outputs it as the signal S11. At this time, the latch circuit 313 holds the data signal Da as the signal S2. Therefore, the same data signal Da is supplied to the comparator 333. As a result, the comparator 333 outputs an L level signal as the signal S12.

  When the original drive signal dA is updated, the latch circuit 313 latches the data signal Db as the signal S2 at the falling edge of the clock signal φ2. At this time, the latch circuit 332 holds the data signal Da as the signal S11. Therefore, the comparator 333 is supplied with the data signal Db as the signal S2 and the data signal Da as the signal S11. As a result, the comparator 333 outputs an H level signal as the signal S12.

  The latch circuit 334 latches the signal S12 at the falling edge of the clock signal CLK and before the latch circuit 332 latches the signal S2. As a result, the latch circuit 334 outputs an H level signal as the signal S13 to the inverter 335 as an output signal of the DATA update detection circuit 331.

  The inverter 335 inverts the logic level of the H level signal output from the DATA update detection circuit 331 and outputs an L level reset signal RST to the determination circuit 350.

  Next, the details of the detection method when the original drive signal dA is not updated will be described with reference to FIG. FIG. 32 is a timing chart for explaining the operation of the detection circuit 320 when the original drive signal dA is not updated.

  The operation of each component included in the DAC circuit 310 is the same as that of the first embodiment, and the description of the operation is omitted.

  The latch circuit 332 latches the data signal Da held as the signal S2 by the latch circuit 313 at the falling edge of the clock signal CLK, and outputs it as the signal S11.

  At this time, the latch circuit 313 holds the data signal Da as the signal S2. Therefore, the same data signal Da is supplied to the comparator 333. As a result, the comparator 333 outputs an L level signal as the signal S12.

  When the original drive signal dA has not been updated, the latch circuit 313 latches the data signal Da based on the same original drive signal dA at the falling edge of the clock signal φ2. At this time, the latch circuit 332 holds the data signal Da as the signal S11. Therefore, the same data signal is continuously input to the comparator 333. As a result, the comparator 333 outputs an L level signal as the signal S12.

  The latch circuit 334 latches the signal S12 at the falling edge of the clock signal CLK and before the latch circuit 332 latches the signal S2. As a result, the latch circuit 334 outputs an L level signal as the signal S13 to the inverter 335 as an output signal of the DATA update detection circuit 331.

  Inverter 335 inverts the logic level of the L-level signal output from DATA update detection circuit 331 and outputs an H-level reset signal RST to determination circuit 350.

  When the L level reset signal RST is input, the determination circuit 350 resets the count value output from the counter 351 to the decoder 352, assuming that the original drive signal dA has been updated. On the other hand, when an H level reset signal RST is input, the determination circuit 350 increments the count value output from the counter 351 to the decoder 352 at the falling edge of the clock signal CLK. When the decoder 352 determines that the count value exceeds a predetermined value, the determination circuit 350 outputs an error signal ERR.

  As described above, the determination circuit 350 in the second embodiment outputs the error signal ERR when the original drive signal dA is not updated. Therefore, as in the first embodiment, it is possible to reduce the drive signal COM from continuously outputting a constant voltage in the print mode.

  In the second embodiment, the latch circuit 313 latches at the falling edge of the clock signal φ2. Therefore, when the clock signal φ2 is not supplied, the signal S2 is not updated.

  That is, the detection circuit 320 in the second embodiment also detects whether or not the clock signal φ2 is supplied based on the comparison between the signal S2 supplied to the comparator 333 and the signal S11. Therefore, with respect to the configuration of the detection circuit 320 of the first embodiment, detection of whether or not the original drive signal dA is updated and detection of whether or not the clock signal φ2 is supplied are performed with a simpler configuration. be able to. Therefore, in the liquid ejection device 1 in the second embodiment, it is possible to achieve the same operational effects as in the first embodiment with a smaller configuration.

3 Third Embodiment Next, a liquid ejection apparatus 1 according to a third embodiment will be described with reference to FIGS. 33 and 34.

  The liquid ejection apparatus 1 according to the third embodiment is the first in that the detection circuit 320 detects whether the drive signal COM is constant based on the drive signal COM output from the drive signal generation circuit 50. Different from the embodiment and the second embodiment. Below, the description which overlaps with 1st Embodiment and 2nd Embodiment is abbreviate | omitted or simplified, and the content different from 1st Embodiment and 2nd Embodiment is mainly demonstrated.

  FIG. 33 is a block diagram showing a circuit configuration of the drive signal generation circuit 50 in the third embodiment. As shown in FIG. 33, the detection circuit 320 in the third embodiment detects whether or not the drive signal COM is constant by detecting a signal based on the drive signal COM fed back through the terminal Vfb. .

  FIG. 34 is a circuit diagram showing an electrical configuration of the detection circuit 320 in the third embodiment.

  The detection circuit 320 in the third embodiment includes a differentiation circuit 360, a window comparator circuit 370, a holding circuit 380, and an inverter 390.

  The differentiation circuit 360 includes a comparator 361, a capacitor 362, and a resistor 363.

  The voltage Vref <b> 2 is supplied to the input terminal (+) of the comparator 361. The input terminal (−) of the comparator 361 is connected to one end of the capacitor 362 and one end of the resistor 363. The output end of the comparator 361 is connected to the other end of the resistor 363.

  Further, the other end of the capacitor 362 is connected to a terminal Vfb of the integrated circuit 500 shown in FIG. The voltage Vcom based on the drive signal COM is supplied to the other end of the capacitor 362 through the terminal Vfb.

  The differentiation circuit 360 configured as described above outputs a constant voltage signal based on the voltage Vref2 to the output terminal of the comparator 361 when the voltage value of the voltage Vcom does not fluctuate. On the other hand, when the voltage value of the voltage Vcom fluctuates, a voltage signal having a substantially pulse shape corresponding to the fluctuation is output to the output terminal of the comparator 361.

  The window comparator circuit 370 includes comparators 371 and 372, an inverter 377, and an OR circuit 378.

  The OR circuit 378 inverts each of the signals supplied to the two input terminals, and calculates and outputs a logical sum of the inverted signals.

  The output signal of the differentiation circuit 360 is supplied to the input terminal (−) of the comparator 371. The voltage Vref3 is supplied to the input terminal (+) of the comparator 371. One output terminal of the OR circuit 378 is connected to the output terminal of the comparator 371.

  The output signal of the differentiation circuit 360 is supplied to the input terminal (−) of the comparator 372. A voltage Vref4 smaller than the voltage Vref3 is connected to the input terminal (+) of the comparator 372. The input terminal of the inverter 377 is connected to the output terminal of the comparator 372. The output terminal of the inverter 377 is connected to the other input terminal of the OR circuit 378.

  In the window comparator circuit 370 configured as described above, when the voltage value of the voltage signal input from the differentiation circuit 360 is larger than any of the voltages Vref3 and Vref4, both the comparator 371 and the comparator 372 are at the L level. The signal is output.

  In this case, the OR circuit 378 is supplied with an L level signal output from the comparator 371 and an H level signal obtained by inverting the L level signal output from the comparator 372 by the inverter 377. Therefore, the OR circuit 378 outputs an H level signal.

  When the voltage value of the voltage signal input from the differentiation circuit 360 is smaller than any of the voltages Vref3 and Vref4, both the comparator 371 and the comparator 372 output an H level signal.

  In this case, the OR circuit 378 is supplied with the H level signal output from the comparator 371 and the L level signal obtained by inverting the H level signal output from the comparator 372 by the inverter 377. Therefore, the OR circuit 378 outputs an H level signal.

  When the voltage value of the voltage signal input from the differentiating circuit 360 is smaller than the voltage Vref3 and larger than the voltage Vref4, the comparator 371 outputs an H level signal, and the comparator 372 outputs an L level signal. To do.

  In this case, the OR circuit 378 is supplied with the H level signal output from the comparator 371 and the H level signal obtained by inverting the L level signal output from the comparator 372 by the inverter 377. Therefore, the OR circuit 378 outputs an L level signal.

As described above, when the voltage value of the voltage signal input from the differentiating circuit 360 is between the voltage Vref3 and the voltage Vref4, the window comparator circuit 370 outputs an L level signal, and the voltage Vref3 and the voltage If not between Vref4, an H level signal is output. The voltage value between the voltage Vref3 and the voltage Vref4 functions as a detection threshold value for determining whether or not the drive signal COM is within a predetermined range. The voltage Vref2 input to the differentiating circuit 360 is set to a voltage value that is larger than the voltage Vref4 and smaller than the voltage Vref3.

  The holding circuit 380 includes NAND circuits 381, 382, 383, 384 and an inverter 385.

  The output of the window comparator circuit 370 is supplied to one input terminal of the NAND circuit 381, and the control signal MASK is supplied to the other input terminal. The output terminal of the NAND circuit 381 is connected to one input terminal of the NAND circuit 383.

  The output of the window comparator circuit 370 is supplied to one of the input terminals of the NAND circuit 382 via the inverter 385, and the control signal MASK is supplied to the other input terminal. The output terminal of the NAND circuit 382 is connected to one of the input terminals of the NAND circuit 384.

  Here, the control signal MASK is a signal for controlling the state of the holding circuit 380 regardless of the output of the window comparator circuit 370. In the present embodiment, the control signal MASK will be described as an H level signal.

  The other input terminal of the NAND circuit 383 is connected to the output terminal of the NAND circuit 384. The output terminal of the NAND circuit 383 is connected to the other input terminal of the NAND circuit 384 and the input terminal of the inverter 390.

  When an H level signal is input from the window comparator circuit 370 to the holding circuit 380 configured as described above, the NAND circuit 381 outputs an L level signal, and the NAND circuit 382 outputs an H level signal. The NAND circuit 383 outputs an H level signal, and the NAND circuit 384 outputs an L level signal. As a result, an H level signal is held by the NAND circuits 383 and 384 as an output of the holding circuit 380.

  When an L level signal is input from the window comparator circuit 370, the NAND circuit 381 outputs an H level signal, the NAND circuit 382 outputs an L level signal, and the NAND circuit 383 outputs an L level signal. NAND circuit 384 outputs an H level signal. As a result, an L level signal is held by the NAND circuits 383 and 384 as an output of the holding circuit 380.

  Then, the signal held as the output of the holding circuit 380 is output to the determination circuit 350 via the inverter 390.

  As in the first embodiment, the determination circuit 350 increments the count value output from the counter 351 at the falling edge of the clock signal CLK when the H level signal is supplied, and the L level signal is supplied. In the case, the count value output from the counter 351 is reset. When the count value exceeds a predetermined value, the decoder 352 outputs an error signal ERR.

  In the detection circuit 320 configured as described above, when the voltage of the drive signal COM fluctuates, the differentiating circuit 360 outputs a substantially pulse-shaped voltage signal corresponding to the voltage fluctuation. When the voltage value of the pulse-shaped voltage signal is larger than the voltage Vref3 or smaller than the voltage Vref4, the window comparator circuit 370 outputs an H level signal. Therefore, the holding circuit 380 outputs an H level signal, and the determination circuit 350 is supplied with an L level signal. Therefore, when the voltage value of the drive signal COM fluctuates more than a predetermined range, the determination circuit 350 resets the count value of the counter 351.

  When the drive signal COM continues at a constant voltage, the differentiating circuit 360 outputs a voltage signal having a constant potential based on the voltage Vref2. The voltage value of the voltage signal having a constant potential based on the voltage Vref2 is smaller than the voltage Vref3 and larger than the voltage Vref4. Therefore, the window comparator circuit 370 outputs an L level signal. Therefore, the holding circuit 380 outputs an L level signal, and the determination circuit 350 is supplied with an H level signal. Therefore, when the drive signal COM continues at a constant voltage, the determination circuit 350 outputs an error signal ERR to the control circuit 100.

  In the liquid ejection device 1 shown in the third embodiment, it is possible to directly detect the voltage waveform of the drive signal COM generated by the drive circuit 51 in the print mode. Therefore, it is possible to improve the detection accuracy as to whether or not the drive signal COM is constant as compared with the first embodiment and the second embodiment.

  The present invention includes substantially the same configuration (for example, a configuration having the same function, method, and result, or a configuration having the same purpose and effect) as the configuration described in the first to third embodiments. In addition, the invention includes a configuration in which a non-essential part of the configuration described in the embodiment is replaced. In addition, the present invention includes a configuration that exhibits the same operational effects as the configuration described in the embodiment or a configuration that can achieve the same object. In addition, the invention includes a configuration in which a known technique is added to the configuration described in the embodiment.

DESCRIPTION OF SYMBOLS 1 ... Liquid discharge apparatus, 2 ... Moving body, 3 ... Movement mechanism, 4 ... Conveyance mechanism, 10 ... Control unit, 20 ... Head unit, 21 ... Discharge module, 24 ... Carriage, 31 ... Carriage motor, 32 ... Carriage guide shaft , 33 ... Timing belt, 35 ... Carriage motor driver, 40 ... Platen, 41 ... Conveyance motor, 42 ... Conveyance roller, 45 ... Conveyance motor driver, 50 ... Drive signal generation circuit, 51 ... Drive circuit, 60 ... Piezoelectric element, 70 DESCRIPTION OF SYMBOLS ... Feed switching circuit, 80 ... Drive IC, 90 ... Voltage generation circuit, 100 ... Control circuit, 190 ... Flexible cable, 210 ... Selection control circuit, 212 ... Shift register, 214 ... Latch circuit, 216 ... Decoder, 230 ... Selection circuit 232: Inverter, 234: Transfer gate, 235, 2 6 ... transistor, 241, 242, 243, 244 ... parasitic diode, 251 ... P substrate, 252 ... polysilicon, 253,254 ... N-type diffusion layer, 255, 256, 257,258 ... electrode, 261 ... N well, 262 ... polysilicon, 263, 264 ... P-type diffusion layer, 265, 266, 267, 268 ... electrode, 310 ... DAC circuit, 311 ... DAC interface, 312 ... comparator, 313 ... latch circuit, 320 ... detection circuit, 321 ... Update detection circuit, 322 ... Clock detection circuit, 323 ... NAND circuit, 324 ... Latch circuit, 325 ... Comparator, 326 ... Latch circuit, 327 ... Frequency divider circuit, 328 ... Latch circuit, 329 ... Differentiation circuit, 330 ... Oscillation circuit 331 ... DATA update detection circuit, 332 ... latch circuit, 333 ... comparator, 334 ... latch Path, 335 ... inverter, 350 ... determination circuit, 351 ... counter, 352 ... decoder, 360 ... differentiation circuit, 361 ... comparator, 362 ... capacitor, 363 ... resistor, 370 ... window comparator circuit, 371, 372 ... comparator 377: Inverter, 378: OR circuit, 380 ... Holding circuit, 381, 382, 383, 384 ... NAND circuit, 385, 390 ... Inverter, 410 ... GVDD generation circuit, 420 ... Signal selection circuit, 430 ... Power supply control signal generation Circuit, 431 ... Inverter, 432 ... Transistor, 450 ... Reference voltage signal generation circuit, 451 ... Comparator, 452, 453 ... Transistor, 454, 455, 456 ... Resistance, 471, 472, 473 ... Transistor, 474, 475 ... Resistance , 500 ... integrated circuit, 510 ... modulation circuit, 512, 513 ... adder, 514 ... comparator, 515 ... inverter, 516 ... integral attenuator, 517 ... attenuator, 520 ... gate drive circuit, 521 ... first gate driver 522 ... Second gate driver, 530 ...
LC discharge circuit, 531 ... resistor, 532 ... transistor, 541 ... capacitor, 542 ... diode, 550 ... output circuit, 551, 552 ... transistor, 553, 554 ... resistor, 560 ... low-pass filter, 561 ... inductor, 562 ... capacitor, 570 ... first feedback circuit, 571,572 ... resistor, 580 ... second feedback circuit, 581,582 ... resistor, 583,584,585 ... condenser, 600 ... discharge part, 601 ... piezoelectric body, 610 ... sealed body, 611, 612 ... electrodes, 621 ... diaphragm, 630 ... pressure chamber substrate, 631 ... cavity, 632 ... nozzle plate, 633 ... vibration absorber, 640 ... casing, 641 ... supply flow path, 651 ... nozzle, 661 ... Supply port, 670 ... Channel substrate, 671 ... Opening, 672 ... Supply channel, 673 ... Communication channel 674: Relay channel, Bst, COM-Out, Com-Out, Ctvh, Ctvh-Out, Drv, Drv-In, En, En-In, Err, Err-Out, Gnd, Gnd-In, Gvd, Hdr, Ifb, Ldr, Sw, TG-In, TG-Out, Vbs, Vbs-Out, Vfb, Vhv, Vhv-In ... terminal, P ... medium

Claims (7)

A drive circuit for outputting a drive signal;
A piezoelectric element having a first electrode to which the drive signal is supplied and a second electrode to which a reference voltage signal is supplied, and being displaced by a potential difference between the first electrode and the second electrode;
A cavity filled with a liquid discharged from a nozzle in accordance with the displacement of the piezoelectric element;
A diaphragm provided between the cavity and the piezoelectric element;
A detection circuit for detecting whether or not the voltage fluctuation of the drive signal is within a predetermined range;
A determination circuit for determining whether or not the drive signal is normal based on a detection result of the detection circuit;
A liquid ejection apparatus comprising: The detection circuit determines that the drive signal is not normal when the detection circuit detects that the voltage fluctuation of the drive signal continues for a predetermined period and is within the predetermined range;
The liquid ejection apparatus according to claim 1, wherein When the determination circuit determines that the drive signal is not normal, the drive circuit controls the voltage value of the drive signal so as to approach the voltage value of the reference voltage signal.
The liquid ejecting apparatus according to claim 1, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. When the determination circuit determines that the drive signal is not normal, the determination circuit outputs a signal for discharging the charge of at least one of the first electrode and the second electrode.
The liquid discharge apparatus according to claim 1, wherein the liquid discharge apparatus is a liquid discharge apparatus. The detection circuit detects whether or not the voltage fluctuation of the drive signal is within the predetermined range based on an original drive signal that is the source of the drive signal.
The liquid discharge apparatus according to claim 1, wherein the liquid discharge apparatus is a liquid discharge apparatus. The detection circuit detects whether the voltage fluctuation of the drive signal is within the predetermined range based on the drive signal;
The liquid ejecting apparatus according to claim 1, wherein the liquid ejecting apparatus is a liquid ejecting apparatus. A piezoelectric element that is displaced by a potential difference generated between the first electrode and the second electrode, a cavity that is filled with a liquid discharged from a nozzle in accordance with the displacement of the piezoelectric element, and the cavity and the piezoelectric element A drive signal generation circuit used in a liquid ejection device having a diaphragm provided therebetween,
A drive circuit for outputting a drive signal supplied to the first electrode of the piezoelectric element;
A detection circuit for detecting whether or not the voltage fluctuation of the drive signal is within a predetermined range;
A determination circuit for determining whether or not the drive signal is normal based on a detection result of the detection circuit;
A drive signal generation circuit comprising:

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