JP6327373B2 - Liquid ejection device and drive signal generation circuit - Google Patents

Description

  The present invention relates to a liquid ejecting apparatus (liquid ejecting apparatus) that ejects (ejects) liquid by applying a drive signal to an actuator. For example, fine liquid is ejected from a nozzle of a liquid ejecting head to print fine particles (dots). By forming it on a medium, it is suitable for a liquid jet printing apparatus that prints predetermined characters, images, and the like.

  In a liquid ejection type printing apparatus, an actuator such as a piezoelectric element is provided in order to eject liquid from a nozzle of a liquid ejection head, and a predetermined drive signal must be applied to the actuator. Since this drive signal has a relatively high potential, the power of the original signal serving as a reference for the drive signal must be amplified by a power amplifier circuit. Therefore, in Patent Document 1 below, a digital power amplifier circuit that has an extremely small power loss and can be downsized as compared with an analog power amplifier is used, and the original signal is pulse-modulated by a modulation circuit to form a modulation signal. Is amplified by a digital power amplifier circuit to obtain a power amplification modulation signal, and the power amplification modulation signal is smoothed by a smoothing filter to obtain a drive signal. This drive signal or its original signal has a portion (time) in which the potential does not change, but the piezoelectric element used as the actuator is a capacitive load, and when the potential of the drive signal does not change, a current is supplied to the actuator. There is no need to supply. Therefore, in the liquid jet printing apparatus described in Patent Document 1, when the potential of the actuator is kept constant, that is, when the potential of the original signal is kept constant, the high-side switching provided in the digital power amplifier circuit is provided. The operation is stopped by turning off both the element Q1 and the low-side switching element Q2, thereby reducing power consumption in the digital power amplifier circuit and the smoothing filter.

JP 2011-5733 A

  Incidentally, in Patent Document 1, the low-side switching element Q2 may be operated with reference to the ground potential, but the high-side switching element Q1 is based on the potential of the output node (connection node with the low-side switching element Q2). Need to work. Therefore, although not shown in Patent Document 1, a bootstrap capacitor that functions as a floating power supply is connected between the external power supply and the output node of the digital power amplifier circuit. Further, since the output node becomes a high potential when the high-side switching element Q1 is turned on, a diode for preventing a backflow is provided between the external power supply and the bootstrap capacitor so that current does not flow backward from the output node to the external power supply side. Provided.

In such a conventional digital power amplifier circuit, when the low-side switching element Q2 is turned on, a current flows from the external power supply to the ground via the diode, and the bootstrap capacitor is charged. In particular, when the low-side switching element Q2 is turned on for the first time with the external power supply turned on, a large current flows instantaneously from the external power supply to the ground. Therefore, a part of this large current is temporarily passed through the smoothing filter. If it flows to a piezoelectric element used as an actuator, liquid may be accidentally discharged from the nozzle or the piezoelectric element may be damaged. In addition, due to this large current, the output voltage of the external power supply drops greatly, and a large reverse current (reverse current) flows due to reverse bias before the diode forward current reaches zero. In order to prevent the diode from being damaged by heat generation, it is necessary to use a diode having a large current resistance, a fast recovery diode, or the like, which causes an increase in cost.

  The present invention has been made in view of the above-described problems, and according to some aspects of the present invention, a liquid that is erroneously discharged or discharged by a current for charging a capacitive element that functions as a floating power source. It is possible to provide a liquid ejection apparatus that can reduce the risk of damage to the piezoelectric element.

  (1) In the liquid ejection device of the present invention, the power supply potential output unit that outputs the first power supply potential that rises from the reference potential and becomes a constant potential, and the first switch drive signal according to the modulation signal of the original drive signal A first switch driving unit that generates a second switch driving unit that generates a second switch driving signal according to the modulation signal; a first switch that operates according to the first switch driving signal; and the second switch. A second switch that operates in accordance with a drive signal; a rectifier provided between an output terminal of the power supply potential output section and a first terminal of the first switch drive section; and a second switch of the first switch. A connection node that electrically connects the terminal and the first terminal of the second switch; a capacitive element provided between the first terminal of the first switch driver and the connection node; Occurs at the connection node A signal conversion unit that converts a signal to be a drive signal, and a piezoelectric element that can be deformed by the drive signal and execute an operation for ejecting liquid, and the first terminal of the second switch drive unit includes The first power supply potential is supplied, the reference potential is supplied to the second terminal of the second switch driving unit, the second power supply potential is supplied to the first terminal of the first switch, A second terminal of one switch driving unit is connected to the connection node, and the reference potential is supplied to the second terminal of the second switch.

  According to the liquid ejection apparatus of the present invention, the first power supply potential rises from the reference potential and becomes a constant potential, so that the output terminal of the power supply potential output unit passes through the connection node between the first switch and the second switch. Therefore, the possibility that a large current flows instantaneously through the piezoelectric element can be reduced, so that the possibility of breakage of the piezoelectric element and erroneous liquid ejection can be reduced.

  (2) The liquid ejection device may include a resistance element provided in series with the rectifying element between the output terminal of the power supply potential output unit and the capacitive element.

  According to this liquid ejection apparatus, the current flowing from the output terminal of the power supply potential output unit to the piezoelectric element can be limited by the resistance element, so that the risk of breakage of the piezoelectric element and erroneous liquid ejection can be further reduced. .

  (3) In the liquid ejection device, the first terminal of the second switch and the second terminal of the second switch are brought into conduction until the first power supply potential reaches the constant potential. This may be a feature.

  According to this liquid ejection apparatus, the second switch is turned on when the first power supply potential is lower than the predetermined potential, and the output terminal of the power supply potential output unit is connected to the reference potential node via the second switch. Current paths are formed. As a result, the amount of current that flows instantaneously from the output terminal of the power supply potential output unit to the reference potential node is reduced, and the amount of instantaneous decrease in the first power supply potential is reduced, so that the reverse current flowing through the rectifier element is reduced, The risk of damage to the rectifying element can be reduced.

(4) In the liquid ejection device, when the first power supply potential starts to rise from the reference potential, the second switch, the first terminal of the second switch, and the second switch The second terminal may start to conduct.

  According to this liquid ejection device, the second switch starts to be turned on as soon as the first power supply potential starts to rise. Therefore, when the first power supply potential is lower, the power supply potential output unit is connected via the second switch. A current path from the output terminal to the reference potential node is formed. As a result, the amount of current that instantaneously flows from the output terminal of the power supply potential output unit to the reference potential node is further reduced, and the amount of instantaneous decrease in the first power supply potential is further reduced. As a result, the risk of damage to the rectifying element can be further reduced.

  (5) In the liquid ejection device, when the potential difference between the second switch drive signal and the reference potential is higher than a threshold value, the first terminal of the second switch and the first switch of the second switch When the two terminals are electrically connected and the first power supply potential starts to rise from the reference potential, the potential of the second switch drive signal may also start to rise.

  According to this liquid ejection apparatus, as soon as the first power supply potential starts to rise, the potential of the second switch drive signal also starts to rise, and when the potential difference between the second switch drive signal and the reference potential exceeds the threshold value. Since the second switch is turned on, when the first power supply potential is lower, a current path is formed from the output terminal of the power supply potential output unit to the reference potential node via the second switch. As a result, the amount of current that instantaneously flows from the output terminal of the power supply potential output unit to the reference potential node is further reduced, and the amount of instantaneous decrease in the first power supply potential is further reduced. As a result, the risk of damage to the rectifying element can be further reduced.

  (6) In the liquid ejecting apparatus, the first power supply potential may be a first potential, a second potential higher than the first potential, and a third potential higher than the second potential. A plurality of potentials including a fourth potential higher than the third potential and a fifth potential higher than the fourth potential, and the first switch is in an on state, The second switch has an on state, an off state, and an unstable state that can be either on or off. A first state in which the first power supply potential is the first potential, the first switch is in an off state, and the second switch is in an on state; and the first power supply potential is in the second state The second switch in which the first switch is in an off state and the second switch is in an unstable state at a potential. A third state in which the first power supply potential is the third potential, the first switch is in an off state, and the second switch is in an off state, and the first power supply potential is in the fourth state. A fourth state in which the first switch is in an unstable state and the second switch is in an off state, and the first power supply potential is in the fifth potential, and the first switch is in an on state, A fifth state in which the second switch is turned off, from the first state to the second state, from the second state to the third state, from the third state to the fourth state. The state may transition from the fourth state to the fifth state.

(7) In the liquid ejection device, the first power supply potential is further higher than a sixth potential higher than the fifth potential, a seventh potential higher than the sixth potential, and the seventh potential. An eighth potential that is higher, a ninth potential that is higher than the eighth potential, a tenth potential that is higher than the ninth potential, an eleventh potential that is higher than the tenth potential, and the eleventh potential, A plurality of potentials including a twelfth potential higher than a potential and a thirteenth potential higher than the twelfth potential, wherein the first power supply potential is the sixth potential, A sixth state in which the first switch is on and the second switch is in an off state; the first power supply potential is the seventh potential; the first switch is in an unstable state; And the seventh power supply potential is the eighth potential, and the seventh power supply potential is the eighth potential. An eighth state in which the switch is off and the second switch is in an off state; the first power supply potential is the ninth potential; the first switch is in an off state; and the second switch is in an unstable state The tenth state in which the first power supply potential is the tenth potential, the first switch is in the off state, and the second switch is in the on state, and the first power supply potential is An eleventh state in which the first switch is turned off and the second switch is turned on at the eleventh potential; the first power supply potential is the twelfth potential; and the first switch is turned off. In a state, the second switch becomes unstable, the first power supply potential is the thirteenth potential, the first switch is off, and the second switch is off. A thirteenth state, and the fifth state To the sixth state, from the sixth state to the seventh state, from the seventh state to the eighth state, from the eighth state to the ninth state, from the ninth state to the tenth state. The state may further change from the tenth state to the eleventh state, from the eleventh state to the twelfth state, and from the twelfth state to the thirteenth state.

1 is a block diagram illustrating an overall configuration of a printing system. It is a schematic sectional drawing of a printer. It is a schematic top view of a printer. It is a figure for demonstrating the structure of a head. It is a figure for demonstrating the drive signal COM from a drive signal generation part, and the control signal used for dot formation. It is a block diagram explaining the structure of a head control part. It is a figure explaining the flow until the production | generation of the drive signal COM. It is a detailed block diagram of a drive signal generation unit and the like according to the first embodiment. It is a figure which shows the circuit structural example of the signal amplification part of 1st Embodiment. It is a figure which shows an example of the signal waveform of a signal amplifier. It is a figure which shows the circuit structural example of the signal amplification part of 2nd Embodiment. It is a figure which shows the circuit structural example of the signal modulation part of 3rd Embodiment, a signal amplification part, and a signal conversion part. It is a figure which shows the structural example of the level shift circuit of 3rd Embodiment. It is a figure which shows the circuit structural example of the signal modulation part of 4th Embodiment, a signal amplification part, and a signal conversion part. It is a figure which shows the structural example of the OE control circuit of 4th Embodiment. It is a figure which shows the circuit structural example of the drive signal generation part of 5th Embodiment.

1. First Embodiment As an embodiment of a liquid ejection apparatus of the present invention, a liquid ejection type printing apparatus applied to a liquid ejection apparatus will be described.

1.1. Configuration of Printing System FIG. 1 is a block diagram illustrating an overall configuration of a printing system including a liquid jet printing apparatus (printer 1) according to a first embodiment. As will be described later, the printer 1 is a line head printer in which a sheet S (see FIGS. 2 and 3) is transported in a predetermined direction and printed in a printing area in the middle of the transport.

  The printer 1 is communicably connected to the computer 80, and a printer driver installed in the computer 80 creates print data for causing the printer 1 to print an image and outputs the print data to the printer 1. The printer 1 includes a controller 10, a paper transport mechanism 30, a head unit 40, and a detector group 70. Although the printer 1 may include a plurality of head units 40, here, one head unit 40 will be representatively shown in FIG.

A controller 10 in the printer 1 is for performing overall control in the printer 1. The interface unit 11 transmits and receives data to and from the computer 80 that is an external device. The interface unit 11 outputs the print data 111 among the data received from the computer 80 to the CPU 12. The print data 111 includes, for example, image data, data specifying a print mode, and the like.

  The CPU 12 is an arithmetic processing unit for performing overall control of the printer 1, and controls the head unit 40 and the paper transport mechanism 30 via the drive signal generator 14, the control signal generator 15, and the transport signal generator 16. To do. The memory 13 is used to secure an area for storing programs and data of the CPU 12, a work area, and the like. The state in the printer 1 is monitored by the detector group 70, and the controller 10 performs control based on the detection result from the detector group 70. Note that the program and data of the CPU 12 may be stored in the storage medium 113. The storage medium 113 may be any one of a magnetic disk such as a hard disk, an optical disk such as a DVD, and a non-volatile memory such as a flash memory, but is not particularly limited. As illustrated in FIG. 1, the CPU 12 may be able to access a storage medium 113 connected to the printer 1. Further, the storage medium 113 may be connected to the computer 80, and the CPU 12 may be able to access the storage medium 113 via the interface unit 11 and the computer 80 (the path is not shown).

  The drive signal generation unit 14 generates a drive signal COM that displaces the piezoelectric element PZT included in the head 41. As will be described later, the drive signal generation unit 14 includes a part of the original drive signal generation unit 25, a signal modulation unit 26, a signal amplification unit 28 (digital power amplification circuit), and a signal conversion unit 29 (smooth filter) (see FIG. 7). The drive signal generation unit 14 generates an original drive signal 125 by the original drive signal generation unit 25 according to an instruction from the CPU 12, and generates a modulation signal 126 by pulse-modulating the original drive signal 125 by the signal modulation unit 26. The amplifying unit 28 amplifies the modulated signal 126, and the signal converting unit 29 smoothes the amplified modulated signal 128 (the amplified modulated signal 126) to generate the drive signal COM.

  The control signal generator 15 generates a control signal according to an instruction from the CPU 12. The control signal is a signal used for controlling the head 41, for example, selecting a nozzle to be ejected. In this embodiment, the control signal generation unit 15 generates a control signal including a clock signal SCK, a latch signal LAT, a channel signal CH, and drive pulse selection data SI & SP. Details of these signals will be described later. The control signal generation unit 15 may have a configuration included in the CPU 12 (that is, a configuration in which the CPU 12 also functions as the control signal generation unit 15).

  Here, the drive signal COM generated by the drive signal generation unit 14 is an analog signal whose voltage continuously changes, and the clock signal SCK, the latch signal LAT, the channel signal CH, and the drive pulse selection data SI & SP which are control signals are digital. Signal. The drive signal COM and the control signal are transmitted to the head 41 of the head unit 40 via the cable 20 which is a flexible flat cable (hereinafter also referred to as FFC). As for the control signal, a plurality of types of signals may be transmitted in a time division manner using a differential serial method. At this time, the number of necessary transmission lines can be reduced as compared with the case where the control signals are transmitted in parallel for each type, and a decrease in slidability due to the superposition of many FFCs can be avoided. The size of the connector provided in the unit 40 is also reduced.

The transport signal generator 16 generates a signal for controlling the paper transport mechanism 30 in accordance with an instruction from the CPU 12. The paper transport mechanism 30 rotatably supports a continuous paper S wound in a roll shape, for example, and transports the paper S by rotation so that predetermined characters, images, and the like are printed in the printing area. For example, the paper transport mechanism 30 transports the paper S in a predetermined direction based on the signal generated by the transport signal generator 16. The carrier signal generation unit 16 may have a configuration included in the CPU 12 (that is, a configuration in which the CPU 12 also functions as the carrier signal generation unit 16).

  The head unit 40 includes a head 41 as a liquid ejection unit. For the sake of space, only one head 41 is shown in FIG. 1, but the head unit 40 of this embodiment may include a plurality of heads 41. The head 41 includes an actuator unit including a piezoelectric element PZT, a cavity CA, and a nozzle NZ, and also includes a head controller HC that controls the displacement of the piezoelectric element PZT. The actuator unit communicates with the cavity CA, the piezoelectric element PZT that can be displaced by the drive signal COM, the cavity CA that is filled with liquid and the internal pressure is increased or decreased by the displacement of the piezoelectric element PZT, It includes a nozzle NZ that ejects liquid as droplets by increasing or decreasing the pressure in the cavity CA. The head controller HC controls the displacement of the piezoelectric element PZT based on the drive signal COM and the control signal from the controller 10.

  Here, in order to distinguish the elements included in each actuator part, the numerals in parentheses are attached to the reference numerals. In the example of FIG. 1, there are three actuator units, and the first actuator unit includes a first piezoelectric element PZT (1), a first cavity CA (1), a first nozzle NZ (1), The actuator section includes a second piezoelectric element PZT (2), a second cavity CA (2), and a second nozzle NZ (2), and the third actuator section includes a third piezoelectric element PZT (3), a third cavity. CA (3) and the third nozzle NZ (3) are included. Note that the number of actuator portions is not limited to three, and may be one or two, for example, or may be four or more. In FIG. 1, for convenience of illustration, the first to third actuator portions are included in one head 41, but a part thereof may be included in another head 41 (not shown).

  The drive signal COM is generated by the drive signal generator 14 as shown in FIG. 1, and the first piezoelectric element PZT (1), the second piezoelectric element PZT (2), the first piezoelectric element PZT (2) via the cable 20 and the head controller HC. 3 is transmitted to the piezoelectric element PZT (3). Further, the control signal including the clock signal SCK, the latch signal LAT, the channel signal CH, and the drive pulse selection data SI & SP is generated by the control signal generator 15 as shown in FIG. Used for control in HC.

1.2. Configuration of Printer FIG. 2 is a schematic sectional view of the printer 1. In the example of FIG. 2, the paper S is described as continuous paper wound in a roll shape. However, the recording medium on which the printer 1 prints an image is not limited to continuous paper, and may be cut paper, cloth, film, or the like. But you can.

The printer 1 includes a winding shaft 21 that feeds the paper S by rotation, and a relay roller 22 that winds the paper S fed from the winding shaft 21 and guides the paper S to the upstream conveying roller pair 31. Then, the printer 1 winds and feeds the paper S, a plurality of relay rollers 32 and 33, an upstream conveyance roller pair 31 disposed on the upstream side in the conveyance direction from the printing area, and a conveyance direction from the printing area. And a downstream conveying roller pair 34 disposed on the downstream side. The upstream-side transport roller pair 31 and the downstream-side transport roller pair 34 are respectively connected to a motor (not shown) to be driven and rotated, and driven rollers 31a and 34a that are driven and rotated as the drive rollers 31a and 34a are rotated. 31b, 34b. The drive rollers 31a and 34a are driven and rotated while the upstream side transport roller pair 31 and the downstream side transport roller pair 34 sandwich the paper S, respectively, so that a transport force is applied to the paper S. The printer 1 includes a relay roller 61 that winds and feeds the paper S sent from the downstream transport roller pair 34, and a winding drive shaft 62 that winds up the paper S sent from the relay roller 61. Winding drive shaft 6
The printed paper S is sequentially wound in a roll shape in accordance with the rotational driving of 2. These rollers and a motor (not shown) correspond to the paper transport mechanism 30 in FIG.

  The printer 1 includes a head unit 40 and a platen 42 that supports the paper S from the opposite side of the printing surface in the printing region. The printer 1 may include a plurality of head units 40. The printer 1 may prepare a head unit 40 for each color of ink, for example, and is capable of ejecting four inks of four colors of yellow (Y), magenta (M), cyan (C), and black (K). The head units 40 may be arranged in the transport direction. In the following description, a single head unit 40 will be described as a representative. However, it is assumed that an ink color is assigned to each nozzle and color printing is possible.

  As shown in FIG. 3, in the head unit 40, a plurality of heads 41 (1) to 41 (4) are arranged in the width direction (Y direction) of the paper S that intersects the transport direction of the paper S. For the sake of explanation, small numbers are assigned in order from the head 41 on the far side in the Y direction. In addition, on the surface (lower surface) of each head 41 that faces the paper S, a large number of nozzles NZ that eject ink are arranged at predetermined intervals in the Y direction. 3 virtually shows the positions of the head 41 and the nozzle NZ when the head unit 40 is viewed from above. The positions of the nozzles NZ at the ends of the heads 41 adjacent to each other in the Y direction (for example, 41 (1) and 41 (2)) are at least partially overlapped. The nozzles NZ are arranged at predetermined intervals in the Y direction for more than that. Therefore, a two-dimensional image is printed on the paper S when the head unit 40 ejects ink from the nozzles NZ to the paper S conveyed without stopping under the head unit 40.

  In FIG. 3, four heads 41 belonging to the head unit 40 are shown for the sake of space, but the present invention is not limited to this. That is, the number of heads 41 may be more or less than four. Moreover, although the head 41 of FIG. 3 is arrange | positioned at zigzag form, it is not restricted to such arrangement | positioning. Here, the ink discharge method from the nozzle NZ is a piezo method in which ink is discharged by applying a voltage to the piezoelectric element PZT to expand and contract the ink chamber in this embodiment. A thermal method in which bubbles are generated inside and ink is ejected by the bubbles may be used.

  In this embodiment, the sheet S is supported by the horizontal surface of the platen 42. However, the present invention is not limited to this. For example, a rotating drum that rotates with the width direction of the sheet S as the rotation axis is used as the platen 42. Ink may be ejected from the head 41 while the paper S is wound and conveyed. In this case, the head unit 40 is inclined and disposed along the arc-shaped outer peripheral surface of the rotating drum. Further, when the ink ejected from the head 41 is, for example, UV ink that is cured by irradiating ultraviolet rays, an irradiator that irradiates ultraviolet rays may be provided on the downstream side of the head unit 40.

  Here, the printer 1 has a maintenance area for cleaning the head unit 40. In the maintenance area of the printer 1, there are a wiper 51, a plurality of caps 52, and an ink receiving portion 53. The maintenance area is located on the back side in the Y direction with respect to the platen 42 (that is, the printing area), and the head unit 40 moves to the back side in the Y direction during cleaning.

The wiper 51 and the cap 52 are supported by the ink receiving portion 53 and can be moved in the X direction (the transport direction of the paper S) by the ink receiving portion 53. The wiper 51 is a plate-like member erected from the ink receiving portion 53, and is formed of an elastic member, cloth, felt, or the like. The cap 52 is a rectangular parallelepiped member formed of an elastic member or the like, and is provided for each head 41. And according to arrangement | positioning of the heads 41 (1) -41 (4) in the head unit 40, the caps 52 (1) -52 (4) are also located in the width direction. Therefore, when the head unit 40 moves to the back side in the Y direction, the head 41 and the cap 52 face each other, and when the head unit 40 descends (or when the cap 52 rises), the cap 52 comes into close contact with the nozzle opening surface of the head 41. The nozzle NZ can be sealed. The ink receiving portion 53 also plays a role of receiving ink ejected from the nozzles NZ when the head 41 is cleaned.

  When ink is ejected from the nozzle NZ provided in the head 41, a minute ink droplet is generated together with the main ink droplet, and the minute ink droplet rises as a mist and adheres to the nozzle opening surface of the head 41. . Further, not only ink but also dust and paper dust adhere to the nozzle opening surface of the head 41. If these foreign substances are left on the nozzle opening surface of the head 41 and left to accumulate, the nozzle NZ is blocked and ink ejection from the nozzle NZ is hindered. Therefore, in the printer 1 of the present embodiment, the wiping process is periodically performed as the cleaning of the head unit 40.

1.3. Drive Signal and Control Signal Details of the drive signal COM and control signal transmitted from the controller 10 through the cable 20 will be described below. First, the structure of the head 41 will be described, and after illustrating the waveforms of the drive signal COM and the control signal, the configuration of the head controller HC will be described.

1.3.1. Head Structure FIG. 4 is a diagram for explaining the structure of the head 41. FIG. 4 shows a nozzle NZ, a piezoelectric element PZT, an ink supply path 402, a nozzle communication path 404, and an elastic plate 406. The ink supply path 402 and the nozzle communication path 404 correspond to the cavity CA.

  Ink drops are supplied to the ink supply path 402 from an ink tank (not shown). The ink droplet is supplied to the nozzle communication path 404. A drive pulse PCOM of the drive signal COM is applied to the piezoelectric element PZT. When the drive pulse PCOM is applied, the piezoelectric element PZT expands and contracts (displaces) according to the waveform, and the elastic plate 406 is vibrated. An ink droplet of an amount corresponding to the amplitude of the drive pulse PCOM is ejected from the nozzle NZ. Actuators composed of such nozzles NZ, piezoelectric elements PZT, and the like are arranged as shown in FIG. 3 to constitute a head 41 having a nozzle row.

1.3.2. Signal Waveform FIG. 5 is a diagram for explaining a drive signal COM from the drive signal generation unit 14 and a control signal used for dot formation. The drive signal COM is a time series connection of drive pulses PCOM as unit drive signals that are applied to the piezoelectric element PZT and eject liquid, and the volume of the cavity CA in which the rising portion of the drive pulse PCOM communicates with the nozzles. And the liquid is ejected from the nozzle as a result of extruding the liquid. The falling portion of the driving pulse PCOM reduces the volume of the cavity CA and extrudes the liquid.

By variously changing the voltage increase / decrease slope and peak value of the drive pulse PCOM consisting of this voltage trapezoidal wave, it is possible to change the amount of liquid drawn in, the speed of drawing in, the amount of liquid pushed out, and the speed of extrusion. Different sizes of dots can be obtained by changing the ejection amount. Therefore, even when a plurality of drive pulses PCOM are connected in time series, a single drive pulse PCOM is selected and applied to the piezoelectric element PZT to eject liquid or select a plurality of drive pulses PCOM. By applying the liquid to the piezoelectric element PZT and ejecting the liquid a plurality of times, dots of various sizes can be obtained. That is, if a plurality of liquids are landed at the same position before the liquid is dried, it is substantially the same as ejecting a large liquid, and the size of the dots can be increased. By combining such techniques, it is possible to increase the number of gradations. Note that the drive pulse PCOM1 at the left end in FIG. 5 is different from the drive pulses PCOM2 to PCOM4 and does not push out only the liquid. This is called microvibration, and is used to suppress or prevent the increase in the viscosity of the nozzle without ejecting liquid.

  In addition to the drive signal COM from the drive signal generator 14, the clock signal SCK, the latch signal LAT, the channel signal CH, and the drive pulse selection data SI & SP are input to the head controller HC as the control signal from the control signal generator 15. Is done. Among them, the latch signal LAT and the channel signal CH are control signals for determining the timing of the drive signal COM, and as shown in FIG. A pulse PCOM is output. The drive pulse selection data SI & SP includes pixel data SI (SIH, SIL) for designating a piezoelectric element PZT corresponding to a nozzle that should eject ink droplets, and waveform pattern data SP of a drive signal COM. SIH and SIL correspond to the upper and lower bits of 2-bit pixel data SI, respectively.

1.3.3. Head Controller FIG. 6 is a block diagram illustrating the configuration of the head controller HC. The head controller HC includes a shift register 211 that stores drive pulse selection data SI & SP for designating a piezoelectric element PZT corresponding to a nozzle that ejects liquid, and a latch circuit 212 that temporarily stores data of the shift register 211. The level shifter 213 applies the voltage of the drive signal COM to the piezoelectric element PZT by converting the level of the output of the latch circuit 212 and supplying the output to the selection switch 201.

  The drive pulse selection data SI & SP is sequentially input to the shift register 211, and the storage area is sequentially shifted from the first stage to the subsequent stage in accordance with the input pulse of the clock signal SCK. The latch circuit 212 latches each output signal of the shift register 211 by the input latch signal LAT after the drive pulse selection data SI & SP for the number of nozzles is stored in the shift register 211. The signal stored in the latch circuit 212 is converted by the level shifter 213 to a voltage level at which the selection switch 201 at the next stage can be turned on / off. This is because the drive signal COM is higher than the output voltage of the latch circuit 212, and the operating voltage range of the selection switch 201 is set higher accordingly. Accordingly, the piezoelectric element PZT whose selection switch 201 is closed by the level shifter 213 is connected to the drive signal COM (drive pulse PCOM) at the connection timing of the drive pulse selection data SI & SP.

  After the drive pulse selection data SI & SP of the shift register 211 is stored in the latch circuit 212, the next print information is input to the shift register 211, and the stored data in the latch circuit 212 is sequentially updated in accordance with the liquid ejection timing. . Even after the selection switch 201 separates the piezoelectric element PZT from the drive signal COM (drive pulse PCOM), the input voltage of the piezoelectric element PZT is maintained at the voltage just before the separation.

1.3.4. Drive Signal FIG. 7 is a diagram for explaining the flow until generation of the drive signal COM. As described above, a part of the original drive signal generation unit 25, the signal modulation unit 26, the signal amplification unit 28 (digital power amplification circuit), and the signal conversion unit 29 (smooth filter) in FIG. 7 correspond to the drive signal generation unit 14. doing. The original drive signal generation unit 25 generates an original drive signal 125 as shown in FIG. 7, for example, based on the print data 111 from the interface unit 11.

  As will be described later, the original drive signal generation unit 25 includes a CPU 12, a DAC 39, and the like. The CPU 12 selects original drive data based on the print data 111, and outputs the original drive signal 125 to the DAC 39.

  When the signal modulation unit 26 receives the original drive signal 125 from the original drive signal generation unit 25, the signal modulation unit 26 performs predetermined modulation to generate a modulation signal 126. The predetermined modulation is pulse density modulation (PDM) in the present embodiment, but other modulation schemes such as pulse width modulation (PWM) may be used.

  The signal amplifying unit 28 receives the modulated signal 126 and performs power amplification to generate an amplified modulated signal 128. The signal converting unit 29 smoothes the amplified modulated signal 128, and a portion modulated to have a wide pulse width is obtained. A portion having a high voltage value and being modulated to a narrow pulse width generates an analog drive signal COM having a low voltage value.

1.4. Configuration of Drive Signal Generation Unit FIG. 8 is a detailed block diagram of the drive signal generation unit 14 and the like of the printer 1 according to the present embodiment. The head 41 includes many piezoelectric elements PZT corresponding to the nozzles. For example, the first piezoelectric element PZT (1), the second piezoelectric element PZT (2), and the third piezoelectric element PZT (3) shown in FIG. 8 correspond to the three piezoelectric elements in FIG. It is a part of the entire piezoelectric element PZT (for example, thousands). In the present embodiment, the drive signal COM can be applied to all the piezoelectric elements PZT including the first piezoelectric element PZT (1), the second piezoelectric element PZT (2), and the third piezoelectric element PZT (3). In FIG. 8, the cavity CA and the nozzle NZ are not shown.

  As shown in FIG. 8, the head 41 includes a head control unit HC, and the head control unit HC includes a selection switch 201 that selects whether to apply the voltage of the drive signal COM to each of the piezoelectric elements PZT. In FIG. 8, illustration of functional blocks other than the selection switch 201 of the head controller HC (for example, the shift register 211 and the like, see FIG. 6) is omitted.

  Here, the amplified modulation signal 128 generated by the signal amplifying unit 28 becomes the drive signal COM via the signal conversion unit 29 realized by a low-pass filter in which the coil L and the capacitor C are combined. Needs to be able to drive all the piezoelectric elements PZT (for example, thousands), and the amplified modulation signal 128 is sufficiently amplified by the signal amplifying unit 28.

  The original drive signal generation unit 25 reads the original drive data from the memory 13 based on the memory 13 that stores the original drive data of the original drive signal 125 configured by digital potential data and the like, and the print data 111 from the interface unit 11. The CPU 12 converts the voltage signal and holds it for a predetermined sampling period, and the DAC 39 converts the voltage signal output from the CPU 12 into an analog signal and outputs it as the original drive signal 125. The CPU 12 outputs an output enable signal OE and an oscillation start signal ST to a gate drive circuit 38 (to be described later) in the signal amplification unit 28.

  The signal modulation unit 26 is a pulse density modulation (PDM) circuit, an error amplifier 37 that amplifies the difference between the original drive signal 125 and the drive signal COM output from the DAC 39, and an output from the error amplifier 37. A comparator 35 that compares the potential of the generated signal with a predetermined potential and generates a modulated signal 126 that is pulse density modulated, the basic principles and features of which include a quantizer, a delay device, and an integrator It becomes the same as the delta-sigma modulator comprised from. The characteristic of ΔΣ modulation is that the error (quantization noise) generated in the quantizer is driven to a higher frequency band than the input signal by two characteristics such as oversampling and noise shaping, and the accuracy for low-frequency signals is high. For example, the quantization noise driven to the frequency band is distributed over a wide band, and the pulse frequency changes according to the input signal level. Since the pulse density modulation method oscillates in response to the input signal level, the output voltage range is wide and suitable for the head drive circuit.

  However, in this embodiment, an error amplifier 37 is used instead of the integrator included in the ΔΣ modulator, and the comparator 35 functioning as a quantizer is based on an error between the original drive signal 125 and the drive signal COM. It is characterized by quantization. According to the configuration of the present embodiment, the signal delay by the comparator 35, the signal amplifying unit 28, and the signal converting unit 29 and the phase delay by the signal converting unit 29 can be reduced by the phase advance correction of the error amplifier 37, and the integrator Since the delay time is unnecessary, the delay time is small and it is suitable for speeding up the circuit. In addition, the signal modulation unit 26 may use a known pulse modulation circuit such as a pulse width modulation (PWM) circuit.

  The signal amplifying unit 28 responds to the half-bridge output stage including the first switch QH on the high side and the second switch QL on the low side for substantially amplifying the power, and the modulation signal 126 from the signal modulating unit 26. And a gate drive circuit 38 for generating a first switch drive signal GH and a second switch drive signal GL for driving the first switch and the second switch, respectively. For example, a power MOSFET can be used as the first switch and the second switch, but is not limited thereto.

  In the signal amplifying unit 28, when the modulation signal 126 is at the high level, the first switch QH is turned on and the second switch QL is turned off. As a result, the amplified modulated signal 128 output from the half bridge output stage The voltage is the supply voltage VHV. On the other hand, when the modulation signal 126 is at a low level, the first switch QH is turned off and the second switch QL is turned on. As a result, the voltage of the amplified modulated signal 128 becomes 0V.

  As described above, when the first switch QH and the second switch QL are digitally driven, a current flows through the on-state switch. However, if the switch resistance is very small, almost no loss occurs. In addition, since no current flows through the switch in the off state, no loss occurs. Therefore, the loss itself of the signal amplifier 28 is extremely small, and a switching element such as a small MOSFET can be used for the first switch and the second switch.

  The amplified modulation signal 128 generated by the signal amplifying unit 28 becomes the driving signal COM via the signal converting unit 29 realized by a low-pass filter in which the coil L and the capacitor C are combined. Since it is necessary to be able to drive the piezoelectric elements PZT (for example, several thousand), the signal amplifying unit 28 sufficiently amplifies them.

  Since the piezoelectric element PZT is a capacitive load, it is not necessary to pass a current when the potential of the drive signal COM (the same applies to the original drive signal 125) does not change. Therefore, in this embodiment, when the potential of the drive signal COM does not change, the CPU 12 sets the output enable signal OE to a low level, and when the output enable signal OE is at a low level, the gate drive circuit 38 Both the second switches are turned off. When both the first switch QH and the second switch QL are turned off, the piezoelectric element PZT, which is a capacitive load, is maintained in a high impedance state, the electric charge stored in the piezoelectric element PZT is retained, and the charge / discharge state is maintained. Or a slight self-discharge. As described above, when the potential of the drive signal COM does not change, both the first switch and the second switch are turned off, so that the first switch QH, the second switch QL, and the coil L of the signal conversion unit 29 consume wastefully. Power consumption can be reduced.

1.5. Configuration of Signal Amplifier FIG. 9 is a diagram illustrating a circuit configuration example of the signal amplifier 28 of the printer 1 according to the present embodiment. In FIG. 9, NMOS transistors are used as the first switch QH and the second switch QL. The drain terminal, which is the first terminal of the first switch QH, is supplied with, for example, a power supply potential VHV of several tens of volts (second power supply potential), and the source terminal, which is the second terminal of the second switch QL, A reference potential of 0 V is supplied, and a source terminal that is the second terminal of the first switch QH and a drain terminal that is the first terminal of the second switch QL are connected. The first switch QH operates in response to the first switch drive signal GH input to the gate terminal, and the second switch QL operates in response to the second switch drive signal GL input to the gate terminal. Then, the signal conversion unit 29 converts a signal generated at the connection node SWN that electrically connects the source terminal of the first switch QH and the drain terminal of the second switch QL into a drive signal COM.

  The gate drive circuit 38 includes a charge pump 381, a diode 382 as a rectifier, a capacitor 383 as a capacitor, a driver control circuit 384, a high side gate driver 385, and a low side gate driver 386.

  The charge pump 381 starts boosting the power supply potential VDD of 3.3 V, for example, in response to the oscillation start signal ST input from the CPU 12 to the ST terminal. The power supply potential GVDD (first power supply potential) output from the output terminal of the charge pump 381 gradually rises from the reference potential (0 V). For example, in the order of several ms, the first switch and the second switch are turned on. It reaches a certain potential (for example, 10 V) that is equal to or greater than the potential difference Vt between the gate and the source necessary for becoming. The charge pump 381 functions as a power supply potential output unit that outputs the power supply potential GVDD of the high side gate driver 385 and the low side gate driver 386.

  The diode 382 is provided between the output terminal of the charge pump 381 and the first terminal of the high-side gate driver 385. The anode terminal of the diode 382 is connected to the output terminal of the charge pump 381, and the cathode terminal of the diode 382. Is connected to the power supply terminal which is the first terminal of the high-side gate driver 385.

  The capacitor 383 is provided between the power supply terminal of the high-side gate driver 385 and the connection node SWN between the source terminal of the first switch QH and the drain terminal of the second switch QL. The first terminal of the capacitor 383 is connected to the capacitor 383. The power supply terminal of the high side gate driver 385 is connected, and the second terminal of the capacitor 383 is connected to the SWN node. In addition, a reference terminal which is a second terminal of the high side gate driver 385 is also connected to the SWN node. The capacitor 383 functions as a bootstrap capacitor.

  When the output enable signal OE input from the CPU 12 to the OE terminal is at a high level, the driver control circuit 384 inputs the high-side gate driver 385 in accordance with the modulation signal 126 input from the signal modulation unit 26 to the IN terminal. The signal IN_H and the input signal IN_L of the low side gate driver 386 are generated. In the present embodiment, when the modulation signal 126 is at a high level, the driver control circuit 384 has the input signal IN_H at a high level and the input signal IN_L at a low level, and when the modulation signal 126 is at a low level, the input signal IN_H is Low level, the input signal IN_L becomes high level. In addition, when the output enable signal OE is at a low level, the driver control circuit 384 sets both the input signal IN_H and the input signal IN_L to a low level.

  The high-side gate driver 385 operates using the capacitor 383 provided between the power supply terminal and the reference terminal as a floating power supply, and generates the first switch drive signal GH according to the input signal IN_H. In this embodiment, the high side gate driver 385 sets the first switch drive signal GH to a high level when the input signal IN_H is at a high level, and sets the first switch drive signal GH to a low level when the input signal IN_H is at a low level. To. The high side gate driver 385 functions as a first switch driving unit that drives the first switch QH.

The low side gate driver 386 has a charge pump 3 connected to the power supply terminal which is the first terminal.
The power supply potential GVDD output from 81 is supplied, the reference terminal which is the second terminal is supplied with the reference potential (0 V), and the second switch drive signal GL is generated according to the input signal IN_L. In the present embodiment, the low-side gate driver 386 sets the second switch drive signal GL to a high level when the input signal IN_L is at a high level, and sets the second switch drive signal GL to a low level when the input signal IN_L is at a low level. To do. The low side gate driver 386 functions as a second switch driving unit that drives the second switch QL.

  FIG. 10 is a diagram illustrating an example of a signal waveform of the signal amplifying unit 28 when the oscillation start signal ST is input. In the present embodiment, when the oscillation start signal ST is at a low level, the modulation signal 126 is set at a low level, whereby the input signal IN_H of the high side gate driver 385 is low and the input signal of the low side gate driver 386 is low. It is assumed that IN_L is at a high level.

  When the oscillation start signal ST changes from the low level to the high level, the charge pump 381 starts boosting, and the power supply potential GVDD output from the charge pump 381 gradually rises. The low-side gate driver 386 operates at the power supply potential GVDD, and since IN_L is at a high level, the potential of the second switch drive signal GL gradually increases following the power supply potential GVDD. The second switch QL is turned on when the potential difference between the second switch drive signal GL, which is a potential difference between the gate and the source, and the reference potential (0 V) is higher than a predetermined threshold.

  Then, a current flows from the output terminal of the charge pump 381 to the reference potential node (ground) via the diode 382, the capacitor 383, and the second switch, and the capacitor 383 is slowly charged by this current. The high side gate driver 385 starts operation with a power supply potential equal to the potential difference between both terminals of the capacitor 383 with reference to the potential of the SWN node. Since IN_H is at a low level, the potential of the first switch drive signal GH is SWN. It remains equal to the node potential. Therefore, the first switch QH remains in the off state because the potential difference between the first switch drive signal GH, which is the potential difference between the gate and the source, and the potential of the SWN node is lower than the threshold value.

  Thus, the power supply potential GVDD rises gently, the first state where the power supply potential GVDD is the first potential V1, the first switch QH is off, and the second switch QL is on is generated. In this first state, the potential of the drive signal COM is the reference potential (0 V), and this drive signal COM is input to the signal modulation unit 26, and after the first state, the modulation signal 126 changes from the low level to the high level. . As a result, the input signal IN_L of the low side gate driver 386 changes from the high level to the low level, and thereafter, the input signal IN_H of the high side gate driver 385 changes from the low level to the high level.

  When IN_L becomes low level, the potential of the second switch drive signal GL changes from GVDD to the reference potential (0 V). At this change point, the second switch QL is in an unstable state that can be either on or off because the potential difference between the gate and the source changes from a state higher than a threshold value to a low state. That is, a transition is made from the first state to a second state in which the power supply potential GVDD is a second potential V2 higher than the first potential V1, the first switch QH is in an off state, and the second switch QL is in an unstable state. To do.

  When the potential of the second switch drive signal GL becomes the reference potential (0 V), the second switch QL is turned off because the potential difference between the gate and the source is lower than the threshold value. That is, a transition is made from the second state to the third state in which the power supply potential GVDD is the third potential V3 higher than the second potential V2, the first switch QH is in the off state, and the second switch QL is in the off state. .

Thereafter, when IN_H becomes high level, the potential difference between the first switch drive signal GH and the SWN node changes so as to be equal to the potential difference between both terminals of the capacitor 383. At this change point, the first switch QH is in an unstable state that can be either on or off because the potential difference between the gate and the source changes from a state lower than a threshold value to a high state. That is, the third state shifts to the fourth state where the power supply potential GVDD is the fourth potential V4 higher than the third potential, the first switch QH is unstable, and the second switch QL is turned off. .

  When the potential difference between the first switch drive signal GH and the SWN node becomes equal to the potential difference between both terminals of the capacitor 383, the first switch QH has the gate-source potential difference higher than the threshold value. Become. That is, a transition is made from the fourth state to the fifth state in which the power supply potential GVDD is the fifth potential V5 higher than the fourth potential V4, the first switch QH is in the on state, and the second switch QL is in the off state. .

  Thereafter, the power supply potential GVDD rises, and from the fifth state, the first switch QH is turned on and the second switch QL is turned off at the sixth potential V6 where the power supply potential GVDD is higher than the fifth potential. Transition to the sixth state. In the fifth state and the sixth state, the potential of the drive signal COM is the power supply potential VHV (for example, 42V), and this drive signal COM is input to the signal modulation unit 26. After the sixth state, the modulation signal 126 is changed from the high level. Change to low level. As a result, the input signal IN_H of the high side gate driver 385 changes from high level to low level, and thereafter, the input signal IN_L of the low side gate driver 386 changes from low level to high level.

  When IN_H becomes low level, the potential of the first switch drive signal GH changes to the potential of the SWN node. At this change point, the first switch QH is in an unstable state that can be either on or off because the potential difference between the gate and the source changes from a state higher than a threshold value to a low state. That is, the transition from the sixth state to the seventh state in which the power supply potential GVDD is the seventh potential V7 higher than the sixth potential V6, the first switch QH is in an unstable state, and the second switch QL is in an off state. To do.

  When the potential of the first switch drive signal GH becomes the potential of the SWN node, the first switch QH is turned off because the potential difference between the gate and the source is lower than the threshold value. That is, the seventh state shifts to the eighth state where the power supply potential GVDD is the eighth potential V8 higher than the seventh potential V7, the first switch QH is off, and the second switch QL is off. .

  Thereafter, when IN_L becomes high level, the potential of the second switch drive signal GL changes to the power supply potential GVDD. At this changing point, the second switch QL is in an unstable state that can be either on or off because the potential difference between the gate and the source changes from a state lower than the threshold value to a high state. That is, the eighth state shifts to the ninth state where the power supply potential GVDD is the ninth potential V9 higher than the eighth potential, the first switch QH is in the off state, and the second switch QL is in the unstable state. .

  When the potential of the second switch drive signal GL becomes the power supply potential GVDD, the second switch QL is turned on because the potential difference between the gate and the source is higher than the threshold value. That is, the transition from the ninth state to the tenth state where the power supply potential GVDD is the tenth potential V10 higher than the ninth potential V9, the first switch QH is off, and the second switch QL is on. .

Thereafter, the power supply potential GVDD rises, and from the tenth state, the first switch QH is turned off and the second switch QL is turned on at the eleventh potential V11 where the power supply potential GVDD is higher than the tenth potential. Transition to the eleventh state. In the tenth state and the eleventh state, the drive signal COM
Is a reference potential (0 V), and this drive signal COM is input to the signal modulation unit 26, and after the eleventh state, the modulation signal 126 changes from a low level to a high level. As a result, the input signal IN_L of the low side gate driver 386 changes from the high level to the low level, and thereafter, the input signal IN_H of the high side gate driver 385 changes from the low level to the high level.

  When IN_L becomes low level, the potential of the second switch drive signal GL changes from GVDD to the reference potential (0 V). At this change point, the second switch QL is in an unstable state that can be either on or off because the potential difference between the gate and the source changes from a state higher than a threshold value to a low state. That is, the transition from the eleventh state to the twelfth state in which the power supply potential GVDD is the twelfth potential V12 higher than the eleventh potential V11, the first switch QH is in the off state, and the second switch QL is in an unstable state. To do.

  When the potential of the second switch drive signal GL becomes the reference potential (0 V), the second switch QL is turned off because the potential difference between the gate and the source is lower than the threshold value. That is, the transition from the twelfth state to the thirteenth state in which the power supply potential GVDD is the thirteenth potential V13 higher than the twelfth potential V12, the first switch QH is in the off state, and the second switch QL is in the off state. .

  Thereafter, while repeating the same transition, the circuit composed of the signal modulation unit 26, the signal amplification unit 28, and the signal conversion unit 29 oscillates, and the drive signal COM corresponding to the original drive signal 125 is generated.

  In the signal amplifier 28 described above, the low-side second switch QL operates with reference to the reference potential (0 V), but the high-side second switch QL includes the first switch QH and the second switch QL. Therefore, a bootstrap capacitor 383 that functions as a floating power supply is connected between the output terminal of the charge pump 381 and the SWN node. Further, since the SWN node becomes a high potential VHV (for example, 42 V) when the first switch QH on the high side is turned on, the output terminal of the charge pump 381 is connected to prevent the current from flowing backward from the SWN node to the charge pump 381 side. A backflow preventing diode 382 is provided between the capacitors 383. When the oscillation start signal ST is input and the second switch QL on the low side is turned on, a current flows from the charge pump 381 to the reference potential node (for example, ground) via the diode 382, and the capacitor 383 is charged.

  In the present embodiment, as soon as the power supply potential GVDD output from the charge pump 381 starts to rise gently in the order of ms, the potential of the second switch drive signal GL output from the low-side gate driver 386 also starts to rise. As a result, the second switch QL on the low side is turned on while the power supply potential GVDD is relatively low, so that the initial current for charging the capacitor 383 can be sufficiently reduced. Further, when the initial current flows, the first switch QH is in the OFF state, so that the current path from the power supply potential VHV to the reference potential is cut off, and the current flowing through the SWN node is only the initial current for charging the capacitor 383. It becomes. Therefore, even if a part of this small initial current flows to the piezoelectric element PZT from the SWN node via the signal conversion unit 29, it is possible to reduce the possibility of ink ejection or destruction of the piezoelectric element.

Further, according to the present embodiment, the power supply potential GVDD output from the charge pump 381 gradually rises in the order of ms, so that the capacitor 383 is slowly charged. Furthermore, as described above, by making the initial current for charging sufficiently small, the instantaneous decrease amount of the power supply potential GVDD output from the charge pump 381 can be made sufficiently small, so that the forward current of the diode 382 Since the reverse bias is not applied before the voltage reaches 0, or the reverse current (reverse current) is small even when the reverse bias is applied, the possibility of damaging the diode 382 can be reduced. Therefore, it is not necessary to use a diode with a large current resistance, a fast recovery diode, or the like as the diode 382, and an unnecessary increase in cost can be prevented. For example, when the diode 382 is built in the same IC chip as the signal amplifier 28, the chip area can be reduced and the cost can be reduced.

  Further, since the amount of decrease in the power supply potential GVDD when the initial current flows is small, it is not necessary to attach a large stabilizing capacitor to the output terminal of the charge pump 381, and low noise and constant cost can be realized.

  Note that the rise time of the power supply potential GVDD, that is, the time from the reference potential (0 V) to the maximum potential (for example, 10 V) is preferably set longer than the charging time constant of the capacitor 383.

2. Second Embodiment In the printer 1 of the second embodiment, the signal amplifying unit 28 includes a resistance element provided in series with the diode 382 between the output terminal of the charge pump 381 and the capacitor 383.

  FIG. 11 is a diagram illustrating a circuit configuration example of the signal amplification unit 28 of the printer 1 according to the second embodiment. In FIG. 11, the same components as those in FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted. In the circuit of FIG. 11, a resistance element 387 is added to the circuit of FIG. 9. One end of the resistance element 387 is connected to the output terminal of the charge pump 381, and the other end is a power source for the high-side gate driver 385. Connected to the terminal. The resistance element 387 functions as a limiting resistor that limits the current for charging the capacitor 383.

  Therefore, according to the second embodiment, compared to the first embodiment, the current flowing from the output terminal of the charge pump 381 to the reference potential node (ground) can be made smaller. The risk of destruction of the element PZT or the damage of the diode 382 can be further reduced.

3. Third Embodiment In each of the above embodiments, ripple noise remains in the drive signal COM due to an error generated by pulse modulation in the signal modulation unit 26 and demodulation in the signal amplification unit 28. However, when this ripple is transmitted through the transmission path to the piezoelectric element PZT, the waveform of the drive signal COM is lost, and the ripple noise disappears immediately before the piezoelectric element PZT. If the ink meniscus does not follow the frequency, the ink ejection is not affected and the performance of the printer 1 does not deteriorate.

  On the other hand, in each of the above embodiments, in order to reduce power consumption, when the potential of the drive signal COM does not change, the output enable signal OE is set to a low level, and the signal modulation unit 26, the signal amplification unit 28, and the signal conversion unit 29 Oscillation by the configured circuit is stopped. When the oscillation is stopped, both the first switch and the second switch are in the OFF state, but the other circuits are in the operating state. Therefore, when noise is added to the input signal of the comparator 35, the output enable signal OE next becomes the high level. The state when oscillation starts at the level becomes indefinite. This indefinite state destabilizes the ripple phase generated in the drive signal COM at the start of oscillation, so that the waveform stability of the drive signal COM is impaired. Therefore, in the third embodiment, the stability of the ripple phase of the drive signal COM is improved by always fixing the oscillation start state to the same state.

  FIG. 12 is a diagram illustrating a circuit configuration example of the signal modulation unit 26, the signal amplification unit 28, and the signal conversion unit 29 of the printer 1 according to the third embodiment. In FIG. 12, the same components as those in FIG. 8 or FIG. The third embodiment is different from the above embodiments in that a level shift circuit 90 is provided between the error amplifier 37 and the comparator 35 in the signal modulation unit 26.

  The level shift circuit 90 receives the output signal of the error amplifier 37 from the B terminal when the output signal of the error amplifier 37 is input to the A terminal, the output enable signal OE is input to the OE terminal, and the output enable signal OE is at high level. When the output enable signal OE is at a low level, the potential of the B terminal is fixed to a potential lower or higher than the comparison voltage in the comparator 35 at the next stage.

  FIG. 13A is a diagram illustrating a configuration example of the level shift circuit 90. In FIG. 13A, the level shift circuit 90 includes a resistance element 221 connected between the A terminal and the B terminal, and a resistance connected in series between the B terminal and the reference potential node (ground). Element 222 and switch 223. The switch 223 is turned off when the output enable signal OE input to the OE terminal is high level, and is turned on when the output enable signal OE is low level. That is, when the output enable signal OE is at a high level (oscillation operation), the output signal of the error amplifier 37 input to the A terminal is propagated to the B terminal, and when the output enable signal OE is at a low level (oscillation is stopped). When the ON resistance of the switch 223 is ignored, the potential difference between the A terminal and the reference potential node (0 V) is the potential divided by the resistance element 221 and the resistance element 222. Accordingly, the potential of the output terminal B is level-shifted in the direction of the reference potential (0 V) when the output enable signal OE is at a low level (when oscillation is stopped). For example, by making the resistance value of the resistance element 222 sufficiently larger than the resistance value of the resistance element 221, the potential of the output terminal B when the output enable signal OE is at a low level (when oscillation is stopped) is set to the reference potential ( 0V), which is lower than the comparison voltage in the comparator 35 at the next stage. As a result, when the output enable signal OE is at a low level (when oscillation is stopped), the output of the comparator 35 is fixed at the reference potential (0 V). When the output enable signal OE is at a low level (when oscillation is stopped), the potential of the output terminal B may be shifted in the direction of the power supply potential. In this case, the modulation signal output from the comparator 35 is used. 126 is fixed to the power supply potential VDD.

  FIG. 13B is a diagram illustrating another configuration example of the level shift circuit 90. In FIG. 13B, the level shift circuit 90 includes a constant voltage source 224 that generates a constant voltage with reference to a reference potential, an output signal of the error amplifier 37 input to the A terminal, or a constant voltage from the constant voltage source 224. And a switch 225 that outputs to the B terminal. The switch 225 selects the output signal of the error amplifier 37 when the output enable signal OE input to the OE terminal is high level and outputs it to the B terminal, and the constant voltage source 224 when the output enable signal OE is low level. Is selected and output to the B terminal. That is, when the output enable signal OE is at a high level (oscillation operation), the output signal of the error amplifier 37 input to the A terminal is propagated to the B terminal, and when the output enable signal OE is at a low level (oscillation is stopped). The output terminal B has a constant potential. If the constant potential generated by the constant voltage source 224 is made lower than the comparison voltage in the comparator 35 at the next stage, the modulation signal 126 output by the comparator 35 when the output enable signal OE is at a low level (when oscillation is stopped). Is fixed at the reference potential (0 V). If the constant potential generated by the constant voltage source 224 is made higher than the comparison voltage in the comparator 35, the modulation signal 126 is fixed to the power supply potential VDD when the output enable signal OE is at a low level (when oscillation is stopped). .

  Thus, according to the third embodiment, since the oscillation start state is fixed, the stability of the ripple phase of the drive signal COM at the start of oscillation can be improved.

4). Fourth Embodiment In the third embodiment, the oscillation start state is always fixed to the same state, but the oscillation stop state is not fixed. Therefore, in the fourth embodiment, the stability of the ripple phase of the drive signal COM is further improved by always fixing the oscillation start state and the oscillation stop state to the same state.

  FIG. 14 is a diagram illustrating a circuit configuration example of the signal modulation unit 26, the signal amplification unit 28, and the signal conversion unit 29 of the printer 1 according to the fourth embodiment. 14, the same components as those in FIG. 12 are denoted by the same reference numerals, and the description thereof is omitted. The fourth embodiment differs from the third embodiment in that an output enable (OE) control circuit 92 is provided in the signal modulation unit 26 between the error amplifier 37 and the comparator 35 instead of the level shift circuit 90. .

  In the OE control circuit 92, the output signal of the error amplifier 37 is input to the A terminal, the output enable signal OE is input to the OE terminal, the modulation signal 126 output from the comparator 35 is input to the C terminal, and the output enable signal OE. When the signal is at the high level, the output signal of the error amplifier 37 is output from the B terminal. When the output enable signal OE is at the low level, the potential at the B terminal is lower or higher than the comparison voltage in the comparator 35 at the next stage. Fix to potential. The OE control circuit 92 generates an OE signal for the gate drive circuit 38 in accordance with the output enable signal OE and the modulation signal 126 and outputs it from the D terminal.

  FIG. 15A is a diagram illustrating a configuration example of the OE control circuit 92. In FIG. 15A, the OE control circuit 92 includes a resistance element 231 connected between the A terminal and the B terminal, and a resistance connected in series between the B terminal and the reference potential node (ground). An element 232 and a switch 233 and an internal OE generation circuit 234 are included. The internal OE generation circuit 234 outputs a high-level internal OE signal when the output enable signal OE is high level, and at the falling edge of the modulation signal 126 when the output enable signal OE changes from high level to low level. An internal OE signal that becomes a low level is output. This internal OE signal is output from the D terminal and input to the OE terminal of the gate drive circuit 38. Therefore, when the internal OE signal changes from high level to low level and oscillation stops, the output of the comparator 35 is always at the reference potential (0 V), and the state at the time of oscillation stop is fixed.

  The switch 233 is turned off if the internal OE signal generated by the internal OE generation circuit 234 is high level, and turned on if the internal OE signal is low level. That is, when the internal OE signal is at a high level (oscillation operation), the output signal of the error amplifier 37 input to the A terminal is propagated to the B terminal, and when the internal OE signal is at a low level (when oscillation is stopped). If the ON resistance of the switch 233 is ignored, the potential of the output terminal B becomes a potential obtained by dividing the potential difference between the A terminal and the reference potential node (0 V) by the resistance element 231 and the resistance element 232. Accordingly, the potential of the output terminal B is level-shifted in the direction of the reference potential (0 V) when the internal OE signal is at a low level (when oscillation is stopped). For example, by making the resistance value of the resistance element 232 sufficiently larger than the resistance value of the resistance element 231, the potential of the output terminal B when the internal OE signal is at a low level (when oscillation is stopped) is set to the reference potential (0 V). ) And lower than the comparison voltage in the comparator 35 at the next stage. As a result, when the internal OE signal is at a low level (when oscillation is stopped), the output of the comparator 35 is fixed at the reference potential (0 V). Thereby, the state at the start of the next oscillation is also fixed.

  Note that the internal OE generation circuit 234 may output an internal OE signal that becomes a rising low level of the modulation signal 126 when the output enable signal OE changes from a high level to a low level. Even in this case, when the internal OE signal changes from the high level to the low level and the oscillation stops, the output of the comparator 35 is always the power supply potential VDD, and the state when the oscillation is stopped is fixed.

  Further, when the internal OE signal is at a low level (when oscillation is stopped), the potential of the output terminal B may be shifted in the direction of the power supply potential. In this case, the modulation signal 126 output by the comparator 35 is used. Is fixed at the power supply potential VDD. Thereby, the state at the start of the next oscillation is also fixed.

  FIG. 15B is a diagram illustrating another configuration example of the OE control circuit 92. In FIG. 15B, the OE control circuit 92 includes an internal OE generation circuit 234, a constant voltage source 235 that generates a constant voltage with reference to the reference potential, and an output signal or constant of the error amplifier 37 that is input to the A terminal. And a switch 236 for selecting a constant voltage from the voltage source 235 and outputting it to the B terminal. The function of the internal OE generation circuit 234 is the same as that in FIG. The internal OE generation circuit 234 fixes the state when oscillation is stopped.

  The switch 236 selects the output signal of the error amplifier 37 when the internal OE signal is high level and outputs it to the B terminal, and selects the constant voltage from the constant voltage source 235 when the internal OE signal is low level. Output to B terminal. That is, when the internal OE signal is at a high level (oscillation operation), the output signal of the error amplifier 37 input to the A terminal is propagated to the B terminal, and when the internal OE signal is at a low level (when oscillation is stopped). The output terminal B has a constant potential. If the constant potential generated by the constant voltage source 235 is made lower than the comparison voltage in the comparator 35 at the next stage, when the internal OE signal is at a low level (when oscillation is stopped), the modulation signal 126 output from the comparator 35 is generated. The reference potential (0 V) is fixed. If the constant potential generated by the constant voltage source 235 is made higher than the comparison voltage in the comparator 35, the modulation signal 126 is fixed to the power supply potential VDD when the internal OE signal is at a low level (when oscillation is stopped). Thereby, the state at the start of the next oscillation is also fixed.

  As described above, according to the fourth embodiment, since the oscillation stop state is fixed, the stability of the ripple phase of the drive signal COM at the start of oscillation can be improved, and the oscillation start state is also fixed. The potential of the drive signal COM when oscillation is stopped can be stabilized.

5. Fifth Embodiment In each of the above embodiments, for example, the self-excited oscillation frequency varies due to variations in the coil L and the capacitor C included in the signal conversion unit 29, and the amplitude of the ripple generated in the drive signal COM varies. If the amplitude of the ripple varies, the center voltage of the ripple also varies, and the waveform accuracy of the drive signal COM may be deteriorated. Therefore, in the fifth embodiment, a function for automatically adjusting the center voltage of the ripple generated in the drive signal COM is added.

  FIG. 16 is a diagram illustrating a circuit configuration example of the drive signal generation unit 14 of the printer 1 according to the fifth embodiment. In FIG. 16, the same components as those in FIG. 8 or FIG. 9 are denoted by the same reference numerals, and the description thereof is omitted. The fifth embodiment is different from the above embodiments in that the drive signal generation unit 14 is provided with a DAC adjustment unit 94 that adjusts the reference voltage of the DAC 39 according to the ripple generated in the drive signal COM.

The DAC adjustment unit 94 includes an average value measurement circuit 241, a correction value calculation circuit 242, and a reference voltage adjustment circuit 243. In the present embodiment, the CPU 12 shifts to the reference voltage adjustment mode of the DAC 39, and in this mode, the m input terminals DIN1 to DINm of the DAC 39 are set to fixed values. In this state, the average value measurement circuit 241 measures the average value of ripples generated in the drive signal COM. Next, the correction value calculation circuit 242 sends the correction value to the reference voltage adjustment circuit 243 until the average value of ripples measured by the average value measurement circuit 241 falls within the target value range. The reference voltage adjustment circuit 243 adjusts the high-potential side reference voltage VRH and the low-potential side reference voltage VRL of the DAC 39 in accordance with the correction value from the correction value calculation circuit 242. The reference voltage adjustment circuit 243 holds the reference voltage VRH and the reference voltage VRL corresponding to the correction value when the average value of the ripple is within the target value range, and the CPU 12 outputs the normal operation mode (output of the drive signal COM). Mode). The reference voltage adjustment mode of the DAC 39 is automatically executed every time the printer 1 is turned on, for example.

  As described above, according to the fifth embodiment, the voltage error of the drive signal COM is automatically corrected, so that the waveform accuracy of the drive signal COM can be maintained regardless of component variations and changes with time. Therefore, it is possible to use a lower-cost part having a large error.

  The above-described embodiments are not limited to the line head type liquid jet printing apparatus, and the same effect can be obtained even with other types of liquid jet printing apparatuses such as a serial head type. .

6). Others The present invention includes configurations that are substantially the same as the configurations described in the above embodiments and application examples (for example, configurations that have the same functions, methods, and results, or configurations that have the same objects and effects). The present invention also includes a configuration in which non-essential portions of the configuration described in the embodiments and the like are replaced. Further, the present invention includes a configuration that achieves the same effect as the configuration described in the embodiments and the like, or a configuration that can achieve the same object. Further, the present invention includes a configuration in which a known technique is added to the configuration described in the embodiments and the like.

  The present invention is not limited to the present embodiment, and various modifications can be made within the scope of the gist of the present invention.

  For example, in each of the above embodiments, the charge pump 381 is used as a power source for the high-side gate driver 385 and the low-side gate driver 386. However, the power pump is not limited to the charge pump, and any power source that can output a slowly rising power source potential may be used. For example, a power supply using an RC time constant circuit may be used.

  The above-described embodiments are examples, and the present invention is not limited to these. For example, the embodiments can be appropriately combined.

DESCRIPTION OF SYMBOLS 1 Printer, 10 Controller, 11 Interface part, 12 CPU, 13 Memory, 14 Drive signal generation part, 15 Control signal generation part, 16 Conveyance signal generation part, 20 Cable, 21 Winding axis, 22 Relay roller, 25 original drive signal generation Unit, 26 signal modulation unit, 28 signal amplification unit, 29 signal conversion unit, 30 paper transport mechanism, 31a driving roller, 31b driven roller, 32 relay roller, 33 relay roller, 34a driving roller, 34b driven roller, 35 comparator, 37 error amplifier, 38 gate drive circuit, 40 head unit, 41 head, 42 platen, 51 wiper, 52 cap, 53 ink receiver, 61 relay roller, 62 take-up drive shaft, 70 detector group, 80 computer, 90 level Shift circuit, 92 output enable OE control circuit, 94 DAC adjustment unit, 111 print data, 112 amplification instruction signal, 125 original drive signal, 126 modulation signal, 128 amplification modulation signal, 201 selection switch, 211 shift register, 212 latch circuit, 213 level shifter 221 resistance element, 222 resistance element, 223 switch, 224 constant voltage source, 225 switch, 231 resistance element, 232 resistance element, 233 switch, 234 internal OE generation circuit, 235 constant voltage source, 236 switch, 241 average value measurement circuit 242 correction value calculation circuit, 243 reference voltage adjustment circuit, 381 charge pump, 382 diode, 383 capacitor, 384 driver control circuit, 385 high side gate driver, 386 low side gate driver, 387 resistance element, 402 Link supply path, 404 nozzle communication path, 406 elastic plate, C condenser, CA cavity, CH channel signal, COM drive signal, GH gate input signal, GL gate input signal, GVDD power supply potential, HC head controller, IN_H high side gate Driver input signal, IN_L Low side gate driver input signal, L coil, LAT latch signal, NZ nozzle, OE output enable signal, PCOM drive pulse, PZT piezoelectric element, QH switching element, QL switching element, S paper, SCK clock signal SI & SP drive pulse selection data, SI pixel data, SP waveform pattern data, ST oscillation start signal, VHV power supply potential

Claims (8)

A liquid ejection apparatus that includes a piezoelectric element and ejects liquid by applying a drive signal to the piezoelectric element,
An original drive signal generator for generating an original drive signal;
A signal modulator that modulates the original drive signal to generate a modulated signal;
A signal amplifying unit including a first switch and a second switch, and amplifying the modulated signal by performing power amplification of the modulated signal by driving the first switch and the second switch;
A signal converter that smoothes the amplified modulated signal to generate the drive signal;
With
The signal modulation unit includes a comparator that generates the modulation signal;
When both the first switch and the second switch are turned off , the potential of the modulation signal is fixed at a low level by lowering the potential of the signal input to the comparator. Liquid ejecting device. Wherein that signal having a constant potential to the comparator is input, a liquid ejecting apparatus according to claim 1, characterized in that the potential of the modulation signal is fixed at the low level. A liquid ejection apparatus that includes a piezoelectric element and ejects liquid by applying a drive signal to the piezoelectric element,
An original drive signal generator for generating an original drive signal;
A signal modulator that modulates the original drive signal to generate a modulated signal;
A signal amplifying unit including a first switch and a second switch, and amplifying the modulated signal by performing power amplification of the modulated signal by driving the first switch and the second switch;
A signal converter that smoothes the amplified modulated signal to generate the drive signal;
With
The liquid ejection apparatus according to claim 1, wherein when both the first switch and the second switch are turned off, the potential of the modulation signal is fixed to a high level . The signal modulation unit includes a comparator that generates the modulation signal;
The liquid ejection apparatus according to claim 3 , wherein the potential of the modulation signal is fixed to a high level by increasing the potential of the signal input to the comparator. The liquid ejecting apparatus according to claim 4 , wherein the potential of the modulation signal is fixed at a high level when a signal having a constant potential is input to the comparator. When the potential of the driving signal does not change, the liquid ejecting apparatus according to any one of claims 1 to 5, characterized in that the both turned off and the first switch and the second switch. A drive signal generation circuit for generating a drive signal for driving a capacitive load,
An original drive signal generator for generating an original drive signal;
A signal modulator that modulates the original drive signal to generate a modulated signal;
A signal amplifying unit including a first switch and a second switch, and amplifying the modulated signal by performing power amplification of the modulated signal by driving the first switch and the second switch;
A signal converter that smoothes the amplified modulated signal to generate the drive signal;
With
The signal modulation unit includes a comparator that generates the modulation signal;
When both the first switch and the second switch are turned off , the potential of the modulation signal is fixed at a low level by lowering the potential of the signal input to the comparator. A drive signal generation circuit. A drive signal generation circuit for generating a drive signal for driving a capacitive load,
An original drive signal generator for generating an original drive signal;
A signal modulator that modulates the original drive signal to generate a modulated signal;
A signal amplifying unit including a first switch and a second switch, and amplifying the modulated signal by performing power amplification of the modulated signal by driving the first switch and the second switch;
A signal converter that smoothes the amplified modulated signal to generate the drive signal;
With
When the first switch and the second switch are both turned off, the potential of the modulation signal is fixed at a high level .