JP7115109B2 - Liquid ejector - Google Patents

Description

The present invention relates to a liquid ejection device.

2. Description of the Related Art Inkjet printers (liquid ejection devices) that eject liquid such as ink to print images and documents are known to use piezoelectric elements such as piezoelectric elements. The piezoelectric elements are provided in the print head so as to correspond to the plurality of nozzles that eject ink and the cavities that store the ink ejected from the nozzles. When the piezoelectric element is displaced according to the drive signal, the vibration plate provided between the piezoelectric element and the cavity is bent, and the volume of the cavity is changed. As a result, a predetermined amount of ink is ejected from the nozzle at a predetermined timing to form dots on the medium.

In Patent Document 1, a piezoelectric element that is displaced based on a potential difference between an upper electrode and a lower electrode is supplied with a drive signal generated based on print data to the upper electrode and a reference voltage is supplied to the lower electrode. , discloses a liquid ejection device that ejects ink by controlling the displacement of a piezoelectric element by controlling whether or not to supply a drive signal by a selection circuit (switch circuit).

JP-A-2017-43007

In a liquid ejecting apparatus that ejects ink based on the displacement of a piezoelectric element as described in Patent Document 1, when an unintended DC voltage is supplied to the piezoelectric element, unintended displacement continues to occur in the piezoelectric element. . When an unintended displacement occurs in the piezoelectric element, the diaphragm is also displaced based on the displacement. As a result, the diaphragm is flexed more than expected, and unintended stress is applied to the diaphragm.

When such unintended stress is applied to the diaphragm continuously for a long period of time, the stress concentrates around the contact point between the diaphragm and the cavity, and cracks or the like may occur in the diaphragm.

Furthermore, when the state in which the diaphragm is unintentionally bent is shifted to the discharge operation, an excessive load is applied to the diaphragm, and the load may cause cracks or the like in the diaphragm.

If a crack occurs in the vibration plate, the ink stored in the cavity leaks from the crack, and the amount of ejected ink varies with changes in the volume of the cavity. As a result, ink ejection accuracy deteriorates.

Furthermore, when ink leaking from the crack adheres to both the upper electrode and the lower electrode of the piezoelectric element, a current path is formed between the upper electrode and the lower electrode through the ink. As a result, the potential of the reference voltage signal supplied to the lower electrode fluctuates. When the reference voltage signal is commonly supplied to a plurality of piezoelectric elements, variations in the potential of the reference voltage signal affect the displacement of the plurality of piezoelectric elements. That is, there is a possibility that the ink ejection accuracy of the entire liquid ejection apparatus may be affected, not just the ejection accuracy from the nozzle corresponding to the cracked vibration plate.

The problem of displacement occurring in the piezoelectric element and the diaphragm due to continuous application of an unintended voltage to the piezoelectric element for a long period of time is a new problem that is not disclosed in Patent Document 1 as well.

One aspect of the liquid ejection device according to the present invention has a first electrode to which a drive signal is supplied and a second electrode to which a reference voltage signal is supplied. a piezoelectric element that is displaced; a cavity filled with liquid ejected from a nozzle as the piezoelectric element is displaced; a diaphragm provided between the cavity and the piezoelectric element; and the drive signal. a first switch circuit having a first terminal to be supplied and a second terminal electrically connected to the first electrode, and controlling supply of the drive signal to the first electrode; It has a first mode in which electric charges at a first node where the first electrode and the second terminal are electrically connected are discharged via a parasitic diode of the first switch circuit.

In one aspect of the liquid ejection device, the first switch circuit includes an NMOS transistor and a PMOS transistor, and the first terminal is electrically connected to the drain terminal of the NMOS transistor and the source terminal of the PMOS transistor. The second terminal is electrically connected to the source terminal of the NMOS transistor and the drain terminal of the PMOS transistor, and in the first mode, the back gate terminal of the NMOS transistor and the back gate terminal of the PMOS transistor are connected. The gate terminal may be electrically connected to the ground terminal.

In one aspect of the liquid ejection device, the first mode may be entered when the first switch circuit is off.

In one aspect of the liquid ejecting apparatus, a reference voltage signal generation circuit that outputs the reference voltage signal from a third terminal, and a second switch circuit that is provided to switch electrical connection between the third terminal and a ground terminal. and a second mode in which the charge of a second node where the second electrode and the third terminal are electrically connected is discharged via the second switch circuit.

In one aspect of the liquid ejecting apparatus, the first mode may be entered after the second mode is entered.

In one aspect of the liquid ejection device, the second mode may be entered when the first switch circuit is off.

In one aspect of the liquid ejecting apparatus, the liquid ejecting apparatus includes a drive circuit that outputs the drive signal from a fourth terminal, and a third switch circuit that is provided to switch electrical connection between the fourth terminal and a ground terminal, A third mode may be provided in which electric charges at a third node to which the first terminal and the fourth terminal are connected are released via the third switch circuit.

In one aspect of the liquid ejection device, the first mode may be entered after the third mode is entered.

In one aspect of the liquid ejection device, the third mode may be set when the first switch circuit is off.

One aspect of the liquid ejection device according to the present invention has a first electrode to which a drive signal is supplied and a second electrode to which a reference voltage signal is supplied. a piezoelectric element that is displaced; a cavity filled with liquid ejected from a nozzle as the piezoelectric element is displaced; a diaphragm provided between the cavity and the piezoelectric element; and the drive signal. a first switch circuit having a first terminal to be supplied and a second terminal electrically connected to the first electrode, and controlling supply of the drive signal to the first electrode; The first switch circuit includes a PMOS transistor, the first terminal electrically connected to the source terminal of the PMOS transistor, the second terminal electrically connected to the drain terminal of the PMOS transistor, and the PMOS transistor The back gate terminal of is electrically connected to one end of the switch element, and the other end of the switch element is electrically connected to the ground terminal.

In one aspect of the liquid ejection device, the source terminal is electrically connected to a first P-type semiconductor layer provided on the N-type semiconductor layer, and the drain terminal is connected to the first P-type semiconductor layer. It may be electrically connected to a second P-type semiconductor layer spaced from the N-type semiconductor layer, and the back gate terminal may be electrically connected to the N-type semiconductor layer.

In one aspect of the liquid ejection device, the switch element is provided in a fourth switch circuit, and the fourth switch circuit supplies a voltage to the back gate terminal or connects the back gate terminal and the ground terminal. You may control whether to electrically connect with.

1 is a perspective view showing a schematic configuration of a liquid ejection device; FIG. 3 is a block diagram showing the electrical configuration of the liquid ejection device; FIG. FIG. 4 is a flowchart for explaining mode transitions in each operation mode of the liquid ejecting apparatus; 3 is a block diagram showing the circuit configuration of a drive signal generation circuit; FIG. 3 is a circuit diagram showing the circuit configuration of a reference voltage signal generation circuit; FIG. 3 is a circuit diagram showing an electrical configuration of a power supply switching circuit; FIG. FIG. 4 is a diagram showing an example of a drive signal COM in print mode; 4 is a block diagram showing the electrical configuration of the ejection module and the driving IC; FIG. 4 is a circuit diagram showing an electrical configuration of a selection circuit; FIG. FIG. 10 is a diagram showing decoded contents in a decoder; FIG. 4 is a diagram for explaining the operation of the drive IC in print mode; Fig. 2 is an exploded perspective view of the ejection module; It is a sectional view showing a schematic structure of a discharge part. FIG. 3 is a diagram showing an example of an ejection module and an arrangement of a plurality of nozzles provided in the ejection module; FIG. 10 is a diagram for explaining the relationship between the displacement of the piezoelectric element and diaphragm and ejection; FIG. 4 is a diagram schematically showing displacements of a piezoelectric element and a diaphragm when a voltage value of an electrode of the piezoelectric element is increased; 4 is a plan view when the diaphragm is viewed from direction Z; FIG. FIG. 4 is a diagram illustrating a case where a diaphragm has a primary natural vibration; FIG. 4 is a diagram illustrating a case where a diaphragm has a third-order natural vibration; FIG. 4 is a diagram for explaining discharge means for discharging electric charges of a piezoelectric element; 3 is a cross-sectional view schematically showing a transistor forming a transfer gate; FIG. FIG. 10 is a flowchart for explaining operations in transition mode;

Preferred embodiments of the present invention will be described below with reference to the drawings. The drawings used are for convenience of explanation. It should be noted that the embodiments described below do not unduly limit the scope of the invention described in the claims. Moreover, not all the configurations described below are essential constituent elements of the present invention.

Hereinafter, the liquid ejecting apparatus according to the present invention will be described by taking an inkjet printer, which is a printing apparatus that ejects ink as liquid, as an example.

Examples of liquid ejecting apparatuses include printing apparatuses such as inkjet printers, color material ejecting apparatuses used for manufacturing color filters of liquid crystal displays, and electrode material ejecting apparatuses used for forming electrodes such as organic EL displays and surface emitting displays. devices, bioorganic matter ejecting devices used for manufacturing biochips, and the like.

1 Configuration of Liquid Ejecting Apparatus A printing apparatus, which is an example of a liquid ejecting apparatus according to the present embodiment, ejects ink according to image data supplied from an external host computer to form dots on a print medium such as paper. It is an inkjet printer that forms and prints an image including characters, figures, etc., according to the image data.

FIG. 1 is a perspective view showing a schematic configuration of the liquid ejection device 1. FIG. FIG. 1 shows a direction X in which the medium P is transported, a direction Y in which the moving body 2 reciprocates across the direction X, and a direction Z in which ink is ejected. In addition, in this embodiment, the direction X, the direction Y, and the direction Z are described as axes orthogonal to each other.

As shown in FIG. 1, the liquid ejecting apparatus 1 includes a moving body 2 and a moving mechanism 3 that reciprocates the moving body 2 along the Y direction.

The moving mechanism 3 includes a carriage motor 31 serving as a driving source for the moving body 2, a carriage guide shaft 32 fixed at both ends, and a timing belt 33 extending substantially parallel to the carriage guide shaft 32 and driven by the carriage motor 31. and have

A carriage 24 included in the moving body 2 is supported by a carriage guide shaft 32 so as to be able to reciprocate, and is fixed to a portion of a timing belt 33 . Therefore, by driving the timing belt 33 by the carriage motor 31 , the moving body 2 is guided by the carriage guide shaft 32 and reciprocates along the Y direction.

A head unit 20 is provided at a portion of the moving body 2 that faces the medium P. As shown in FIG. This head unit 20 has a large number of nozzles, and ink is ejected along the direction Z from each of the nozzles. Control signals and the like are also supplied to the head unit 20 via the flexible cable 190 .

The liquid ejection device 1 includes a transport mechanism 4 that transports the medium P along the direction X on the platen 40 . The transport mechanism 4 includes a transport motor 41 that is a drive source, and transport rollers 42 that are rotated by the transport motor 41 to transport the medium P along the direction X. As shown in FIG.

An image is formed on the surface of the medium P by the head unit 20 ejecting ink onto the medium P at the timing when the medium P is conveyed by the conveying mechanism 4 .

FIG. 2 is a block diagram showing the electrical configuration of the liquid ejection device 1. As shown in FIG.

As shown in FIG. 2, the liquid ejection device 1 has a control unit 10 and a head unit 20. As shown in FIG. Also, the control unit 10 and the head unit 20 are connected by a flexible cable 190
connected via

The control unit 10 includes a control circuit 100 , a carriage motor driver 35 , a transport motor driver 45 and a voltage generation circuit 90 .

The control circuit 100 supplies a plurality of control signals and the like for controlling various configurations based on image data supplied from the host computer.

Specifically, the control circuit 100 supplies a control signal CTR 1 to the carriage motor driver 35 . The carriage motor driver 35 drives the carriage motor 31 according to the control signal CTR1. This controls the movement in the direction Y of the carriage 24 shown in FIG.

Also, the control circuit 100 supplies a control signal CTR2 to the transport motor driver 45 . The carry motor driver 45 drives the carry motor 41 according to the control signal CTR2. Thereby, the movement of the medium P in the direction X by the transport mechanism 4 shown in FIG. 1 is controlled.

The control circuit 100 also supplies the head unit 20 with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, an operation mode signal MC, a drive data signal DRV, and a select signal EN.

The voltage generation circuit 90 generates a voltage VHV of DC 42 V, for example, and supplies it to the head unit 20 . Note that the voltage VHV may also be supplied to various components included in the control unit 10 .

The head unit 20 includes a drive signal generation circuit 50 , a power supply switching circuit 70 , a drive IC 80 and an ejection module 21 .

A voltage VHV, a drive data signal DRV, and a select signal EN are supplied to the drive signal generation circuit 50 .

The drive signal generation circuit 50 class-D-amplifies a signal based on the drive data signal DRV to a voltage based on the voltage VHV, thereby generating the drive signal COM and supplying it to the drive IC 80 . Further, the drive signal generation circuit 50 generates a reference voltage signal VBS of, for example, DC 5V by stepping down the voltage VHV, and supplies the reference voltage signal VBS to the ejection module 21 . The drive signal generation circuit 50 also generates a power supply control signal CTVHV based on the drive data signal DRV and supplies the power supply switching circuit 70 with the power supply control signal CTVHV. Here, the select signal EN determines whether the drive data signal DRV supplied to the drive signal generation circuit 50 is a data signal for generating the drive signal COM or a data signal for generating the power supply control signal CTVHV. It is a signal for instructing.

Further, the drive signal generation circuit 50 supplies an error signal ERR to the control circuit 100 when the drive signal COM to be generated is not normal.

The power supply switching circuit 70 is supplied with the voltage VHV and the power supply control signal CTVHV. The power supply switching circuit 70 switches the potential of the voltage VHV-TG supplied to the driving IC 80 between the potential based on the voltage VHV and the ground potential in accordance with the power supply control signal CTVHV.

The drive IC 80 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, an operation mode signal MC, a voltage VHV-TG and a drive signal COM.

The drive IC 80 selects or deselects the drive signal COM in a predetermined period based on the clock signal SCK, print data signal SI, operation mode signal MC, latch signal LAT, and change signal CH. Then, the drive signal COM selected by the drive IC 80 is supplied to the ejection module 21 as the drive signal VOUT. The voltage VHV-TG is used, for example, to generate a high-voltage logic signal for selecting the drive signal COM.

The ejection module 21 has a plurality of ejection portions 600 including piezoelectric elements 60 .

A drive signal VOUT supplied to the ejection module 21 is supplied to one end of the piezoelectric element 60 . A reference voltage signal VBS is supplied to the other end of the piezoelectric element 60 . The piezoelectric element 60 is displaced according to the potential difference between the drive signal VOUT and the reference voltage signal VBS. Then, an amount of ink corresponding to the displacement is ejected from the ejection section 600 .

Details of the drive signal generation circuit 50, the power supply switching circuit 70, the drive IC 80, and the ejection module 21 will be described later. Further, in FIG. 2, the liquid ejection apparatus 1 is provided with one head unit 20, but a plurality of head units 20 may be provided. In addition, in FIG. 2, the head unit 20 has one ejection module 21, but a plurality of ejection modules 21 may be provided.

The liquid ejecting apparatus 1 as described above has a plurality of operation modes including print mode, standby mode, transition mode and sleep mode.

The print mode is an operation mode in which printing can be executed by ejecting ink onto the medium P based on supplied image data. The standby mode is an operation mode in which printing can be executed in a short time when image data is supplied while power consumption is reduced compared to the print mode. Transition mode is an operation mode during transition from standby mode to sleep mode. Sleep mode is an operation mode that can further reduce power consumption compared to standby mode.

Here, the relationship between the operation modes of the liquid ejecting apparatus 1 will be described with reference to FIG. 3. FIG. FIG. 3 is a flowchart for explaining mode transitions in each operation mode of the liquid ejecting apparatus 1. As shown in FIG.

As shown in FIG. 3, when power is supplied to the liquid ejection apparatus 1, the control circuit 100 controls the operation mode to the standby mode (S110). After transitioning to the standby mode, the control circuit 100 determines whether or not a predetermined time has elapsed (S120).

If the predetermined time has not passed (N of S120), the control circuit 100 determines whether image data is supplied to the liquid ejection device 1 (S130).

If the image data is not supplied (N of S130), the standby mode is continued. On the other hand, if image data is supplied (Y of S130), the control circuit 100 controls the operation mode to print mode (S140).

In the print mode, the drive signal generation circuit 50 determines whether the drive signal COM is normal (S150). If the drive signal COM is normal (Y of S150), it is determined whether or not printing corresponding to the supplied image data has been completed (S160). If printing has not ended (N of S160), the drive signal generation circuit 50 determines whether or not the drive signal COM is normal (S150).

In the print mode, when printing corresponding to the supplied image data is completed (Y of S160), the control circuit 100 controls the operation mode to the standby mode (S110).

When the predetermined time has passed (Y of S120) and when the drive signal COM is not normal (N of S150), the control circuit 100 controls the operation mode to the transition mode (S170). After ending the transition mode, the control circuit 100 controls the operation mode to the sleep mode (S180).

After transitioning to the sleep mode, the control circuit 100 determines whether image data is supplied to the liquid ejection device 1 (S190).

If the image data is not supplied (N of S190), the sleep mode is continued. On the other hand, if image data is supplied (Y of S190), the control circuit 100 controls the operation mode to print mode (S140).

The liquid ejecting apparatus 1 may include operation modes other than the operation modes described above as the plurality of operation modes. For example, the liquid ejecting apparatus 1 may include operation modes such as a test print mode in which test printing is performed on the medium P, and a stop mode in which the operation is stopped due to running out of ink, transportation failure of the medium P, or the like.

2 Configuration and Operation of Drive Signal Generation Circuit Next, the drive signal generation circuit 50 will be described with reference to FIG. FIG. 4 is a block diagram showing the circuit configuration of the drive signal generation circuit 50. As shown in FIG. As shown in FIG. 4, the drive signal generation circuit 50 has an integrated circuit 500, an output circuit 550, a first feedback circuit 570, a second feedback circuit 580, and a plurality of other circuit elements.

The drive signal generation circuit 50 also includes terminals Drv-In, En-In, Err-Out, Vhv-In, Vbs-Out, Ctvh-Out, and Com-Out for electrically connecting to various external components. , Gnd-In. Among them, the ground potential (for example, 0 V) of the liquid ejection device 1 is supplied to the terminal Gnd-In.

The integrated circuit 500 includes a GVDD generation circuit 410, a signal selection circuit 420, a power supply control signal generation circuit 430, a reference voltage signal generation circuit 450, a DAC (Digital to Analog Converter) circuit 310, a detection circuit 320, a determination circuit 350, and a modulation circuit 510. , a gate drive circuit 520 and an LC discharge circuit 530 .

The integrated circuit 500 also includes terminals Drv, En, Err, Vhv, Vfb, Vbs, Ctvh, Bst, Hdr, Sw, Gvd, Ldr, and Gnd for electrically connecting to various components of the drive signal generation circuit 50. has a plurality of terminals including;

A voltage VHV is supplied to the GVDD generating circuit 410 through a terminal Vhv-In and a terminal Vhv. The GVDD generation circuit 410 transforms the voltage VHV to generate the voltage GVDD and supplies it to the reference voltage signal generation circuit 450 and the gate drive circuit 520 .

The GVDD generating circuit 410 is composed of, for example, a linear regulator circuit or a switching regulator circuit. Note that the GVDD generation circuit 410 may be provided outside the integrated circuit 500 .

The signal selection circuit 420 is supplied with the drive data signal DRV through the terminal Drv-In and the terminal Drv, and the select signal EN through the terminal En-In and the terminal En. The signal selection circuit 420 determines whether the drive data signal DRV is a signal to be supplied to the DAC circuit 310 or a signal to be supplied to each of the reference voltage signal generation circuit 450, the power supply control signal generation circuit 430, and the LC discharge circuit 530. is determined based on the select signal EN, and supplied to each of the components.

Specifically, the signal selection circuit 420 includes a plurality of registers (not shown). Then, when the drive data signal DRV is a signal to be supplied to the DAC circuit 310, the signal selection circuit 420 holds the drive data signal DRV in a plurality of registers corresponding to the DAC circuit 310 according to the select signal EN. Then, the signal selection circuit 420 supplies the held signal to the DAC circuit 310 as the digital original drive signal dA.

On the other hand, when the drive data signal DRV is a signal to be supplied to each of the reference voltage signal generation circuit 450, the power supply control signal generation circuit 430, and the LC discharge circuit 530, the signal selection circuit 420 selects the drive data signal DRV according to the select signal EN. Data corresponding to each of the reference voltage signal generation circuit 450, the power supply control signal generation circuit 430, and the LC discharge circuit 530 are held in predetermined registers. Then, the signal selection circuit 420 supplies the held signals to the power supply control signal generation circuit 430, the LC discharge circuit 530, and the reference voltage signal generation circuit 450 as the discharge control signals DIS1, DIS2, and DIS3.

A discharge control signal DIS<b>1 is supplied to the power supply control signal generation circuit 430 . The power supply control signal generation circuit 430 includes an open drain circuit (not shown). Then, when the supplied discharge control signal DIS1 is a signal indicating active, the power supply control signal generation circuit 430 turns off the open drain circuit and sets the terminal Ctvh to high impedance.

On the other hand, when the discharge control signal DIS1 is a signal indicating inactivity, the power supply control signal generation circuit 430 turns on the open drain circuit and sets the terminal Ctvh to the ground potential. At this time, the L-level power supply control signal CTVHV is supplied to the power supply switching circuit 70 shown in FIG. 2 via the terminal Ctvh and the terminal Ctvh-Out.

In the description of FIG. 20 and the like that will be described later, it is assumed that the open drain circuit included in the power supply control signal generation circuit 430 is composed of an NMOS transistor. Further, it is assumed that the discharge control signal DIS1 is supplied to the gate terminal of the NMOS transistor through an inverter circuit. Therefore, in this embodiment, a signal indicating that the discharge control signal DIS1 is active is a signal of H level, and a signal indicating that the discharge control signal DIS1 is inactive is a signal of L level. Note that the power supply control signal generation circuit 430 is not limited to an open drain circuit, and may be configured by, for example, a push-pull circuit.

A voltage GVDD is supplied to the reference voltage signal generation circuit 450 . The reference voltage signal generation circuit 450 steps down the supplied voltage GVDD to generate a reference voltage signal VBS.

FIG. 5 is a circuit diagram showing the circuit configuration of the reference voltage signal generation circuit 450. As shown in FIG. The reference voltage signal generation circuit 450 includes a comparator 451 , transistors 452 and 453 and resistors 454 , 455 and 456 . In the following description, it is assumed that the transistor 452 is a PMOS transistor and the transistor 453 is an NMOS transistor.

A voltage Vref1 is supplied to the input terminal (-) of the comparator 451 . Also, the input terminal (+) of the comparator 451 is commonly connected to one end of the resistor 454 and one end of the resistor 455 . Also, the output terminal of the comparator 451 is connected to the gate terminal of the transistor 452 .

A voltage GVDD is supplied to the source terminal of transistor 452 . A drain terminal of the transistor 452 is commonly connected to the other end of the resistor 454, one end of the resistor 456, and the terminal Vbs outputting the reference voltage signal VBS.

The other end of resistor 456 is connected to the drain terminal of transistor 453 .

A discharge control signal DIS3 is supplied to the gate terminal of the transistor 453 . A ground potential is supplied to the source terminal of the transistor 453 .

A ground potential is supplied to the other end of the resistor 455 .

As described above, the reference voltage signal generation circuit 450 constitutes a series regulator circuit.

The input terminal (+) of the comparator 451 is supplied with a voltage obtained by dividing the reference voltage signal VBS by the resistors 454 and 455 . When the voltage supplied to the input terminal (+) of the comparator 451 is higher than the voltage Vref1 supplied to the input terminal (-) of the comparator 451, the comparator 451 outputs an H level signal. At this time, the transistor 452 is controlled to be off. Therefore, the voltage GVDD is not supplied to the terminal Vbs.

On the other hand, when the voltage supplied to the input terminal (+) of the comparator 451 is lower than the voltage Vref1 supplied to the input terminal (-) of the comparator 451, the comparator 451 outputs an L level signal. At this time, the transistor 452 is turned on. Therefore, the voltage GVDD is supplied to the terminal Vbs.

As described above, the reference voltage signal generation circuit 450 compares the signal based on the reference voltage signal VBS with the voltage Vref1 in the comparator 451, and controls the transistor 452 to step down the voltage GVDD to reach the target. A voltage value reference voltage signal VBS is generated.

Further, when the discharge control signal DIS3 supplied to the gate terminal of the transistor 453 is an H level signal, the transistor 453 is turned on. At this time, the ground potential is supplied to the terminal Vbs through the resistor 456 . In other words, the transistor 453 is provided so as to switch electrical connection between the terminal Vbs and the terminal Vbs-Out and the ground potential. This transistor 453 is an example of the second switch circuit.

Returning to FIG. 4, the reference voltage signal VBS generated by the reference voltage signal generation circuit 450 is supplied to the ejection module 21 shown in FIG. 2 via the terminal Vbs and the terminal Vbs-Out. This reference voltage signal VBS functions as a reference voltage with which the piezoelectric element 60 is displaced. A terminal Vbs-Out for outputting the reference voltage signal VBS from the reference voltage signal generation circuit 450 is an example of a third terminal.

Note that the reference voltage signal generation circuit 450 may be provided outside the integrated circuit 500 , and furthermore, may be provided outside the drive signal generation circuit 50 .

The DAC circuit 310 converts the original drive signal dA into an analog original drive signal aA and supplies it to the modulation circuit 510 . The DAC circuit 310 also supplies the detection circuit 320 with a digital signal based on the original drive signal dA.

The detection circuit 320 detects whether the signal based on the original drive signal dA supplied from the DAC circuit 310 is within a predetermined range.

The determination circuit 350 determines whether or not the original drive signal dA is normal according to the detection result of the detection circuit 320 . When determining that the original drive signal dA is not normal, the determination circuit 350 generates an error signal ERR and supplies it to the control circuit 100 shown in FIG. 2 via the terminal Err and the terminal Err-Out.

Modulation circuit 510 includes adder 512 , adder 513 , comparator 514 , inverter 515 , integral attenuator 516 and attenuator 517 .

The integral attenuator 516 attenuates and integrates the voltage signal of the drive signal COM supplied via the terminal Vfb, and supplies the voltage signal to the input terminal (−) of the adder 512 .

The input terminal (+) of the adder 512 is supplied with the original drive signal aA. The adder 512 subtracts the voltage signal supplied to the input terminal (-) of the adder 512 from the integration attenuator 516 from the original drive signal aA supplied to the input terminal (+), and integrates the result. Then, the subtracted and integrated voltage signal is supplied to the input terminal (+) of the adder 513 .

Here, the maximum voltage of the original drive signal aA may be a low voltage of about 2V, for example, while the maximum voltage of the drive signal COM may be a high voltage of about 40V, for example. Therefore, the integral attenuator 516 attenuates the voltage of the drive signal COM in order to match the amplitude ranges of both voltages when obtaining the deviation.

The attenuator 517 attenuates the high frequency component of the voltage signal of the drive signal COM input via the terminal Ifb, and supplies the voltage to the input terminal (−) of the adder 513 .

The adder 513 outputs to the comparator 514 a voltage signal As obtained by subtracting the voltage supplied to the input terminal (−) from the attenuator 517 from the voltage supplied to the input terminal (+) from the adder 512 .

The voltage signal As output from the adder 513 is a voltage obtained by subtracting the voltage supplied to the terminal Vfb and further subtracting the voltage supplied to the terminal Ifb from the voltage of the original drive signal aA. That is, the voltage signal As is a voltage signal obtained by correcting the deviation obtained by subtracting the attenuation voltage of the output drive signal COM from the target voltage of the original drive signal aA with the high frequency component of the drive signal COM.

Comparator 514 generates modulation signal Ms based on voltage signal As supplied from adder 513 . Specifically, the comparator 514 generates the H-level modulation signal Ms when the voltage of the voltage signal As supplied from the adder 513 is increasing and when it reaches or exceeds a predetermined threshold value Vth1. Further, the comparator 514 generates the L-level modulation signal Ms when the voltage of the voltage signal As is decreasing and when it is below the predetermined threshold value Vth2. Note that the threshold Vth1 and the threshold Vth2 are set to have a relationship of threshold Vth1>threshold Vth2.

The comparator 514 supplies the generated modulated signal Ms to the first gate driver 521 included in the gate drive circuit 520 . The comparator 514 also supplies the generated modulated signal Ms to the second gate driver 522 included in the gate drive circuit 520 via the inverter 515 . Therefore, the signal supplied from the comparator 514 to the first gate driver 521 and the signal supplied to the second gate driver 522 have mutually exclusive logic levels.

Here, that the logic levels of the signals supplied to the first gate driver 521 and the second gate driver 522 are in an exclusive relationship means that the logic levels of the signals supplied to the first gate driver 521 and the second gate driver 522 It includes the concept that the timing is controlled so that the levels do not become H level at the same time.

Gate drive circuit 520 includes a first gate driver 521 and a second gate driver 522 .

The first gate driver 521 level-shifts the voltage value of the modulation signal Ms output from the comparator 514, and outputs it from the terminal Hdr as the first amplification control signal Hgd.

Specifically, of the power supply voltage of the first gate driver 521, a voltage is supplied to the high potential side through the terminal Bst and to the low potential side through the terminal Sw. A terminal Bst is commonly connected to one end of a capacitor 541 provided outside the integrated circuit 500 and the cathode terminal of a diode 542 for preventing backflow. Also, the other end of the capacitor 541 is connected to the terminal Sw. Also, the anode terminal of the diode 542 is connected to the terminal Gvd to which the voltage GVDD is supplied. Therefore, the potential difference between the terminal Bst and the terminal Sw is approximately equal to the potential difference across the capacitor 541, that is, the voltage GVDD. Then, the first gate driver 521 generates the first amplification control signal Hgd having a voltage higher than the terminal Sw by the voltage GVDD according to the input modulation signal Ms, and outputs the first amplification control signal Hgd from the terminal Hdr.

The second gate driver 522 operates on the lower potential side than the first gate driver 521 does. The second gate driver 522 level-shifts the voltage value of the signal obtained by inverting the modulated signal Ms output from the comparator 514 by the inverter 515, and outputs it from the terminal Ldr as the second amplification control signal Lgd.

Specifically, the voltage GVDD is supplied to the high potential side of the power supply voltage of the second gate driver 522, and the ground potential is supplied to the low potential side. Then, the second gate driver 522 generates the second amplification control signal Lgd having a voltage higher than the terminal Gnd by the voltage GVDD according to the inverted signal of the supplied modulation signal Ms, and outputs the second amplification control signal Lgd from the terminal Ldr.

LC discharge circuit 530 includes resistor 531 and transistor 532 . Note that the transistor 532 is assumed to be an NMOS transistor in the following description.

One end of the resistor 531 is connected to the terminal Vfb. Also, the other end of the resistor 531 is connected to the drain terminal of the transistor 532 .

A discharge control signal DIS2 is supplied to the gate terminal of the transistor 532 . A ground potential is supplied to the source terminal of the transistor 532 .

When the discharge control signal DIS2 of H level is supplied to the gate terminal of the transistor 532, the transistor 532 is turned on. At this time, the ground potential is supplied via the resistors 531 and 571 and the transistor 532 to the terminal Com-Out to which the drive signal COM is output. In other words, the transistor 532 is provided so as to switch the electrical connection between the terminal Com-Out and the ground potential. This transistor 532 is an example of a third switch circuit.

The output circuit 550 has transistors 551 and 552, resistors 553 and 554, and a low pass filter 560 (Low Pass Filter). In the following description, the transistors 551 and 552 are assumed to be NMOS transistors.

A voltage VHV is supplied to the drain terminal of the transistor 551 . Also, the gate terminal of the transistor 551 is connected to one end of the resistor 553 . Also, the source terminal of the transistor 551 is connected to the terminal Sw. The other end of resistor 553 is connected to terminal Hdr. Therefore, the gate terminal of the transistor 551 is supplied with the first amplification control signal Hgd.

The drain terminal of transistor 552 is connected to the source terminal of transistor 551 . Also, the gate terminal of the transistor 552 is connected to one end of the resistor 554 . A ground potential is supplied to the source terminal of the transistor 552 . The other end of resistor 554 is connected to terminal Ldr. Therefore, the gate terminal of the transistor 552 is supplied with the second amplification control signal Lgd.

In the transistors 551 and 552 connected as described above, when the transistor 551 is controlled to be turned off and the transistor 552 is controlled to be turned on, the connection point to which the terminal Sw is connected is at the ground potential, and the terminal Bst is at the voltage level. GVDD is supplied. On the other hand, when the transistor 551 is controlled to be on and the transistor 552 is controlled to be off, the voltage VHV is supplied to the connection point to which the terminal Sw is connected. Therefore, the terminal Bst is supplied with the voltage VHV+the voltage GVDD. That is, the first gate driver 521 that drives the transistor 551 uses the capacitor 541 as a floating power supply, and according to the operation of the transistors 551 and 552, the voltage of the terminal Sw changes to the ground potential or the voltage VHV. The gate terminal is supplied with the first amplification control signal Hgd whose L level is the voltage VHV and whose H level is the voltage VHV+voltage GVDD. The transistor 551 performs a switching operation based on the first amplification control signal Hgd.

The second gate driver 522 that drives the transistor 552 outputs the second amplification control signal Lgd whose L level is the ground potential and whose H level is the voltage GVDD regardless of the operation of the transistors 551 and 552 . The transistor 552 performs a switching operation based on the second amplification control signal Lgd.

As described above, an amplified modulated signal obtained by amplifying the modulated signal Ms based on the voltage VHV is generated at the connection point between the source terminal of the transistor 551 and the drain terminal of the transistor 552 . That is, the transistors 551 and 552 function as an amplifier circuit that amplifies the voltage of the modulation signal Ms. As described above, the first amplification control signal Hgd and the second amplification control signal Lgd that drive the transistors 551 and 552 are in an exclusive relationship. That is, the transistors 551 and 552 are controlled so as not to be turned on at the same time.

Low pass filter 560 includes inductor 561 and capacitor 562 .

One end of the inductor 561 is commonly connected to the source terminal of the transistor 551 and the drain terminal of the transistor 552 . Also, the other end of the inductor 561 is commonly connected to a terminal Com-Out from which the drive signal COM is output and one end of the capacitor 562 . A ground potential is supplied to the other end of the capacitor 562 .

Thus, inductor 561 and capacitor 562 smooth the amplified modulated signal provided to the junction of transistors 551 and 552 . Thereby, the amplified modulated signal is demodulated to generate the driving signal COM.

The first feedback circuit 570 includes resistors 571 and 572 . One end of the resistor 571 is connected to the terminal Com-Out. The other end of the resistor 571 is commonly connected to the terminal Vfb and one end of the resistor 572 . A voltage VHV is supplied to the other end of the resistor 572 . As a result, the drive signal COM that has passed through the first feedback circuit 570 from the terminal Com-Out is pulled up and fed back to the terminal Vfb.

The second feedback circuit 580 includes resistors 581,582 and capacitors 583,584,585.

One end of the capacitor 583 is connected to the terminal Com-Out. Also, the other end of the capacitor 583 is commonly connected to one end of the resistor 581 and one end of the resistor 582 . A ground potential is supplied to the other end of the resistor 581 . Thereby, the capacitor 583 and the resistor 581 function as a high pass filter. The cutoff frequency of the high-pass filter composed of the capacitor 583 and resistor 581 is set to approximately 9 MHz, for example.

Also, the other end of the resistor 582 is commonly connected to one end of the capacitor 584 and one end of the capacitor 585 . A ground potential is supplied to the other end of the capacitor 584 . Thereby, the resistor 582 and the capacitor 584 function as a low pass filter. The cutoff frequency of the low-pass filter composed of resistor 582 and capacitor 584 is set to, for example, approximately 160 MHz.

Since the second feedback circuit 580 is composed of a high-pass filter and a low-pass filter, the second feedback circuit 580 functions as a band-pass filter that passes a predetermined frequency range of the drive signal COM. do.

The other end of capacitor 585 is connected to terminal Ifb. As a result, of the high-frequency components of the driving signal COM that has passed through the second feedback circuit 580, the DC component is cut and fed back to the terminal Ifb.

By the way, the drive signal COM is a signal obtained by smoothing the amplified modulated signal by the low-pass filter 560 . This drive signal COM is fed back to the adder 512 after being integrated and subtracted via the terminal Vfb. Therefore, it self-oscillates at a frequency determined by the feedback delay and the feedback transfer function. However, since the amount of delay in the feedback path via the terminal Vfb is large, it may not be possible to increase the frequency of self-oscillation to a level sufficient to ensure the accuracy of the drive signal COM only by feedback via the terminal Vfb. . Therefore, by providing a path for feeding back the high-frequency component of the drive signal COM via the terminal Ifb in addition to the path via the terminal Vfb, the delay in the entire circuit can be reduced. As a result, the frequency of the voltage signal As becomes high enough to ensure the accuracy of the drive signal COM compared to the case where there is no path via the terminal Ifb.

Of the drive signal generation circuit 50 described above, the configuration including the modulation circuit 510, the gate drive circuit 520, the LC discharge circuit 530, the output circuit 550, the capacitor 541, and the diode 542 generates the drive signal COM described above. A terminal Com-Out, which corresponds to the driving circuit 51 and outputs a driving signal COM, is an example of the fourth terminal.

3 Configuration and Operation of Power Supply Switching Circuit Next, the configuration and operation of the power supply switching circuit 70 will be described with reference to FIG. FIG. 6 is a circuit diagram showing the electrical configuration of the power supply switching circuit 70. As shown in FIG.

The feed switching circuit 70 includes transistors 471 , 472 , 473 and resistors 474 , 475 . In the following description, the transistor 471 is assumed to be a PMOS transistor, and the transistors 472 and 473 are assumed to be NMOS transistors.

A source terminal of the transistor 471 is connected to one end of the resistor 474 and supplied with the voltage VHV. Also, the gate terminal of the transistor 471 is commonly connected to the other end of the resistor 474 and the drain terminal of the transistor 472 . Also, the drain terminal of the transistor 471 is connected to one end of the resistor 475 .

A voltage Vdd1 is supplied to the gate terminal of the transistor 472 . The source terminal of the transistor 472 is connected to the gate terminal of the transistor 473 and supplied with the power supply control signal CTVHV. Here, the voltage Vdd1 is a DC voltage signal with an arbitrary voltage value.

The drain terminal of transistor 473 is connected to the other end of resistor 475 . A ground potential is supplied to the source terminal of the transistor 473 .

The power supply switching circuit 70 configured as described above switches whether or not to supply the voltage VHV as the voltage VHV-TG to the drive IC 80 in accordance with the power supply control signal CTVHV supplied from the drive signal generation circuit 50 .

Specifically, when the discharge control signal DIS1 indicating inactivity is supplied to the power supply control signal generation circuit 430, the power supply control signal generation circuit 430 sets the terminal Ctvh-Out to the ground potential. Therefore, the power supply control signal CTVHV becomes an L level signal. As a result, the transistor 473 is turned off and the transistor 472 is turned on. Therefore, the ground potential is supplied to the gate terminal of the transistor 471 through the transistor 472 . Therefore, transistor 471 is controlled to be on.

As described above, when the power supply control signal CTVHV is an L level signal, the transistor 471 is controlled to be on and the transistor 473 is controlled to be off. Therefore, the power supply switching circuit 70 supplies the voltage VHV supplied via the transistor 471 to the driving IC 80 as the voltage VHV-TG.

On the other hand, when the discharge control signal DIS1 indicating active is supplied to the power supply control signal generation circuit 430, the power supply control signal generation circuit 430 sets the terminal Ctvh-Out to high impedance. At this time, the voltage of the terminal Ctvh-Out becomes the voltage Vdd1 supplied through the transistor 472. FIG. In other words, the power supply control signal CTVHV becomes an H level signal. This turns on the transistor 473 . At this time, the voltage VHV is supplied to the drain terminal of the transistor 472 and the gate terminal of the transistor 471 through the resistor 474 . Therefore, transistor 471 is controlled to be off.

As described above, when the power supply control signal CTVHV is an H level signal, the transistor 471 is controlled to be turned off and the transistor 473 is controlled to be turned on. Therefore, the power supply switching circuit 70 supplies the ground potential supplied via the resistor 475 and the transistor 472 to the driving IC 80 as the voltage VHV-TG.

4 Configuration and Operation of Driving IC Next, the configuration and operation of the driving IC 80 will be described.

First, an example of the drive signal COM supplied to the drive IC 80 will be described with reference to FIG. After that, the configuration and operation of the driving IC 80 will be described with reference to FIGS. 8 to 11. FIG.

FIG. 7 is a diagram showing an example of the drive signal COM in the print mode. FIG. 7 shows a period T1 from the rise of the latch signal LAT to the rise of the change signal CH, a period T2 from the rise of the change signal CH after the period T1, and the latch signal LAT after the period T2. and a period T3 until it rises. A cycle consisting of these periods T1, T2, and T3 is a cycle Ta for forming new dots on the medium P. FIG.

As shown in FIG. 7, in the print mode, the drive signal generation circuit 50 generates the voltage waveform Adp during the period T1. When the voltage waveform Adp1 is supplied to the piezoelectric element 60, a predetermined amount, specifically, a medium amount of ink is ejected from the corresponding ejector 600. FIG.

Further, the drive signal generation circuit 50 generates the voltage waveform Bdp during the period T2. When the voltage waveform Bdp is supplied to the piezoelectric element 60 , a small amount of ink smaller than the predetermined amount is ejected from the corresponding ejector 600 .

Further, the drive signal generation circuit 50 generates the voltage waveform Cdp during the period T3. When the voltage waveform Cdp is supplied to the piezoelectric element 60 , the piezoelectric element 60 is displaced to such an extent that ink is not ejected from the corresponding ejection section 600 . Therefore, no dots are formed on the medium P. This voltage waveform Cdp is a voltage waveform for vibrating the ink in the vicinity of the nozzle aperture of the ejection section 600 to prevent the viscosity of the ink from increasing. In the following description, displacing the piezoelectric element 60 to such an extent that ink is not ejected from the ejection section 600 in order to prevent the viscosity of ink from increasing will be referred to as "micro-vibration".

Here, the voltage value at the start timing and the voltage value at the end timing of the voltage waveform Adp, the voltage waveform Bdp, and the voltage waveform Cdp are all common to the voltage Vc. That is, the voltage waveforms Adp, Bdp, and Cdp are voltage waveforms whose voltage values start at the voltage Vc and end at the voltage Vc. Therefore, in the print mode, the drive signal generation circuit 50 outputs the drive signal COM having a voltage waveform in which the voltage waveforms Adp, Bdp, and Cdp are continuous in the period Ta.

Then, the voltage waveform Adp is supplied to the piezoelectric element 60 during the period T1, and the voltage waveform Bdp is supplied during the period T2. is discharged. As a result, a “large dot” is formed on the medium P. In addition, the voltage waveform Adp is supplied to the piezoelectric element 60 during the period T1, and the voltage waveform Bdp is not supplied during the period T2, so that a moderate amount of ink is ejected from the ejection section 600 during the period Ta. As a result, a “medium dot” is formed on the medium P. Also, the voltage waveform Adp is not supplied to the piezoelectric element 60 during the period T1, and the voltage waveform Bdp is supplied during the period T2, so that a small amount of ink is ejected from the ejecting section 600 during the period Ta. As a result, a "small dot" is formed on the medium P. Further, the voltage waveforms Adp and Bdp are not supplied to the piezoelectric element 60 during the periods T1 and T2, and the voltage waveform Cdp is supplied during the period T3. do. In this case, no dots are formed on the medium P.

Next, an example of the drive signal COM in the standby mode, transition mode and sleep mode will be described. Illustration of an example of the drive signal COM in the standby mode, transition mode, and sleep mode is omitted.

No ink is ejected onto the medium P in the standby mode, transition mode, and sleep mode. Therefore, periods T1, T2 and T3 are not defined. Therefore, in the standby mode, transition mode and sleep mode, the latch signal LAT and change signal CH are L level signals.

In the standby mode, the drive signal generation circuit 50 controls the voltage value of the drive signal COM to approach the voltage value of the reference voltage signal VBS.

In sleep mode, the drive signal generation circuit 50 stops operating. Here, the drive signal generation circuit 50 stops operating when the drive data signal DRV for stopping the generation of the drive signal COM is supplied to the drive signal generation circuit 50 . The signal generation circuit 50 includes outputting the ground potential as the drive signal COM.

Also, the transition mode is an operation mode during transition from the standby mode to the sleep mode as described above. In the present embodiment, the drive signal generation circuit 50 controls the voltage value of the drive signal COM to approach the voltage value of the reference voltage signal VBS before the transition to the transition mode, and stops the operation after the transition to the transition mode.

FIG. 8 is a block diagram showing the electrical configuration of the ejection module 21 and the drive IC 80. As shown in FIG. As shown in FIG. 8, the driving IC 80 includes a selection control circuit 210 and multiple selection circuits 230 .

The selection control circuit 210 is supplied with a clock signal SCK, a print data signal SI, a latch signal LAT, a change signal CH, an operation mode signal MC and a voltage VHV-TG. Also, in the selection control circuit 210, a set of a shift register 212 (S/R), a latch circuit 214, and a decoder 216 is provided corresponding to each discharge section 600. FIG. That is, the head unit 20 is provided with sets of shift registers 212 , latch circuits 214 , and decoders 216 as many as the total number n of ejection sections 600 .

The shift register 212 temporarily holds the 2-bit print data [SIH, SIL] included in the print data signal SI for each corresponding ejection unit 600 .

Specifically, the shift registers 212 of the number of stages corresponding to the discharge section 600 are cascade-connected to each other, and the serially supplied print data signal SI is sequentially transferred to subsequent stages according to the clock signal SCK. In FIG. 8, in order to distinguish the shift registers 212, they are indicated as 1st stage, 2nd stage, .

Each of the n latch circuits 214 latches the print data [SIH, SIL] held in the corresponding shift register 212 at the rise of the latch signal LAT.

Each of the n decoders 216 decodes the 2-bit print data [SIH, SIL] latched by the corresponding latch circuit 214 and the 2-bit operation mode data [MCH, MCL] included in the operation mode signal MC. to generate a selection signal S and supply it to the selection circuit 230 .

The selection circuit 230 is provided corresponding to each ejection section 600 . i.e. 1
The number of selection circuits 230 included in one head unit 20 is the same as the total number n of ejection sections 600 included in the head unit 20 . The selection circuit 230 controls supply of the drive signal COM to the piezoelectric element 60 based on the selection signal S supplied from the decoder 216 . This selection circuit 230 is an example of a first switch circuit.

FIG. 9 is a circuit diagram showing the electrical configuration of the selection circuit 230 corresponding to one ejection section 600. As shown in FIG.

As shown in FIG. 9, the selection circuit 230 has an inverter 232 (NOT circuit) and a transfer gate 234 . Also, the transfer gate 234 includes a transistor 235 that is an NMOS transistor and a transistor 236 that is a PMOS transistor.

A select signal S is provided from decoder 216 to the gate terminal of transistor 235 . The selection signal S is logically inverted by the inverter 232 and supplied to the gate terminal of the transistor 236 as well.

The drain terminal of transistor 235 and the source terminal of transistor 236 are connected to terminal TG-In. A driving signal COM is supplied to the terminal TG-In. By controlling the transistors 235 and 236 to be turned on or off according to the selection signal S, the drive signal VOUT is output from the terminal TG-Out to which the source terminal of the transistor 235 and the drain terminal of the transistor 236 are commonly connected. and supplied to the ejection module 21 . This terminal TG-In corresponds to the first terminal described above, and the terminal TG-Out is an example of the second terminal. In the following description, the case where the transistors 235 and 236 of the transfer gate 234 are controlled to be conductive is referred to as controlling the transfer gate 234 to be ON, and the transistors 235 and 236 are controlled to be non-conductive. The controlled case may be referred to as controlling the transfer gate 234 to be off.

Next, the decoded contents of the decoder 216 will be described with reference to FIG. FIG. 10 is a diagram showing decoded contents in the decoder 216. As shown in FIG.

The decoder 216 receives 2-bit print data [SIH, SIL], 2-bit operation mode data [MCH, MCL], latch signal LAT, and change signal CH.

In the print mode where the operation mode data [MCH, MCL] are [1, 1], the decoder 216 outputs the print data [SIH, SIL] and outputs a logic level selection signal S.

Specifically, when the print data [SIH, SIL] is [1, 1] that defines a "large dot" in the print mode, the decoder 216 sets the H level in the period T1, the H level in the period T2, and the H level in the period T3. select signal S that becomes L level at .

Further, when the print data [SIH, SIL] is [1, 0] that defines a "medium dot" in the print mode, the decoder 216 outputs H level in the period T1, L level in the period T2, and L level in the period T3. A selection signal S is output.

Further, when the print data [SIH, SIL] is [0, 1] that defines a "small dot" in the print mode, the decoder 216 outputs an L level during the period T1, an H level during the period T2, and an H level during the period T2.
It outputs the selection signal S that becomes L level in the period T3.

Further, when the print data [SIH, SIL] is [0, 0] that defines "micro-vibration" in the print mode, the decoder 216 outputs an L level during the period T1, an L level during the period T2, and an H level during the period T3. A selection signal S is output.

Also, the decoder 216 determines the logic level of the selection signal S regardless of the print data [SIH, SIL] and the periods T1, T2, T3 in the standby mode, transition mode, and sleep mode.

Specifically, the decoder 216 outputs the H-level selection signal S in the standby mode where the operation mode data [MCH, MCL] is [1, 0].

Further, the decoder 216 outputs an L-level selection signal S in the transition mode in which the operation mode data [MCH, MCL] are [0, 0].

Further, the decoder 216 outputs an L-level selection signal S in the sleep mode in which the operation mode data [MCH, MCL] are [0, 1].

Here, the logic level of the selection signal S is level-shifted to a high-amplitude logic based on the voltage VHV-TG by a level shifter (not shown).

The operation of generating the drive signal VOUT based on the drive signal COM in the drive IC 80 described above and supplying it to the ejection section 600 included in the ejection module 21 will be described with reference to FIG. 11 .

FIG. 11 is a diagram for explaining the operation of the drive IC 80 in print mode.

In the print mode, the print data signal SI is serially supplied in synchronization with the clock signal SCK and sequentially transferred in the shift register 212 corresponding to the ejection section 600 . Then, when the supply of the clock signal SCK is stopped, the print data [SIH, SIL] corresponding to the ejection unit 600 is held in each of the shift registers 212 . Note that the print data signals SI are supplied in the order corresponding to the last n stages, .

Here, when the latch signal LAT rises, each of the latch circuits 214 latches the print data [SIH, SIL] held in the corresponding shift register 212 all at once. 11, LT1, LT2, . . . , LTn indicate the print data [SIH, SIL] latched by the latch circuits 214 corresponding to the 1st, 2nd, .

The decoder 216 outputs the logic level selection signal S according to the content shown in FIG. 10 in each of the periods T1, T2, and T3 according to the dot size defined by the latched print data [SIH, SIL]. do.

When the print data [SIH, SIL] is [1, 1], the selection circuit 230 selects the voltage waveform Adp in the period T1, selects the voltage waveform Bdp in the period T2, and selects the voltage waveform Bdp in the period T3 according to the selection signal S. Do not select the voltage waveform Cdp in . As a result, the drive signal VOUT corresponding to the large dot shown in FIG.

Further, when the print data [SIH, SIL] is [1, 0], the selection circuit 230 selects the voltage waveform Adp in the period T1 according to the selection signal S, does not select the voltage waveform Bdp in the period T2, and selects the voltage waveform Bdp in the period T2. Do not select the voltage waveform Cdp at T3. As a result, the drive signal VOUT corresponding to the medium dot shown in FIG. 11 is supplied to the ejection section 600 .

Further, when the print data [SIH, SIL] is [0, 1], the selection circuit 230 does not select the voltage waveform Adp in the period T1, selects the voltage waveform Bdp in the period T2, and selects the voltage waveform Bdp in the period T2 according to the selection signal S. Do not select the voltage waveform Cdp at T3. As a result, the drive signal VOUT corresponding to the small dot shown in FIG.

When the print data [SIH, SIL] is [0, 0], the selection circuit 230 follows the selection signal S and does not select the voltage waveform Adp in the period T1, selects the voltage waveform Bdp in the period T2, and selects the voltage waveform Bdp in the period T2. Do not select the voltage waveform Cdp at T3. As a result, the drive signal VOUT corresponding to the minute vibration shown in FIG. 11 is supplied to the ejection section 600 .

No printing occurs in standby mode, transition mode, and sleep mode. Therefore, in the standby mode, transition mode, and sleep mode in this embodiment, the clock signal SCK and the print data signal SI are L level signals in addition to the latch signal LAT and change signal CH described above. Therefore, shift register 212 and latch circuit 214 do not operate. Therefore, in the standby mode, the transition mode and the sleep mode, the decoder 216 determines the logic level of the selection signal S according to the operation mode signal MC, as described above.

In the standby mode in which the operation mode data [MCH, MCL] are [1, 0], the selection circuit 230 selects the drive signal COM having a voltage value equivalent to the reference voltage signal VBS in accordance with the supplied H-level selection signal S. selected and supplied to the ejection section 600 as the drive signal VOUT.

In the standby mode in which the operation mode data [MCH, MCL] are [1, 0], the selection circuit 230 selects the drive signal COM having a voltage value equivalent to the reference voltage signal VBS in accordance with the supplied H-level selection signal S. select. As a result, the drive signal VOUT having a voltage value equivalent to the reference voltage signal VBS is supplied to the ejection section 600 .

When the operation mode data [MCH, MCL] is [0, 0] in the transition mode, the selection circuit 230 turns off the transfer gate 234 in accordance with the L-level selection signal S supplied. As a result, the drive signal COM is not supplied to the ejection section 600 as the drive signal VOUT.

In addition, in the sleep mode in which the operation mode data [MCH, MCL] are [0, 1], the selection circuit 230 does not select the drive signal COM as the drive signal VOUT according to the L-level selection signal S supplied. As a result, the voltage supplied to the piezoelectric element 60 immediately before is held.

5 Configuration and Operation of Discharge Portion Next, the configuration and operation of the discharge module 21 and the discharge portion 600 will be described. 12 is an exploded perspective view of the ejection module 21. FIG. 13 is a cross-sectional view taken along line III-III in FIG. 12 and is a cross-sectional view showing a schematic configuration of the discharge section 600. As shown in FIG.

As shown in FIGS. 12 and 13, the discharge module 21 includes a substantially rectangular channel substrate 670 elongated in the X direction. A pressure chamber substrate 630 , a vibration plate 621 , a plurality of piezoelectric elements 60 , a housing portion 640 and a sealing body 610 are provided on one side of the flow path substrate 670 in the Z direction. A nozzle plate 632 and a vibration absorber 633 are provided on the other side of the channel substrate 670 in the Z direction. Each component of the ejection module 21 is a substantially rectangular member elongated in the direction X, like the channel substrate 670, and is joined to each other using an adhesive or the like.

As shown in FIG. 12, the nozzle plate 632 is a plate-like member formed with a plurality of nozzles 651 arranged along the X direction. Such a nozzle 651 is an opening provided in the nozzle plate 632 and communicating with a cavity 631 to be described later.

The channel substrate 670 is a plate-like member for forming an ink channel. As shown in FIGS. 12 and 13, the channel substrate 670 is formed with openings 671 , supply channels 672 , and communication channels 673 . The opening 671 is an elongated through-hole along the direction X that penetrates in the direction Z and is commonly formed in the plurality of nozzles 651 . Also, the supply channel 672 and the communication channel 673 are through holes formed corresponding to the plurality of nozzles 651 respectively. Furthermore, as shown in FIG. 13, one surface of the channel substrate 670 in the direction Z is provided with a relay channel 674 formed in common with the plurality of supply channels 672 . The relay channel 674 communicates the opening 671 with the plurality of supply channels 672 .

The housing part 640 is a structure manufactured by, for example, injection molding of a resin material, and is fixed to the other surface of the channel substrate 670 in the Z direction. As shown in FIG. 13, the housing portion 640 is formed with a supply channel 641 and a supply port 661 . The supply channel 641 is a recess corresponding to the opening 671 of the channel substrate 670 , and the supply port 661 is a through hole communicating with the supply channel 641 . The space where the opening 671 of the channel substrate 670 and the supply channel 641 of the housing 640 communicate with each other functions as a reservoir for storing the ink supplied from the supply port 661 .

The vibration absorber 633 is configured to absorb pressure fluctuations occurring inside the reservoir. Specifically, the vibration absorber 633 closes the opening 671, the relay channel 674, and the plurality of supply channels 672 formed in the channel substrate 670, and constitutes the bottom surface of the reservoir. It is fixed to one surface side in the direction Z of 670 . Such a vibration absorber 633 includes, for example, a compliance substrate that is a flexible sheet member that can be elastically deformed.

As shown in FIGS. 12 and 13, the pressure chamber substrate 630 is a plate-like member in which a plurality of cavities 631 corresponding to a plurality of nozzles 651 are formed. The plurality of cavities 631 are elongated along the direction Y and arranged side by side along the direction X. As shown in FIG. One end of the cavity 631 in the direction Y communicates with the supply channel 672 , and the other end of the cavity 631 in the direction Y communicates with the communication channel 673 .

As shown in FIGS. 12 and 13, a vibration plate 621 is fixed to the surface of the pressure chamber substrate 630 opposite to the surface to which the channel substrate 670 is connected. The diaphragm 621 is an elastically deformable plate-like member. Specifically, as shown in FIG. 13 , the channel substrate 670 and the vibration plate 621 face each other with a space inside each cavity 631 . That is, the diaphragm 621 constitutes the upper surface that is part of the wall surface of the cavity 631 .

The cavity 631 is positioned between the channel substrate 670 and the vibration plate 621 and functions as a pressure chamber that applies pressure to the ink filled inside the cavity 631 .

As shown in FIGS. 12 and 13, a plurality of piezoelectric elements 60 are provided on the surface of the diaphragm 621 opposite to the cavity 631 . In other words, diaphragm 621 is provided between cavity 631 and piezoelectric element 60 . A plurality of piezoelectric elements 60 are arranged in the direction X so as to correspond to a plurality of cavities 631 . When the vibration plate 621 vibrates in association with the deformation of the piezoelectric element 60 , the pressure inside the cavity 631 fluctuates, and ink is ejected from the nozzle 651 . Specifically, the piezoelectric element 60 is an actuator that deforms when a drive signal VOUT is supplied. As shown in FIG. . A drive signal VOUT is supplied to the electrode 611 and a reference voltage signal VBS is supplied to the electrode 612 . In this case, in the piezoelectric element 60 , the central portion of the piezoelectric body 601 along with the diaphragm 621 deforms vertically with respect to both end portions according to the potential difference between the electrodes 611 and 612 . As the piezoelectric element 60 deforms, ink is ejected from the nozzle 651 . Here, the vibration plate 621 functions as a diaphragm that is displaced by the piezoelectric element 60 and expands/contracts the internal volume of the cavity 631 filled with ink. The electrode 611 included in the piezoelectric element 60 is an example of a first electrode, and the electrode 612 is an example of a second electrode.

12 and 13 is a structure that protects the plurality of piezoelectric elements 60 and reinforces the mechanical strength of the pressure chamber substrate 630 and diaphragm 621. For example, the diaphragm 621 is attached with an adhesive. Fixed. A plurality of piezoelectric elements 60 are accommodated inside recesses formed in the surface of the sealing body 610 facing the diaphragm 621 .

In the ejection module 21 configured as described above, the configuration including the piezoelectric element 60 , the cavity 631 , the vibration plate 621 and the nozzle 651 is the ejection section 600 .

FIG. 14 is a diagram showing an example of the arrangement of the ejection module 21 and the plurality of nozzles 651 provided in the ejection module 21 when the liquid ejection device 1 is viewed from above along the direction Z. FIG. Note that in FIG. 14 , the head unit 20 is described as having four ejection modules 21 .

As shown in FIG. 14, each ejection module 21 is formed with a nozzle row L composed of a plurality of nozzles 651 arranged in a row in a predetermined direction. Each nozzle row L is formed by n nozzles 651 arranged in a row along the X direction.

Note that the nozzle row L shown in FIG. 14 is an example and may have a different configuration. For example, in each nozzle row L, the n nozzles 651 may be arranged in a staggered manner so that the even-numbered nozzles 651 and the odd-numbered nozzles 651 counted from the end have different positions in the Y direction. Also, each nozzle row L may be formed in a direction different from the direction X. Further, in the first embodiment, the number of nozzle rows L provided in each ejection module 21 is exemplified as "1", but each ejection module 21 is formed with "2" or more nozzle rows L. may

Here, in the present embodiment, the n nozzles 651 forming the nozzle row L are provided in the ejection module 21 at a high density of 300 or more per inch. Therefore, in the ejection module 21 , n piezoelectric elements 60 are also provided at high density corresponding to the n nozzles 651 .

Further, in this embodiment, the piezoelectric body 601 used for the piezoelectric element 60 is preferably a thin film having a thickness of, for example, 1 μm or less. Thereby, the amount of displacement of the piezoelectric element 60 with respect to the potential difference between the electrodes 611 and 612 can be increased.

Here, the ejection operation of ink ejected from the nozzles 651 will be described with reference to FIG. 15 . 15A and 15B are diagrams for explaining the relationship between the displacement of the piezoelectric element 60 and the vibration plate 621 and ejection when the drive signal VOUT is supplied to the piezoelectric element 60. FIG. 15 is a cross-sectional view of two of the plurality of piezoelectric elements 60, the cavity 631 and the nozzle 651 included in the discharge module 21 as seen from the direction Y. FIG. (1) of FIG. 15 schematically shows the displacement of the piezoelectric element 60 and the diaphragm 621 when the voltage Vc is supplied as the driving signal VOUT. 15B shows the piezoelectric element 60 and diaphragm 621 when the voltage value of the drive signal VOUT supplied to the piezoelectric element 60 is controlled so as to approach the reference voltage signal VBS from the voltage Vc. is shown schematically. FIG. 15(3) shows the piezoelectric element 60 and diaphragm when the voltage value of the driving signal VOUT supplied to the piezoelectric element 60 is controlled to be more distant from the reference voltage signal VBS than the voltage Vc. 621 displacements are shown schematically.

In the state shown in (1) of FIG. 15, the piezoelectric element 60 and the diaphragm 621 move in the direction Z according to the potential difference between the drive signal VOUT supplied to the electrode 611 and the reference voltage signal VBS supplied to the electrode 612. bent. At this time, the voltage Vc is supplied to the electrode 611 as the driving signal VOUT. The voltage Vc is the voltage value at the start timing and end timing of the voltage waveforms Adp, Bdp, and Cdp, as described above. That is, the state of the piezoelectric element 60 and the vibration plate 621 shown in (1) of FIG. 15 is the reference state of the piezoelectric element 60 in the print mode.

Then, when the voltage value of the drive signal VOUT is controlled to approach the voltage value of the reference voltage signal VBS, as shown in FIG. The resulting displacement is reduced. At this time, the internal volume of the cavity 631 expands, and ink is supplied to the cavity 631 from the reservoir.

After that, the voltage value of the drive signal VOUT is controlled so as to depart from the voltage value of the reference voltage signal VBS. At this time, as shown in (3) of FIG. 15, the displacement along the direction Z of the piezoelectric element 60 and the vibration plate 621 increases. At this time, the internal volume of the cavity 631 is reduced, and the ink filled in the cavity 631 is ejected from the nozzle 651 .

In this embodiment, by supplying the drive signal VOUT to the piezoelectric element 60, the states shown in (1) to (3) of FIG. 15 are repeated. As a result, ink is ejected from the nozzles 651 and dots are formed on the medium P. FIG. Note that the displacement of the piezoelectric element 60 and the diaphragm 621 shown in (1) to (3) of FIG. As it grows, it grows along the direction Z. In other words, the amount of ink ejected from the nozzles 651 is controlled according to the potential difference between the drive signal VOUT and the reference voltage signal VBS.

It should be noted that the displacement of the piezoelectric element 60 and the vibration plate 621 with respect to the drive signal VOUT shown in FIG. 15 is merely an example. is pulled in, and the potential difference between the drive signal VOUT and the reference voltage signal VBS becomes small, the ink filled in the cavity 631 may be ejected from the nozzle 651 .

6 Details of Transition Mode and Discharge of Piezoelectric Element As described above, in the sleep mode, the transfer gate 234 of the selection circuit 230 is controlled to be off. Ideally, the voltage and current supplied to electrode 611 in sleep mode is blocked by transfer gate 234 . Therefore, the electrode 611 holds the voltage immediately before the transfer gate 234 is turned off. Therefore, by bringing the voltage supplied to the electrode 611 closer to the voltage of the reference voltage signal VBS supplied to the electrode 612 immediately before the transfer gate 234 is turned off, the piezoelectric element 60 can be displaced in the sleep mode. can be reduced.

However, the transfer gate 234 and the piezoelectric element 60 have resistance components. Therefore, even when the transfer gate 234 is controlled to be off, the electrode 611 is supplied with a leak current through the transfer gate 234 and the resistance component of the piezoelectric element 60 . Therefore, electric charges resulting from the leakage current are accumulated in the electrode 611 . Therefore, the voltage value of the electrode 611 increases, and the piezoelectric element 60 may be displaced unintentionally.

FIG. 16 is a diagram schematically showing the displacement of the piezoelectric element 60 and diaphragm 621 when the voltage value of the electrode 611 rises due to leak current. 16 is a cross-sectional view of two of the plurality of piezoelectric elements 60, the cavity 631, and the nozzle 651 included in the discharge module 21 as seen from the direction Y. FIG. (1) of FIG. 16 shows the displacements of the piezoelectric element 60 and the diaphragm 621 immediately after the transition to the sleep mode. 16B shows the displacement of the piezoelectric element 60 and diaphragm 621 when charges are accumulated in the electrode 611 due to leakage current generated in the transfer gate 234 and piezoelectric element 60. In FIG. there is

As shown in (1) of FIG. 16 , the piezoelectric element 60 immediately after transitioning to the sleep mode is displaced based on the potential difference between the voltage of the electrode 611 and the voltage of the electrode 612 . At this time, the electrode 611 retains the voltage immediately before transitioning to the sleep mode. That is, the voltage of the electrode 611 immediately after transitioning to the sleep mode is the voltage assumed to be held in the electrode 611 . Therefore, the piezoelectric element 60 is displaced within the assumed range, and similarly the diaphragm 621 is displaced within the assumed range. At this time, a stress F1 within an assumed range is generated at the contact α between the diaphragm 621 and the cavity 631 .

FIG. 16(1) illustrates a case where the voltage of the electrode 611 and the voltage of the electrode 612 are different immediately before transitioning to the sleep mode, but the voltage of the electrode 611 and the voltage of the electrode 612 are the same. is preferably a voltage value of In this case, the piezoelectric element 60 and diaphragm 621 are not displaced.

When electric charge due to leakage current or the like is accumulated in the electrode 611, the potential difference between the voltage of the electrode 611 and the voltage of the electrode 612 increases, and as shown in (2) of FIG. Displacement increases. Therefore, the displacement of diaphragm 621 also increases. At this time, a larger than expected stress F2 may occur at the contact point α between the diaphragm 621 and the cavity 631 .

Also, the stress generated at the contact point between the diaphragm 621 and the cavity 631 may vary depending on the position of the contact point between the diaphragm 621 and the cavity 631 in the Y direction. Specifically, the stress generated at the contact point between the diaphragm 621 and the cavity 631 is greater at the contact point between the diaphragm 621 and the cavity 631 where the displacement of the diaphragm 621 in the direction Z is maximum. stress occurs.

A factor of such a displacement that occurs in the diaphragm 621 is, for example, natural vibration that occurs in the diaphragm 621 . FIG. 17 is a plan view of the diaphragm 621 viewed from the direction Z. FIG. As shown in FIG. 17, the cavity 631 in this embodiment is elongated along the Y direction, and the vibration plate 621 may have natural vibration along the Y direction. Such natural vibration occurs in the vibration region D between the first contact DL and the second contact DR where the diaphragm 621 and the cavity 631 are in contact.

FIG. 18 is a diagram exemplifying a case where the diaphragm 621 has a primary natural vibration. As shown in FIG. 18, when the first-order natural vibration occurs in the diaphragm 621, the displacement ΔD of the diaphragm 621 caused by the natural vibration becomes maximum at the central portion of the vibration region D. As shown in FIG. Specifically, when the distance from the first contact DL to the second contact DR is d in the vibration region D, the distance from the first contact DL is d/2 and the distance from the second contact DR is The displacement ΔD of the diaphragm 621 becomes maximum at the point of d/2.

19A and 19B are diagrams illustrating a case where a third-order natural vibration is generated in the diaphragm 621. FIG. As shown in FIG. 19, when the tertiary natural vibration occurs in the diaphragm 621, the displacement ΔD of the diaphragm 621 caused by the natural vibration is the second The maximum distance is d/2 from the contact DR, d/6 from the first contact DL, and d/6 from the second contact DR.

As described above, in the direction Y, a larger stress F2 may be applied to the contact α between the diaphragm 621 and the cavity 631 at the point where the displacement ΔD of the diaphragm 621 is maximum.

Furthermore, in an operation mode that continues for a long time, such as a sleep mode, the stress F2 may continue to be applied to the contact α of the diaphragm 621 for a long time, and as a result, cracks may occur in the diaphragm 621 . In addition, if the print mode is switched to when the vibration plate 621 is displaced more than expected, the vibration plate 621 may be subjected to an excessive load due to the displacement of the piezoelectric element 60 during ink ejection. As a result, cracks may occur in diaphragm 621 .

If a crack occurs in the vibration plate 621, the ink filled in the cavity 631 leaks from the crack. Therefore, there is a possibility that the amount of ejected ink may vary with the change in the internal volume of the cavity 631 . As a result, ink ejection accuracy deteriorates.

Also, when the ink leaking from the crack adheres to both the electrodes 611 and 612, a current path is formed between the electrodes 611 and 612 via the ink. As a result, the voltage value of the reference voltage signal VBS supplied to the electrode 612 may fluctuate. In the liquid ejection device 1 shown in this embodiment, the reference voltage signal VBS is commonly supplied to the plurality of electrodes 612 . Therefore, when the voltage value of the reference voltage signal VBS fluctuates, it affects the displacement of the plurality of piezoelectric elements 60 . As a result, the ejection accuracy of the liquid ejecting apparatus 1 as a whole may be affected.

Therefore, in the present embodiment, the electrodes 611 and 612 of the piezoelectric element 60 are prevented from being unintentionally displaced continuously for a long period of time due to an unintended potential difference between the electrodes 611 and 612 . It comprises three discharge means for discharging charges 611,612.

FIG. 20 is a diagram for explaining discharge means for discharging the charge of the piezoelectric element 60. FIG. In FIG. 20, the parasitic diodes 241, 242, 243 and 244 formed in the transfer gate 234 are indicated by dashed lines.

The first discharge means discharges electric charges through a first discharge path A shown in FIG. Specifically, in the first discharging means, the electric charge accumulated between the terminal TG-Out and the electrode 611 through the plurality of parasitic diodes formed in the transfer gate 234 and the terminal Com-Out and the terminal TG −In is discharged. A mode in which the first discharging means is performed is an example of a first mode.

Details of the parasitic diodes 241, 242, 243, and 244 formed in the transfer gate 234 will now be specifically described with reference to FIG.

FIG. 21 is a cross-sectional view schematically showing transistors 235 and 236 forming transfer gate 234. As shown in FIG.

As shown in FIG. 21, transistor 235 includes polysilicon 252, N-type diffusion layers 253 and 254, and a plurality of electrodes.

N-type diffusion layers 253 and 254 are provided on P-substrate 251 so as to be spaced apart from each other. Also, the polysilicon 252 is provided between the N-type diffusion layers 253 and 254 via an insulating layer (not shown).

Electrode 255 is electrically connected to polysilicon 252 . An electrode 256 is electrically connected to the N-type diffusion layer 253 . An electrode 257 is electrically connected to the N-type diffusion layer 254 .

The electrode 255 functions as a gate terminal, one of the electrodes 256 and 257 functions as a drain terminal, and the other functions as a source terminal. Note that in this embodiment, the electrode 256 is described as a drain terminal, and the electrode 257 is described as a source terminal.

In the transistor 235 constructed as described above, a PN junction is formed at each of the contact surface between the P substrate 251 and the N-type diffusion layer 253 and the contact surface between the P-substrate 251 and the N-type diffusion layer 254 . Therefore, the transistor 235 has a parasitic diode 243 with the P substrate 251 as the anode and the N-type diffusion layer 253 as the cathode, and a parasitic diode 244 with the P substrate 251 as the anode and the N-type diffusion layer 254 as the cathode. .

An electrode 258 is electrically connected to the P substrate 251 . Here, since the transistor 235 is formed on the P-substrate 251 , the electrode 258 functions as a back gate terminal of the transistor 235 . A ground potential is supplied to the electrode 258 .

Transistor 236 includes an N-well 261, polysilicon 262, P-type diffusion layers 263, 264 and a plurality of electrodes.

P-type diffusion layers 263 and 264 are spaced apart from each other on an N-well 261 formed in P-substrate 251 . Also, the polysilicon 262 is provided between the P-type diffusion layers 263 and 264 via an insulating layer (not shown).

An electrode 265 is electrically connected to the polysilicon 262 . An electrode 266 is electrically connected to the P-type diffusion layer 263 . An electrode 267 is electrically connected to the P-type diffusion layer 264 .

The electrode 265 functions as a gate terminal, one of the electrodes 266 and 267 functions as a drain terminal, and the other functions as a source terminal. Note that in this embodiment, the electrode 266 is described as a drain terminal and the electrode 267 is described as a source terminal.

In the transistor 236 configured as described above, a PN junction is formed at each of the contact surface between the N well 261 and the P type diffusion layer 263 and the contact surface between the N well 261 and the P type diffusion layer 264 . Therefore, the transistor 236 is formed with a parasitic diode 242 having the P-type diffusion layer 263 as an anode and an N-well 261 as a cathode, and a parasitic diode 241 having the P-type diffusion layer 264 as an anode and the N-well 261 as a cathode terminal. be.

Here, the N-well 261 is an example of an N-type semiconductor layer, the P-type diffusion layer 264 electrically connected to an electrode 267 that is a source terminal is an example of a first P-type semiconductor layer, and the drain terminal is an example of a first P-type semiconductor layer. A P-type diffusion layer 263 electrically connected to a certain electrode 266 is an example of a second P-type semiconductor layer.

An electrode 268 is electrically connected to the N well 261 . Since transistor 236 is formed in N-well 261 , electrode 268 functions as the backgate terminal of transistor 236 . That is, the electrode 268 that is the back gate terminal is electrically connected to the N well 261 . A voltage VHV-TG is supplied to the electrode 268 .

Returning to FIG. 20, the first discharge means via the first discharge path A including the parasitic diodes 241, 242, 243 and 244 described above will be described.

In the first discharging means, first, an H-level discharge control signal DIS1 is supplied to the power supply control signal generation circuit 430 .

The discharge control signal DIS<b>1 supplied to the power supply control signal generation circuit 430 is supplied to the transistor 432 via the inverter 431 . Thereby, the transistor 432 is controlled to be off.

As described above, when the transistor 432 is turned off, the transistor 473 of the power supply switching circuit 70 is turned on. When transistor 473 is controlled on, voltage VHV-TG becomes the ground potential supplied through resistor 475 . As a result, the electrode 268 of the transistor 236 forming the transfer gate 234 becomes the ground potential. Therefore, the potential of the node a to which the terminal COM-Out and the terminal TG-In are connected becomes the ground potential via the parasitic diode 241 . Similarly, the potential of the node b to which the terminal TG-Out and the electrode 611 are connected becomes the ground potential via the parasitic diode 242 .

In other words, the charge stored at node a is released through parasitic diode 241, resistor 475 and transistor 473, and similarly the charge stored at node b is released through parasitic diode 242, resistor 475 and transistor 473. emitted through

As described above, in the first discharging means, the power supply switching circuit 70 sets the potential of the voltage VHV-TG to the ground potential based on the discharge control signal DIS1. In other words, the electrode 268 of the transistor 236 supplied with the voltage VHV-TG is electrically connected to the drain terminal of the transistor 473 . Also, the source terminal of the transistor 473 is electrically connected to the ground terminal. When the transistor 473 is turned off based on the discharge control signal DIS1, the power supply switching circuit 70 supplies the electrode 268 with the voltage VHV-TG. On the other hand, when the transistor 473 is turned on based on the discharge control signal DIS1, the power supply switching circuit 70 electrically connects the electrode 268 and the terminal Gnd-In. As a result, the charges stored in the nodes a and b are released via the parasitic diodes 241 and 242 . Therefore, unintentional accumulation of charge in the electrode 611 is reduced. Here, the transistor 473 is an example of a switch element. Also, the drain terminal of the transistor 473 is an example of one end of the switch element, and the source terminal is an example of the other end of the switch element. A power supply switching circuit 70, which includes a transistor 473 and controls whether the voltage VHV-TG is supplied to the electrode 268 of the transistor 236 or electrically connects the electrode 268 to the terminal Gnd-In, is a fourth switch circuit. is an example.

Also, the charges at the nodes a and b discharged by the first discharging means are the charges at the terminals TG-In and TG-Out of the transfer gate 234 . Therefore, the discharge of electric charge by the first discharging means is possible regardless of whether the transfer gate 234 is controlled to be ON or OFF. Therefore, it is possible to further reduce the possibility that an unintended charge is accumulated in the electrode 611 .

The configuration of the power supply switching circuit 70 is not limited to the configuration described above, and may be any configuration as long as the potential of the electrode 268 of the transistor 236 can be switched to the ground potential.

Next, the second discharging means will be explained. The second discharging means discharges the charge stored in the node a through the second discharging path B including the LC discharging circuit 530 .

When discharging the charge by the second discharge means, first, the H-level discharge control signal DIS2 is supplied to the transistor 532 of the LC discharge circuit 530 . This turns on the transistor 532 . Therefore, the potential of node a becomes the ground potential supplied via resistors 571 and 531 and transistor 532 . In other words, the charge stored at node a is released through resistors 571 and 531 and transistor 532 . A mode in which the second discharging means is performed is an example of a third mode.

When the drive signal generation circuit 50 stops operating, the node a may be supplied with the voltage VHV through the resistors 572 and 571 . Since the second discharging means can discharge the charge of the node a, it is possible to reduce the accumulation of the charge caused by the voltage VHV in the node a.

As described above, the second discharging means can discharge the charge of the node a, so that the potential of the node a can be lowered. Therefore, leakage current generated from terminal TG-In of transfer gate 234 to terminal TG-Out is reduced. That is, it is possible to reduce the increase in the voltage of the node b due to the leakage current. Therefore, it is possible to further reduce the possibility that an unintended charge is accumulated in the electrode 611 .

Note that the LC discharge circuit 530 may have any structure as long as it can discharge the charge of the node a. good too.

Next, the third discharging means will be explained. The third discharging means discharges the electric charge accumulated in the node c where the electrode 612 and the terminal Vbs-Out are connected through the third discharging path C including the transistor 453 of the reference voltage signal generating circuit 450 .

When discharging the electric charge by the third discharging means, first, the H-level discharge control signal DIS3 is supplied to the transistor 453 of the reference voltage signal generation circuit 450 . This turns on the transistor 453 . Therefore, the potential of node c becomes the ground potential supplied via resistor 456 and transistor 453 . In other words, the charge stored at node c is released through resistor 456 and transistor 453 . A mode in which the third discharging means is performed is an example of a second mode.

As described above, the piezoelectric element 60 is displaced by the potential difference between the voltages of the electrodes 611 and 612 . By discharging the charge stored in the node c by the third discharging means, supply of an unintended voltage to the electrode 612 can be reduced. Therefore, it is possible to further reduce the occurrence of unintended displacement of the piezoelectric element 60 . Here, node b shown in FIG. 20 corresponds to the above-described first node, node c corresponds to the above-described second node, and node a is an example of a third node.

In this embodiment, the discharge of charges by the above-described first discharging means, second discharging means and third discharging means is performed in transition mode. Therefore, with reference to FIG. 22, the method of discharging charges by the first discharging means, the second discharging means and the third discharging means in this embodiment will be described.

FIG. 22 is a flow chart diagram for explaining the operation of the transition mode.

First, the control circuit 100 controls the voltage value of the drive signal COM to approach the voltage value of the reference voltage signal VBS before the operation mode transitions to the transition mode (S171). Specifically, the control circuit 100 supplies to the drive signal generation circuit 50 the drive data signal DRV in which the voltage value of the drive signal COM becomes the voltage value of the reference voltage signal VBS. Based on the supplied drive data signal DRV, the drive signal generation circuit 50 controls the voltage value of the drive signal COM so as to approach the voltage value of the reference voltage signal VBS.

In the transition mode, the voltage values of both the drive signal COM and the reference voltage signal VBS may fluctuate in the process of transitioning the operation mode to the sleep mode. Therefore, by controlling the voltage value of the drive signal COM to approach the voltage value of the reference voltage signal VBS before transitioning to the transition mode, the possibility of an unintended potential difference occurring in the piezoelectric element 60 in the transition mode is reduced. can do.

Note that the expression that the voltage value of the drive signal COM is controlled so as to approach the voltage value of the reference voltage signal VBS preferably means that the voltage value of the drive signal COM and the voltage value of the reference voltage signal VBS are the same. However, in a broad sense, the voltage value should be controlled so as to approach the piezoelectric element 60 to such an extent that unintended displacement does not occur due to the potential difference between the drive signal COM and the reference voltage signal VBS. Specifically, it is preferable that the potential difference between the drive signal COM and the reference voltage signal VBS is controlled to be 2 V or less.

Then, when the voltage value of the drive signal COM and the voltage value of the reference voltage signal VBS are sufficiently close to each other, the control circuit 100 controls the operation mode to the transition mode (S172).

After the operation mode transitions to the transition mode, the control circuit 100 controls the transfer gate 234 to turn off (S173). As a result, the voltage supplied to the electrode 611 is held at the voltage immediately before transitioning to the transition mode, that is, the voltage sufficiently close to the voltage of the reference voltage signal VBS.

When a predetermined time has elapsed after transfer gate 234 is turned off, control circuit 100 controls the discharge of charges by the second discharging means (S174). That is, it becomes a mode in which the second discharging means is performed. Specifically, the control circuit 100 supplies the driving signal generating circuit 50 with the driving data signal DRV for generating the H-level discharge control signal DIS2.

After the transfer gate 234 is turned off, the charge accumulated in the node a is discharged by the second discharging means, thereby lowering the voltage of the node a. Therefore, the leak current generated in the transfer gate 234 is reduced, and the voltage rise of the electrode 611 caused by the leak current is reduced. It should be noted that the discharge of electric charges by the second discharging means may be continued until the mode is changed to the print mode or the standby mode.

After a predetermined period of time has elapsed after the discharge of the charge by the second discharging means has started, the control circuit 1
00 controls the discharge of charges by the third discharging means (S175). That is, it becomes a mode in which the third discharging means is performed. Specifically, the control circuit 100 supplies the drive data signal DRV for generating the H-level discharge control signal DIS3 to the drive signal generation circuit 50 . By discharging the charge stored in the node c by the third discharging means before discharging the charge stored in the node b by the first discharging means, the voltage supplied to the electrode 612 is applied to the electrode 611. The increase with respect to the supplied voltage is reduced. That is, it is possible to reduce the occurrence of displacement in the piezoelectric element 60 in the direction opposite to the displacement that occurs in the piezoelectric element 60 during the printing operation. As a result, it becomes possible to reduce the stress generated in the piezoelectric element 60 and the vibration plate 621 .

Note that the discharge of charges by the second discharge means and the discharge of charges by the third discharge means may be executed simultaneously by the control circuit 100, for example, and the discharge of charges by the third discharge means may be performed first. , discharge of the charge by the second discharging means may be performed. Also, the discharge of electric charges by the third discharging means may be continued until the mode is changed to the print mode or the standby mode.

Then, when a predetermined time has elapsed after the discharge of charges by the second discharge means and the third discharge means has started, the control circuit 100 controls the discharge of charges by the first discharge means (S176). That is, it becomes a mode in which the first discharging means is performed. Specifically, the control circuit 100 supplies the drive signal generation circuit 50 with the drive data signal DRV for generating the H-level discharge control signal DIS1. As a result, the charges stored in the electrode 611 are released. Therefore, the possibility that an unintended voltage is generated in the piezoelectric element 60 is reduced, and the occurrence of unintended displacement in the piezoelectric element 60 and the vibration plate 621 is reduced. It should be noted that the discharge of electric charges by the first discharging means may be continued until the mode is changed to the print mode or the standby mode.

When a predetermined time elapses after the first discharge means, the second discharge means, and the third discharge means start discharging electric charges, the control circuit 100 changes the operation mode as shown in FIG. Transition to sleep mode. The discharge of electric charges by the first discharging means, the second discharging means, and the third discharging means may be continued in the sleep mode.

7 Effects In the liquid ejection device 1 according to the present embodiment described above, the electric charge of the electrode 611 of the piezoelectric element 60 is discharged via the parasitic diodes 241 and 242 formed in the transfer gate 234 by the first discharge means. be able to. Therefore, the occurrence of unintended voltage in the electrode 611 of the piezoelectric element 60 is reduced. Therefore, application of unintended voltage to the piezoelectric element 60 is reduced, and thus unintended displacement of the piezoelectric element 60 is reduced.

Further, in the liquid ejecting apparatus 1 according to the present embodiment, the charge of the node a can be discharged by the second discharging means. Therefore, the voltage of node a can be lowered, and the leakage current generated through the resistance component of transfer gate 234 can be reduced. Therefore, application of unintended voltage to the piezoelectric element 60 due to leakage current is further reduced, and thus unintended displacement of the piezoelectric element 60 is further reduced.

Further, in the liquid ejecting apparatus 1 according to the present embodiment, it is possible to discharge the charge of the node c by the third discharging means. Therefore, application of unintended voltage to the electrode 612 of the piezoelectric element is reduced. Therefore, the occurrence of unintended displacement of the piezoelectric element 60 is further reduced.

The present invention includes configurations that are substantially the same as the configurations described in the embodiments (for example, configurations that have the same function, method, and result, or configurations that have the same purpose and effect). Moreover, the present invention includes configurations in which non-essential portions of the configurations described in the embodiments are replaced. In addition, the present invention includes a configuration that achieves the same effects or achieves the same purpose as the configurations described in the embodiments. In addition, the present invention includes configurations obtained by adding known techniques to the configurations described in the embodiments.

DESCRIPTION OF SYMBOLS 1... Liquid ejection apparatus 2... Moving body 3... Moving mechanism 4... Transport mechanism 10... Control unit 20... Head unit 21... Ejection module 24... Carriage 31... Carriage motor 32... Carriage guide shaft , 33 timing belt 35 carriage motor driver 40 platen 41 transport motor 42 transport roller 45 transport motor driver 50 drive signal generation circuit 51 drive circuit 60 piezoelectric element 70 Power supply switching circuit 80 Drive IC 90 Voltage generation circuit 100 Control circuit 190 Flexible cable 210 Selection control circuit 212 Shift register 214 Latch circuit 216 Decoder 230 Selection circuit , 232... inverter, 234... transfer gate, 235, 236... transistor, 241, 242, 243, 244... parasitic diode, 251... P substrate, 252... polysilicon, 253, 254... N-type diffusion layer, 255, 256, 257, 258... Electrode 261... N well 262... Polysilicon 263, 264... P-type diffusion layer 265, 266, 267, 268... Electrode 310... DAC circuit 320... Detection circuit 350... Judgment circuit 410 GVDD generation circuit 420 signal selection circuit 430 power supply control signal generation circuit 431 inverter 432 transistor 450 reference voltage signal generation circuit 451 comparator 452, 453 transistor 454, 455 , 456... resistors, 471, 472, 473... transistors, 474, 475... resistors, 500... integrated circuits, 510... modulation circuits, 512, 513... adders, 514... comparators, 515... inverters, 516... integral attenuators , 517... Attenuator 520... Gate drive circuit 521... First gate driver 522... Second gate driver 530... LC discharge circuit 531... Resistor 532... Transistor 541... Capacitor 542... Diode 550... Output circuit 551, 552 Transistor 553, 554 Resistor 560 Low-pass filter 561 Inductor 562 Capacitor 570 First feedback circuit 571, 572 Resistor 580 Second feedback circuit 581, 582... Resistor 583, 584, 585... Capacitor 600... Ejection part 601... Piezoelectric body 610... Sealing body 611, 612... Electrode 621... Diaphragm 630... Pressure chamber substrate 631 Cavity 632 Nozzle plate 633 Vibration absorber 640 Housing 641 Supply channel 651 Nozzle 661 Supply port 670 Channel substrate 671 Opening , 672 supply channel, 673 communication channel, 674 relay channel, Bst, COM-Out, Com-Out, Ctvh, Ctvh-Out, Drv, Drv-In, En, En-In, Err, Err -Out, GVDD, Gnd, Gnd-In, Gvd, Hdr, Ifb, Ldr, Sw, TG-In, TG-Out, Vbs, Vbs-Out, Vfb, Vhv, Vhv-In... terminal, P... medium, S …selection signal

Claims (14)

a piezoelectric element having a first electrode supplied with a drive signal and a second electrode supplied with a reference voltage signal, the piezoelectric element being displaced by a potential difference between the first electrode and the second electrode;
a cavity filled with liquid ejected from a nozzle as the piezoelectric element is displaced;
a diaphragm provided between the cavity and the piezoelectric element;
a first switch circuit having a first terminal to which the drive signal is supplied and a second terminal electrically connected to the first electrode, and controlling supply of the drive signal to the first electrode; ,
with
having a first mode in which electric charge at a first node where the first electrode and the second terminal are electrically connected is discharged via a parasitic diode of the first switch circuit;
the first switch circuit includes an NMOS transistor and a PMOS transistor;
a drain terminal of the NMOS transistor and a source terminal of the PMOS transistor are electrically connected to the first terminal;
a source terminal of the NMOS transistor and a drain terminal of the PMOS transistor are electrically connected to the second terminal;
In the first mode, the backgate terminal of the NMOS transistor and the backgate terminal of the PMOS transistor are electrically connected to a ground terminal.
A liquid ejection device characterized by: When the first switch circuit is off, the first mode is entered,
2. The liquid ejecting apparatus according to claim 1, wherein: a reference voltage signal generation circuit that outputs the reference voltage signal from a third terminal;
a second switch circuit capable of switching electrical connection between the third terminal and the ground terminal;
with
having a second mode in which the charge of a second node where the second electrode and the third terminal are electrically connected is discharged via the second switch circuit;
3. The liquid ejecting apparatus according to claim 1, wherein: After entering the second mode, entering the first mode,
4. The liquid ejecting apparatus according to claim 3 , characterized in that: When the first switch circuit is off, the second mode is entered,
5. The liquid ejecting apparatus according to claim 3 , wherein: a piezoelectric element having a first electrode supplied with a drive signal and a second electrode supplied with a reference voltage signal, the piezoelectric element being displaced by a potential difference between the first electrode and the second electrode;
a cavity filled with liquid ejected from a nozzle as the piezoelectric element is displaced;
a diaphragm provided between the cavity and the piezoelectric element;
a first switch circuit having a first terminal to which the drive signal is supplied and a second terminal electrically connected to the first electrode, and controlling supply of the drive signal to the first electrode; ,
with
having a first mode in which electric charge at a first node where the first electrode and the second terminal are electrically connected is discharged via a parasitic diode of the first switch circuit;
a reference voltage signal generation circuit that outputs the reference voltage signal from a third terminal;
a second switch circuit capable of switching electrical connection between the third terminal and the ground terminal;
with
a second mode in which the charge of a second node where the second electrode and the third terminal are electrically connected is discharged via the second switch circuit;
After entering the second mode, entering the first mode,
A liquid ejection device characterized by: a piezoelectric element having a first electrode supplied with a drive signal and a second electrode supplied with a reference voltage signal, the piezoelectric element being displaced by a potential difference between the first electrode and the second electrode;
a cavity filled with liquid ejected from a nozzle as the piezoelectric element is displaced;
a diaphragm provided between the cavity and the piezoelectric element;
a first switch circuit having a first terminal to which the drive signal is supplied and a second terminal electrically connected to the first electrode, and controlling supply of the drive signal to the first electrode; ,
with
having a first mode in which electric charge at a first node where the first electrode and the second terminal are electrically connected is discharged via a parasitic diode of the first switch circuit;
a reference voltage signal generation circuit that outputs the reference voltage signal from a third terminal;
a second switch circuit capable of switching electrical connection between the third terminal and the ground terminal;
with
a second mode in which the charge of a second node where the second electrode and the third terminal are electrically connected is discharged via the second switch circuit;
When the first switch circuit is off, the second mode is entered,
A liquid ejection device characterized by: a drive circuit that outputs the drive signal from a fourth terminal;
a third switch circuit capable of switching electrical connection between the fourth terminal and the ground terminal;
a third mode in which the charge of a third node where the first terminal and the fourth terminal are connected is discharged via the third switch circuit;
8. The liquid ejecting apparatus according to any one of claims 1 to 7 , characterized by: a piezoelectric element having a first electrode supplied with a drive signal and a second electrode supplied with a reference voltage signal, the piezoelectric element being displaced by a potential difference between the first electrode and the second electrode;
a cavity filled with liquid ejected from a nozzle as the piezoelectric element is displaced;
a diaphragm provided between the cavity and the piezoelectric element;
a first switch circuit having a first terminal to which the drive signal is supplied and a second terminal electrically connected to the first electrode, and controlling supply of the drive signal to the first electrode; ,
with
having a first mode in which electric charge at a first node where the first electrode and the second terminal are electrically connected is discharged via a parasitic diode of the first switch circuit;
a drive circuit that outputs the drive signal from a fourth terminal;
a third switch circuit capable of switching electrical connection between the fourth terminal and the ground terminal;
a third mode in which the charge of a third node where the first terminal and the fourth terminal are connected is discharged via the third switch circuit;
A liquid ejection device characterized by: After entering the third mode, entering the first mode,
10. The liquid ejecting apparatus according to claim 8 or 9 , characterized in that: When the first switch circuit is off, the third mode is entered,
11. The liquid ejecting apparatus according to any one of claims 8 to 10 , characterized in that: a piezoelectric element having a first electrode supplied with a drive signal and a second electrode supplied with a reference voltage signal, the piezoelectric element being displaced by a potential difference between the first electrode and the second electrode;
a cavity filled with liquid ejected from a nozzle as the piezoelectric element is displaced;
a diaphragm provided between the cavity and the piezoelectric element;
a first switch circuit having a first terminal to which the drive signal is supplied and a second terminal electrically connected to the first electrode, and controlling supply of the drive signal to the first electrode; ,
with
the first switch circuit includes a PMOS transistor;
the first terminal is electrically connected to the source terminal of the PMOS transistor;
the second terminal is electrically connected to the drain terminal of the PMOS transistor;
a back gate terminal of the PMOS transistor is electrically connected to one end of the switch element;
the other end of the switch element is electrically connected to a ground terminal;
A liquid ejection device characterized by: the source terminal is electrically connected to a first P-type semiconductor layer provided on the N-type semiconductor layer;
the drain terminal is electrically connected to a second P-type semiconductor layer provided on the N-type semiconductor layer apart from the first P-type semiconductor layer;
the back gate terminal is electrically connected to the N-type semiconductor layer;
13. The liquid ejecting apparatus according to claim 12 , characterized in that: The switch element is provided in a fourth switch circuit,
The fourth switch circuit controls whether to supply a voltage to the back gate terminal or to electrically connect the back gate terminal and the ground terminal.
14. The liquid ejecting apparatus according to claim 12 or 13 , characterized in that:

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