JP2019161674A - Imaging unit and imaging apparatus - Google Patents

Abstract

To densely provide photoelectric converters in an imager comprising a differential comparator for comparing a reference level with the signal level of an analog image signal.SOLUTION: An imaging unit comprises: the imager which comprises a pixel part including the plural photoelectric converters; a signal processor for processing a digital signal outputted from the imager; and the differential comparator which is disposed in the imager, compares the reference level with the signal level of an output signal generated in accordance with an electric charge amount photoelectrically converted by the pixel part, and outputs a digital signal.SELECTED DRAWING: Figure 3

Description

  The present invention relates to an imaging unit and an imaging apparatus.

Conventionally, in a digital pixel sensor chip (Digital Pixel Sensor Chip), a sensor unit including a photodiode, a comparison unit that compares an output signal from the sensor unit and a lamp voltage, and a memory unit that records an output from the comparison unit are provided. (For example, refer nonpatent literature 1).
[Prior art documents]
[Patent Literature]
[Non-Patent Document 1] IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 12, DECEMBER 2001, A 10000 Frames / s CMOS Digital Pixel Sensor, Stuart Kleinfelder, SukHwan Lim, Xinqiao Liu, and Abbas El Gamal, FELOW, IE

  In the above-described digital pixel sensor chip, each pixel includes a comparison unit and a memory unit in addition to the sensor unit. Therefore, one pixel is composed of a large number of transistors. Therefore, it has been difficult to provide pixels with high density in the digital pixel sensor chip.

  In the first aspect of the present invention, an imaging unit having a pixel unit including a plurality of photoelectric conversion units, a signal processing unit that processes a digital signal output from the imaging unit, and a reference level disposed in the imaging unit An imaging unit is provided that includes a differential comparator that outputs a digital signal by comparing the signal level of an output signal that is generated according to the amount of charge photoelectrically converted in a pixel portion.

  It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. In addition, a sub-combination of these feature groups can also be an invention.

2 is a cross-sectional view of a single-lens reflex camera 400. FIG. 3 is a block diagram illustrating a configuration example of an imaging unit 200. FIG. FIG. 2 is a circuit schematic diagram of a pixel unit 11 and a signal processing circuit 22 of the imaging unit 200 in the first embodiment. 5 is a time chart illustrating the operation of the imaging unit 200. FIG. 2 is a diagram illustrating an element layout of a pixel unit 11. FIG. 3 is a diagram illustrating a positional relationship between a photoelectric conversion unit 31, a photoelectric conversion unit 33, and a microlens 50 in a pixel unit 11. FIG. 6 is a diagram illustrating a modification of the positional relationship between the photoelectric conversion unit 31, the photoelectric conversion unit 33, and a microlens 50 in the pixel unit 11. FIG. FIG. 6 is a circuit schematic diagram of a pixel unit 12 and a signal processing circuit 22 of an imaging unit 300 in a second embodiment. It is a time chart figure explaining operation of image pick-up unit 300 in a 2nd embodiment. FIG. 10 is a circuit schematic diagram of a pixel unit 13 and a signal processing circuit 22 of an imaging unit 310 in a third embodiment.

  Hereinafter, the present invention will be described through embodiments of the invention, but the following embodiments do not limit the invention according to the claims. In addition, not all the combinations of features described in the embodiments are essential for the solving means of the invention.

  FIG. 1 is a cross-sectional view of a single-lens reflex camera 400. A single-lens reflex camera 400 as an example of an imaging apparatus includes an imaging unit 200, a lens unit 500, and a camera body 600. A lens unit 500 is attached to the camera body 600. The lens unit 500 includes an optical system arranged along the optical axis 410 in the lens barrel, and guides an incident subject light flux to the imaging unit 200 of the camera body 600.

  In this example, a single-lens reflex camera 400 will be described as an example of an imaging apparatus, but the camera body 600 may be regarded as an imaging apparatus. Further, the imaging device is not limited to an interchangeable lens camera provided with a mirror unit, but may be an interchangeable lens camera without a mirror unit, or a lens integrated camera regardless of the presence or absence of the mirror unit. In this example, the direction in which the subject luminous flux travels along the optical axis 410 is defined as the third direction. The directions perpendicular to the third direction and perpendicular to each other are defined as a first direction and a second direction.

  A lens mount 550 is coupled to the camera body 600. The camera body 600 includes a mirror 672 on the third direction side of the body mount 660. The mirror 672 is fixed to the shaft so as to be rotatable between an oblique position provided to be inclined with respect to the subject light beam incident in the third direction from the lens unit 500 and a retracted position for retreating from the subject light beam. .

  When the mirror 672 is in the oblique position, most of the subject light beam incident through the lens unit 500 is reflected by the mirror 672 and guided to the focus plate 652. The focus plate 652 is arranged at a position conjugate with the light receiving surface of the imaging unit 200 to visualize the subject image formed by the optical system of the lens unit 500. The subject image formed on the focus plate 652 is observed from the viewfinder 650 through the pentaprism 654 and the viewfinder optical system 656.

  The focus plate 652, the pentaprism 654, and the mirror 672 are supported by a mirror box 670 as a structure. The imaging unit 200 is attached to the mirror box 670. When the mirror 672 is retracted to the retracted position and the front curtain and the rear curtain of the shutter unit 340 are in the open state, the subject luminous flux that passes through the lens unit 500 reaches the light receiving surface of the imaging unit 200.

  On the side opposite to the shutter unit 340 with respect to the imaging unit 200, a body substrate 620 and a rear display unit 634 are sequentially arranged. A rear display unit 634 employing a liquid crystal panel or the like is located on the rear surface of the camera body 600. Electronic circuits such as a CPU 622 and an image processing unit 624 are mounted on the body substrate 620. The output of the imaging unit 200 is delivered to the image processing unit 624.

  FIG. 2 is a block diagram illustrating a configuration example of the imaging unit 200. The imaging unit 200 includes an imaging unit 10 and a signal processing unit 20. The imaging unit 10 may be a chip having the function of the imaging unit 10, and the signal processing unit 20 may be a chip having the function of the signal processing unit 20. A light beam enters the imaging unit 10 from the third direction. The imaging unit 10 and the signal processing unit 20 are provided so as to overlap at least partially in the direction of the optical axis 410. In this example, the entire imaging unit 10 is provided so as to be almost completely overlapped with the signal processing unit 20. The imaging unit 10 and the signal processing unit 20 are electrically connected to each other through the bump 15.

  The imaging unit 10 includes a pixel unit 11. The pixel unit 11 has a plurality of photoelectric conversion units arranged two-dimensionally in the first direction and the second direction. Each of the plurality of photoelectric conversion units photoelectrically converts incident light. That is, each of the plurality of photoelectric conversion units generates an electric charge according to the amount of light flux incident from the third direction. Therefore, the pixel unit 11 generates an analog image signal in accordance with the photoelectrically converted charge amount. Further, the pixel unit 11 converts an analog image signal into a digital signal. Thereafter, the pixel unit 11 outputs the converted digital signal to the signal processing circuit 22 of the signal processing unit 20.

  The signal processing unit 20 includes a signal processing circuit 22 and a focus detection unit 26. The signal processing circuit 22 processes a digital signal. The signal processing circuit 22 includes a latch unit 24. The latch unit 24 includes a counter circuit. The latch unit 24 counts the digital signal output from the imaging unit 10 with a counter circuit, thereby generating a pixel value corresponding to the analog image signal. The generated pixel value is output from the latch unit 24 to the focus detection unit 26 and the image processing unit 624.

  The focus detection unit 26 detects the focus position of the optical system through which the incident light has passed. Specifically, the focus detection unit 26 detects the image shift amount of the pair of images based on the digital image signal. Further, the focus detection unit 26 performs a calculation according to the image shift amount, and calculates a defocus amount that is a deviation of the current image formation plane from the planned image formation plane. In order to adjust the defocus amount, the position of the lens in the lens unit 500 of the single-lens reflex camera 400 is adjusted.

  The image processing unit 624 includes an image processing ASIC 625 and a recording unit 626. The image processing ASIC 625 performs various image processing using the recording unit 626 as a work space, and generates image data. When generating image data in the JPEG file format, the image processing ASIC 625 executes compression processing after performing white balance processing, gamma processing, and the like. The generated image data is recorded in the recording unit 626. The rear display unit 634 displays an image corresponding to the image data recorded in the recording unit 626 for a preset time.

  FIG. 3 is a circuit schematic diagram of the pixel unit 11 and the signal processing circuit 22 of the imaging unit 200 in the first embodiment. Note that each transistor is an n-type MOS transistor unless otherwise specified in this example. Of the two terminals other than the gate of the n-type MOS transistor, the high potential terminal is referred to as the drain, and the low potential terminal is referred to as the source. On the other hand, in two terminals other than the gate of the p-type MOS transistor, a high potential terminal is referred to as a source, and a low potential terminal is referred to as a drain.

  First, the configuration of the pixel unit 11 and the signal processing circuit 22 will be described. The pixel unit 11 includes a plurality of pixel sharing units 48. In FIG. 3, only the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 adjacent to each other in the second direction are shown, but the pixel sharing unit 48 is further arranged in the first direction and the second direction. A plurality are provided. A common voltage VDD is applied to each pixel sharing unit 48.

  One pixel sharing unit 48 includes first to fourth photoelectric conversion units 31-L, 31-R, 33-L, and 33-R, and first to fourth transfer transistors 32-L, 32-R, and 34. -L and 34-R, first and second switching transistors 38-L and 38-R, and a differential comparator 49. In this example, the pixel unit 11 in the imaging unit 10 includes a differential comparator 49. That is, the imaging unit 10 and the differential comparator 49 are provided on the same semiconductor chip. As described above, the signal processing circuit 22 includes the latch unit 24 and the signal source 25, and the latch unit 24 includes a plurality of counter circuits 28.

  A common terminal Tx1_L is connected to the gate of the first transfer transistor 32-L in the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2. Similarly, a common terminal Tx1_R is connected to the gates of the second transfer transistors 32-R in the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2. The common terminal Tx2_R is connected to the gate of the third transfer transistor 34-L, and the common terminal Tx2_L is connected to the gate of the fourth transfer transistor 34-R.

  Furthermore, in the other plurality of pixel sharing units 48 that are continuous in the second direction, the common terminal Tx1_L is shared by the gate of the first transfer transistor 32-L, and the common gate T of the second transfer transistor 32-R is shared. The common terminal Tx2_L is connected to the gate of the third transfer transistor 34-L, and the common terminal Tx2_R is connected to the gate of the fourth transfer transistor 34-R. Note that a different terminal Tx1_L, a terminal Tx1_R, a terminal Tx2_L, and a terminal Tx2_R are provided in different rows from the row in which the first pixel sharing portion 48-1 and the second pixel sharing portion 48-2 are located.

  The latch unit 24 includes a set of a plurality of counter circuits 28 corresponding to the plurality of pixel sharing units 48 that are continuous in the second direction. In FIG. 3, counter circuits 28-1 to 28-4 constituting a set of a plurality of counter circuits 28 are shown. The counter circuit 28-1 is connected to the second output unit 44, and the counter circuit 28-1 is connected to the first output unit 43. Two counter circuits 28 are provided for each pixel sharing unit 48. The latch unit 24 corresponds to a row different from the row in which the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located, and is different from the set of counter circuits 28. Counter circuit 28.

  The differential comparator 49 includes a first input unit 41, a second input unit 42, a first output unit 43, and a second output unit 44. The differential comparator 49 includes a transistor 35 -L whose gate is the first input unit 41 and a transistor 35 -R whose gate is the second input unit 42. The sources of transistors 35 -L and 35 -R are shorted and connected to the drain of transistor 30. The source of the transistor 30 is connected to a constant current source. The constant current source connected to the source of the transistor 30 is a constant current source that regulates the current flowing through the differential comparator 49.

  The differential comparator 49 includes p-type transistors 36-L and 36-R. The voltage VDD is applied to the sources of the p-type transistors 36-L and 36-R. The gates of the p-type transistors 36 -L and 36 -R are short-circuited to each other and connected to the drain of the p-type transistor 39. The p-type transistors 36 -L and 36 -R function as a load of the differential comparator 49. A predetermined constant voltage is applied to the gates of the p-type transistors 36 -L and 36 -R by the p-type transistor 39 and the constant current source connected to the p-type transistor 39. A predetermined voltage is applied between the sources and drains of the p-type transistors 36-L and 36-R. As a result, the p-type transistors 36-L and 36-R are operated in the saturation region. With such a configuration, each of the p-type transistors 36-L and 36-R functions as a high-resistance load.

  The drain of the p-type transistor 36 -L is connected to one of the source and drain of the transistor 37 and the drain of the transistor 35 -L. Similarly, the drain of the p-type transistor 36-R is connected to the other of the source and the drain of the transistor 37 and the drain of the transistor 35-R.

  One of the source and the drain in the P-type transistor 37 is connected to the first output unit 43. The other of the source and the drain of the P-type transistor 37 is connected to the second output unit 44. By turning on the P-type transistor 37, the first output unit 43 and the second output unit 44 are electrically connected. Thereby, the voltage level of the 1st output part 43 and the 2nd output part 44 can be made equal.

  The pixel unit 11 inputs an output signal generated according to the amount of charge photoelectrically converted in the photoelectric conversion unit 31 or 33 to one of the first input unit 41 and the second input unit 42. In addition, the pixel unit 11 inputs a reference level signal from the DAC 46 to the other of the first input unit 41 and the second input unit 42. The differential comparator 49 of this example compares the reference level with the signal level of the voltage signal input to the first input unit 41 and the second input unit 42, and compares the first output unit 43 and the second output unit 44. A digital signal corresponding to the comparison result is output from either one of the above.

  In this example, one DAC 46 is provided for a plurality of pixel sharing units 48 that are continuous in the second direction. That is, a different DAC 46 is provided in a row different from the row where the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located. Similarly, one terminal Tx1_L, one terminal Tx1_R, one terminal Tx2_L, and one terminal Tx2_R are provided for a plurality of pixel sharing units 48 that are continuous in the second direction. That is, different terminals Tx1_L, terminals Tx1_R, terminals Tx2_L, and terminals Tx2_R are provided in different rows from the row where the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are located. As a modification, only one DAC 46 may be provided. In this case, the output of the DAC 46 is provided for each row using a selector or a decoder.

  The counter circuit 28-2 of the latch unit 24 is the result of comparing the signal level of the first photoelectric conversion unit 31 -L or the third photoelectric conversion unit 33 -L and the reference level input from the DAC 46. 1 digital signal is input. The counter circuit 28-1 of the latch unit 24 has a result of comparing the signal level of the second photoelectric conversion unit 31 -R or the fourth photoelectric conversion unit 33 -R and the reference level input from the DAC 46. A second digital signal is input. When the first digital signal is input from the first output unit 43 to the counter circuit 28-2, the second digital signal may not be used. Conversely, when the second digital signal is input from the second output unit 44 to the counter circuit 28-1, the first digital signal may not be used. That is, the first digital signal and the second digital signal may be switched and input to the latch unit 24.

  In this example, when the voltage value of the signal input to the first input unit 41 is lower than the voltage value of the signal input to the second input unit 42, the first output unit 43 supplies the counter circuit 28-2. A high voltage signal is output. On the other hand, when the voltage value input to the first input unit 41 is higher than the voltage value input to the second input unit 42, a low voltage signal is output from the first output unit 43 to the counter circuit 28-2. Is done.

  Similarly, when the voltage value input to the second input unit 42 is lower than the voltage value input to the first input unit 41, a high voltage signal is output from the second output unit 44 to the counter circuit 28-1. Is done. On the other hand, when the voltage value input to the second input unit 42 is higher than the voltage value input to the first input unit 41, a low voltage signal is output from the second output unit 44 to the counter circuit 28-1. .

  The signal source 25 supplies a pulse signal having a constant cycle to each counter circuit 28. In this example, the timing at which the magnitude relationship between the voltage value of the first input unit 41 or the second input unit 42 and the voltage value in the reference signal of the ramp waveform of the DAC 46 changes is specified using the pulse signal of the fixed period. The The fixed period of the pulse signal may be a time width corresponding to the minimum step width of the voltage value in the ramp waveform output from the DAC 46.

  The counter circuit 28-2 is a signal in a period from the timing when the monotonically increasing ramp waveform is input to the second input unit 42 to the timing when the voltage value of the second input unit 42 becomes equal to or higher than the voltage value of the first input unit 41. The number of pulses of the source 25 is counted. This period is referred to as a first count period for convenience. The number of pulses counted in the first count period is handled as a reset level in the photoelectric conversion unit 31 or 33. In addition, the counter circuit 28-2 is a period from the timing when the monotonously decreasing ramp waveform is input to the second input unit 42 to the timing when the voltage value of the second input unit 42 is equal to or lower than the voltage value of the first input unit 41. The number of pulses of the signal source 25 is counted. This period is referred to as a second count period for convenience. The number of pulses counted in the second count period is handled as an output level in the photoelectric conversion unit 31 or 33. A value obtained by subtracting the reset level from the output level is treated as a pixel value in the digital image signal. Note that the second count period becomes longer as the amount of charge accumulated in the photoelectric conversion unit 31 or 33 increases, so that the number of pulses counted in the second count period increases.

  The cathode of the first photoelectric conversion unit 31-L is connected to the source of the first transfer transistor 32-L. The drain of the first transfer transistor 32-L is connected to the first input unit 41. The first transfer transistor 32-L switches whether the first photoelectric conversion unit 31-L is connected to the first input unit 41 or not. The cathode of the second photoelectric conversion unit 31-R is connected to the source of the second transfer transistor 32-R. The drain of the second transfer transistor 32-R is connected to the second input unit. The second transfer transistor 32-R switches whether the second photoelectric conversion unit 31-R is connected to the second input unit 42 or not.

  The cathode of the third photoelectric conversion unit 33-L is connected to the source of the third transfer transistor 34-L. The drain of the third transfer transistor 34 -L is connected to the first input unit 41. The third transfer transistor 34 -L switches whether to connect the third photoelectric conversion unit 33 -L to the first input unit 41. The cathode of the fourth photoelectric conversion unit 33-R is connected to the source of the fourth transfer transistor 34-R. The drain of the fourth transfer transistor 34 -R is connected to the second input unit 42. The fourth transfer transistor 34 -R switches whether or not the fourth photoelectric conversion unit 33 -R is connected to the second input unit 42.

  The DAC 46 that is a digital-analog conversion unit is provided in the imaging unit 200. The drain of the first switching transistor 38 -L and the drain of the second switching transistor 38 -R are both connected to the DAC 46. The gate of the first switching transistor 38-L is connected to the terminal R_L, and the gate of the second switching transistor 38-R is connected to the terminal R_R. The source of the first switching transistor 38 -L is connected to the first input unit 41, and the source of the second switching transistor 38 -R is connected to the second input unit 42.

  The DAC 46 sequentially generates a reference level having a ramp waveform and a reset level having a pulse waveform. For example, when the charge accumulated in the first input unit 41 is reset, the DAC 46 generates a reset level signal having a pulse waveform. The terminal R_L outputs a high voltage to turn on the first switching transistor 38-L. Thus, the first switching transistor 38-L is connected between the first input unit 41 and the first transfer transistor 32-L before the first photoelectric conversion unit 31-L is connected to the first input unit 41. A reset level signal can be input to the wiring between them. Thereby, the electric charge accumulated in the first input unit 41 is removed.

  Similarly, when resetting the electric charge accumulated in the second input section 42, the DAC 46 generates a reset level signal having a pulse waveform. The terminal R_R outputs a high voltage to turn on the second switching transistor 38-R. Thus, the second switching transistor 38-R is connected between the second input unit 42 and the second transfer transistor 32-R before connecting the second photoelectric conversion unit 31-R to the second input unit 42. A reset level signal can be input to the wiring between them. Thereby, the electric charge accumulated in the second input unit 42 is removed.

  The first switching transistor 38 -L also switches whether to input the reference level of the DAC 46 to the first input unit 41. Similarly, the second switching transistor 38 -R switches whether to input the reference level of the DAC 46 to the second input unit 42. For example, when a ramp waveform reference level is input to the first input unit 41, the DAC 46 generates a signal having the ramp waveform. The terminal R_L outputs a high voltage to turn on the first switching transistor 38-L. When the terminal R_L outputs a low voltage, the first switching transistor 38-L is turned off.

  In this example, the latch unit 24 is provided not in the imaging unit 10 but in the signal processing circuit 22 in the signal processing unit 20. Thereby, in the imaging unit 10, an area corresponding to the latch unit 24 can be allocated to the pixel sharing unit 48. In addition, in the pixel sharing unit 48, one differential comparator 49 is provided for the first to fourth photoelectric conversion units 31-L to 33-R. Accordingly, the exclusive area of the photoelectric conversion units 31 and 33 in the pixel unit 11 can be increased as compared with the conventional example in which one comparison unit is provided for one photodiode. Therefore, in the pixel unit 11 having the differential comparator 49, the photoelectric conversion units 31 and 33 can be provided at a higher density than in the past.

  In this example, the constant current source connected to the drain of the p-type transistor 39 and the constant current source connected to the source of the transistor 30 are described as components of the pixel portion 11. However, the constant current source may be provided in the imaging unit 200 and may not be provided in the pixel unit 11. Further, one constant current source may be provided in one pixel sharing unit 48 and connected in common to the drain of the p-type transistor 39 and the source of the transistor 30.

  Next, the operation of the differential comparator 49 will be described. The differential comparator 49 of this example compares the voltage value of the analog image signal input to the first input unit 41 with the voltage value of the ramp voltage of the DAC 46 input to the second input unit 42. In this specification, the comparison operation is referred to as a first comparison operation. In the first comparison operation, the differential comparator 49 compares, for example, the signal level of the first photoelectric conversion unit 31-L with the reference level of the ramp waveform. In this case, the pixel unit 11 inputs the output signal of the first photoelectric conversion unit 31 -L to the first input unit 41 and inputs the reference level of the ramp waveform to the second input unit 42.

  In the first comparison operation, an analog image signal is input to the first input unit 41 from one of the first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L. The first transfer transistor 32-L outputs the charge accumulated in the first photoelectric conversion unit 31-L to the first input unit 41. Similarly, the third transfer transistor 34 -L outputs the charge accumulated in the third photoelectric conversion unit 33 -L to the first input unit 41. By selectively setting the terminals Tx1_L and Tx2_L to a high voltage at different timings, the first transfer transistor 32-L and the third transfer transistor 34-L can be selectively turned on. As a result, the first transfer transistor 32-L and the third transfer transistor 34-L cause the charges accumulated in the first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L to have different timings. To the first input unit 41. Therefore, analog image signals are input to the first input unit 41 from the first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L at different timings.

  In the first comparison operation, a ramp waveform reference signal is input from the DAC 46 to the second input unit 42. The voltage value of the ramp waveform reference signal monotonously increases or decreases with time. In the first comparison operation, the DAC 46 of this example inputs a reference signal that monotonously decreases from a high voltage value to a low voltage value to the second input unit 42. In another operation, the DAC 46 inputs a high voltage reference signal to the second input unit 42 for a predetermined time. In yet another operation, the DAC 46 inputs a reference signal that monotonously decreases from a low voltage value to a high voltage value to the second input unit 42.

  When the first comparison operation is not performed, the terminal R_L outputs a high voltage to turn on the first switching transistor 38-L, and the DAC 46 outputs a high voltage, whereby the first input unit 41 can be the high voltage of the DAC 46. Thereby, since the electric charge output to the 1st input part 41 can be removed, the electric charge output to the 1st input part 41 is not influenced by the electric charge output previously.

  Further, the differential comparator 49 of this example compares the voltage signal of the analog image signal input to the second input unit 42 with the reference signal of the ramp waveform of the DAC 46 input to the first input unit 41. In this specification, the comparison operation is referred to as a second comparison operation. For example, in the second comparison operation, the differential comparator 49 compares the signal level of the second photoelectric conversion unit 31-R with the reference level. In this case, the pixel unit 11 inputs the output signal of the second photoelectric conversion unit 31 -R to the second input unit 42 and inputs the reference level to the first input unit 41.

  In the second comparison operation, an analog image signal is input to the second input unit 42 from one of the second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R. The second transfer transistor 32-R outputs the charge accumulated in the second photoelectric conversion unit 31-R to the second input unit 42. Similarly, the fourth transfer transistor 34 -R outputs the charge accumulated in the fourth photoelectric conversion unit 33 -R to the second input unit 42. By selectively setting the terminals Tx1_R and Tx2_R to the high voltage at different timings, the second transfer transistor 32-R and the fourth transfer transistor 34-R can be selectively turned on. As a result, the second transfer transistor 32-R and the fourth transfer transistor 34-R cause the charges accumulated in the second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R to have different timings. Is output to the second input unit 42. Therefore, analog image signals are input to the second input unit 42 from the second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R at different timings.

  In the second comparison operation, the ramp voltage is input from the DAC 46 to the first input unit 41. The voltage signal of the DAC 46 in the second comparison operation is the same as that in the first comparison operation. When the second comparison operation is not performed, the terminal R_R outputs a high voltage to turn on the second switching transistor 38-R, and the DAC 46 outputs a high voltage, whereby the second input unit 42 can be the high voltage of the DAC 46. Thereby, the electric charge output to the 2nd input part 42 can be removed. Therefore, the charge output to the second input unit 42 is not affected by the previously output charge.

  FIG. 4 is a time chart for explaining the operation of the imaging unit 200. The horizontal axis indicates time. The vertical axis of each signal indicates the voltage value. Tx1_L and Tx1_R indicate voltage values output from the terminals Tx1_L and Tx1_R in FIG. 3, respectively. Tx2_L and Tx2_R respectively indicate voltage values output from the terminals Tx2_L and Tx2_R in FIG. R_L and R_R indicate voltage values output from terminals R_L and R_R in FIG. 3, respectively. R_c represents the voltage value of the gate of the P-type transistor 37 in FIG. DAC indicates a voltage value output from the DAC 46 in FIG. 4 shows voltage values of the first input unit 41, the second input unit 42, the first output unit 43, and the second output unit 44 of FIG.

  From time t1 to time t9, the electric charge photoelectrically converted by the first photoelectric conversion unit 31-L is output as a digital signal to the counter circuit 28-2. Time from time t1 to t9 corresponds to the first comparison operation. From time t9 to t10, the charge photoelectrically converted by the second photoelectric conversion unit 31-R is output to the counter circuit 28-1 as a digital signal. Time from time t9 to t10 corresponds to the second comparison operation.

  From time t10 to t11, the charge photoelectrically converted by the third photoelectric conversion unit 33-L is output to the counter circuit 28-2. After time t11, the charge photoelectrically converted by the fourth photoelectric conversion unit 33-R is output to the counter circuit 28-1. Since the operation after time t9 is a repetition of the operation from time t1 to t9, only the operation from time t1 to t9 will be described below. Also, from time t1 to t9, the output of the second output unit 44 is not used by the counter circuit 28-1, and is illustrated as a low voltage. Similarly in other periods, the output not used in the counter circuit 28 is illustrated as a low voltage.

  At time t1, the terminal R_L becomes a high voltage. At time t1, the DAC 46 outputs a reset voltage. As a result, the first switching transistor 38-L is turned on, and the charge of the first input unit 41 is reset. At time t1, R_c becomes a low voltage. As a result, the P-type transistor 37 is turned on, and the first input unit 41 and the second input unit 42 have the same potential. The high voltage at terminal R_L and DAC 46 continues until time t2. R_c changes to a high voltage before time t2. From time t1 to t2, the first input unit 41 becomes a high voltage.

  At time t2, the terminals R_L and the DAC 46 become low voltage. As a result, the first switching transistor 38-L is turned off. At time t2, the terminal R_R becomes a high voltage. As a result, the second switching transistor 38-R is turned on. While the second switching transistor 38 -R is turned on, the potential of the second input unit 42 can follow the potential of the DAC 46 to be a high voltage. The DAC 46 is at a low voltage until time t3. Since the reset operation is completed, the terminal R_L becomes a low voltage from t2 to t9, and the first switching transistor 38-L is turned off.

  At time t3, the second switching transistor 38-R is in the on state. The DAC 46 inputs a monotonically increasing ramp voltage. Since the terminal R_R maintains a high voltage, a monotonically increasing ramp voltage is input to the second input unit 42. Note that the maximum value of the ramp voltage output by the DAC 46 is greater than the reset voltage output by the DAC 46 at time t1.

  After the time t3 and before the time t4, the potential of the first input unit 41 is higher than the reference voltage input to the second input unit 42. Therefore, the first output unit 43 outputs a low voltage. However, at time t <b> 4, the potential of the first input unit 41 becomes lower than the reference voltage input to the second input unit 42. As a result, the first output unit 43 outputs a high voltage. Note that a period from t3 when the monotonously increasing ramp waveform is input to the second input unit 42 to t4 when the voltage value of the second input unit 42 becomes equal to or higher than the voltage value of the first input unit 41 is a period. This corresponds to the first count period described in the description of FIG.

  At time t5, the terminal Tx1_L becomes a high voltage. Thereby, charge transfer from the first photoelectric conversion unit 31 -L to the first input unit 41 is started. From time t5 to time t6, the terminal Tx1_L maintains the high voltage. As a result, the potential of the first input unit 41 decreases from time t5 to time t6 by the amount corresponding to the voltage corresponding to the amount of accumulated charge.

  From time t6 to t7, the DAC 46 maintains a high voltage. At time t7, the DAC 46 starts to input a monotonically decreasing ramp voltage. At time t7, the terminal R_R is on. As a result, the second switching transistor 38 -R is turned on, and a monotonically decreasing ramp voltage is input to the second input unit 42.

  At time t8, the potential of the first input unit 41 becomes higher than the reference voltage input to the second input unit 42. Therefore, the first output unit 43 outputs a low voltage. A period from t7 when the monotonously decreasing ramp waveform is input to the second input unit 42 to t8 when the voltage value of the second input unit 42 is equal to or lower than the voltage value of the first input unit 41 is set. This corresponds to the second count period described in the description of FIG.

  FIG. 5 is a diagram illustrating an element layout of the pixel unit 11. As in FIG. 3, the first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 are indicated by dotted line frames. The first pixel sharing unit 48-1 and the second pixel sharing unit 48-2 have the same configuration. The first photoelectric conversion unit 31-L and the third photoelectric conversion unit 33-L are provided side by side in the first direction. Similarly, the second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R are provided side by side in the first direction. The first photoelectric conversion unit 31-L and the third photoelectric conversion unit 31-R are provided side by side in a second direction perpendicular to the first direction. Similarly, the third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R are provided side by side in the second direction.

  In the region of the first photoelectric conversion unit 31-L, the first transfer transistor 32-L is provided so as to overlap. In addition, the second transfer transistor 32-R is provided to overlap the region of the second photoelectric conversion unit 31-R. Further, the third transfer transistor 34 -L is provided in an overlapping manner in the region of the third photoelectric conversion unit 33 -L. In addition, a fourth transfer transistor 34-R is provided to overlap the region of the fourth photoelectric conversion unit 33-R.

  The differential comparator 49 is provided between the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R, and between the third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R. Between. The differential comparator 49 is indicated by a dotted frame. The 1st input part 41 and the 2nd input part 42 are provided so that it may have a long side parallel to the 1st direction. The first input unit 41 is adjacent to the first transfer transistor 32-L and the third transfer transistor 34-L in the second direction. Similarly, the second input unit 42 is adjacent to the second transfer transistor 32-R and the fourth transfer transistor 34-R in the second direction.

  With this configuration, the first input unit 41, the first transfer transistor 32-L, and the third transfer transistor 34-L can be provided close to each other. In addition, the second input unit 42, the second transfer transistor 32-R, and the fourth transfer transistor 34-R can be provided close to each other. Therefore, the wiring length between the input unit and the transfer transistors 32 and 34 can be shortened. Therefore, signal delay between the transfer transistors 32 and 34 and the input unit, and noise generated between the transfer transistors 32 and 34 and the input unit can be reduced.

  FIG. 6 is a diagram illustrating a positional relationship between the photoelectric conversion unit 31, the photoelectric conversion unit 33, and the microlens 50 in the pixel unit 11. The first photoelectric conversion unit 31-L, the second photoelectric conversion unit 31-R, the third photoelectric conversion unit 33-L, and the fourth photoelectric conversion unit 33-R are the same as those in FIG. For simplicity, the photoelectric conversion units 31 and 33 are indicated by squares. The microlens 50 is indicated by a circle. The microlens 50, the photoelectric conversion unit 31, and the photoelectric conversion unit 33 are provided in the order of the microlens 50, the photoelectric conversion unit 31, or the photoelectric conversion unit 33 in the third direction. A light beam incident from the subject passes through each microlens 50 and enters the photoelectric conversion unit 31 and the photoelectric conversion unit 33.

  FIG. 7 is a diagram illustrating a modification of the positional relationship between the photoelectric conversion unit 31, the photoelectric conversion unit 33, and the microlens 50 in the pixel unit 11. In this example, corresponding to one microlens 50, the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R or the third photoelectric conversion unit 33-L and the fourth photoelectric conversion. 6 is different from the example of FIG. 6 in that the portion 33-R is provided. For example, one microlens 50 is provided in common to the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R.

  The first photoelectric conversion unit 31-L and the second photoelectric conversion unit 33-L are adjacent in the first direction. The second photoelectric conversion unit 31-R and the fourth photoelectric conversion unit 33-R are also adjacent in the first direction. Further, the first photoelectric conversion unit 31-L and the second photoelectric conversion unit 31-R are adjacent in the second direction. The third photoelectric conversion unit 33-L and the fourth photoelectric conversion unit 33-R are also adjacent in the second direction.

  The focus detection line 70 includes a plurality of first photoelectric conversion units 31-L and second photoelectric conversion units 31-R adjacent in the second direction in the second direction. One image is generated from the charges photoelectrically converted by the plurality of first photoelectric conversion units 31 -L in the focus detection line 70. Further, another image is generated from the charges photoelectrically converted by the plurality of second photoelectric conversion units 31 -R in the focus detection line 70. By comparing the one image with another image, the image shift amount of the pair of images described above is calculated. Therefore, the focus of the optical system can be detected using the focus detection line 70.

  FIG. 8 is a circuit schematic diagram of the pixel unit 12 and the signal processing circuit 22 of the imaging unit 300 in the second embodiment. The difference from the first embodiment is the configuration of the pixel sharing unit 58. In addition to the configuration of the pixel sharing unit 48 in the first embodiment, the pixel sharing unit 58 of this example includes a fifth transfer transistor 82-L, a sixth transfer transistor 82-R, and a first diode 81- It further includes L and a second diode 81-R, a seventh transfer transistor 84-L and an eighth transfer transistor 84-R, and a third diode 83-L and a fourth diode 83-R.

  The fifth transfer transistor 82 -L is provided between the first transfer transistor 32-L and the first input unit 41. The sixth transfer transistor 82 -R is provided between the second transfer transistor 32-R and the second input unit 42. Similarly, the seventh transfer transistor 84-L is provided between the third transfer transistor 34-L and the first input unit 41, and the eighth transfer transistor 84-R is the fourth transfer transistor 34-L. -R is provided between the second input section 42 and the second input section 42.

  The cathode of the first diode 81-L is provided between the drain of the first transfer transistor 32-L and the source of the fifth transfer transistor 82-L. The anode of the first diode 81-L is grounded. The cathode of the second diode 81-R is provided between the drain of the second transfer transistor 32-R and the source of the sixth transfer transistor 82-R. The cathode of the third diode 83-L is provided between the drain of the third transfer transistor 34-L and the source of the seventh transfer transistor 84-L. The cathode of the fourth diode 83-R is provided between the drain of the fourth transfer transistor 34-R and the source of the eighth transfer transistor 84-R. The anodes of the second diode 81-R, the third diode 83-L, and the fourth diode 83-R are installed.

  The fifth transfer transistor 82 -L switches whether to transfer the charge transferred from the first transfer transistor 32-L to the first input unit 41. Similarly, the seventh transfer transistor 84 -L switches whether to output the charge transferred from the third transfer transistor 34 -L to the first input unit 41. The sixth transfer transistor 82-R switches whether to output the charge transferred from the second transfer transistor 32-R to the second input unit 42. Similarly, the eighth transfer transistor 84-R switches whether to output the charge transferred from the fourth transfer transistor 34-R to the second input unit 42.

  The charge transferred from the first transfer transistor 32-L to the cathode of the first diode 81-L is held at the cathode of the first diode 81-L for a predetermined period. By appropriately adjusting the characteristics of the first diode 81-L, the pn junction interface of the first diode 81-L is completely depleted. As a result, the charge is transferred to and held by the cathode of the first diode 81-L, thereby preventing the charge from flowing to the ground and disappearing. Similarly, the second diode 81-R, the third diode 83-L, and the fourth diode 83-R hold the charge transferred to the cathode.

  FIG. 9 is a time chart for explaining the operation of the imaging unit 300 in the second embodiment. This example is a so-called global shutter system. In the global shutter system, all the first transfer transistors 32-L, the second transfer transistors 32-R, the third transfer transistors 34-L, and the fourth transfers of all the pixel sharing units 58 in the pixel unit 12 are used. The transistor 34-R is turned on at the same time. Accordingly, the charges accumulated in the first photoelectric conversion unit 31-L, the second photoelectric conversion unit 31-R, the third photoelectric conversion unit 33-L, and the fourth photoelectric conversion unit 33-R are simultaneously From the first transfer transistor 32-L, the second transfer transistor 32-R, the third transfer transistor 34-L, and the fourth transfer transistor 34-R, the first diode 81-L, the second diode 81 -R, transferred to the cathodes of the third diode 83-L and the fourth diode 83-R, respectively. As a result, compared with a rolling shutter system in which charge transfer is performed for each of the plurality of photoelectric conversion units 31 or the plurality of photoelectric conversion units 33 that are continuously provided in the first direction, Distortion can be improved.

  In this example, the first transfer transistor 32-L and the second transfer transistor 32-R, and the third transfer transistor 34-L and the fourth transfer transistor 34-R are simultaneously operated from time t1 to time t2. Turned on. In the pixel sharing unit 58 other than the pixel sharing unit 58 shown in the figure, the first transfer transistor 32-L and the second transfer transistor 32-R, and the third transfer transistor 34-L and the fourth transfer transistor 34-L are also included. The transfer transistors 34-R are simultaneously turned on from time t1 to t2.

  The charges transferred from the first transfer transistor 32-L, the second transfer transistor 32-R, the third transfer transistor 34-L, and the fourth transfer transistor 34-R are temporarily transferred to the first diode 81-. L, the second diode 81-R, the third diode 83-L, and the fourth diode 83-R are respectively held at the cathodes. The subsequent operation is the same as that of the first embodiment in FIG. Note that Tx in FIG. 4 corresponds to Ts in FIG. That is, the charges held at the cathodes of the first diode 81-L, the second diode 81-R, the third diode 83-L, and the fourth diode 83-R are transferred to the fifth transfer transistor 82- By sequentially turning on L, the sixth transfer transistor 82-R, the seventh transfer transistor 84-L, and the eighth transfer transistor 84-R, the data is sequentially transferred to the first input unit 41 or the second input unit 42. The For example, the fifth transfer transistor 82-L is turned on by setting the terminal Ts1_L to a high voltage, and the charge held at the cathode of the first diode 81-L is output to the first input unit 41.

  In the first and second embodiments, in one differential comparator 49, the outputs of the two photoelectric conversion units 31-L and 33-L are connected to the first input unit 41, and the other two photoelectric conversion units 31 are connected. The form in which the outputs of -R and 33-R are connected to the second input unit 42 is shown. However, one differential comparator 49 may further include a plurality of photoelectric conversion units. That is, the outputs of the four photoelectric conversion units may be connected to the first input unit 41, and the outputs of the other four photoelectric conversion units may be connected to the second input unit 42. Alternatively, the outputs of the eight photoelectric conversion units may be connected to the first input unit 41, and the outputs of the other eight photoelectric conversion units may be connected to the second input unit 42. The output from each photoelectric conversion unit to the first input unit 41 or the second input unit 42 may be controlled using the terminal Tx common to the gates of each row as in the first embodiment, or the second implementation. As in the embodiment, control may be performed by using the terminal Tx and the terminal Ts common to the gates of the respective rows. By connecting the outputs of eight or more photoelectric conversion units to one differential comparator 49, the number of photoelectric conversion units for one differential comparator 49 is smaller than when connecting the outputs of four photoelectric conversion units. To increase. Since a certain occupied area is required to configure one differential comparator 49, the ratio of the occupied area of the differential comparator 49 to one photoelectric conversion unit can be reduced by this configuration.

  FIG. 10 is a circuit schematic diagram of the pixel unit 13 and the signal processing circuit 22 of the imaging unit 310 in the third embodiment. The difference from the first embodiment is the configuration of the pixel sharing unit 68. The pixel sharing unit 68 of this example includes a first photoelectric conversion unit 31-L, a first transfer transistor 32-L, a first switching transistor 38-L, a second switching transistor 38-R, and a differential A comparator 49 is provided. The latch unit 24 has one counter circuit 28 for one pixel sharing unit 68.

  In this example, the signal level of the output signal generated according to the amount of charge photoelectrically converted in the first photoelectric conversion unit 31 -L is input to the first input unit 41. Further, the reference level of the DAC 46 is input to the second input unit 42. Then, the signal level of the output signal and the reference level of the DAC 46 are compared. The comparison operation is the same as in the first embodiment. The comparison result is output from the first output unit 43 to the counter circuit 28-2.

  With the configuration of this example, the latch unit 24 is provided not in the imaging unit 10 but in the signal processing circuit 22 of the signal processing unit 20. Thereby, in the imaging unit 10, an area corresponding to the latch unit 24 can be allocated to the pixel sharing unit 68. Thus, the area occupied by the photoelectric conversion units 31 and 33 in the pixel unit 13 can be increased as compared with the conventional example in which one differential comparator 49 is provided for one photodiode. Therefore, in the pixel portion 13 having the differential comparator 49, the photoelectric conversion portions 31 and 33 can be provided at a higher density than conventional. In the first embodiment, four photoelectric conversion units 31 and 33 are provided for one differential comparator 49. Therefore, in the first embodiment, the ratio of the occupied area of the differential comparator 49 to one photoelectric conversion unit can be reduced as compared with the case of the third embodiment.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. It will be apparent to those skilled in the art that various modifications or improvements can be added to the above embodiment. It is apparent from the description of the scope of claims that embodiments with such changes or improvements can be included in the technical scope of the present invention.

  The order of execution of each process such as operations, procedures, steps, and stages in the apparatus, system, program, and method shown in the claims, the description, and the drawings is particularly “before” or “prior to”. It should be noted that the output can be realized in any order unless the output of the previous process is used in the subsequent process. Even if the operation flow in the claims, the description, and the drawings is described using “first”, “next”, etc. for convenience, it means that it is essential to carry out in this order. It is not a thing.

DESCRIPTION OF SYMBOLS 10 Image pick-up part, 11 pixel part, 12 pixel part, 13 pixel part, 15 bump, 20 signal processing part, 22 signal processing circuit, 24 latch part, 25 signal source, 26 focus detection part, 28 counter circuit, 30 transistor, 31 Photoelectric conversion unit, 32 transfer transistor, 33 photoelectric conversion unit, 34 transfer transistor, 35 transistor, 36 transistor, 37 transistor, 38 switching transistor, 39 transistor, 41 first input unit, 42 second input unit, 43 first output unit , 44 Second output unit, 46 DAC, 48 pixel sharing unit, 49 differential comparator, 50 microlens, 58 pixel sharing unit, 68 pixel sharing unit, 70 focus detection line, 81 diode, 82 transfer transistor, 83 diode, 84 Transfer transistor, 200 300, imaging unit, 310 imaging unit, 340 shutter unit, 410 optical axis, 400 single lens reflex camera, 500 lens unit, 550 lens mount, 600 camera body, 620 body substrate, 622 CPU, 624 image processing unit, 625 image Processing ASIC, 626 Recording unit, 634 Rear display unit, 650 finder, 652 Focus plate, 654 Pentaprism, 656 Finder optical system, 660 Body mount, 670 Mirror box, 672 Mirror

Claims (12)

An imaging unit having a pixel unit including a plurality of photoelectric conversion units;
A signal processing unit for processing a digital signal output from the imaging unit;
An imaging device that is disposed in the imaging unit and includes a reference level and a differential comparator that outputs the digital signal by comparing a signal level of an output signal generated according to the amount of charge photoelectrically converted in the pixel unit. unit. The differential comparator is
Having a first input part and a second input part,
The differential comparator outputs the digital signal according to a comparison result of signal levels of signals input to the first input unit and the second input unit,
The imaging unit according to claim 1, wherein the pixel unit inputs the output signal to one of the first input unit and the second input unit, and inputs the signal of the reference level to the other. The pixel unit includes a first photoelectric conversion unit and a second photoelectric conversion unit in which a signal level of the output signal is compared with the reference level in the differential comparator,
When the differential comparator compares the signal level of the first photoelectric conversion unit with the reference level, the pixel unit inputs the output signal of the first photoelectric conversion unit to the first input unit, and , Input a reference level to the second input unit,
When the differential comparator compares the signal level of the second photoelectric conversion unit with the reference level, the pixel unit inputs the output signal of the second photoelectric conversion unit to the second input unit, and The imaging unit according to claim 2, wherein a reference level is input to the first input unit. The pixel portion is
A first transfer transistor for switching whether to connect the first photoelectric conversion unit to the first input unit;
A second transfer transistor for switching whether or not to connect the second photoelectric conversion unit to the second input unit;
A first switching transistor for switching whether to input the reference level to the first input unit;
The imaging unit according to claim 3, further comprising: a second switching transistor that switches whether to input the reference level to the second input unit. A digital-to-analog converter that sequentially generates a reference level having a ramp waveform and a reset level having a pulse waveform;
The first switching transistor inputs the reset level to a wiring between the first input unit and the first transfer transistor before connecting the first photoelectric conversion unit to the first input unit. And
The second switching transistor inputs the reset level to a wiring between the second input unit and the second transfer transistor before connecting the second photoelectric conversion unit to the second input unit. The imaging unit according to claim 4. The pixel portion is
A third photoelectric conversion unit and a fourth photoelectric conversion unit, wherein a signal level of the output signal is compared with the reference level in the differential comparator;
A third transfer transistor that outputs the charge accumulated in the third photoelectric conversion unit to the first input unit;
The imaging unit according to claim 5, further comprising: a fourth transfer transistor that outputs the electric charge accumulated in the fourth photoelectric conversion unit to the second input unit. The pixel portion is
A fifth transfer transistor, which is provided between the first transfer transistor and the first input unit, and switches whether to transfer the charge transferred from the first transfer transistor to the first input unit; ,
A sixth transfer transistor which is provided between the second transfer transistor and the second input unit and switches whether to transfer the charge transferred from the second transfer transistor to the second input unit; Further comprising
The imaging unit according to claim 4, wherein the first transfer transistor and the second transfer transistor are simultaneously turned on. The first photoelectric conversion unit and the third photoelectric conversion unit are provided side by side in the first direction,
The second photoelectric conversion unit and the fourth photoelectric conversion unit are provided side by side in the first direction,
The first photoelectric conversion unit and the second photoelectric conversion unit are provided side by side in a second direction perpendicular to the first direction,
The imaging unit according to claim 6, further comprising a microlens provided in common to the first photoelectric conversion unit and the second photoelectric conversion unit.   The imaging unit according to claim 3, wherein the differential comparator is provided between the first photoelectric conversion unit and the second photoelectric conversion unit. The signal processing unit
The first digital signal, which is the result of comparing the signal level of the first photoelectric conversion unit and the reference level, and the result of comparing the signal level of the second photoelectric conversion unit and the reference level. The imaging unit according to any one of claims 3 to 9, further comprising a latch unit that is switched and inputted with two digital signals.   11. The imaging unit according to claim 1, wherein at least a part of the imaging unit and the signal processing unit are provided to overlap in the optical axis direction and are electrically connected to each other through a bump.   An imaging device comprising the imaging unit according to any one of claims 1 to 11.

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