JP2019153203A - Image forming apparatus - Google Patents

Abstract

To prevent, when an operation frequency of a clock signal of a SoC is lowered, an engine side from being operated and to allow the engine to be operated after the SoC is returned to its normal mode.SOLUTION: An engine control unit 1 has a dummy transfer control unit 15 for accessing a memory 3 to transfer a dummy data from the memory, a latency measuring unit 12 for measuring time of delay due to the transfer, and a SoC mode determining unit 13 for determining, based on the measured time of delay, whether an operating clock frequency is a normal operating clock frequency relating to a function module used in communication between a SoC 2 and the engine control unit 1 or an operating clock frequency which is lowered as compared with the normal operating clock frequency. If the SoC mode determining unit determines that the operating clock frequency of the function module is lowered, then the engine control unit continuously makes the dummy transfer control unit transferring the dummy data until the operating clock frequency becomes the normal one, and starts transfer of image data after the SoC is returned to its operation mode with the normal operating clock frequency.SELECTED DRAWING: Figure 1

Description

  The present invention relates to an image forming apparatus.

Conventionally, an image forming apparatus is provided with an engine control unit that controls various processes (image formation, paper conveyance, fixing, etc.) until image data received from a controller is printed on a recording medium.
In addition, SoC (System-on-a-chip) is generally adopted as the controller, and in addition to the functions of a general microcontroller such as a processor core on one chip of an integrated circuit, application Modules are designed so that the target functions are integrated and function as a system in cooperation.
Furthermore, in recent years, SoC has adopted a technology that automatically lowers the operating frequency of a module that is not operating and automatically returns to the normal frequency when the module is in use for the purpose of reducing power consumption. Has been.
Japanese Patent Application Laid-Open No. 2004-133620 discloses a technique for returning a memory controller from a power saving mode before a command to the memory controller reaches the memory controller.
When the target memory controller is in the power saving mode, it is known that the delay time until the response is returned, that is, the latency is increased with respect to commands and data received in the power saving mode. It has been.

Conventionally, a SoC that automatically switches the operation of a module to an energy saving mode is mounted on a multifunction peripheral (MFP) as a main controller of the controller.
In a conventional multi-function peripheral (MFP), if there is a data transfer request from the engine side during the energy saving mode, the latency increases until the normal frequency is returned from the energy saving mode, and the engine side There is a problem in that data transfer may not be completed by the timing requested by (1), and abnormal images may occur.
In addition, in the case of a SoC in which the frequency of the clock signal can be changed dynamically and dynamically in multiple stages for each module, it is difficult to detect from the outside that the frequency of the clock signal is in a lowered state. There was a problem that there was.
Patent Document 1 discloses that an object is returned from a power saving mode before the operation is started.
However, there is a problem that the SoC state cannot be clearly grasped from the outside.
One embodiment of the present invention has been made in view of the above, and its purpose is to return the SoC to the normal mode without operating the engine side when the operating frequency of the SoC clock signal is lowered. After that, it is to operate the engine.

  In order to solve the above-mentioned problem, the invention according to claim 1 includes at least one functional module whose operating frequency is switchable, and reduces the operating frequency when the functional module is in the energy-saving mode, and the energy-saving mode The SoC having a function of returning to the normal operating frequency after returning to the normal mode, the SoC connection memory connected to the SoC, the SoC connected to the SoC, and accessing the SoC connection memory An image forming apparatus comprising: a control unit that switches an operation mode of the functional module to an energy saving mode or a normal mode, wherein the control unit accesses the SoC connection memory and transfers dummy data from the SoC connection memory. A data transfer means and a delay for measuring a delay time related to the transfer by the dummy data transfer means; Based on the time measurement means and the delay time measured by the delay time measurement means, the normal operation frequency of the functional module used in the communication between the SoC and the control unit, or the normal operation frequency SoC mode determination means for determining whether the operating frequency is lower than the normal frequency, and when the control unit determines that the operating frequency of the functional module has decreased, the control unit normally The dummy data transfer means continues to transfer dummy data until the operating frequency reaches the normal operating frequency, and starts transferring image data after the SoC returns to the normal operating frequency.

  According to the present invention, when the operating frequency of the SoC clock signal is lowered, the engine can be operated after the SoC returns to the normal mode without operating the engine side.

FIG. 2 is a diagram illustrating a configuration of a controller and an engine of the image forming apparatus according to the first embodiment of the present invention. It is a figure explaining each structure of the latency measurement part shown in FIG. 1, an SoC mode determination part, and a latency threshold value. 3 is a timing chart showing an outline of a detection operation by a controller and an engine of the image forming apparatus according to the first embodiment of the present invention. 3 is a diagram illustrating a configuration of a dummy transfer control unit of the image forming apparatus according to the first embodiment of the present invention. FIG. 4 is a timing chart for explaining the operation of a command detection unit among the components of the dummy transfer control unit of the image forming apparatus according to the first embodiment of the present invention. It is a figure explaining the structure of the controller and engine of an image forming apparatus which concern on 2nd Embodiment of this invention.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings.
The present invention has the following configuration in order to operate the engine after the SoC returns to the normal mode without operating the engine side when the operating frequency of the SoC clock signal is lowered.
In other words, the image forming apparatus of the present invention includes at least one functional module whose operation frequency can be switched. When the functional module is in the energy saving mode, the operation frequency is reduced and the energy saving mode is returned to the normal mode. The SoC (system on chip) having the function of returning to the normal operating frequency, the SoC connection memory connected to the SoC, and the SoC connection memory connected to the SoC and accessing the SoC connection memory can change the operation mode of the functional module. An image forming apparatus comprising: a control unit that switches to an energy saving mode or a normal mode, wherein the control unit accesses a SoC connection memory and transfers dummy data from the SoC connection memory; and a dummy data transfer unit Delay time measuring means for measuring the delay time related to the transfer by the delay time, and delay time Based on the delay time measured by the measuring means, the SoC determines whether the operating frequency is a normal operating frequency related to the functional module used in the communication between the SoC and the control unit or the operating frequency is lower than the normal operating frequency. And when the SoC mode determination means determines that the operating frequency of the functional module is reduced, the control unit determines that the dummy data transfer means is set until the normal operating frequency is reached. The dummy data transfer is continuously executed, and image data transfer is started after the SoC returns to the normal operating frequency.
With the above configuration, when the operating frequency of the SoC clock signal is lowered, the engine can be operated after the SoC returns to the normal mode without operating the engine side.
The features of the present invention described above will be described in detail with reference to the following drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
Hereinafter, the features of the present invention will be described in detail with reference to the drawings.

<Image forming apparatus>
FIG. 1 is a diagram illustrating a configuration of a controller and an engine of the image forming apparatus according to the first embodiment of the present invention.
When the controller is in the normal mode, the SoC that is one of the components of the controller also needs to be in the normal mode.
However, in recent SoCs, in order to reduce power consumption as much as possible, fine power control may be possible for each module.
In the example shown in FIG. 1, when the controller and the engine are connected by PCI express and the packet transfer by PCI express is not executed, the Root module on the SoC side has a function of automatically reducing the operating frequency. ing.
SoC may not be considered as an energy saving mode when only the operating frequency of the Root module is lowered.
The return time from the occurrence of a PCI express packet to the return of the frequency to the normal state is also about several hundreds of us. In applications where real-time processing is not required, there is no effect due to the decrease in frequency.

However, when used when transferring image data in a multi-function peripheral device (MFP), real-time processing is required, and the above-described performance degradation during the period of several hundreds of us cannot be allowed.
Since the operation of lowering the operating frequency in the Root module is automatically executed unintentionally by hardware, even if the controller is in the normal mode (not in the energy saving mode), some functions of the SoC (FIG. 1). In the example shown in FIG. 5, Root 21) may be in a state corresponding to the energy saving mode.
When used when transferring image data in a multi-function peripheral device (MFP), it is necessary to execute image data transfer after the SoC 2 Root module returns to the normal mode. Therefore, the SoC 2 (Root) is required on the engine 10 side. ) Operation mode must be determined.
Conventionally, when the controller is in the normal mode, the SoC 2 is also in the normal mode. When the engine side is in the normal mode, the controller side is always in the normal mode (the SoC 2 is also in the normal mode). It was not necessary to determine the operation mode of SoC2.

For this reason, there has been a problem that the state of the SoC cannot be clearly understood from the outside.
Therefore, the present invention is to operate the engine after the SoC returns to the normal mode without operating the engine side when the operating frequency of the SoC clock signal is lowered.

<Engine control unit>
The engine control unit 1 constitutes a control unit and controls various processes (image formation, paper conveyance, fixing, etc.) until the image data received from the controller 20 is printed on a recording medium.
Endp 11 is a PCI express-Endpoint module, and is connected to Root 21 provided in the controller 20. The Endp 11 is connected to the bus 17 of the engine control unit 1, and mediates data transfer between the module connected to the bus 17 and the SoC 2 and the memory 3 provided in the controller 20.
The latency measuring unit 12 constitutes a delay time measuring unit, and measures the delay time until the dummy data transfer DMAC 16 reads an address in a certain area of the memory 3 and acquires data from the memory 3. Specifically, the delay time is a time from when a read command is input to Endp 11 until read data is output from Endp 11.
The measurement result measured by the latency measuring unit 12 is transferred to the SoC mode determining unit 13.
The measurement result of the delay time measured by the latency measuring unit 12 can also be confirmed by the CPU 22 and the CPU 113 via the bus 17.

The SoC mode determination unit 13 constitutes an SoC mode determination unit, and compares the delay time received from the latency measurement unit 12 with the time threshold acquired from the latency threshold 14. When the delay time is longer than the time threshold, the SoC mode determination unit 13 determines that at least a part of the functions of the SoC 2 has transitioned to the energy saving mode in which the operating frequency is in a lowered state or the like.
The SoC mode determination unit 13 determines that the SoC 2 is in the normal mode when the delay time is shorter than the time threshold. The SoC mode determination unit 13 notifies the interrupt controller 114 of an interrupt factor when the SoC 2 transitions to the normal mode or when the SoC 2 transitions to the energy saving mode. The determination result of the SoC mode determination unit 13 can be confirmed by the CPU 113 and the CPU 22 as necessary via the bus 17.
The threshold storage register 141 is a storage area for setting a delay time used for determining whether the SoC 2 is in the normal mode or the energy saving mode.

The dummy transfer control unit 15 constitutes a dummy data transfer means, and activates the dummy data transfer DMAC 16 when a desired command is detected among the controller-engine commands stored in the command buffer 19. .
For example, the dummy transfer control unit 15 uses an engine return notification command transferred from the engine 10 to the controller 20, a print start notification command transferred from the controller 20 to the engine 10, etc. The data is output to the transfer DMAC 16.

<Operation mode of dummy transfer control unit>
In the present embodiment, the dummy transfer control unit 15 includes the following four operation modes, and the operation modes can be switched from the CPU 22 or the CPU 113.
[1] The dummy transfer control unit 15 controls the dummy data transfer DMAC 16 so as to continue the dummy data transfer until the SoC 2 returns to the normal mode, and stops the dummy data transfer after the return to the normal mode. Control.
[2] The dummy transfer control unit 15 controls the dummy data transfer DMAC 16 so that the dummy data transfer is continued until the printing operation is completed even when the SoC 2 returns to the normal mode.
[3] The dummy transfer control unit 15 controls the dummy data transfer DMAC 16 so as to transfer dummy data only between the sheets (a period in which no image data transfer occurs) after the SoC 2 returns to the normal mode.
[4] The dummy transfer control unit 15 controls the DMAC 16 for dummy data transfer so as to continue transferring dummy data regardless of the SoC2 mode.
In the case of the operation modes [1], [2], and [3], the operation mode of SoC 2 is determined from the output result of the SoC mode determination unit 13.

The dummy transfer control unit 15 switches the setting of the band limiting unit 18.
In the case of the operation mode [1], a minimum bandwidth necessary for the SoC 2 to return is set.
In the case of the operation mode [2], the operation is performed with the same band setting as that of the operation mode [1] until the SoC2 returns to the normal mode, and the SoC2 maintains the normal mode after the SoC2 returns to the normal mode. It operates with the minimum bandwidth required.
When transferring image data for each line, when transferring data at certain time intervals (line cycle), after the data transfer is completed within the line cycle, until the next data transfer starts When this waiting time is long, there is a possibility that the specific function of SoC2 shifts to the energy saving mode.
By continuing the dummy data transfer during the image data transfer, it is possible to prevent the frequency of the Root 21 from being lowered even when the SoC 2 is designed to reduce the operating frequency of the Root 21 in a short time of about the line period. it can.

In the case of the operation mode [3], until the SoC 2 returns to the normal mode, it operates with the same band setting as the operation mode [1], detects the page start command, stops the transfer of dummy data, Dummy data transfer is resumed upon detection of the end command.
After the SoC 2 returns to the normal mode, the SoC 2 operates in the minimum band necessary for maintaining the normal mode.
Accordingly, even when the SoC 2 has a specification for reducing the operating frequency of the Root 21 in a time as short as the interval between sheets, it is possible to prevent the Root 21 frequency from being lowered.
In the case of the operation mode [4], the operation is performed with the same band setting as the band setting after returning to the normal mode in the operation mode [2].

In addition, the optimal value of each band shall be determined by prior evaluation.
In the case of the operation mode [4], as a method for changing each operation mode, switching is performed according to the setting contents of the three registers (152, 153, 154) shown in FIG.
The dummy data transfer DMAC 16 operates in response to an instruction from the dummy transfer control unit 15, and accesses the memory 3 via the bandwidth limiting unit 18, the bus 17, the Endp 11, the Root 21, and the bus 23.
The bus 17 relays data transferred from the master module (DMAC, CPU, etc.) to the slave module (memory, buffer, etc.), and arbitrates data transfer between the modules.
The transfer of image data has a high bus priority and the transfer of dummy data has a low bus priority. Therefore, even if the transfer of dummy data continues, the transfer of image data will not be delayed.
In this embodiment, it is assumed that the AXI protocol is used when transferring image data and latency measurement data, and the APB protocol is used when register access is performed.

The bandwidth limiter 18 limits the bandwidth by inserting a WAIT for every several commands with respect to the command output from the dummy data transfer DMAC 16.
The bandwidth is adjusted by the interval at which WAIT is inserted (the number of commands that can be issued continuously) and the WAIT time.
The command buffer 19 is used when exchanging commands between the engine 10 and the controller 20. At this time, when the transmitting side writes to the command buffer 19 and the receiving side reads from the command buffer 19, the command that has been read is deleted from the command buffer.

The image data transfer DMAC 110 reads the image data stored in the memory 3 via the bus 17, Endp 11, Root 21, and bus 23, and transfers the read data to the image processing unit 111.
The image data transfer DMAC 110 operates in accordance with an instruction from the CPU 113, and the CPU 113 operates as necessary (the operation mode of the above-described dummy transfer control unit is [1], [2], or [3]. ), The timing at which the notification is received from the interrupt controller 114 is used as a trigger signal.
When receiving the notification from the interrupt controller 114, the image data transfer DMAC 110 reads the determination result by the SoC mode determination unit 13, confirms that the SoC 2 has returned to the normal mode, and then activates the image data transfer DMAC 110. To do.
The image processing unit 111 performs image processing such as resolution conversion, enlargement / reduction, smoothing processing, dither processing, and the like, and transfers the image-processed data to the image output unit 112.
The image output unit 112 controls a device (laser, LED, inkjet head, etc.) that forms an image.
The CPU 113 executes setting / control of the image processing module, various motors, and various sensors.
The interrupt controller 114 receives interrupt signals from various modules, and transmits an interrupt notification to the SoC 2 via the Endp 11.
In the present embodiment, it is assumed that a masking function for interrupt factors is provided.

<Controller>
The controller 20 includes a SoC 2 and a memory 3, and the SoC 2 includes a Root 21, a CPU 22, and a bus 23.
The Root 21 is a PCI express-Root Complex module and is connected to the Endp 11. The Root 21 is connected to the SoC 2 bus 23 and mediates data transfer between the module connected to the bus 23, the engine 10 side, the CPU 22, and the memory 3.
The Root 21 is connected to the bus 23 and mediates data transfer between the modules connected to the bus 23, the CPU 22, and the memory 3. When a communication packet does not occur in PCI express during a certain time, the operating frequency of the Root 21 is lowered and power consumption is reduced.
The SoC 2 is responsible for main control of the image forming apparatus, and controls image data exchange with an external network, drawing processing, and the like.

When fine power control is possible and no communication packet is generated in PCI express during a certain time, the operating frequency of the Root 21 is lowered to reduce power consumption.
When the operating frequency of the Root 21 is lowered, the latency of data transfer via the Root 21 is increased. Therefore, the latency measuring unit 12 determines the operation mode of the SoC 2 by measuring the latency from when the read command is issued until the read data is received when the memory 3 is read from the dummy data transfer DMAC 16 on the engine side. can do.
In addition, since the Root 21 of the SoC 2 automatically returns to the normal operating frequency when a transfer packet is generated, it returns to the normal operating frequency by the packet generated by the dummy data transfer DMAC 16.
The CPU 22 manages main control of the image forming apparatus.
The bus 23 mediates data transfer between various modules inside the SoC 2. A number of modules (network control, storage control, etc.) are connected to the bus 23.

<Latency measurement unit, SoC mode determination unit, latency threshold>
FIG. 2 is a diagram illustrating the configuration of the latency measurement unit, the SoC mode determination unit, and the latency threshold illustrated in FIG.
The count trigger generation unit 121 monitors the AXI signal between the Endp 11 and the bus 17 and detects the transfer timing of the address / data used for the dummy transfer DMAC 16. Since the AXI protocol includes the ID of the module serving as the bus master, the address / data issued by the dummy transfer DMAC 16 can be detected by detecting the ID.
The count trigger generation unit 121 generates a count start trigger signal at the timing when the read address transfer (bus 17 → Endp11) is detected, and causes the counter 122 to start the count operation.
The count trigger generation unit 121 generates a count end trigger signal at the timing when the read data transfer (Endp11 → bus 17) is detected, and counts the value of the counter 122 at the count end trigger signal assert timing. Write to.

<Timing chart>
FIG. 3 is a timing chart showing an outline of the detection operation by the controller and engine of the image forming apparatus according to the first embodiment of the present invention.
The counter 122 starts counting from zero every time it receives a count start trigger signal from the count trigger generation unit 121. The maximum time (number of clocks) that can be counted by the counter 122 is sufficiently large with respect to the latency of SoC2, and when the count value becomes maximum, the count start trigger signal is asserted next. Hold up to the maximum value.
The count result storage register 123 stores the value of the counter 122 at the timing of counting end trigger signal assertion. The count result storage register 123 is connected to the bus 17 by the APB protocol and can be accessed from the SoC 2 or the CPU 113.

The threshold storage register (upper limit) 141 and the threshold storage register (lower limit) 142 are storage areas for setting a delay time used for determining whether the SoC 2 is in the normal mode or the energy saving mode.
The delay time when the SoC 2 is in the normal mode is measured in advance at the stage of evaluation before mass production of the image forming apparatus. Here, in the measurement, the dummy data transfer DMAC 16 continuously reads the area of the memory 3 for a sufficiently long time, and the SoC 2 has completed the return to the normal mode. This is performed by acquiring 12 measurement results, that is, the value of the count result storage register 123.

In the present embodiment, the first threshold value set in the threshold value storage register (upper limit) 141 is the longest time when measured a plurality of times, and the second threshold value set in the threshold value storage register (lower limit) 142 is measured a plurality of times. The shortest time.
Note that if the result of multiple measurements can be approximated to a normal distribution, the value “average value + standard deviation × 3” is set as the first threshold value as the setting value of the threshold value storage register (upper limit) 141, and the threshold value is stored. A value of “average value−standard deviation × 3” may be set as the second threshold value as the setting value of the register (lower limit) 142.
Here, the average value and the standard deviation may be calculated based on the delay time when measured by the latency measuring unit 12 a plurality of times.

When detecting a transition from the normal mode to the energy saving mode, the first threshold value of the threshold value storage register (upper limit) 141 is used for the determination. On the other hand, when the transition from the energy saving mode to the normal mode is detected, the second threshold value of the threshold value storage register (lower limit) 142 is used for the determination.
By properly using the upper limit first threshold value and the lower limit second threshold value, erroneous detection at the time of mode transition can be prevented.
The threshold storage register (upper limit) 141 and the threshold storage register (lower limit) 142 are connected to the bus 17 by the APB protocol and can be accessed from the SoC 2 or the CPU 113.
When only one of the transition from the normal mode to the energy saving mode and the transition from the energy saving mode to the normal mode is detected, only the corresponding threshold value storage registers may be used.
A configuration in which only one threshold value storage register is used and an average value is set as the threshold value is also conceivable. In this case, the value of the threshold value storage register may be directly input to the comparator 131 without using the selector 134.

The selector 134 selects and outputs the first threshold value of the threshold value storage register (upper limit) 141 and the second threshold value of the threshold value storage register (lower limit) 142.
When the value of the determination result storage register 132 indicates the energy saving mode, the second threshold value of the threshold value storage register (lower limit) 142 is output. When the value of the determination result storage register 132 indicates the normal mode, the threshold value is output. The first threshold value of the storage register (upper limit) 141 is output.
The comparator 131 compares the value of the count result storage register 123 with the output value of the selector 134. If the count result storage register value is larger, the value indicates the energy saving mode (= “0” in this embodiment). ) And the count result storage register value is smaller, a value indicating the normal mode (= “1” in the present embodiment) is output.

The determination result storage register 132 always stores the output value of the comparator 131 (for each operation clock).
Further, it is connected to the bus 17 by the APB protocol and can be accessed from the SoC 2 or the CPU 113.
The inversion detection unit 133 generates a pulse signal every time the value of the determination result storage register 132 changes, and this pulse signal is output to the interrupt controller 114 as an interrupt signal.
The SoC 2 that has detected the interrupt signal reads the value of the determination result storage register 132 via the bus 17 to determine whether it is the energy saving mode or the normal mode.

<Internal signal of latency measurement unit>
FIG. 3 is a timing chart for explaining the excerpt of the AXI signal related to the operation of the present embodiment and the operation of the internal signal of the latency measuring unit 12.
“arvalid” is a signal for controlling the read address (bus 17 → Endp11), and indicates that the output data (arid and arddr) of the bus 17 is valid when “1” at timing t31.
Arready is a read address control signal (Endp11 → bus 17), and when “1”, indicates that Endp11 can receive data (arid and arddr).
arid [7: 0] is a signal for determining the read address issuing module, and indicates the ID of the bus master module connected to the bus 17. In this embodiment, arid [7: 0] is an 8-bit signal, and the AXI-ID of the dummy data transfer DMAC 16 is “16”.
Araddr [31: 0] is a signal for designating a slave device storing read target data, and indicates an address value assigned to a slave module connected to the bus 17.

rvalid is a read data control signal (Endp11 → bus 17). When it is “1”, it indicates that the output data (rid, rdata, and rlast) of Endp11 is valid.
“ready” is a read data control signal (bus 17 → Endp11), and when “1” indicates that the bus 17 can receive data (rid, rdata, and rlast).
rid [7: 0] is a signal for determining the read data transfer destination module, and indicates the ID of the bus master module connected to the bus 17. In the present embodiment, rid [7: 0] is an 8-bit signal, and the AXI-ID of the dummy data transfer DMAC 16 is “16”.
rdata [127: 0] indicates data read from a specified address (specified by ardrdr).
rlast indicates the final data when the burst transfer is executed. In the present embodiment, rlast is assumed that the dummy data transfer DMAC 16 operates with the burst number “1”. The AXI protocol includes a signal that indicates the number of bursts. In the description of this embodiment, the description of the burst operation is omitted.

The count start trigger signal is asserted when all of the following three conditions are satisfied, as shown at timing t31.
・ Arvalid is asserted.
・ Arready is asserted.
The value of arid [7: 0] is “16”.

The count end trigger signal is asserted when all of the following four conditions are satisfied, as shown at timing t36.
• rvalid is asserted.
-Rready is asserted.
The value of rid [7: 0] is “16”.
• rlast is asserted.

As shown at timing t32, the counter 122 starts counting when the count start trigger signal is asserted (validated), and counts up at every rising edge of the operation clock signal. When the count value has advanced to the maximum countable value, the counter 122 maintains the maximum value until the next count start trigger signal is asserted.
The count result storage register 123 stores the count value when the count end trigger signal is asserted as shown at timing t36, and stores “N” in the example shown in FIG. 3 as shown at timing t37. The energy saving mode and the normal mode are discriminated by comparing the value of “N” with the set value of the latency threshold 14.

<Dummy transfer control unit>
FIG. 4 is a diagram illustrating the configuration of the dummy transfer control unit 15 of the image forming apparatus according to the first embodiment of the present invention.
The command detection unit 151 monitors the AXI signal between the bus 17 and the command buffer 19 and detects a command written by the SoC 2 in the command buffer 19.
When the detected command matches the return dummy transfer start trigger setting register 152, the command detection unit 151 asserts a return transfer start trigger signal.
When the detected command matches the maintenance dummy transfer start trigger setting register 153, the command detection unit 151 asserts a maintenance transfer start trigger signal.
If the detected command matches the dummy transfer stop trigger setting register 154, the command detection unit 151 asserts a transfer stop trigger signal.

In this embodiment, an engine return notification command is set in the return dummy transfer start timing setting register 152. (Common setting for modes [1] [2] [3] [4])
The return dummy transfer start timing setting register 152 is connected to the bus 17 by the APB protocol and can be accessed from the SoC 2 or the CPU 113.
In this embodiment, the maintenance dummy transfer start trigger setting register 153 has a command for notifying the start of printing for each job (in the case of mode [2]) or a command for notifying the start of printing for each page (mode [3]). ) Or zero (in the case of mode [4], a value for which no command is defined = “zero” in this embodiment).
The maintenance dummy transfer start timing setting register 153 is connected to the bus 17 by the APB protocol and is accessible from the SoC 2 or the CPU 113.

In this embodiment, in the dummy transfer stop timing setting register 154, a command for notifying the start of printing for each job (in the case of mode [1]) or a command for notifying the end of printing for each job (in the case of mode [2]). ) Or a command for notifying the end of printing for each page (in the case of mode [3]) or an engine energy saving mode transition command (in the case of mode [4]).
The dummy transfer stop timing setting register 154 is connected to the bus 17 by the APB protocol and is accessible from the SoC 2 or the CPU 113.
The transfer state determination unit 155 receives the return transfer start trigger signal, the maintenance transfer start trigger signal, and the transfer stop trigger signal, and whether the dummy data transfer DMAC 16 is in the return transfer state, the sustain transfer state, or the stop state. Is determined. Based on the output of the transfer state discriminating unit 155, it is selected whether the outputs of the selector 1510 and the selector 1511 are for restoration or for maintenance.

The return bandwidth setting register (the number of commands that can be issued continuously) 156 and the return bandwidth setting register (WAIT time) 158 set the minimum bandwidth required for the SoC 2 to return based on the results of measurement in advance. Both registers are connected to the bus 17 by the APB protocol and can be accessed from the SoC 2 or the CPU 113.
The maintenance bandwidth setting register (number of commands that can be issued continuously) 157 and the maintenance bandwidth setting register (WAIT time) 159 set the minimum bandwidth necessary for the SoC 2 to return based on the result of measurement in advance. Both registers are connected to the bus 17 by the APB protocol and can be accessed from the SoC 2 or the CPU 113.

The selector 1510 outputs the value of the return bandwidth setting register (the number of commands that can be continuously issued) 156 when the output of the transfer state determination unit 155 indicates that the return transfer is being performed, and the output of the transfer state determination unit 155 When the maintenance transfer is in progress, the value of the maintenance bandwidth setting register (number of commands that can be issued continuously) 157 is output.
The selector 1511 outputs the value of the return band setting register (WAIT time) 157 when the output of the transfer state determination unit 155 indicates that a return transfer is being performed, and the output of the transfer state determination unit 155 indicates that the transfer is being maintained. Is output, the value of the maintenance band setting register (WAIT time) 159 is output.

When the OR logic 1512 detects the assertion of the return transfer start trigger signal or the assertion of the maintenance transfer start trigger signal, the OR logic 1512 generates a transfer start signal of the dummy data transfer DMAC 16.
The dummy data transfer DMAC 16 starts operating when it detects a transfer start signal output from the OR logic 1512 and stops operating when it detects a transfer stop signal (= transfer stop trigger) output from the command detection unit 151.

<Command detector>
FIG. 5 is a timing chart for explaining the operation of the command detection unit 151 among the components of the dummy transfer control unit 15 of the image forming apparatus according to the first embodiment of the present invention.
wvalid is a write data control signal (bus 17 → command buffer 19), and as shown at timing t51, the output data (wid, wdata, and wlast) of the bus 17 is valid when it is “1”. It shows that.

“ready” is a write data control signal (command buffer 19 → bus 17). When “1”, the command buffer 19 can receive data (wid, wdata, and wlast).
wid [7: 0] is a signal for determining the transfer destination module of the write data, and indicates the ID of the bus master module connected to the bus 17. In the present embodiment, it is assumed that wid [7: 0] is an 8-bit signal and the AXI-ID of Endp11 is “11”. In this embodiment, since SoC2 access passes through Endp11, when detecting SoC2 access, the ID of Endp11 may be detected.

wdata [31: 0] indicates data to be written to a specified address (specified by waddr).
“wlast” indicates the final data when the burst transfer is executed. In the present embodiment, it is assumed that the number of bursts is “1” when writing to the command buffer. A signal indicating the number of bursts exists in the AXI protocol. In the description of this embodiment, the description of the burst operation is omitted.
The command issued by SoC2 is the value of wdata [31: 0] when all of the following four conditions are satisfied.
-Wvalid is asserted.
-Ready is asserted.
The value of wid [7: 0] is “11”.
• wlast is asserted.
A desired command can be detected by comparing the value of wdata [31: 0] when the above four conditions are satisfied with the values of the registers 152, 153, and 154.

Second Embodiment
FIG. 6 is a diagram illustrating the configuration of the controller and engine of the image forming apparatus according to the second embodiment of the present invention.
With reference to FIG. 6, a simple configuration for preventing the start of image data transfer when a part of the SoC is in the energy saving mode will be described.
6 does not include the latency measurement unit 12, the SoC mode determination unit 13, the latency threshold value 14, and the dummy transfer control unit 15 illustrated in FIG.
In the second embodiment, by operating the dummy data transfer DMAC 16 at all times, the Root 21 in the SoC 2 can be prevented from shifting to the energy saving mode with a simple configuration.
Thereby, the dummy transfer control unit 15 can continue to transfer dummy data from the memory 3 at all times.

<Summary of Actions and Effects of Aspect Examples of this Embodiment>
<First aspect>
The image forming apparatus according to this aspect includes at least one functional module whose operating frequency can be switched. When the functional module is in the energy saving mode, the operating frequency is lowered, and after returning from the energy saving mode to the normal mode, the normal time is reached. Engine control unit that switches the operation mode of the functional module to the energy-saving mode or the normal mode by accessing the memory 3 connected to the SoC 2 and the memory 3 connected to the SoC 2 The engine control unit 1 accesses the memory 3 to transfer dummy data from the memory 3 and a delay time related to transfer by the dummy transfer control unit 15. The latency measuring unit 12 that measures the delay time and the delay time measured by the latency measuring unit 12 Accordingly, the SoC mode determination unit 13 that determines whether the operation frequency is a normal operation frequency related to the functional module used in the communication between the SoC 2 and the engine control unit 1 or is lower than the normal operation frequency. When the SoC mode determination unit 13 determines that the operating frequency of the functional module has decreased, the engine control unit 1 causes the dummy transfer control unit 15 to execute dummy data until the normal operating frequency is reached. The transfer of the image data is continuously executed, and the transfer of the image data is started after the SoC 2 returns to the normal operating frequency.
According to this aspect, when the SoC mode determination unit 13 determines that the operating frequency of the functional module has decreased, the engine control unit 1 performs the dummy transfer control unit until the normal operating frequency is reached. 15 continuously executes the transfer of the dummy data, and starts the transfer of the image data after the SoC 2 returns to the normal operating frequency.
Thereby, when the operating frequency of the clock signal of the SoC is lowered, the engine can be operated after the SoC returns to the normal mode without operating the engine side.

<Second aspect>
The SoC mode determination unit 13 of this aspect includes a first threshold value used for determination when transitioning from the normal mode to the energy saving mode, and a second threshold value used for determination when transitioning from the energy saving mode to the normal mode. To do.
According to this aspect, the SoC mode determination unit 13 includes the first threshold value used for determination when transitioning from the normal mode to the energy saving mode, and the second threshold value used for determination when transitioning from the energy saving mode to the normal mode. In addition, it is possible to suppress a determination error between the normal mode and the energy saving mode.

<Third aspect>
The dummy transfer control unit 15 of this aspect is characterized by designating an address corresponding to a certain area of the memory 3 and reading data from the memory 3.
According to this aspect, the dummy transfer control unit 15 reads the data from the memory 3 by designating an address corresponding to a certain area of the memory 3, so that the dummy transfer control unit 15 continuously executes the transfer of the dummy data. can do.

<4th aspect>
The dummy transfer control unit 15 according to this aspect is characterized in that the engine control unit 1 operates at a timing when the engine control unit 1 returns to the normal mode.
According to this aspect, the dummy transfer control unit 15 operates at the timing when the engine control unit 1 returns to the normal mode, so that, for example, the dummy transfer control unit 15 starts transferring dummy data with sufficient timing before starting printing. can do.

<5th aspect>
The dummy transfer control unit 15 of this aspect operates at a timing before starting a printing operation.
According to this aspect, since the dummy transfer control unit 15 operates at the timing before starting the printing operation, the dummy transfer control unit 15 starts transferring dummy data at the timing immediately before the start of printing. And band consumption can be suppressed.

<Sixth aspect>
The image forming apparatus according to this aspect is characterized in that the dummy transfer control unit 15 continues to transfer the dummy data at a constant time interval even after the SoC 2 operates at the normal operating frequency.
According to this aspect, the image forming apparatus allows the dummy transfer control unit 15 to continue transferring dummy data at a constant time interval even after the SoC 2 starts operating at a normal operating frequency. It is possible to prevent the SoC 2 from transitioning to the energy saving mode between the papers or during the transfer waiting time within the line cycle.

<Seventh aspect>
The image forming apparatus according to this aspect is characterized in that the fixed time interval during which the dummy transfer control unit 15 operates is shorter than the idle time between pages.
According to this aspect, in the image forming apparatus, the fixed time interval in which the dummy transfer control unit 15 operates is shorter than the idle time between pages, so that the SoC 2 enters the energy saving mode during the waiting time between sheets. It is possible to prevent transition.

<Eighth aspect>
The image forming apparatus according to this aspect is characterized in that the fixed time interval in which the dummy transfer control unit 15 operates is shorter than the transfer waiting time within the line period.
According to this aspect, in the image forming apparatus, the fixed time interval in which the dummy transfer control unit 15 operates is shorter than the transfer waiting time in the line cycle, so that the SoC2 Can be prevented from shifting to the energy saving mode.

<Ninth aspect>
The image forming apparatus according to this aspect includes at least one functional module whose operating frequency can be switched. When the functional module is in the energy saving mode, the operating frequency is lowered, and after returning from the energy saving mode to the normal mode, the normal time is reached. SoC2 (system on chip) having a function of returning to the operating frequency of the above, a memory 3 connected to the SoC2, and a connection to the SoC2 to access the memory 3, thereby changing the operation mode of the functional module to the energy saving mode or the normal mode. The engine control unit 1 includes a dummy transfer control unit 15 that accesses the memory 3 and transfers dummy data from the memory 3, and the dummy transfer control unit 15. Is characterized in that the transfer of dummy data from the memory 3 is always continued.
According to this aspect, the engine control unit 1 includes the dummy transfer control unit 15 that accesses the memory 3 and transfers dummy data from the memory 3, and the dummy transfer control unit 15 always transfers dummy data from the memory 3. Continue.
Thereby, the dummy transfer control unit 15 can continue to transfer dummy data from the memory 3 at all times.

DESCRIPTION OF SYMBOLS 1 ... Engine control part, 2 ... SoC, 3 ... Memory, 10 ... Engine, 11 ... Endp, 110 ... DMAC for image data transfer, 111 ... Image processing part, 112 ... Image output part, 113 ... CPU, 114 ... Controller, DESCRIPTION OF SYMBOLS 12 ... Latency measurement part, 121 ... Count opportunity generation part, 122 ... Counter, 123 ... Count result storage register, 127 ... Rdata, 131 ... Comparator, 132 ... Determination result storage register, 133 ... Inversion detection part, 134 ... Selector, 14 ... Latency threshold, 141 ... Threshold storage register, 15 ... Dummy transfer control unit, 151 ... Command detection unit, 1510 ... Selector, 1511 ... Selector, 1512 ... OR logic, 152 ... Register, 152 ... Return dummy transfer start trigger setting Register, 153... Maintenance dummy transfer start timing setting register, 15 ... Dummy transfer stop timing setting register, 155 ... Transfer state determination unit, 16 ... Dummy data transfer DMAC, 16 ... Dummy transfer DMAC, 17 ... Bus, 18 ... Band limiter, 19 ... Command buffer, 20 ... Controller, 21 ... Root, 22 ... CPU, 23 ... Bus

JP 2011-090613 A

Claims (9)

A function comprising at least one functional module whose operating frequency can be switched, a function of reducing the operating frequency when the functional module is in the energy saving mode, and returning to the normal operating frequency after returning from the energy saving mode to the normal mode. SoC with
A SoC connection memory connected to the SoC;
A control unit connected to the SoC and switching the operation mode of the functional module to an energy saving mode or a normal mode by accessing the SoC connection memory,
The controller is
Dummy data transfer means for accessing the SoC connection memory and transferring dummy data from the SoC connection memory;
A delay time measuring means for measuring a delay time related to the transfer by the dummy data transfer means;
Based on the delay time measured by the delay time measuring means, the normal operation frequency of the functional module used in the communication between the SoC and the control unit or an operation lower than the normal operation frequency SoC mode determination means for determining whether the frequency,
The controller is
If the SoC mode determination means determines that the operating frequency of the functional module is decreasing, the dummy data transfer means continues to transfer dummy data until the normal operating frequency is reached. The image forming apparatus starts transfer of image data after the SoC returns to a normal operating frequency.   The SoC mode determination means includes a first threshold value used for determination when transitioning from the normal mode to the energy saving mode, and a second threshold value used for determination when transitioning from the energy saving mode to the normal mode. The image forming apparatus according to 1.   2. The image forming apparatus according to claim 1, wherein the dummy data transfer unit reads data from the SoC connection memory by designating an address corresponding to a certain area of the SoC connection memory.   The image forming apparatus according to claim 1, wherein the dummy data transfer unit operates at a timing when the control unit returns to a normal mode.   The image forming apparatus according to claim 1, wherein the dummy data transfer unit operates at a timing before starting a printing operation.   5. The image according to claim 3, wherein the dummy data transfer unit continues to transfer dummy data at a constant time interval even after the SoC starts operating at a normal operating frequency. Forming equipment.   6. The image forming apparatus according to claim 5, wherein the predetermined time interval during which the dummy data transfer unit operates is shorter than a free time between pages.   6. The image forming apparatus according to claim 5, wherein the fixed time interval during which the dummy data transfer unit operates is shorter than a transfer waiting time within a line cycle. A function comprising at least one functional module whose operating frequency can be switched, a function of reducing the operating frequency when the functional module is in the energy saving mode, and returning to the normal operating frequency after returning from the energy saving mode to the normal mode. SoC with
A SoC connection memory connected to the SoC;
A control unit connected to the SoC and switching the operation mode of the functional module to an energy saving mode or a normal mode by accessing the SoC connection memory,
The controller is
Dummy data transfer means for accessing the SoC connection memory and transferring dummy data from the SoC connection memory;
The image forming apparatus, wherein the dummy data transfer means continues to transfer dummy data from the SoC connection memory at all times.

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