JP2006099643A - Page printer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a page printer gaining appropriate control of timing with which an operating frequency of a mounted CPU is changed. <P>SOLUTION: A control unit 10c switches an operating frequency of a CPU 11 to a higher operating frequency when the state where an access request signal outputted from the CPU 11 to a RAM 15 per unit hour exceeds a first threshold continues for a first upper limit period of time or more, and/or the state where an access request signal outputted from an IO controller 14 to the RAM 15 per unit hour exceeds a second threshold, continues for a third upper limit period of time or more. The control unit 10c switches the operating frequency of the CPU 11 to a lower frequency when the state where the access request signal outputted from the CPU 11 to the RAM 15 per unit hour does not exceed the first threshold continues for a second upper limit period of time or more, and the state where the access request signal outputted from the IO controller 14 to the RAM 15 does not exceed the second threshold, continue for a fourth upper limit period of time or more. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a page printer.

  In recent years, with the increase in CPU speed, an increase in power consumption of the CPU and an accompanying increase in the amount of heat generation have become problems. As is well known, the power consumption of the CPU generally increases in proportion to the operating frequency and increases in proportion to the square of the operating voltage. For this reason, some high-speed CPUs have a function of changing the operating frequency and operating voltage in order to reduce power consumption as much as possible.

  Recently, high-speed CPUs having the functions described above are installed not only in computers but also in page printers that require high resolution, high image quality, and high processing speed. It has become.

  Some conventional page printers equipped with a CPU as described above switch this operation mode when the operation mode is changed from the normal mode to the power saving mode when there is no print request for a certain period of time. In some cases, the CPU operating voltage is switched to a voltage lower than usual.

  However, since it is difficult for this type of page printer to appropriately control the timing of changing the CPU operating frequency, the CPU operating frequency is changed in conjunction with the operation mode switching, and the operation mode switching is called. The operating frequency of the CPU was not changed at an independent timing.

  The present invention has been made in view of the above-described conventional circumstances, and an object thereof is to appropriately control the timing of changing the operating frequency of a CPU mounted on a page printer.

  A page printer according to a first aspect invented to solve the above problems is a CPU that operates by selectively using a high operating frequency and a low operating frequency, and transmits data from the host computer to the RAM. A page printer equipped with an IO controller that performs the above processing, a first request signal acquisition unit that acquires an access request signal output from the CPU to the RAM, and an access request acquired by the request signal acquisition unit per unit time A first access state determination unit that determines whether or not the number of signals exceeds a predetermined first threshold, and a time that the first access state determination unit determines that the number of times exceeds the first threshold Is stored in the storage unit when the predetermined first upper limit time is exceeded, and the first access is performed when the number of times does not exceed the first threshold. When the time determined by the state determination unit exceeds a predetermined second upper limit time, a CPU operation state determination unit that records information indicating a frequent state in the storage unit, and an access request signal that the IO controller outputs to the RAM A second request signal acquisition unit to acquire, a second access state determination unit to determine whether or not the number of access request signals acquired per unit time by the request signal acquisition unit exceeds a predetermined second threshold, and the number of times When the time that the second access state determination unit determines that exceeds the second threshold exceeds a predetermined third upper limit time, information indicating a frequent state is recorded in the storage unit, and the number of times is When the time that the second access state determination unit determines that it does not exceed the second threshold exceeds a predetermined fourth upper limit time, the IO controller operation that records information indicating a sparse state in the storage unit The information stored in the storage unit by the state determination unit and the CPU operation state determination unit is information indicating a sparse state, and the information stored in the storage unit by the IO controller operation state determination unit is information indicating a sparse state. In some cases, the CPU is operated at a low operating frequency, and in other cases, a CPU operation control unit that operates the CPU at a high operating frequency is provided.

  With this configuration, the state in which the access request signal output from the CPU to the RAM per unit time exceeds the first threshold continues for the first upper limit time and / or the unit from the IO controller to the RAM. When the state in which the access request signal output per time exceeds the second threshold continues for the third upper limit time or longer, the CPU operating frequency is switched to a higher operating frequency. Further, the state where the access request signal output from the CPU to the RAM per unit time does not exceed the first threshold continues for the second upper limit time and the access request output from the IO controller to the RAM per unit time. When the state where the signal does not exceed the second threshold value continues for the fourth upper limit time or longer, the operating frequency of the CPU is switched to a lower operating frequency. At this time, the CPU processing speed can be increased by selecting an optimal value for each of the first threshold value, the second threshold value, the first upper limit time, the second upper limit time, the third upper limit time, and the fourth upper limit time. The CPU operating frequency can be switched to a lower one only when it is not so necessary. As a result, the timing for changing the operating frequency of the CPU is appropriately controlled.

  A page printer according to a second aspect invented to solve the above-described problem is a page printer equipped with a CPU that operates by selectively using a high operating frequency and a low operating frequency. A request signal acquisition unit for acquiring an access request signal output by the CPU to the RAM, and an access for determining whether or not the number of access request signals acquired per unit time by the request signal acquisition unit exceeds a predetermined first threshold value. When the time that the access state determination unit determines that the number of times exceeds the first threshold exceeds a predetermined first upper limit time, the state determination unit records information indicating the frequent state in the storage unit, When the time that the access state determination unit determines that the number of times does not exceed the first threshold exceeds a predetermined second upper limit time, information indicating a sparse state is recorded in the storage unit Operating state determination unit, and when the information in the storage unit is in a frequent state, the CPU is operated at a high operating frequency, and when the information in the storage unit is in a sparse state, the CPU is set to a low operating frequency. It is characterized by having a CPU operation control unit that operates.

  With this configuration, when the state in which the access request signal output from the CPU to the RAM per unit time exceeds the first threshold continues for the first upper limit time or more, the CPU operates at a higher operating frequency. When the state where the access request signal output from the CPU to the RAM per unit time does not exceed the first threshold continues for the second upper limit time or longer, the CPU operating frequency is switched to a lower operating frequency. At this time, by appropriately selecting optimal values for each of the first threshold value, the first upper limit time, and the second upper limit time, the CPU operating frequency is switched to a lower one when the CPU processing speed is not necessary. Will be able to. As a result, the timing for changing the operating frequency of the CPU is appropriately controlled.

  A page printer according to a third aspect invented to solve the above problem is a CPU that operates by selectively using a high operating frequency and a low operating frequency, and data from a host computer is stored in a RAM. A page printer equipped with an IO controller that performs processing to be transmitted to a request signal acquisition unit that acquires an access request signal that the IO controller outputs to the RAM, and an access that the request signal acquisition unit acquires per unit time An access state determination unit that determines whether or not the number of request signals exceeds a predetermined second threshold; a time that the access state determination unit determines that the number of times exceeds the second threshold is predetermined When the third upper limit time is exceeded, information indicating a frequent state is recorded in the storage unit, and the access is performed when the number of times does not exceed the second threshold value. When the time determined by the state determination unit exceeds a predetermined fourth upper limit time, the operation state determination unit that records information indicating a sparse state in the storage unit, and the information in the storage unit is in a frequent state And a CPU operation control unit that operates the CPU at a low operating frequency when information in the storage unit is in a sparse state.

  With this configuration, when the state where the access request signal output from the IO controller to the RAM per unit time exceeds the second threshold continues for the third upper limit time or longer, the CPU operating frequency becomes high. When the state where the access request signal output per unit time from the IO controller to the RAM does not exceed the second threshold continues for the fourth upper limit time or longer, the CPU operating frequency is switched to a lower operating frequency. At this time, by appropriately selecting optimal values for each of the predetermined second threshold value, first upper limit time, and second upper limit time, the CPU operating frequency is lowered when the CPU processing speed is not so much required. And can be switched. As a result, the timing for changing the operating frequency of the CPU is appropriately controlled.

  As described above, according to the present invention, it is possible to appropriately control the timing for changing the operating frequency of the CPU mounted on the page printer.

  Hereinafter, four examples for carrying out the present invention will be described with reference to the accompanying drawings.

Embodiment 1

  FIG. 1 is a configuration diagram of a page printer 10 according to the first embodiment of the present invention. The page printer 10 includes a print engine 10a, an operation unit 10b, and a control unit 10c as main components.

  The print engine 10a is a mechanism that actually performs printing on paper. The operation unit 10b is a device that receives an operation by a user. The control unit 10c instructs a print control process for causing the print engine 10a to perform printing in accordance with print data transmitted from a host computer (not shown) and a process to be executed by the user through an operation on the operation unit 10b. It is a unit that performs processing to acquire.

  FIG. 2 is a configuration diagram of the control unit 10c. The control unit 10c includes a CPU 11, a CPU bus controller 12, a host IF 13, an IO controller 14, a RAM 15, a memory bus controller 16, a first state determination circuit 17, a second state determination circuit 18, and a CPU operation control circuit 19. ing.

  The CPU 11 is a unit that performs processing as the control unit 10c by comprehensively controlling each unit according to a program in a ROM (not shown). That is, the CPU 11 instructs a print control process for causing the print engine 10a to perform printing according to print data transmitted from a host computer (not shown) and a process to be executed by the user through an operation on the operation unit 10b. The process of acquiring is performed. The CPU 11 operates at either a normal maximum operating frequency or an operating frequency lower than the normal maximum operating frequency. Upon receiving an instruction from a CPU operation control circuit 19 described later, the CPU 11 responds to the instruction. It has a function to operate by switching to the operating frequency.

  The CPU bus controller 12 is a control circuit that outputs requests and data output from the CPU 11 to the memory bus controller 16 and delivers data output from the memory bus controller 16 to the CPU 11.

  The host IF 13 is an interface with a host computer (not shown). The IO controller 14 outputs a request and data output from the host IF 13, the operation unit 10 b and a ROM (not shown) to the memory bus controller 16, and outputs data output from the memory bus controller 16 to the host IF 13, the operation unit 10 b, This is a control circuit for transferring from a ROM (not shown). The IO controller 14 is also a circuit for controlling the host IF 13 and a ROM (not shown).

  The RAM 15 is a memory used for generating data to be supplied to the print engine 10a based on received print data. The RAM 12 is also a memory from which a program to be executed is read from a ROM (not shown).

  The memory bus controller 16 has a function of controlling the RAM 15, a process of storing print data in the RAM 15, and a function of executing a data transfer process of supplying data on the RAM 15 to the print engine 10a through an interface (not shown). It is a circuit having.

  The first state determination circuit 17 is a circuit that determines the operation state of the CPU 11 by counting the “CPU-RAM access request” signal output from the CPU bus controller 12 to the memory bus controller 16. The first state determination circuit 17 is connected to a command bus that connects the CPU bus controller 12 and the memory bus controller 16.

  The second state determination circuit 18 is a circuit that determines the operation state of the CPU 11 by counting the “IO-RAM access request” signal output from the IO controller 14 to the memory bus controller 16. The second state determination circuit 18 is connected to a command bus that connects the IO controller 14 and the memory bus controller 16.

  FIG. 3 is a configuration diagram of the first state determination circuit 17. The first state determination circuit 17 includes an A timer 171t, an A register 171r, a comparator 172, a B counter 173c, a B register 173r, a comparator 174, a C counter 175c, a C register 175r, a comparator 176, a D counter 177c, and a D register. 177r, a comparator 178, and an E register 179 are provided.

  The A timer 171t is a circuit that measures time by counting the number of rising edges of a pulse of an input clock signal. The A register 171r is a circuit that stores an upper limit value (that is, a time upper limit value) of the number of pulses (that is, measurement time) counted by the A timer 171t. The comparator 172 compares the number of pulses (measurement time) counted by the A timer 171t with the upper limit value (time upper limit value) in the A register 171r, and outputs the A signal when the pulse number reaches the upper limit value. This is a circuit that outputs only once to other circuits described later. Further, the comparator 172 outputs a reset signal to the A timer 171t simultaneously with outputting the A signal. When the A timer 171t receives the reset signal, the A timer 171t resets the counted number of pulses and restarts the time measurement from the beginning. Accordingly, the A timer 171t, the A register 171r, and the comparator 172 form a circuit group that repeatedly detects a point in time at which a predetermined time indicated by the above time upper limit value has elapsed.

  The B counter 173 c is a circuit that counts the number of times that the “CPU-RAM access request” signal (hereinafter abbreviated as “request signal”) is output from the CPU bus controller 12. The B counter 173c is connected to the comparator 172. When the B signal is received from the comparator 172, the B counter 173c resets the output count of the request signal that has been counted and counts the output count of this signal. Start over. The B register 173r is a circuit that stores a threshold value (corresponding to a first threshold value) of the number of output times of the request signal. The comparator 174 compares the number of output times of the request signal counted by the B counter 173c with the threshold value in the B register 173r. When the output number does not exceed the threshold value, the request signal is output within the upper limit time. A B-signal indicating that the number of times does not exceed the threshold value is output to another circuit described later, and when the number of output times exceeds the threshold value, the number of output times of the request signal within the upper limit time satisfies the threshold value. A B + signal indicating that the value has been exceeded is output to another circuit described later. When the comparator 174 switches from a B-signal output state (hereinafter referred to as “B-state”) to a B + signal output state (hereinafter referred to as “B + state”), A hold signal is output to the B counter 173c. When the B counter 173c receives the hold signal, the B counter 173c maintains the counted number without increasing it. However, when the B counter 173c receives the A signal from the comparator 172 in the hold state, the B counter 173c resets the maintained number of times. Accordingly, the B counter 173c, the B register 173r, and the comparator 174 repeatedly detect whether or not the number of output of the request signal per upper limit time exceeds the threshold (whether it is the B + state or the B− state). (Corresponding to a first access state determination unit).

  The C counter 175c is a circuit that counts the number of times the A signal is output from the comparator 172 in the B + state and does not count the number of output of the A signal in the B− state. Further, when the C counter 175c detects the B− state while counting the number of times of output of the A signal in the B + state (assuming that it is in the B− state when the A signal is output), the count value up to that time is detected. Is reset and waits until the B + state is reached. After the B + state is reached, the A signal output count in that state is counted again from the beginning. That is, the C counter 175c is a circuit that measures the continuous existence time of the B + state. The C register 175r is a circuit that stores a threshold value (corresponding to the first upper limit time) of the number of output of the A signal in the B + state (continuous existence time of the B + state). The comparator 176 is a circuit that compares the number of times counted by the C counter 175c with a threshold value in the C register 175r, and outputs a C signal when the number of A signal outputs in the B + state exceeds the threshold value. The comparator 176 outputs a hold signal to the C counter 175c at the same time as outputting the C signal. When receiving the hold signal, the C counter 175c maintains the counted number without increasing it. However, when the C counter 175c detects the B-state in the hold state, the C counter 175c resets the maintained number of times. Accordingly, the C counter 175c, the C register 175r, and the comparator 176 form a circuit group (corresponding to the CPU operation state determination unit) that outputs the C signal only while the continuous existence time of the B + state exceeds the first upper limit time. ing.

  The D counter 177c is a circuit having an operation opposite to that of the C counter 175c. That is, the D counter 177c is a circuit that counts the number of times the A signal is output from the comparator 172 in the B− state and does not count the number of output of the A signal in the B + state. Further, when the D counter 177c detects the B + state while counting the number of times of output of the A signal in the B− state (if it is in the B− state when the A signal is output), the D counter 177c calculates the count value up to that time. After resetting and waiting for the B-state, the number of A signal outputs in that state is counted again from the beginning. That is, the D counter 177c is a circuit that measures the continuous existence time of the B-state. The D register 177r is a circuit that stores a threshold value (corresponding to the second upper limit time) of the number of times of output of the A signal in the B-state (continuous existence time of the B-state). The comparator 178 is a circuit that compares the number counted by the D counter 177c with the threshold value in the D register 177r, and outputs the D signal when the number of times the A signal is output in the B-state exceeds the threshold value. is there. The comparator 178 outputs a D signal and simultaneously outputs a hold signal to the D counter 177c. When receiving the hold signal, the D counter 177c maintains the counted number without increasing it. However, when the D counter 177c detects the B + state in the hold state, the D counter 177c resets the maintained number of times. Accordingly, the D counter 177c, the D register 177r, and the comparator 178 include a circuit group (corresponding to the CPU operation state determination unit) that outputs the D signal only while the continuous existence time of the B-state exceeds the second upper limit time. It has become.

  The E register 179 includes information (for example, “1”) indicating the state in which the C signal is output from the comparator 176 (hereinafter referred to as “C state”, which corresponds to a frequent state), and the comparison This is a circuit for storing any information (for example, “0”) indicating the state in which the D signal is output from the device 178 (hereinafter referred to as “D state”, corresponding to a sparse state). When the E register 179 continues to store information indicating the D state and detects the C state when the A signal is output from the comparator 172, the E register 179 converts the stored information into the C state. The information is continuously stored until the D state is detected even after the C signal is not output. Further, when the E register 179 detects the D state when the A signal is output from the comparator 172 while the information indicating the C state is being stored, the E register 179 changes the stored information to the D state. The information is switched to the information shown, and the information is continuously stored until the C state is detected even after the D signal is not output. That is, the E register 179 detects whether the CPU 11 is frequently accessing the RAM 15 by detecting the C state or the D state determined based on the number of output of the request signal (storage unit). Equivalent).

  FIG. 4 is a configuration diagram of the second state determination circuit 18. As shown in FIG. 4, the second state determination circuit 18 includes an A timer 181t, an A register 181r, a comparator 182, a B counter 183c, a B register 183r, a comparator 184, a C counter 185c, a C register 185r, and a comparator. 186, a D counter 187c, a D register 187r, a comparator 188, and an E register 189.

  As apparent from comparison between FIG. 4 and FIG. 3, the second state determination circuit 18 has the same circuit configuration as the first state determination circuit 17. The second state determination circuit 18 has two differences in configuration. The first difference is that the first state determination circuit 17 uses the output count of the “CPU-RAM access request” signal to determine the operation state of the CPU 11, while the second state determination circuit 18 The number of times of output of the “IO-RAM access request” signal is used to determine the operation state of the IO controller 14. The second difference is that the threshold value stored in the B register 173r of the first state determination circuit 17, the threshold value stored in the C register 175r, and the threshold value stored in the D register 177r are “CPU-RAM access request”, respectively. Is optimized for the threshold value stored in the B register 183r of the second state determination circuit 18 (corresponding to the second threshold value), the threshold value stored in the C register 185r (corresponding to the third upper limit time), and , The threshold value (corresponding to the fourth upper limit time) stored in the D register 187r is optimized for the “IO-RAM access request”.

  With this configuration, the E register 189 of the second state determination circuit 18 detects the C state or the D state determined based on the number of times of output of the “IO-RAM access request” signal, so that the IO controller 14 is a circuit for storing whether or not the RAM 15 is frequently accessed.

  The CPU operation control circuit 19 switches the operating frequency of the CPU 11 based on the information stored in the E register 179 of the first state determination circuit 17 and the information stored in the E register 189 of the second state determination circuit 18. This is a circuit for instructing In the first embodiment, the CPU operation control circuit 19 is such that the information stored in the E register 179 of the first state determination circuit 17 is information indicating the D state and the E register 189 of the second state determination circuit 18. When the information stored in is information indicating the D state, the CPU 11 is instructed to operate at an operating frequency lower than normal (that is, in the low speed mode), and otherwise, the CPU 11 is instructed. On the other hand, it is instructed to operate at a normal operating frequency (that is, in a high-speed mode).

  With the configuration as described above, the page printer 10 of the first embodiment operates as described below.

  In this page printer 10, after the main power is turned on, the CPU operation control circuit 19 instructs the CPU 11 to operate at a normal operating frequency (that is, in the high speed mode), and the CPU 11 performs various initial settings. Then, the host IF 13 shifts to a state of waiting for a process for accepting print data from a host computer (not shown) and a process for accepting an operation by the operation unit 10b.

  In such a standby state, the CPU 11 and the IO controller 14 hardly issue a “CPU-RAM access request” signal or an “IO-RAM access request” signal, so the number of times the request signals are output within the predetermined time. Does not exceed the threshold value stored in the B registers 173r and 183r. If the B-state not exceeding the threshold value is maintained for a time longer than the time defined by the threshold value stored in the D registers 177r and 187r, the C signal is not output from the C registers 175r and 185r. The D signals are output from the D registers 177r and 187r, and the information in the E register 179 of the first state determination circuit 17 and the information in the E register 189 of the second state determination circuit 18 are both in the C state. The information indicating is switched to the information indicating the D state.

  Then, the CPU operation control circuit 19 instructs the CPU 11 to operate at an operation frequency lower than normal (that is, in the low speed mode). In response to this instruction, the CPU 11 operates at an operating frequency lower than normal. At this time, the amount of power consumed by the CPU 11 decreases, and as a result, the amount of heat generated by the CPU 11 also decreases.

  Further, when print data is sent from a host computer (not shown) while the CPU 11 is operating in the low speed mode, the IO controller 14 frequently outputs an “IO-RAM access request” signal. Thus, the number of times the request signal is output within the predetermined time exceeds the threshold stored in the B register 183r. If such a B + state exceeding the threshold is maintained for a time longer than the time defined by the threshold stored in the C register 185r, the D signal is not output from the D register 187r and the C signal is output from the C register 185r. Is output, and the information in the E register 189 of the second state determination circuit 18 is switched from information indicating the D state to information indicating the C state.

  Then, the CPU operation control circuit 19 detects that the information in the E register 189 of the second state determination circuit 18 has been switched to information indicating the D state, and makes the CPU 11 operate at a normal operating frequency (that is, the high-speed mode). Instruct) to work. In response to this instruction, the CPU 11 operates at a normal operating frequency. At this time, the CPU 11 can process print data and a program in a ROM (not shown) at a high speed at a normal processing speed (in a high-speed mode).

  Further, when the CPU 11 performs such print data processing or a program in a ROM (not shown), the CPU 11 frequently outputs a “CPU-RAM access request” signal. The number of outputs within a certain time exceeds the threshold stored in the B register 173r. When such a B + state exceeding the threshold is maintained for a time longer than the time defined by the threshold stored in the C register 175r, the D signal is not output from the D register 177r and the C signal is output from the C register 175r. Is output, and the information in the E register 179 of the first state determination circuit 17 is switched from information indicating the D state to information indicating the C state. However, even if the information in the E register 179 of the first state determination circuit 17 is switched to the information indicating the C state, the information in the E register 189 of the second state determination circuit 18 is switched to the information indicating the C state first. Therefore, the CPU operation control circuit 19 keeps the CPU 11 operating at the normal operating frequency (that is, in the high speed mode).

  Further, when the print data is not sent from the host computer (not shown) while the CPU 11 is operating in the high speed mode, the IO controller 14 outputs almost an “IO-RAM access request” signal. The number of times the request signal is output within the predetermined time does not exceed the threshold stored in the B register 183r. If such a B-state that does not exceed the threshold is maintained for a time longer than the time defined by the threshold stored in the D register 187r, the C signal is not output from the C register 185r and the D register 187r is output. The D signal is output, and the information in the E register 189 of the second state determination circuit 18 is switched from the information indicating the C state to the information indicating the D state. However, even if the information in the E register 189 of the second state determination circuit 18 is switched to the information indicating the D state, the information in the E register 179 of the first state determination circuit 17 remains the information indicating the C state. Therefore, the CPU operation control circuit 19 keeps the CPU 11 operating at the normal operating frequency (that is, in the high speed mode).

  After that, when the CPU 11 finishes processing the print data and executes the program in the ROM (not shown) and enters the standby state as described above, the CPU 11 hardly outputs the “CPU-RAM access request” signal. The number of outputs within the predetermined time does not exceed the threshold stored in the B register 173r. If such a B-state that does not exceed the threshold is maintained for a time longer than the time defined by the threshold stored in the D register 177r, the C register 175r does not output the C signal and the D register 177r The D signal is output, and the information in the E register 179 of the first state determination circuit 17 is switched from the information indicating the C state to the information indicating the D state.

  At this time, both the information in the E register 179 of the first state determination circuit 17 and the information in the E register 189 of the second state determination circuit 18 are switched to information indicating the D state. 19 instructs the CPU 11 to operate at an operating frequency lower than normal (that is, in a low-speed mode). In response to this instruction, the CPU 11 again operates at an operating frequency lower than normal, and the power consumption and heat generation amount of the CPU 11 are reduced.

  In other words, the page printer 10 according to the first embodiment is configured so that the CPU 11 is lower than usual when the CPU 11 is in an operation state in which the RAM 15 is hardly accessed and the IO controller 14 is in an operation state in which the RAM 15 is hardly accessed. Operate at the operating frequency.

  Here, the threshold values stored in the B register 173r, C register 175r, and D register 177r of the first state determination circuit 17, and the B register 183r, C register 185r, and D register of the second state determination circuit 18, respectively. By appropriately selecting the threshold value stored in each of the 187r, the CPU 11 is operated in the high speed mode only during a period in which high speed processing such as processing of print data and execution of a program in a ROM (not shown) is necessary. During the period when the high-speed processing is unnecessary, the CPU 11 can be operated in the low-speed mode. As a result, the timing for changing the operating frequency of the CPU 11 is appropriately controlled. However, the first state determination circuit 17 and the second state determination circuit 18 shown in FIGS. 3 and 4 are small in scale, and even if the ASIC is designed and manufactured so that these circuits 17 and 18 are incorporated, the cost can be reduced. Little up.

Embodiment 2

  FIG. 5 is a configuration diagram of the control unit 10c in the page printer 10 according to the second embodiment. As is obvious from comparison between FIG. 5 and FIG. 2, the second embodiment is different from the first embodiment in that the CPU operation control circuit 19 includes a register 19a. The register 19a is a circuit that stores a flag indicating whether or not the CPU operation control circuit 19 permits execution of the operation frequency switching process of the CPU 11.

  The CPU operation control circuit 19 stores the E register 179 of the first state determination circuit 17 when the flag stored in the register 19a indicates that the CPU 11 is allowed to execute the operation frequency switching process. Based on the information and the information stored in the E register 189 of the second state determination circuit 18, the operating frequency of the CPU 11 is controlled as in the first embodiment. On the other hand, when the flag stored in the register 19a indicates that the CPU 11 is not permitted to execute the operation frequency switching process, the CPU operation control circuit 19 operates the CPU 11 at the normal operation frequency at all times. Let

  The flag stored in the register 19a is switched by an operation input to the operation unit 10b. That is, the user of the page printer 10 according to the second embodiment can select whether or not the operation frequency of the CPU 11 is automatically switched.

Embodiment 3

  FIG. 6 is a configuration diagram of the control unit 10c in the page printer 10 according to the third embodiment. As is clear from comparison between FIG. 6 and FIG. 2, the third embodiment is different from the first embodiment in that the second state determination circuit 18 is not provided. The CPU operation control circuit 19 of the third embodiment determines the operating frequency of the CPU 11 based on information stored in the E register 179 of the first state determination circuit 17. That is, when the information in the E register 179 of the first state determination circuit 17 is switched to information indicating the D state, the CPU operation control circuit 19 causes the CPU 11 to operate at a lower operating frequency than normal (that is, in the low speed mode). When the information in the E register 179 is switched to the information indicating the C state, the CPU 11 is operated at the normal operating frequency (that is, in the high speed mode). According to the page printer 10 of the third embodiment, since there is no second state determination circuit 18, there is no condition for determining the access state of the IO controller 14 to the RAM 15 compared to the first embodiment. Therefore, it is possible to avoid the cost of incorporating the second state determination circuit 18 into the ASIC.

Embodiment 4

  FIG. 7 is a configuration diagram of the control unit 10c in the page printer 10 of the fourth embodiment. As is clear from comparison between FIG. 7 and FIG. 2, the fourth embodiment is different from the first embodiment in that the first state determination circuit 17 is not provided. The CPU operation control circuit 19 of the fourth embodiment determines the operating frequency of the CPU 11 based on information stored in the E register 189 of the second state determination circuit 18. That is, when the information in the E register 189 of the second state determination circuit 18 is switched to information indicating the D state, the CPU operation control circuit 19 causes the CPU 11 to operate at a lower operating frequency than normal (that is, in the low speed mode). When the information in the E register 189 is switched to the information indicating the C state, the CPU 11 is operated at the normal operating frequency (that is, in the high speed mode). According to the page printer 10 of the fourth embodiment, since the first state determination circuit 17 is not provided, there is no condition for determining the access state of the CPU 11 to the RAM 15 as compared with the first embodiment. This eliminates the cost of incorporating the one-state determination circuit 17 into the ASIC.

  In the first to fourth embodiments described above, the CPU operation control circuit 19 has been described as instructing the CPU 11, but the present invention is not limited to this. For example, when switching of the operating frequency of the CPU 11 is controlled by software in a ROM (not shown), the CPU operation control circuit 19 may output an interrupt signal to this software.

  In the first to fourth embodiments described above, the CPU operation control circuit 19 has been described as determining the instruction to be sent to the CPU 11 by reading the information in the E registers 179 and 189 of the state determination circuits 17 and 18. It is not limited to this. For example, when switching of the operating frequency of the CPU 11 is controlled by software in a ROM (not shown), this software may read information in the E registers 179 and 189 instead of the CPU operation control circuit 19. Good. In this case, this software determines and switches the operating frequency of the CPU 11.

1 is a configuration diagram of a page printer according to a first embodiment of the present invention. Block diagram of page printer controller Configuration diagram of first state determination circuit of control unit Configuration diagram of second state determination circuit of control unit The block diagram of the control part of the 2nd Embodiment of this invention The block diagram of the control part of the 3rd Embodiment of this invention The block diagram of the control part of the 4th Embodiment of this invention

Explanation of symbols

10 page printer 10a print engine 10b operation unit 10c control unit 11 CPU
12 CPU bus controller 13 Host IF
14 IO controller 15 RAM
16 memory bus controller 17 first state determination circuit 171t A timer 173c B counter 175c C counter 177c D counter 179 E register 18 second state determination circuit 181t A timer 183c B counter 185c C counter 187c D counter 189 E register 19 CPU operation control Circuit 19a Register

Claims (4)

A page printer equipped with a CPU that operates by selectively using a high operating frequency and a low operating frequency, and an IO controller that performs processing for transmitting data from the host computer to the RAM,
A first request signal acquisition unit for acquiring an access request signal output from the CPU to the RAM;
A first access state determination unit that determines whether or not the number of access request signals acquired per unit time by the request signal acquisition unit exceeds a predetermined first threshold;
When the number of times that the first access state determination unit determines that the number of times exceeds the first threshold exceeds a predetermined first upper limit time, information indicating a frequent state is recorded in a storage unit, and the number of times CPU operation state determination unit that records information indicating a frequent state in the storage unit when the time that the first access state determination unit determines that is not greater than the first threshold exceeds a predetermined second upper limit time ,
A second request signal acquisition unit for acquiring an access request signal output from the IO controller to the RAM;
A second access state determination unit that determines whether or not the number of access request signals acquired by the request signal acquisition unit per unit time exceeds a predetermined second threshold;
When the time that the second access state determination unit determines that the number of times exceeds the second threshold exceeds a predetermined third upper limit time, information indicating a frequent state is recorded in a storage unit, and the number of times IO controller operation state in which information indicating a sparse state is recorded in the storage unit when the time that the second access state determination unit determines that the second access state determination unit does not exceed the second threshold exceeds a predetermined fourth upper limit time A determination unit, and
When the information stored in the storage unit by the CPU operation state determination unit is information indicating a sparse state, and the information stored in the storage unit by the IO controller operation state determination unit is information indicating a sparse state, the CPU A page printer comprising a CPU operation control unit that operates the CPU at a low operating frequency, and otherwise operates the CPU at a high operating frequency. The operation switching unit performs processing for rewriting information in the storage unit when the control permission is obtained from the user through the input device, and when the control permission is not obtained from the user, 2. The page printer according to claim 1, wherein information indicating a high operating frequency is stored in the storage unit. A page printer equipped with a CPU that operates by selectively using a high operating frequency and a low operating frequency,
A request signal acquisition unit for acquiring an access request signal output from the CPU to the RAM;
An access state determination unit that determines whether the number of access request signals acquired per unit time by the request signal acquisition unit exceeds a predetermined first threshold;
When the time that the access state determination unit determines that the number of times exceeds the first threshold exceeds a predetermined first upper limit time, information indicating a frequent state is recorded in a storage unit, and the number of times is An operation state determination unit that records information indicating a sparse state in the storage unit when the time that the access state determination unit determines that it does not exceed the first threshold exceeds a predetermined second upper limit time; and
A CPU operation control unit that operates the CPU at a high operating frequency when the information in the storage unit is in a frequent state, and operates the CPU at a low operating frequency when the information in the storage unit is in a sparse state. A page printer. A page printer equipped with a CPU that operates by selectively using a high operating frequency and a low operating frequency, and an IO controller that performs processing for transmitting data from the host computer to the RAM,
A request signal acquisition unit for acquiring an access request signal output from the IO controller to the RAM;
An access state determination unit that determines whether or not the number of access request signals acquired by the request signal acquisition unit per unit time exceeds a predetermined second threshold;
When the time that the access state determination unit determines that the number of times exceeds the second threshold exceeds a predetermined third upper limit time, information indicating a frequent state is recorded in a storage unit, and the number of times is An operation state determination unit that records information indicating a sparse state in the storage unit when the time that the access state determination unit determines that the second threshold value is not exceeded exceeds a predetermined fourth upper limit time; and
A CPU operation control unit that operates the CPU at a high operating frequency when the information in the storage unit is in a frequent state, and operates the CPU at a low operating frequency when the information in the storage unit is in a sparse state. A page printer.