JP2019145834A - Method for manufacturing multilayer ceramic capacitor - Google Patents

Abstract

To provide: a multilayer ceramic capacitor of which humidity resistance can be ensured even if a side margin part is made thin; and a method for manufacturing the multilayer ceramic capacitor.SOLUTION: A multilayer ceramic capacitor comprises a lamination part and a side margin part. The lamination part has: a plurality of ceramic layers stacked in a first direction; and a plurality of internal electrodes each disposed between the plurality of ceramic layers. The side margin part covers the lamination part from a second direction orthogonal to the first direction, of which porosity is 1% or less.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a multilayer ceramic capacitor having a side margin portion retrofitted and a method for manufacturing the same.

  In recent years, with the miniaturization and high performance of electronic devices, there has been an increasing demand for miniaturization and large capacity of multilayer ceramic capacitors used in electronic devices. In order to meet this demand, it is effective to increase the crossing area of the internal electrodes of the multilayer ceramic capacitor as much as possible.

  For example, Patent Documents 1 and 2 describe a method in which a side margin portion for ensuring insulation around the internal electrode is formed later on a laminated chip with the internal electrode exposed on the side surface. As a result, the side margin portion can be made thin, and the crossing area of the internal electrodes can be made relatively large.

JP 2012-191159 A JP 2014-204116 A

  However, in the method in which the side margin portion is retrofitted to the side surface of the multilayer chip, when the side margin portion is thin, moisture or the like easily enters the multilayer chip from the outside through the thin side margin portion. For this reason, there exists a possibility that the moisture resistance of a multilayer ceramic capacitor may fall.

  In view of the circumstances as described above, an object of the present invention is to provide a multilayer ceramic capacitor in which moisture resistance is ensured even when the thickness of the side margin portion is reduced, and a method for manufacturing the same.

In order to achieve the above object, a multilayer ceramic capacitor according to an embodiment of the present invention includes a multilayer portion and a side margin portion.
The stacked unit includes a plurality of ceramic layers stacked in a first direction, and a plurality of internal electrodes arranged between the plurality of ceramic layers.
The side margin portion covers the stacked portion from a second direction orthogonal to the first direction and has a pore ratio of 1% or less.

According to this configuration, the pore ratio of the side margin portion is 1% or less. Thereby, since the density of the side margin portion is high, even if the thickness of the side margin portion is reduced, it becomes difficult for moisture or the like to enter the laminated portion from the outside through the side margin portion.
Therefore, according to the present invention, it is possible to manufacture a multilayer ceramic capacitor in which moisture resistance is ensured even if the thickness of the side margin portion is reduced.

The side margin portion may have a dimension in the second direction of 5 μm or more.
Thereby, the moisture resistance of the multilayer ceramic capacitor can be further improved.

The plurality of internal electrodes may have an oxidized region adjacent to the side margin portion and having a dimension in the second direction of 0.4 μm or more.
By setting the size of the oxidized region in the second direction to 0.4 μm or more, it is possible to suppress short-circuit failure between the internal electrodes and IR failure in the multilayer ceramic capacitor.

The side margin portion may have a dimension in the second direction of 15 μm or less.
Thereby, the moisture resistance of the multilayer ceramic capacitor is ensured.

The side margin portion may have a dimension in the second direction of 10 μm or less.
Thereby, it is possible to detect whether or not the side margin portion is peeled from the laminated portion without destroying the laminated ceramic capacitor by using an optical microscope or the like.

  The laminated part may include a cover part having a dimension in the first direction equal to or larger than a dimension in the second direction of the side margin part.

  This makes it difficult for moisture and the like to enter the multilayer portion from the outside, and suppresses a decrease in moisture resistance of the multilayer ceramic capacitor.

A method for manufacturing a multilayer ceramic capacitor according to an aspect of the present invention includes a plurality of ceramic layers stacked in a first direction, and a capacitor forming unit including a plurality of internal electrodes disposed between the plurality of ceramic layers. A non-fired laminated chip made of insulating ceramics and having a cover portion covering the capacitance forming portion from the first direction,
By covering the laminated chip from a second direction orthogonal to the first direction at a side margin portion made of insulating ceramic, an unfired element body is produced,
By firing the unfired element body, an element body having a pore ratio of 1% or less in the side margin after firing is produced.
For example, in the method for manufacturing the multilayer ceramic capacitor, a plurality of ceramic sheets laminated in the first direction are formed by laminating and pressing a plurality of ceramic sheets on which unfired internal electrodes are formed in the first direction. And a capacitor forming part having the plurality of internal electrodes arranged between the plurality of ceramic layers, an unfired cover part made of insulating ceramics and covering the capacitor forming part from the first direction; In order to obtain a plurality of unfired laminated chips each having an unfired laminated sheet,
By cutting the unfired laminated sheet, the unfired laminated chip is produced,
By covering the laminated chip from a second direction orthogonal to the first direction with an unfired side margin made of insulating ceramic, an unfired element body is produced,
Hydrostatic pressure is applied to the green body,
By firing the unfired element body that has been subjected to hydrostatic pressure, an element body having a pore ratio of 1% or less in the side margin after firing is produced.

  According to the manufacturing method, the pore ratio of the side margin after firing is 1% or less. Thereby, since the denseness of the side margin part after baking is high, even if the thickness of the side margin part is reduced, it becomes difficult for moisture or the like to enter the capacitance forming part from the outside through the side margin part. Therefore, even if the thickness of the side margin portion is reduced by the above manufacturing method, it is possible to manufacture a multilayer ceramic capacitor in which moisture resistance is ensured.

The dimension of the cover part in the first direction may be greater than or equal to the dimension of the side margin part in the second direction.
This makes it difficult for moisture and the like to enter the multilayer chip from the outside, and suppresses a decrease in moisture resistance of the multilayer ceramic capacitor.

  The side margin portion may have a dimension in the second direction of 20 μm or less.

This facilitates the supply of oxygen to the internal electrode through the side margin when firing the unfired element body, and an oxidized region is favorably formed at the end of the internal electrode.
Therefore, even if foreign matter or the like adheres to the side surface of the laminated chip where the end portion of the internal electrode is exposed in the manufacturing process, conduction between the internal electrodes through the foreign matter or the like on the side surface of the element body after firing is suppressed. Therefore, short-circuit failure between internal electrodes, IR failure, and the like are effectively suppressed.

  The laminated chip may cover the unfired element body with the side margin portion by punching a side margin sheet whose main component is an insulating ceramic.

  Hydrostatic pressure may be applied to the green body.

Binder removal treatment is applied to the green body.
Ceramics may be deposited on the side margin portion subjected to the binder removal treatment.

  Ceramic powder may be sprayed onto the side margin portion that has been subjected to the binder removal treatment.

  Ceramics may be sputtered on the side margin portion that has been subjected to the binder removal treatment.

  Ceramics may be vacuum-deposited on the side margin portion that has been subjected to binder removal processing.

  Even if the thickness of the side margin portion is reduced, it is possible to provide a multilayer ceramic capacitor in which moisture resistance is ensured and a method for manufacturing the same.

1 is a perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention. It is sectional drawing along the AA 'line of FIG. 1 of the said multilayer ceramic capacitor. It is sectional drawing along the BB 'line | wire of FIG. 1 of the said multilayer ceramic capacitor. FIG. 4 is an enlarged schematic view showing a region P of FIG. 3 of the multilayer ceramic capacitor. It is a flowchart which shows the manufacturing method of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a top view which shows the manufacturing process of the said multilayer ceramic capacitor. It is sectional drawing which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a schematic diagram which shows the manufacturing process of the said multilayer ceramic capacitor. It is a schematic diagram which shows the manufacturing process of the said multilayer ceramic capacitor. It is a schematic diagram which shows the manufacturing process of the said multilayer ceramic capacitor. It is a perspective view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a side view of the base body of the conventional multilayer ceramic capacitor. It is an expanded sectional view which shows the manufacturing process of the said multilayer ceramic capacitor. It is a graph which shows the evaluation result of the multilayer ceramic capacitor which concerns on the Example of this invention. It is a graph which shows the evaluation result of the said multilayer ceramic capacitor.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
In the drawing, an X axis, a Y axis, and a Z axis that are orthogonal to each other are shown as appropriate. The X axis, Y axis, and Z axis are common in all drawings.

[Overall Configuration of Multilayer Ceramic Capacitor 10]
1 to 3 are views showing a multilayer ceramic capacitor 10 according to an embodiment of the present invention. FIG. 1 is a perspective view of a multilayer ceramic capacitor 10. 2 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along the line AA ′ of FIG. 3 is a cross-sectional view of the multilayer ceramic capacitor 10 taken along line BB ′ of FIG.

The multilayer ceramic capacitor 10 includes an element body 11, a first external electrode 14, and a second external electrode 15.
The element body 11 typically has two side surfaces facing the Y-axis direction and two main surfaces facing the Z-axis direction. The ridges connecting the surfaces of the element body 11 are chamfered. The shape of the element body 11 is not limited to such a shape. For example, each surface of the element body 11 may be a curved surface, and the element body 11 may have a rounded shape as a whole.
The first and second external electrodes 14 and 15 cover the both end surfaces in the X-axis direction of the element body 11 and extend to four surfaces connected to the both end surfaces in the X-axis direction. Thereby, in any of the first and second external electrodes 14 and 15, the shape of the cross section parallel to the XZ plane and the cross section parallel to the XY axis is U-shaped.

The element body 11 includes a stacked portion 16 and a side margin portion 17.
The stacked unit 16 has a configuration in which a plurality of flat ceramic layers extending along the XY plane are stacked in the Z-axis direction.

The stacked unit 16 includes a capacitance forming unit 18 and a cover unit 19.
The capacitance forming unit 18 includes a plurality of first internal electrodes 12 and a plurality of second internal electrodes 13. The first and second internal electrodes 12, 13 are alternately arranged between the plurality of ceramic layers along the Z-axis direction. The first internal electrode 12 is connected to the first external electrode 14 and insulated from the second external electrode 15. The second internal electrode 13 is connected to the second external electrode 15 and insulated from the first external electrode 14.

  The first and second internal electrodes 12 and 13 are each made of a conductive material and function as internal electrodes of the multilayer ceramic capacitor 10. As the conductive material, for example, a metal material containing nickel (Ni), copper (Cu), palladium (Pd), platinum (Pt), silver (Ag), gold (Au), or an alloy thereof is used. Typically, a metal material mainly composed of nickel (Ni) is employed.

The capacity forming part 18 is formed of ceramics. In the capacitance forming portion 18, a high dielectric constant material is used as a material constituting the ceramic layer in order to increase the capacitance of each ceramic layer between the first internal electrode 12 and the second internal electrode 13. As a material constituting the capacitance forming portion 18, for example, a polycrystal of barium titanate (BaTiO ₃ ) -based material, that is, a perovskite structure polycrystal including barium (Ba) and titanium (Ti) can be used. .

In addition to the barium titanate (BaTiO ₃ ) system, the material forming the capacitance forming unit 18 is not limited to the strontium titanate (SrTiO ₃ ) system, the calcium titanate (CaTiO ₃ ) system, and the magnesium titanate (MgTiO ₃ ) system. A polycrystal such as calcium zirconate (CaZrO ₃ ), calcium zirconate titanate (Ca (Zr, Ti) O ₃ ), barium zirconate (BaZrO ₃ ) or titanium oxide (TiO ₂ ) There may be.

  The cover portion 19 has a flat plate shape extending along the XY plane, and covers the upper and lower surfaces of the capacitance forming portion 18 in the Z-axis direction. The cover portion 19 is not provided with the first and second internal electrodes 12 and 13.

  As shown in FIG. 3, the side margin portion 17 is formed on both side surfaces S <b> 1 and S <b> 2 of the capacitance forming portion 18 and the cover portion 19 facing the Y-axis direction.

  As described above, in the element body 11, the surfaces other than the both end surfaces in the X-axis direction where the first and second external electrodes 14 and 15 of the capacitance forming portion 18 are provided are covered with the side margin portion 17 and the cover portion 19. . The side margin portion 17 and the cover portion 19 mainly have a function of protecting the periphery of the capacitance forming portion 18 and ensuring the insulation of the first and second internal electrodes 12 and 13.

  The side margin part 17 and the cover part 19 are also formed of ceramics. The ceramic forming the side margin portion 17 and the cover portion 19 is preferably a dielectric polycrystal having the same composition system as the main phase of the capacitance forming portion 18 as a main phase. Thereby, the internal stress in the element body 11 is suppressed.

  The side margin portion 17 has a pore ratio of 1% or less. As a result, the density of the ceramics constituting the side margin portion 17 is high, so that it is difficult for moisture to enter the capacitance forming portion 18 from the outside through the side margin portion 17. Therefore, the moisture resistance of the multilayer ceramic capacitor 10 is ensured.

  Further, since the pore ratio of the side margin portion 17 is 1% or less, the side margin portion 17 has high rigidity against physical impact. As a result, the multilayer ceramic capacitor 10 also has improved rigidity against a physical impact from the outside.

  Note that the pore ratio of the present embodiment is calculated by the following procedure, for example. First, the cross section of the side margin portion 17 is imaged at a predetermined magnification using a scanning electron microscope (SEM). Next, a plurality of pores appearing in an image obtained by imaging the cross section of the side margin portion 17 are selected, the cross sectional area of the pores is measured, and an average value thereof is calculated. And the ratio of the said average value with respect to the cross-sectional area of the imaged side margin part 17 is calculated.

In the present embodiment, it is preferable to reduce the dimension D1 of the side margin portion 17 in the Y-axis direction. By reducing the dimension D1, the crossing area of the internal electrodes 12, 13 can be increased as much as possible, and the capacitance of the multilayer ceramic capacitor 10 can be increased.
However, from the viewpoint of ensuring the moisture resistance of the multilayer ceramic capacitor 10, the dimension D1 is preferably 5 μm or more.

In the present embodiment, it is preferable that the dimension D1 of the side margin portion 17 is 10 μm or less. Thereby, when there is a gap between the stacked portion 16 and the side margin portion 17, this gap can be detected by observing the surface of the side margin portion 17 with an optical microscope or the like.
Therefore, the gap between the multilayer part 16 and the side margin part 17 can be detected without observing the cross section of the multilayer ceramic capacitor 10.
That is, it is possible to detect whether or not the side margin portion 17 is peeled from the multilayer portion 16 by using an optical microscope or the like without destroying the multilayer ceramic capacitor 10.

  The side margin portion 17, the capacitance forming portion 18, and the cover portion 19 according to the present embodiment include, for example, magnesium (Mg), manganese (Mn), aluminum (Al), calcium, in addition to barium (Ba) and titanium (Ti). (Ca), vanadium (V), chromium (Cr), zirconium (Zr), molybdenum (Mo), tungsten (W), tantalum (Ta), niobium (Nb), silicon (Si), boron (B), yttrium (Y), europium (Eu), gadolinium (Gd), dysprosium (Dy), holmium (Ho), erbium (Er), ytterbium (Yb), lithium (Li), potassium (K) or sodium (Na), etc. One or more metal elements may be further contained.

  With the above configuration, in the multilayer ceramic capacitor 10, when a voltage is applied between the first external electrode 14 and the second external electrode 15, a plurality of pieces between the first internal electrode 12 and the second internal electrode 13 are provided. A voltage is applied to the ceramic layer. As a result, in the multilayer ceramic capacitor 10, charges corresponding to the voltage between the first external electrode 14 and the second external electrode 15 are stored.

Note that the multilayer ceramic capacitor 10 according to the present embodiment only needs to include the multilayer portion 16 and the side margin portion 17, and other configurations can be appropriately changed. For example, the number of the first and second internal electrodes 12 and 13 can be appropriately determined according to the size and performance required for the multilayer ceramic capacitor 10.
2 and 3, the number of the first and second internal electrodes 12 and 13 is limited to four to make it easier to see the facing state of the first and second internal electrodes 12 and 13. However, in practice, more first and second internal electrodes 12 and 13 are provided to ensure the capacity of the multilayer ceramic capacitor 10.

  FIG. 4 is a schematic diagram showing the region P shown in FIG. 3 in an enlarged manner, and is a schematic diagram showing the end portions of the first and second internal electrodes 12 and 13 in an enlarged manner.

  As shown in FIG. 4, the first and second internal electrodes 12, 13 have an oxidation region E formed at the end exposed at the side surface S <b> 2 of the stacked portion 16. Oxidized region E is a region where conductivity is reduced by oxidation. In addition, as shown in the figure, the oxidized region E is formed at the end portions of the internal electrodes 12 and 13 so as to be adjacent to the side margin portion 17.

  As an example, the oxidation region E is a complex oxide (for example, 3) including a metal element included in the side margin portion 17, the cover portion 19, and the capacitance forming portion 18 and a metal element constituting the internal electrodes 12 and 13. (Elementary oxide) as a main component.

  Further, the oxidized region E is preferably formed on all of the end portions of the first and second internal electrodes 12 and 13, but may not be formed on a part thereof.

  The dimension D2 of the oxidation region E in the Y-axis direction can be, for example, about several hundred to several thousand nm, and is preferably 400 nm or more. In the present embodiment, by setting the dimension D2 of the oxidized region E to 400 nm or more, it is possible to suppress a short circuit failure between the internal electrodes 12 and 13 and an IR (Insulation Resistance) failure in the multilayer ceramic capacitor 10.

  In FIG. 4, the dimension D2 of the plurality of oxidized regions E is equally shown for convenience of explanation. However, in this embodiment, the dimension D2 may be different for each oxidation region E. In this case, the dimension D2 of the oxidized region E can be an average value of the oxidized regions E formed at the end portions of all the internal electrodes 12 and 13.

[Method of Manufacturing Multilayer Ceramic Capacitor 10]
FIG. 5 is a flowchart showing a method for manufacturing the multilayer ceramic capacitor 10. 6 to 16 are views showing a manufacturing process of the multilayer ceramic capacitor. Hereinafter, a method for manufacturing a multilayer ceramic capacitor will be described with reference to FIGS.

(Step S01: Ceramic sheet preparation process)
In step S01, a first ceramic sheet 101 and a second ceramic sheet 102 for forming the capacitance forming portion 18 and a third ceramic sheet 103 for forming the cover portion 19 are prepared. The ceramic sheets 101, 102, and 103 are mainly composed of insulating ceramics and are configured as unfired dielectric green sheets. The ceramic sheets 101, 102, and 103 are formed into a sheet shape using, for example, a roll coater or a doctor blade.

  FIG. 6 is a plan view of the ceramic sheets 101, 102, 103. At this stage, the ceramic sheets 101, 102, 103 are not cut for each multilayer ceramic capacitor 10. FIG. 6 shows cutting lines Lx and Ly when cutting each multilayer ceramic capacitor 10. The cutting line Lx is parallel to the X axis, and the cutting line Ly is parallel to the Y axis.

  As shown in FIG. 6, the first ceramic sheet 101 is formed with unfired first internal electrodes 112 corresponding to the first internal electrodes 12, and the second ceramic sheet 102 is not yet formed corresponding to the second internal electrodes 13. A fired second internal electrode 113 is formed. Note that no internal electrode is formed on the third ceramic sheet 103 corresponding to the cover portion 19.

  The first and second internal electrodes 112 and 113 can be formed using, for example, a conductive paste containing nickel (Ni). For example, a screen printing method or a gravure printing method can be used to form the first and second internal electrodes 112 and 113 using a conductive paste.

  The first and second internal electrodes 112 and 113 are disposed over two regions adjacent to each other in the X-axis direction that are partitioned by the cutting line Ly, and extend in a band shape in the Y-axis direction. The first internal electrode 112 and the second internal electrode 113 are shifted in the X-axis direction by one row of regions partitioned by the cutting line Ly. That is, the cutting line Ly passing through the center of the first internal electrode 112 passes through the region between the second internal electrodes 113, and the cutting line Ly passing through the center of the second internal electrode 113 passes through the region between the first internal electrodes 112. Passing through.

(Step S02: Lamination process)
In step S02, the laminated sheet 104 is produced by laminating the ceramic sheets 101, 102, 103 prepared in step S01.

  FIG. 7 is an exploded perspective view of the laminated sheet 104 obtained in step S02. In FIG. 7, for convenience of explanation, the ceramic sheets 101, 102, and 103 are shown in an exploded manner. However, in the actual laminated sheet 104, the ceramic sheets 101, 102, and 103 are integrated by being crimped by hydrostatic pressure or uniaxial pressure. Thereby, the high-density laminated sheet 104 is obtained.

In the laminated sheet 104, the first ceramic sheets 101 and the second ceramic sheets 102 corresponding to the capacitance forming unit 18 are alternately laminated in the Z-axis direction.
In the laminated sheet 104, the third ceramic sheet 103 corresponding to the cover portion 19 is laminated on the upper and lower surfaces in the Z-axis direction of the first and second ceramic sheets 101 and 102 that are alternately laminated. In the example shown in FIG. 7, three third ceramic sheets 103 are laminated, but the number of third ceramic sheets 103 can be changed as appropriate.

(Step S03: Cutting process)
In step S03, an unfired laminated chip 116 is produced by cutting the laminated sheet 104 obtained in step S02 with a rotary blade or a push cutting blade.

  FIG. 8 is a plan view of the laminated sheet 104 after step S03. The laminated sheet 104 is cut along the cutting lines Lx and Ly while being fixed to the holding member C. Thereby, the lamination sheet 104 is separated into pieces and the lamination chip 116 is obtained. At this time, the holding member C is not cut, and the laminated chips 116 are connected by the holding member C.

FIG. 9 is a diagram illustrating a state in which the laminated sheet 104 is cut. In FIG. 9, for convenience of explanation, the total number of internal electrodes 112 and 113 is four, and the total number of ceramic sheets 101, 102, and 103 is five.
When the laminated sheet 104 is cut by a cutting blade F such as a push cutting blade, the cutting blade F that is cutting the laminated sheet 104 drags the internal electrodes 112 and 113, and the end portions of the internal electrodes 112 and 113 are shown in FIG. As shown, it may be stretched in the Z-axis direction. Thereby, in side surface S3, S4 of the lamination | stacking chip | tip 116, internal electrodes 112 and 113 may contact each other via the extended part.

  However, in the internal electrodes 112 and 113 according to the present embodiment, the oxidized region E is satisfactorily formed at the ends as shown in FIG. Therefore, even when the internal electrodes 112 and 113 are extended when the laminated sheet 104 is cut and the ends of the internal electrodes 112 and 113 are in contact with each other through the extended portions, The short circuit failure is suppressed.

  FIG. 10 is a perspective view of the multilayer chip 116 obtained in step S03. On the multilayer chip 116, an unfired capacitance forming portion 118 and a cover portion 119 are formed. In the multilayer chip 116, the unfired first and second internal electrodes 112 and 113 are exposed on both side surfaces S3 and S4 facing the Y-axis direction that are cut surfaces.

(Step S04: Side margin portion forming step)
In step S04, an unfired element body 111 is manufactured by providing unfired side margin portions 117 on the side surfaces S3 and S4 of the multilayer chip 116.

In step S04, in order to provide the side margin portions 117 on the both side surfaces S3 and S4 of the multilayer chip 116, the orientation of the multilayer chip 116 is appropriately changed by reattaching a holding member such as a tape.
In particular, in step S04, side margin portions 117 are provided on both side surfaces S3 and S4 facing the Y-axis direction, which is a cut surface of the laminated chip 116 in step S03. For this reason, in step S04, it is preferable to peel the laminated chip 116 from the holding member C in advance and rotate the direction of the laminated chip 116 by 90 degrees.

  FIGS. 11 to 13 are schematic diagrams showing the process of step S04, and show how the side margin sheet 117s is punched into the laminated chip 116. FIG. Hereinafter, the process of step S04 will be described in order.

First, a side margin sheet 117s for forming the side margin portion 117 is prepared. The side margin sheet 117s is composed of an insulating ceramic as a main component and is formed as an unfired dielectric green sheet, similarly to the ceramic sheets 101, 102, and 103 prepared in step S01.
The side margin sheet 117s is formed into a sheet shape by using, for example, a roll coater or a doctor blade. Further, the side margin sheet 117s is adjusted so that the thickness in the Y-axis direction is thin.

  Next, as shown in FIG. 11, the side margin sheet 117 s is disposed on the flat elastic body 400. Then, the multilayer chip 116 is arranged so that the side surface S4 of the multilayer chip 116 and the side margin sheet 117s face each other in the Y-axis direction. In step S04, the side surface S3 of the laminated chip 116 is held by the tape T as shown in FIG. 11 by appropriately changing the direction of the laminated chip 116 by the attaching process of a holding member such as a tape.

  Subsequently, the side surface S4 of the multilayer chip 116 is pressed against the side margin sheet 117s by moving the multilayer chip 116 in the Y-axis direction toward the side margin sheet 117s.

At this time, as shown in FIG. 12, the laminated chip 116 bites into the elastic body 400 together with the side margin sheet 117s. Accordingly, the elastic body 400 rises in the Y-axis direction and pushes up the side margin sheet 117s by the pressing force in the Y-axis direction applied to the elastic body 400 from the multilayer chip 116.
Thereby, a shearing force is applied from the elastic body 400 to the side margin sheet 117s, and the side margin sheet 117s facing the side surface S4 in the Y-axis direction is cut off. The side margin sheet 117s is attached to the side surface S4.

  Next, when the laminated chip 116 is moved in the Y-axis direction so that the laminated chip 116 is separated from the elastic body 400, only the side margin sheet 117s attached to the side surface S4 is separated from the elastic body 400 as shown in FIG. To do. As a result, the side margin portion 117 is formed on the side surface S4 of the multilayer chip 116.

Here, by adjusting the punching conditions when the side surfaces S3 and S4 of the multilayer chip 116 punch the side margin sheet 117s, it is possible to improve the ceramic density of the side margin portion 17 after the firing step described later. is there.
Specifically, the speed at which the multilayer chip 116 punches the side margin sheet 117s and the punching pressure that the multilayer chip 116 applies to the side margin sheet 117s are adjusted, so that the ceramic of the side margin portion 17 after the firing process is adjusted. It is possible to improve the density.

Subsequently, by holding the laminated chip 116 held on the tape T on another tape, the side surface S3 of the laminated chip 116 is exposed, and the side surface S3 and the side margin sheet 117s are opposed to each other in the Y-axis direction. Then, the side margin part 117 is formed also on the side surface S3 through the same process as the above process for forming the side margin part 117 on the side surface S4.
As a result, an unfired element body 111 in which side margin portions 117 are formed on both side surfaces S3 and S4 of the laminated chip 116 is obtained. In the present embodiment, the ceramic density of the side margin portion 17 after firing is also improved by applying hydrostatic pressure to the unfired element body 111.

FIG. 14 is a perspective view of the unfired element body 111 obtained in step S04.
In the unfired element body 111, the end portions of the internal electrodes 112 and 113 exposed on the side surfaces S3 and S4 are covered with the side margin portion 117, and the end portions in the X-axis direction of the internal electrodes 112 and 113 are in the X-axis direction. The structure exposed to end surface S5 is taken.

  FIG. 15 is a view showing a manufacturing process of a conventional multilayer ceramic capacitor element body, and is a side view of the element body. With reference to FIG. 15, the effect | action by adjusting the thickness of the side margin sheet | seat 117s is demonstrated.

In the conventional multilayer ceramic capacitor, if the side margin sheet for forming the side margin portion is thick in the manufacturing process, the cutability of the side margin sheet may be poor when the multilayer chip 316 punches the side margin sheet.
As a result, the end portion 312a of the internal electrode 312 may be exposed on the side surface S7 of the multilayer chip 316 where the side margin portion 317 is formed by punching the side margin sheet, as shown in FIG.

If the end 312a of the internal electrode 312 is exposed to the side surface S7 without being covered with the insulating side margin portion 317, foreign matter or the like adheres to the side surface S7 that is not covered with the side margin portion 317 during the manufacturing process. In such a case, in the fired multilayer ceramic capacitor, the end portions 312a of the internal electrode 312 are electrically connected to each other through the foreign matter, which may cause a short circuit failure.
Further, since the side margin portion 317 does not cover the end portion 312a of the internal electrode 312, the end portion 312a is not easily protected from moisture and the like, and thus the moisture resistance of the fired multilayer ceramic capacitor may be reduced. .

  On the other hand, the side margin sheet 117s according to the present embodiment is adjusted to be thin. As a result, the side margin sheet 117s is more easily cut than the conventional side margin sheet when the laminated chip 116 is punched.

Therefore, the unfired element body 111 formed by punching the side margin sheet 117s by the laminated chip 116 does not expose the end portions of the internal electrodes 112 and 113 to the side surfaces S3 and S4 as shown in FIG. It becomes composition.
Therefore, short circuit failure and a decrease in moisture resistance of the multilayer ceramic capacitor 10 due to the exposure of the end portions of the internal electrodes 112 and 113 on the side surfaces S3 and S4 are suppressed.

Note that the method of forming the side margin portion 117 on both side surfaces S3 and S4 of the multilayer chip 116 is not limited to the method of punching the side margin sheet 117s.
For example, the side margin sheet 117s may be formed by pasting side margin sheets 117s that have been cut in advance to both side surfaces S3 and S4 of the multilayer chip 116.
Alternatively, the side margin portions 117 may be formed on both side surfaces S3 and S4 of the multilayer chip 116 by dipping the both side surfaces S3 and S4 of the multilayer chip 116 in a paste material made of ceramics.

(Step S05: barrel polishing process)
In step S05, the base body 111 is chamfered by barrel-polishing the unfired base body 111 obtained in step S04.

  In the above-described step S04, the unfired element body 111 is formed by forming sheet-like side margin portions 117 on both side surfaces S3 and S4 of the multilayer chip 116. For this reason, as shown in FIG. 14, the element body 111 has ridges (locations where two surfaces intersect) and corners (locations where three surfaces intersect) connecting each surface of the element body 111.

  If the element body 111 has ridges and corners, the element bodies 111 collide with each other in the manufacturing process, so that the element body 111 is cracked or chipped. Accordingly, in order to suppress such cracks and chips, the ridges and corners of the element body 111 are chamfered.

  As a processing method for chamfering the ridges and corners of the element body 111, barrel polishing is effective in improving manufacturing efficiency. Barrel polishing can be performed, for example, by enclosing a plurality of unfired element bodies 111, a polishing medium, and a liquid in a barrel container, and applying a rotational motion or vibration to the barrel container.

  FIG. 16 is an enlarged cross-sectional view of the unfired element body 111 after barrel polishing, and is an enlarged view showing the vicinity of the ridge portion R of the capacitance forming portion 118.

In general, an unfired element body composed of a laminated chip and a side margin portion has a side margin portion near the ridge portion of the capacitance forming portion when the ridge portion and the corner portion are chamfered by barrel polishing or the like. The thickness tends to be excessively thin.
For this reason, moisture or the like tends to enter the multilayer chip from the outside through the excessively thinned portion of the side margin portion, and the moisture resistance of the multilayer ceramic capacitor may be reduced.

  Therefore, in the present embodiment, in the element body 111, the thickness of the side margin sheet 117s is adjusted so that the dimension D4 of the cover portion 119 in the Z-axis direction is equal to or larger than the dimension D3 of the side margin portion 117 in the Y-axis direction. The Thereby, in the element body 111 after barrel polishing, the dimension D5 of the side margin portion 117 near the ridge portion R of the capacitance forming portion 118 is suppressed from being excessively reduced.

  In step S05, from the viewpoint of ensuring the moisture resistance of the multilayer ceramic capacitor 10, the dimension D3 of the side margin part 117 is approximately the same as the dimension D5 of the side margin part 117 near the ridge R in the element body 111 after barrel polishing. It is preferable that Specifically, in the base body 111 after barrel polishing, the dimensions D3 and D5 of the side margin portion 117 are preferably 10 μm or more.

In step S05, in the element body 111 after barrel polishing, the dimension D4 of the cover part 119 is preferably equal to or larger than the dimension D3 of the side margin part 117. Thereby, the dimension of the cover part 19 in the Z-axis direction after the baking process described later becomes equal to or larger than the dimension of the side margin part 17 in the Y-axis direction.
This makes it difficult for moisture and the like to enter the multilayer chip 16 from the outside through the side margin portion 17 in the vicinity of the ridge portion R of the capacitor forming portion 18, and suppresses a decrease in moisture resistance of the multilayer ceramic capacitor 10. .

(Step S06: Firing step)
In step S06, the unfired element body 111 obtained in step S05 is fired to produce the element body 11 of the multilayer ceramic capacitor 10 shown in FIGS.
That is, in step S06, the first and second internal electrodes 112 and 113 become the first and second internal electrodes 12 and 13, the laminated chip 116 becomes the laminated portion 16, and the side margin portion 117 becomes the side margin portion 17. .

  In the side margin portion 17 after firing, the punching pressure and speed when the laminated chip 116 punches the side margin sheet 117s is adjusted in step S04 described above, or the element body 111 is subjected to hydrostatic pressure. By adjusting the content of glass or the like contained in the side margin sheet 117s, the pore ratio becomes 1% or less.

The firing temperature of the element body 111 in step S05 can be determined based on the sintering temperature of the laminated chip 116 and the side margin portion 117. For example, when a barium titanate (BaTiO ₃ ) -based material is used as the ceramic, the firing temperature of the element body 111 can be about 1000 to 1300 ° C. The firing can be performed, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere. In the present embodiment, the firing is performed in a low oxygen partial pressure atmosphere (4.0 × 10 ⁻⁹ ppm).

Here, in this embodiment, by setting the thickness of the side margin portion 117 of the element body 111 in the Y-axis direction to 20 μm or less, oxygen is supplied to the internal electrodes 112 and 113 via the side margin portion 117 during firing. As a result, the oxidized region E is favorably formed at the end portions of the internal electrodes 112 and 113.
Therefore, even if foreign matter or the like adheres to the side surfaces S3 and S4 of the laminated chip 116 where the end portions of the internal electrodes 112 and 113 are exposed during the manufacturing process, the foreign matter or the like on the side surfaces S1 and S2 of the element body 11 after firing is interposed. The conduction between the internal electrodes 12, 13 is suppressed. Therefore, short circuit failure and IR failure between the internal electrodes 12 and 13 are effectively suppressed.

(Step S07: External electrode forming step)
In step S07, the first and second external electrodes 14 and 15 are formed on the element body 11 obtained in step S06, whereby the multilayer ceramic capacitor 10 shown in FIGS.

  In step S07, first, an unfired electrode material is applied so as to cover one X-axis direction end face of the element body 11, and an unfired electrode material is applied so as to cover the other X-axis direction end face of the element body 11. To do. The applied unfired electrode material is baked, for example, in a reducing atmosphere or a low oxygen partial pressure atmosphere to form a base film on the element body 11. Then, an intermediate film and a surface film are formed on the base film baked on the element body 11 by a plating process such as electrolytic plating, and the first and second external electrodes 14 and 15 are completed.

  Note that part of the processing in step S07 may be performed before step S06. For example, before step S06, an unfired electrode material is applied to both end surfaces S5 in the X-axis direction of the unfired element body 111. In step S06, the unfired element body 111 is sintered and simultaneously fired. The base film for the first and second external electrodes 14 and 15 may be formed by baking an electrode material.

(Modification)
The manufacturing method of the multilayer ceramic capacitor 10 is not limited to the above-described manufacturing method, and a change or addition of a manufacturing process may be appropriately performed.
For example, the binder component and the solvent component may be removed from the element body 111 by performing a binder removal process on the element body 111 before firing.

  As a method of performing a binder removal process on the element body 111, for example, the element body 111 accommodated in an alumina sheath is subjected to heat treatment at a temperature of 350 to 600 ° C. for 1 hour to 8 hours in an electric furnace in a reducing atmosphere. The method of performing etc. are mentioned. In this case, the temperature rising rate of the electric furnace can be set to 1 to 10 ° C./min, for example.

In the present embodiment, ceramics may be deposited on the side margin portion 117 that has been subjected to the binder removal process. Thereby, ceramics are filled in the voids of the ceramic particles generated by the binder removal, and the ceramic density of the side margin portion 17 after the firing process is improved.
As the ceramic deposited on the side margin portion 117 that has been subjected to the binder removal processing, typically, a ceramic having the same composition as the insulating ceramic that is the main component of the side margin sheet 117s is employed.

  As a method for depositing ceramics on the side margin part 117 subjected to the binder removal process, for example, a spray drying method in which ceramic powder is sprayed on the side margin part 117, or particles constituting ceramics are attached to the side margin part 117. A sputtering method, a vacuum deposition method, or the like is employed.

  Examples of the present invention will be described below.

[Preparation of unfired body]
According to the said manufacturing method, 200 each of the sample of the unbaking element | base_body which concerns on Examples 1-8 and Comparative Examples 1-6 was produced. The samples according to Examples 1 to 8 and Comparative Examples 1 to 6 were manufactured under common manufacturing conditions except for the thickness of the side margin portion and the denseness of the ceramics constituting the side margin portion.

(Example 1)
In the sample according to Example 1, the thickness of the side margin portion 117 is 2 μm.

(Example 2)
In the sample according to Example 2, the thickness of the side margin portion 117 is 5 μm.

(Example 3)
The sample according to Example 3 is a sample in which the side margin portion 117 is formed by using the side margin sheet 117s having a thickness of 9 μm.

Example 4
In the sample according to Example 4, the thickness of the side margin portion 117 is 10 μm.

(Example 5)
In the sample according to Example 5, the side margin portion 117 has a thickness of 15 μm.

(Example 6)
The sample according to Example 6 is a sample in which the side margin portion 117 is formed by using the side margin sheet 117s having a thickness of 19 μm.

(Example 7)
In the sample according to Example 7, the thickness of the side margin portion 117 is 20 μm.

(Example 8)
In the sample according to Example 8, the thickness of the side margin portion 117 is 25 μm.

(Comparative Example 1)
The sample according to Comparative Example 1 has a side margin portion thickness of 2 μm.

(Comparative Example 2)
The sample according to Comparative Example 2 has a side margin portion thickness of 5 μm.

(Comparative Example 3)
The sample according to Comparative Example 3 has a side margin portion thickness of 10 μm.

(Comparative Example 4)
The sample according to Comparative Example 4 has a side margin portion thickness of 15 μm.

(Comparative Example 5)
The sample according to Comparative Example 5 has a side margin portion thickness of 20 μm.

(Comparative Example 6)
The sample according to Comparative Example 6 has a side margin portion thickness of 25 μm.

[Evaluation of green body]
(Detection of samples with side margin peeling)
Of the 200 samples according to Examples 2, 4, 5, 7, and 8, an optical microscope was used to evaluate whether or not the sample from which the side margin portion 117 was peeled off from the multilayer chip 116 could be detected. Table 1 summarizes the results.
The “peeling length” shown in Table 1 is the dimension of the gap between the laminated chip 116 and the side margin portion 117.

Referring to Table 1, it can be seen that in Examples 5, 7, and 8, samples with a peel length of 50 μm or more can be detected, but cannot be detected when the length is less than 50 μm. On the other hand, in Examples 2 and 4, it was confirmed that detection was possible in any sample regardless of the peeling length.
Therefore, by setting the thickness of the side margin portion in the unfired element body 111 to 10 μm or less, a sample in which a gap is generated between the multilayer chip 116 and the side margin portion 117 can be detected regardless of the peeling length. It was experimentally confirmed that this was possible.

(Measurement of element exposed width)
Twenty samples were selected from the 200 samples according to Examples 3 and 6, and the element body exposure widths of the selected 20 samples were measured. FIG. 17 is a graph summarizing the results.
Note that “element body exposed width in the end face side region” shown in FIG. 17 means that the side margin portion 117 and the X-axis direction end face S5 in the side surfaces S3 and S4 of the laminated chip 116 on which the side margin portion 117 is formed. It is a dimension of the X-axis direction in the area | region between.
In addition, the “element body exposed width of the main surface side region” is the distance between the side margin portion 117 and the Z-axis direction main surface S6 on the side surfaces S3 and S4 of the multilayer chip 116 where the side margin portion 117 is formed. Is the dimension in the Z-axis direction in the region (see FIG. 14).

  Referring to FIG. 17, it can be seen that in Example 3, the element body exposed widths of the end face side region and the main surface side region are smaller on average than Example 6. From this result, it was experimentally confirmed that the exposed width of the element body in the end face side region and the main surface side region can be reduced by reducing the thickness of the side margin sheet 117s.

[Production of multilayer ceramic capacitors]
Examples 1, 2, 4, 5, 7, 8 and Examples 1, 2, 4, 5, 7, 8, and 8 according to the above production method using the unfired element bodies according to Comparative Examples 1 to 6 and Samples of multilayer ceramic capacitors according to Comparative Examples 1 to 6 were produced.

[Evaluation of multilayer ceramic capacitors]
(Evaluation of moisture resistance)
The samples of the multilayer ceramic capacitors according to Examples 1, 2, 4, 5, 7, and 8 and Comparative Examples 1 to 6 were evaluated for moisture resistance.
Specifically, 200 samples of Examples 1, 2, 4, 5, 7, and 8 and Comparative Examples 1 to 6 are held in a state where a rated voltage of 45 ° C., 95% humidity, and 10V is applied. A hygroscopic test was conducted. And the electrical resistance value was measured about each sample after a hygroscopic test, and the sample whose electrical resistance value was less than 10 MΩ was judged to be a failure. Table 2 is a table summarizing the thickness of the side margin, the pore rate, and the number of failures for each sample.

  Referring to Table 2, although samples with failures were not confirmed in the samples according to Comparative Examples 5 and 6, samples with failures were confirmed with the samples according to Comparative Examples 1 to 4. The samples according to Comparative Examples 1 to 6 have a pore ratio larger than 1%.

  The reason for the failure confirmed in the samples according to Comparative Examples 1 to 4 is that the thickness of the side margin portion is relatively thin and the number of pores included in the side margin portion is large. It is inferred that moisture has penetrated into the multilayer chip.

  From this result, it was confirmed that when the pore ratio of the side margin portion is larger than 1%, it is difficult to ensure the moisture resistance of the multilayer ceramic capacitor if the thickness of the side margin portion is 15 μm or less.

  On the other hand, in the samples according to Examples 1, 2, 4, 5, 7, and 8, although the sample according to Example 1 was confirmed to have a failure, the samples according to Examples 2, 4, 5, 7, and 8 were In such samples, no failed sample was confirmed. The samples according to Examples 1, 2, 4, 5, 7, and 8 have a pore ratio of 1% or less.

  From this result, it was confirmed that the moisture resistance of the multilayer ceramic capacitor 10 was ensured by setting the pore ratio of the side margin portion 17 to 1% or less even when the thickness of the side margin portion 17 was set to 15 μm or less. Then, it was confirmed that the moisture resistance of the multilayer ceramic capacitor 10 is more effectively ensured when the pore ratio of the side margin portion 17 is 1% or less and the thickness is 5 μm or more.

(Calculation of IR failure rate)
The IR failure rate of the samples according to Examples 1, 2, 4, 5, 7, and 8 was calculated. At this time, a sample having an IR defect rate of 10% or less was determined to be acceptable.
Table 3 and FIG. 18 show the thickness of the side margin portion 117 of the sample of the unfired element body 111 according to Examples 1, 2, 4, 5, 7, and 8, and Examples 1, 2, 4, 5, 7 8 is a table and a graph summarizing the dimension D2 of the oxidation region E of the sample of the multilayer ceramic capacitor 10 according to FIGS.

The dimension D2 of the oxidation region shown in Table 3 and FIG. 18 is an average value of the dimension D2 of the oxidation region E formed in 200 samples according to Examples 1, 2, 4, 5, 7, and 8.
Further, the IR failure rate shown in Table 3 and FIG. 18 indicates the proportion of samples in which IR failure occurs among the 200 samples according to Examples 1, 2, 4, 5, 7, and 8. The sample in which the above-mentioned IR failure has occurred is a sample in which the CR product is less than 1 MΩ under the condition where a rated voltage of 6 V is applied.

Referring to Table 3 and FIG. 18, the sample according to Example 8 has an IR defect rate of greater than 10%, but the samples according to Examples 1, 2, 4, 5, and 7 have an IR defect rate of 10% or less. It was.
The reason why the IR defect rate of the sample according to Example 8 is larger than 10% is that the thickness of the side margin portion 117 of the unfired element body 111 is greater than 20 μm, and thus oxidation of the end portions of the internal electrodes 112 and 113 is caused. It is presumed that the insulation resistance between the internal electrodes 112 and 113 was lowered because the oxidation region E was not sufficiently formed at the ends of the internal electrodes 112 and 113 without being promoted.

  From this result, when the thickness of the side margin portion 117 is 20 μm or less, it is experimentally confirmed that the IR defect in the multilayer ceramic capacitor 10 can be suppressed by ensuring that the dimension D2 of the oxidized region E is 0.4 μm or more. Confirmed.

[Other Embodiments]
As mentioned above, although embodiment of this invention was described, this invention is not limited only to the above-mentioned embodiment, Of course, a various change can be added.

  For example, in the multilayer ceramic capacitor 10, the capacitance forming portion 18 may be divided into a plurality of pieces in the Z-axis direction. In this case, it is sufficient that the first and second internal electrodes 12 and 13 are alternately arranged along the Z-axis direction in each capacitance forming portion 18, and the first internal electrode 12 or the first internal electrode 12 is switched at the portion where the capacitance forming portion 18 is switched. Two internal electrodes 13 may be arranged continuously.

DESCRIPTION OF SYMBOLS 10 ... Multilayer ceramic capacitor 11 ... Element body 12 ... 1st internal electrode 13 ... 2nd internal electrode 14 ... 1st external electrode 15 ... 2nd external electrode 16 ... Multilayer part 17 ... Side margin part 18 ... Capacitance formation part 19 ... Cover Part 111 ... Unfired element body 116 ... Unfired multilayer chip E ... Oxidized region

Claims (8)

By laminating a plurality of ceramic sheets on which unfired internal electrodes are formed in the first direction and press-bonding, the plurality of ceramic layers laminated in the first direction, and between the plurality of ceramic layers A plurality of unsintered laminated chips each having a capacitor forming part having the plurality of internal electrodes arranged and an unsintered cover part made of insulating ceramics and covering the capacitor forming part from the first direction. To produce an unfired laminated sheet to obtain
By cutting the unfired laminated sheet, the unfired laminated chip is produced,
An unfired element body is produced by covering the laminated chip from a second direction orthogonal to the first direction with an unfired side margin portion made of insulating ceramics,
Applying hydrostatic pressure to the green body,
A method for manufacturing a multilayer ceramic capacitor, wherein an unfired element body subjected to hydrostatic pressure is fired to produce an element body having a pore ratio of 1% or less in the side margin after firing. It is a manufacturing method of the multilayer ceramic capacitor according to claim 1,
The method for manufacturing a multilayer ceramic capacitor, wherein a dimension of the unfired cover portion in the first direction is equal to or greater than a dimension of the unfired side margin portion in the second direction. A method for producing a multilayer ceramic capacitor according to claim 1 or 2,
The method for producing a multilayer ceramic capacitor, wherein the unfired side margin portion has a dimension in the second direction of 20 μm or less. A method for manufacturing a multilayer ceramic capacitor according to any one of claims 1 to 3,
A method for manufacturing a multilayer ceramic capacitor, wherein the multilayer chip is formed by punching a side margin sheet mainly composed of an insulating ceramic to cover the unfired element body with the unfired side margin portion. A method for producing a multilayer ceramic capacitor according to any one of claims 1 to 4,
A binder removal treatment is performed on the green body.
A method for manufacturing a multilayer ceramic capacitor, comprising depositing ceramics on the unfired side margin portion subjected to binder removal processing. It is a manufacturing method of the multilayer ceramic capacitor according to claim 5,
A method for producing a multilayer ceramic capacitor, wherein ceramic powder is sprayed onto the unfired side margin portion that has been subjected to binder removal processing. It is a manufacturing method of the multilayer ceramic capacitor according to claim 5,
A method for manufacturing a multilayer ceramic capacitor, comprising sputtering ceramics on the unfired side margin portion subjected to binder removal processing. It is a manufacturing method of the multilayer ceramic capacitor according to claim 5,
A method for manufacturing a multilayer ceramic capacitor, comprising: vacuum-depositing ceramics on the unfired side margin portion subjected to binder removal processing.

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