JP2019145760A - Interposer and printed circuit board including the same - Google Patents

Abstract

To minimize an area occupied by an interposer and a printed circuit board including the same, in an electronic apparatus.SOLUTION: An interposer 300 connecting a first board 100 mounting multiple first electronic elements E1 on one face 110 and a second board 200 mounting multiple second electronic elements E2 on one face 210 includes: an isolating layer 310 placed between the first and second boards, so that one face faces one face of the first board, and the other face faces one face of the second board, multiple first cavities 320 opening to one face and receiving the first electronic elements, multiple second cavities 330 opening to the other face and receiving the second electronic elements, and a via 340 penetrating from one face to the other face of the isolating layer, and electrically connecting the first and second boards. The via passes between the multiple first cavities, and between the multiple second cavities.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an interposer and a printed circuit board including the interposer.

  The use of various electronic devices has increased explosively, and with the development of digital technology and semiconductor technology, the application fields for precise and complex electronic devices have become widespread. Due to the high density of internal parts of electronic devices, the PCB area required to connect individual parts (active, passive) is increased. On the other hand, the size of the battery tends to increase. For this reason, it is necessary to efficiently arrange and mount the PCB in a limited space of the electronic device.

Korean Registered Patent No. 10-1324595

  According to one aspect of the present invention, in an interposer for connecting a first substrate having a plurality of first electronic elements mounted on one surface and a second substrate having a plurality of second electronic elements mounted on one surface, An insulating layer disposed between the first substrate and the second substrate so that the other surface faces one surface of the first substrate and the other surface faces one surface of the second substrate; A plurality of first cavities for accommodating the first electronic elements, a plurality of second cavities open to the other surface for accommodating the second electronic elements, and penetrating from one surface of the insulating layer to the other surface. And vias electrically connecting the first substrate and the second substrate, the vias being provided by an interposer that passes between the plurality of first cavities and between the plurality of second cavities. Is done.

  According to one aspect of the present invention, in an interposer for connecting a first substrate having a plurality of first electronic elements mounted on one surface and a second substrate having a plurality of second electronic elements mounted on one surface, the one surface has An insulating layer disposed between the first substrate and the second substrate is opened to the one surface so as to face one surface of the first substrate and the other surface face one surface of the second substrate. A plurality of first cavities accommodating the first electronic elements, a plurality of second cavities opened to the other surface and accommodating the second electronic elements, and penetrated from one surface of the insulating layer to the other surface, Vias that electrically connect the first substrate and the second substrate, the insulating layer is composed of a plurality of layers, and the vias are stacked vertically on each of the plurality of layers of the insulating layer ( interposer including via conductors formed to be stacked There is provided.

  According to one aspect of the present invention, a first substrate having a plurality of first electronic elements mounted on one surface, a second substrate having a plurality of second electronic elements mounted on one surface, the first substrate, and the first substrate An interposer for connecting two substrates, wherein the interposer has one surface facing one surface of the first substrate and the other surface facing one surface of the second substrate. An insulating layer disposed between the two substrates, a plurality of first cavities open to the one surface to accommodate the first electronic element, and a plurality of open to the other surface to accommodate the second electronic element. A second cavity and a via penetrating from one surface of the insulating layer to the other surface and electrically connecting the first substrate and the second substrate, wherein the via includes the plurality of first cavities. Printed circuit board passing between and between the plurality of second cavities There is provided.

  According to one aspect of the present invention, a first substrate having a plurality of first electronic elements mounted on one surface, a second substrate having a plurality of second electronic elements mounted on one surface, the first substrate, and the first substrate An interposer for connecting two substrates, wherein the interposer has one surface facing one surface of the first substrate and the other surface facing one surface of the second substrate. An insulating layer disposed between the two substrates, a plurality of first cavities open to the one surface to accommodate the first electronic element, and a plurality of open to the other surface to accommodate the second electronic element. A second cavity and a via penetrating from one surface of the insulating layer to the other surface and electrically connecting the first substrate and the second substrate, and the insulating layer is composed of a plurality of layers. The vias are stacked up and down (sta) on each of the plurality of layers of the insulating layer. Printed circuit board comprising a via conductor formed so as to be k) is provided.

It is a figure which shows the electronic device with which the printed circuit board was mounted | worn. It is a figure which shows the printed circuit board based on the Example of this invention. It is a figure which shows the interposer which concerns on the Example of this invention. It is a figure which shows the interposer which concerns on the Example of this invention. It is a figure which shows the manufacturing method of the interposer based on the Example of this invention. It is a figure which shows the manufacturing method of the interposer based on the Example of this invention. FIG. 3 illustrates an interposer according to various embodiments of the present invention. FIG. 3 illustrates an interposer according to various embodiments of the present invention. FIG. 3 illustrates an interposer according to various embodiments of the present invention.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of an interposer and a printed circuit board including the interposer according to the present invention will be described in detail with reference to the accompanying drawings. A duplicate description is omitted.

  In addition, the first and second terms used in the following are merely identification symbols for distinguishing the same or corresponding components, and the same or corresponding components are limited by the first and second terms. It will never be done.

  In addition, the term “coupled” does not mean that each component is in direct physical contact with each other in the contact relationship between the components, but other configurations are interposed between the components, It is used as a concept that encompasses all cases where components are in contact with other components.

  FIG. 1 is a view showing an electronic device on which a printed circuit board is mounted, FIG. 2 is a view showing a printed circuit board according to an embodiment of the present invention, and FIGS. 3 and 4 are views of the present invention. It is a figure which shows the interposer which concerns on an Example.

  Smartphones and various electronic devices are equipped with printed circuit boards. Components necessary for the electronic device are mounted on the printed circuit board, and the electrical connection between the components is enabled by the printed circuit board, thereby realizing the function of the electronic device. The printed circuit board may be a main board.

  As shown in FIG. 1, especially in the portable electronic device 1, a printed circuit board 10 and a battery 20 as main boards are mounted in the electronic device housing, but the size of the display is increased and the camera is expensive. When the specification of the electronic device 1 becomes high, such as having a resolution function, the power consumption corresponding to the specification increases, so the capacity and size of the battery 20 also need to be increased. As the size of the battery 20 increases, the area that the printed circuit board 10 can occupy relatively decreases. Conversely, when the area occupied by the printed circuit board 10 is reduced, the area allocated to the battery 20 is increased, so that the battery 20 can be increased in size.

  The printed circuit board 10 according to the embodiment of the present invention has a multilayer structure, a stack structure, or a sandwich structure as shown in FIG. The area occupied by the battery 20 can be minimized, and the area occupied by the battery 20 can be increased.

  Referring to FIG. 2, the printed circuit board 10 according to the embodiment of the present invention includes a first substrate 100, a second substrate 200, and an interposer 300.

  The first substrate 100 and the second substrate 200 are mounted with electronic elements and play a substantial role as a printed circuit board. The interposer 300 supports the first substrate 100 and the second substrate 200 and the first substrate 100. And the second substrate 200 is electrically connected.

  The first substrate 100 and the second substrate 200 are spaced apart from each other and form a multilayer structure, a stack structure, and a sandwich structure. Specifically, the first substrate 100 and the second substrate 200 are spaced apart so that the one surface 110 of the first substrate 100 and the one surface 210 of the second substrate 200 face each other.

  Each of the first substrate 100 and the second substrate 200 is plate-shaped, and may be a multilayer substrate composed of a plurality of insulating material layers and a plurality of circuit layers, and may be 8 layers or 10 layers based on the circuit layers. It can be a substrate.

  The insulating material layers of the first substrate 100 and the second substrate 200 are layers formed of an insulating material such as epoxy resin, polyimide resin, BT resin, LCP (Liquid Crystal Polymer). The circuit layer is formed of a conductive material such as a metal such as copper (Cu) and is designed to have a specific pattern. The circuit layer is formed on one side or both sides of the insulating material layer, and circuit layers of different layers can be electrically connected via a connection conductor penetrating the insulating material layer.

  A plurality of first electronic elements E1 are mounted on one surface 110 of the first substrate 100. Here, the first electronic element E1 may include an active element, a passive element, an integrated circuit, or the like, but there is no limitation on the type. A plurality of third electronic elements E3 may be mounted on the other surface 120 of the first substrate 100.

  A first pad 130 is provided on one surface 110 of the first substrate 100. The first pad 130 can be electrically connected to the first electronic element E1 and / or the third electronic element E3 through the circuit layer. In particular, the first pad 130 and the third electronic element E3 are connected not only via the circuit layer but also via vias formed through the first substrate 100.

  The first pad 130 may be a part of a circuit layer located on the outermost layer from the side 110 of the first substrate 100. Specifically, the first pad 130 may be a part of a circuit layer formed on the outermost insulating material layer of the first substrate 100 and covered with a solder resist. The first pad 130 may be a solder resist. It can be exposed through the opening.

  A plurality of first pads 130 may be formed.

  A plurality of second electronic elements E2 are mounted on the one surface 210 of the second substrate 200. Here, the second electronic element E2 may include an active element, a passive element, an integrated circuit, and the like, and the type is not limited.

  In addition, a second pad 230 is provided on one surface 210 of the second substrate 200. The second pad 230 can be electrically connected to the second electronic element E2 through the circuit layer.

  The second pad 230 may be a part of a circuit layer located on the outermost layer from the one surface side of the second substrate 200. Specifically, the second pad 230 may be a part of a circuit layer formed on the outermost insulating material layer of the second substrate 200 and covered with a solder resist. The second pad 230 may be a solder resist. It can be exposed through the opening.

  A plurality of second pads 230 may be formed.

  One surface 110 of the first substrate 100 and one surface 210 of the second substrate 200 face each other, and the first pad 130 and the second pad 230 face each other. Here, the positions of the first pad 130 and the second pad 230 correspond to each other, and specifically, a line (for example, a line) connected from the first pad 130 to the second pad 230 (or vice versa) A line connecting the centers of the first pad 130 and the second pad 230 may be perpendicular to each of the first substrate 100 and the second substrate 200. However, the positions of the first pad 130 and the second pad 230 do not exactly match each other, and the positions of the first pad 130 and the second pad 230 may be shifted within a range where they can be connected to each other. That is, a line (for example, a line connecting the centers of the first pad 130 and the second pad 230) connected from the first pad 130 to the second pad 230 (or vice versa) is the first substrate 100 and the second pad 230. It can be diagonal to the substrate 200.

  Meanwhile, a plurality of first pads 130 and a plurality of second pads 230 may be formed, and a plurality of first pads 130 and a plurality of second pads 230 may be formed corresponding to each other. .

  The interposer 300 is interposed between the first substrate 100 and the second substrate 200. That is, the interposer 300 is coupled to all of the one surface 110 of the first substrate 100 and the one surface 210 of the second substrate 200, and the separation state between the first substrate 100 and the second substrate 200 can be maintained by the interposer 300.

  Referring to FIGS. 2 and 3, the interposer 300 includes an insulating layer 310, a first cavity 320, a second cavity 330, and a via 340.

  The insulating layer 310 is a plate-like layer formed of an insulating material such as an epoxy resin, a polyimide resin, or a BT resin. Specifically, the insulating layer 310 includes PPG (prepreg), build up film (ex. Ajinomoto Build up Film). Etc.

  The insulating layer 310 is disposed between the first substrate 100 and the second substrate 200 with one surface facing one surface of the first substrate 100 and the other surface facing one surface of the second substrate 200.

  The insulating layer 310 can include a plurality of layers 311, 312, and 313. For example, as shown in FIG. 2, the insulating layer 310 can be composed of three layers 311, 312, and 313. The three layers 311, 312, and 313 can be formed of the same or different materials. When formed from different materials, the middle layer 311 and the two layers 312, 313 can be formed of different materials.

  A solder resist SR can be formed on one surface and the other surface of the insulating layer 310, and the solder resist SR can be formed around the via 340 and the via pad 350.

  The first cavity 320 is formed on one surface of the insulating layer 310 so as to be opposed to the first substrate 100, and the second cavity 330 is formed on the other surface of the insulating layer 310 so as to be opened. It faces the two substrates 200. The first cavity 320 accommodates the first electronic element E1, and the second cavity 330 accommodates the second electronic element E2. That is, the positions of the first cavity 320 and the second cavity 330 can be determined by the positions of the first electronic element E1 and the second electronic element E2. Since most of the first electronic element E1 and the second electronic element E2 have a shape close to a rectangular parallelepiped, the first cavity 320 and the second cavity 330 can have a rectangular parallelepiped shape, but are not limited thereto.

  A plurality of first cavities 320 are formed. There are also a plurality of first electronic elements E1 mounted on the first substrate 100. One of the first cavities 320 can accommodate one of the first electronic elements E1. However, the present invention is not limited to this, and one of the first cavities 320 may accommodate two or more of the plurality of first electronic elements E1. In this case, one of the first cavities 320 accommodates the adjacent first electronic element E1.

  The depth (height) of the first cavity 320 may be determined by the maximum of the two or more first electronic elements that are accommodated. Alternatively, the shape of the first cavity 320 can be formed corresponding to the height of the first electronic element to be accommodated. For example, when an electronic element having a large height (referred to as electronic element A) and an electronic element having a small height (referred to as electronic element B) are both accommodated in the first cavity 320, the first cavity 320 may be Corresponding to A and B, all of a relatively deep portion and a relatively shallow portion can be included.

  A plurality of second cavities 330 are formed. There are also a plurality of second electronic elements E2 mounted on the second substrate 200. One of the second cavities 330 can accommodate one of the second electronic elements E2. However, the present invention is not limited thereto, and one of the second cavities 330 can accommodate two or more of the plurality of second electronic elements E2. In this case, one of the second cavities 330 accommodates the adjacent second electronic element E2.

  The depth (height) of the second cavity 330 may be determined by the largest of the two or more second electronic elements accommodated. Or the shape of the 2nd cavity 330 can be formed corresponding to the height of the 2nd electronic element to accommodate. For example, when an electronic element having a large height (referred to as electronic element C) and an electronic element having a small height (referred to as electronic element D) are accommodated in the second cavity 330, the second cavity 330 is Corresponding to C and D, all of a relatively deep portion and a relatively shallow portion can be included.

  Although the first cavity 320 and the second cavity 330 are formed on both surfaces of the insulating layer 310, the first cavity 320 and the second cavity 330 do not necessarily correspond to each other. However, when the first cavity 320 and the second cavity 330 correspond to each other, the unprocessed insulating layer 310 remains between the first cavity 320 and the second cavity 330, and the first cavity 320 and the second cavity 330. 330 may not be merged with each other.

  The metal layer 400 may be formed on the inner surfaces of the first cavity 320 and the second cavity 330. The inner surfaces of the first cavity 320 and the second cavity 330 refer to the bottom surface and inner wall surface of the first cavity 320 and the second cavity 330, and thus the entire inner surfaces of the first cavity 320 and the second cavity 330 are formed. Covered by a metal layer 400. The metal layer 400 can play an EMI (electromagnetic interference) shielding role. The metal layer 400 can be formed of a metal such as copper (Cu).

  The metal layer 400 formed on the inner surfaces of the first cavity 320 and the second cavity 330 can be connected to the ground, and can be connected to the ground through a ground via. That is, the metal layer 400 has an EMI shielding function and a ground function, and since the metal has a high thermal conductivity, it can also have a heat dissipation function. In particular, heat generated from the electronic device can be dispersed to the ground through the metal layer 400.

  Meanwhile, the heat dissipation member 500 may be accommodated in the first cavity 320 and the second cavity 330. Therefore, the heat dissipation member 500 may be interposed between the first cavity 320 and the first electronic element E1, and the heat dissipation member 500 may be interposed between the second cavity and the second electronic element E2. In particular, when the metal layer 400 is formed on the inner surfaces of the first cavity 320 and the second cavity 330, between the metal layer 400 and the first electronic element E1, and between the metal layer 400 and the second electronic element E2. The heat radiating member 500 can be formed. The heat radiating member 500 functions as a heat spreader and may be formed of a material having high thermal conductivity.

  When the insulating layer 310 includes a plurality of layers 311, 312, and 313, the depth of the first cavity 320 or the second cavity 330 can be determined regardless of the thickness of each of the layers constituting the insulating layer 310. That is, the depth of the first cavity 320 or the second cavity 330 may be deeper than the thickness of one layer of the insulating layer 310 and shallower than the thickness of the two layers of the insulating layer 310. Further, the depth of the first cavity 320 or the second cavity 330 may be shallower than the thickness of one layer of the insulating layer 310.

  The via 340 penetrates from one surface of the insulating layer 310 to the other surface, and electrically connects the first substrate 100 and the second substrate 200. Specifically, the via 340 is electrically connected to the first substrate 100 and the second substrate 200 by bonding to the first pad 130 and the second pad 230.

  The via 340 passes between the plurality of first cavities 320 and passes between the plurality of second cavities 330. That is, the via 340 is formed in a region adjacent to the first cavity 320 and the second cavity 330. When the first substrate 100 and the second substrate 200 are electrically connected to each other, the via 340 can reduce a path and reduce a signal loss.

  When the insulating layer 310 includes a plurality of layers, the via 340 may include via conductors 341, 342, and 343 formed to be stacked for each layer. Here, “to be stacked” means that the via conductors 341, 342, and 343 are connected vertically, specifically, two adjacent via conductors (the via conductor A at the bottom and the via conductor A at the top). This means that there is a portion where the upper surface of the via conductor A and the lower surface of the via conductor B overlap in the vertical direction. However, in the case where a via pad is formed on the upper surface of the via conductor A, the via conductor B passes through the via pad even if the upper surface of the via conductor A and the lower surface of the via conductor B do not exist clearly in the vertical direction. If it is located within the range connecting to the via conductor A, it is stacked.

  On the other hand, when the insulating layer 310 is composed of the three layers 311, 312, and 313, the cross-sectional areas of the via conductors 342 and 343 formed in the two layers 312 and 313 located on the outer side are closer to the inner side. It may be smaller. In this case, based on FIG. 2, the vertical cross section of the via conductor 342 formed in the layer 312 above the center layer 311 is an inverted trapezoid, and the via conductor formed in the layer 313 below. The vertical cross section of 343 is a (positive) trapezoid.

  When the insulating layer 310 includes a plurality of layers 311, 312, and 313, the via 340 includes via conductors 341, 342, and 343 stacked in each layer 311, 312, 313, so that the total thickness of the insulating layer 310 is increased. Regardless, the via 340 can be easily formed.

  When the insulating layer 310 is formed as a single layer, the via 340 is elongated vertically by the entire thickness of the insulating layer 310, and it is not easy to completely fill the via 340. On the other hand, when the insulating layer 310 is composed of a plurality of layers 311, 312, and 313, the upper and lower lengths of the via conductors 341, 342, and 343 are relatively small, and the volume of fill plating is reduced. Fill plating is facilitated, and the reliability of the via 340 is improved.

  Via pads 350 are formed at both ends of the via 340. Via pads 350 formed at both ends of the via 340 face the first pad 130 and the second pad 230, respectively.

  A via pad 350 on the first substrate 100 side of the via 340 is bonded to the first pad 130, and a via pad 350 on the second substrate 200 side of the via 340 is bonded to the second pad 230.

  The via pad 350 on the first substrate 100 side of the via 340 may be joined to the first pad 130 by a solder, and the via pad 350 on the second substrate 200 side of the via 340 may be joined to the second pad 230 by a solder.

  The interposer 300 according to the embodiment of the present invention may further include a second via 360.

  2 to 4 show the second via 360 formed at the edge of the insulating layer 310.

  The second via 360 penetrates from one surface of the insulating layer 310 to the other surface and is electrically connected to the first substrate 100 and the second substrate 200. That is, both ends of the second via 360 are joined to the first pad 130 and the second pad 230 by solder or the like.

  The second via 360 may have the same function as the via 340, that is, a function of electrically connecting the first substrate 100 and the second substrate 200.

  Alternatively, a part of the plurality of second vias 360 may have the same function as the above-described via 340, and the other part may be a ground via connected to the ground. The second via 360 used as a ground via can be electrically connected to the metal layer 400 on the inner surfaces of the first cavity 320 and the second cavity 330 described above.

  The second via 360 and the metal layer 400 can be connected via a circuit 400 ′ formed on one surface and / or the other surface of the insulating layer 310. In addition, a via pad 370 may be formed on the second via 360, and the circuit 400 ′ may be in contact with the via pad 370. Thereby, the heat generated from the electronic elements E1 and E2 can be moved to the heat dissipation member 500, the metal layer 400, the second via 360, and the ground, and can be dispersed and released.

  Meanwhile, the second via 360 may include via conductors 361, 362, and 363 formed to be stacked for each layer of the insulating layer 310. In the second via 360, like the via 340, the center lines of the via conductors 361, 362, 363 may be stacked so as to match or slightly shift.

  Hereinafter, a method for forming the interposer 300 will be described.

  5 and 6 are diagrams showing a method for manufacturing the interposer 300 according to the embodiment of the present invention. 5 and 6 show the case where the insulating layer 310 is composed of three layers 311, 312, and 313.

  Referring to FIG. 5, first, a double-sided copper-clad laminate is prepared (see FIG. 5A).

  The double-sided copper-clad laminate is obtained by laminating copper foils M on both sides of an insulating material 311 made of PPG or the like. When manufacturing the interposer 300, it is not always necessary to use a copper-clad laminate. Other metal foils can be used instead of the foil.

  First via conductors 341 and 361 are formed on the prepared copper-clad laminate (see FIG. 5B). The copper foils on both sides of the copper clad laminate are patterned into via pads that are in contact with the via conductors 341 and 361. The via conductors 341 and 361 formed here are for the via 340 and the second via 360.

  In FIG. 5C, single-sided copper-clad laminates are laminated on both sides of the insulating material 311. Here, other insulating materials 312 and 313 are laminated on the upper and lower sides of the insulating material 311, respectively. However, the single-sided copper-clad laminate is not laminated at this stage, and after the insulating materials 312 and 313 are first laminated, the copper foil or the metal foil M may be laminated sequentially.

  In FIG. 5D, the via hole VH is processed in the insulating material 312. The via hole VH is processed by a laser or the like. The via hole VH processed in FIG. 5D is formed in contact with the via pad so as to be stacked with the via conductors 341 and 361 formed in FIG.

  In FIG. 5E, the first cavity 320 is formed. The first cavity 320 can be processed by a laser, a router, a CNC drill, or the like.

  The width of the first cavity 320 is determined by the width of the first electronic element E1 accommodated, and the depth of the first cavity 320 is determined by the height of the first electronic element E1 accommodated.

  A plurality of first cavities 320 are formed.

  In FIG. 6A, the via hole VH and the second cavity 330 are formed. The via hole VH can be formed by the same method as the via hole VH processed in FIG. That is, the via hole VH is formed in contact with the via pad so as to be stacked with the via conductors 341 and 361 formed in FIG.

  The second cavity 330 can be processed by a laser, a router, a CNC drill, or the like. The width of the second cavity 330 is determined by the width of the accommodated second electronic element E2, and the depth of the second cavity 330 is determined by the height of the accommodated second electronic element E2.

  A plurality of second cavities 330 are formed.

  In FIG. 6B, the metal layer 400 is formed on the inner surfaces of the first cavity 320 and the second cavity 330, one surface of the insulating layer 310, and the other surface. The metal layer 400 can be formed by a plating method. Further, at this stage, the via hole VH is fill-plated to form via conductors 342, 343, 362, and 363. By forming the via conductors 342, 343, 362, 363, the via 340 and the second via 360 are completed. The metal layer 400 and the via conductors 342, 343, 362, 363 can be simultaneously plated by a wet plating method.

  In FIG. 6C, the metal layer 400 is patterned to form a circuit 400 ′ and via pads 350, 370. However, the metal layer 400 is maintained on the inner surfaces of the first cavity 320 and the second cavity 330. As a result, the metal layer 400 is insulated from the via 340 and can be connected to the second via 360 via the circuit 400 ′.

  In FIG. 6D, the solder resist SR is applied at a position where the metal layer 400 is removed by patterning of the metal layer 400. With the solder resist SR, the via pad 350 of the via 340 can be completely insulated from the metal layer 400.

  In the following, various embodiments relating to the interposer 300 of the present invention will be described.

  7-9 illustrate an interposer 300 according to various embodiments of the present invention.

  Referring to FIG. 7, in the interposer 300 according to the embodiment of the present invention, the via conductors 341, 342, and 343 of the via 340 are stacked, and the center lines of the via conductors 341, 342, and 343 are shifted as described above. Alternatively, the via conductors adjacent to each other may have a vertically overlapping portion or may be connected to each other via a via pad.

  When the via 340 is not formed in a straight line due to the influence of the position and size of the electronic element and the cavity, that is, the center of the first pad 130 and the center of the second pad 230 do not coincide with each other vertically. If the center of each of the via pads 341, 342, and 343 is slightly shifted and stacked, the first pad 130 and the second pad 230 are hatched. Can be connected.

  That is, even when the positions of the first pad 130 and the second pad 230 are shifted from each other, the electrical connection between the first substrate 100 and the second substrate 200 is facilitated by using the stack relationship of the via conductors 341, 342, and 343. Can be realized.

  Referring to FIG. 8, in the interposer 300 according to the embodiment of the present invention, the first cavity 320 and the second cavity 330 may be merged with each other. That is, the first cavity 320 and the second cavity 330 are formed to correspond to each other, and the height of the first electronic element E1 and the height of the second electronic element E2 are high, so that the first cavity 320 and the second cavity 330 are high. If it is difficult to leave the insulating layer 310 between the first cavity 320 and the second cavity 330, the first cavity 320 and the second cavity 330 may be merged. In this case, the metal layer 400 is also integrally formed on the inner wall of the first cavity 320 and the inner wall of the second cavity 330.

  In FIG. 8, the size of the first cavity 320 is different from the size of the second cavity 330, but the size of the first cavity 320 and the size of the second cavity 330 may be the same. In this case, the first cavity 320 and the second cavity 330 can be processed simultaneously in the manufacturing process of the interposer 300.

  Referring to FIG. 9, as in FIG. 8, the first cavity 320 and the second cavity 330 are merged, but the first cavity 320 is merged with the two second cavities 330. This merging of cavities can be realized in various ways depending on the size and position of the electronic device.

  Although one embodiment of the present invention has been described above, addition and modification of constituent elements are within the scope not departing from the spirit of the present invention described in the scope of claims for those skilled in the art. The present invention can be modified and changed in various ways by deletion, addition, etc., and this is also included in the scope of the right of the present invention.

100 First substrate 110 One side 120 Other side 130 First pad E1 First electronic element E3 Third electronic element 200 Second substrate 210 One side 220 Other side 230 Second pad E2 Second electronic element 300 Interposer 310 Insulating layer 311, 312, 313 layer 320 first cavity 330 second cavity 340 via 341, 342, 343 via conductor 350 via pad 360 second via 361, 362, 363 via conductor 370 via pad 400 metal layer 400 ′ circuit 500 heat dissipation member

Claims (25)

In an interposer for connecting a first substrate having a plurality of first electronic elements mounted on one surface and a second substrate having a plurality of second electronic elements mounted on one surface,
An insulating layer disposed between the first substrate and the second substrate such that one surface faces one surface of the first substrate and the other surface faces one surface of the second substrate;
A plurality of first cavities open to the one side and containing the plurality of first electronic elements;
A plurality of second cavities open to the other surface and containing the plurality of second electronic elements;
A via penetrating from one surface of the insulating layer to the other surface and electrically connecting the first substrate and the second substrate;
The via is an interposer that passes between the plurality of first cavities and between the plurality of second cavities.   The interposer according to claim 1, wherein the insulating layer includes a plurality of layers.   The interposer according to claim 2, wherein the via includes a via conductor formed so as to be stacked vertically on the plurality of layers. The insulating layer is composed of three layers,
4. The interposer according to claim 3, wherein the cross-sectional area of the via conductor formed in each of the two layers located on the outer side of the three layers becomes smaller toward the inner side.   5. The via pad to be bonded to the first pad formed on one surface of the first substrate and the second pad formed on one surface of the second substrate is formed at both ends of the via. Interposer as described in any one.   6. The semiconductor device according to claim 1, further comprising a second via penetrating from one surface of the insulating layer to the other surface, electrically connected to the first substrate and the second substrate, and formed at an edge of the insulating layer. The interposer as described in A metal layer is formed on an inner surface of the plurality of first cavities and an inner surface of the plurality of second cavities;
The interposer according to claim 6, wherein the metal layer is electrically connected to the second via.   The interposer according to any one of claims 1 to 6, wherein a metal layer is formed on an inner surface of the plurality of first cavities and an inner surface of the plurality of second cavities.   The interposer according to any one of claims 1 to 8, wherein at least one of the plurality of first cavities accommodates at least two of the plurality of first electronic elements.   The interposer according to any one of claims 1 to 9, wherein at least one of the plurality of first cavities is vertically merged with at least one of the plurality of second cavities. In an interposer for connecting a first substrate having a plurality of first electronic elements mounted on one surface and a second substrate having a plurality of second electronic elements mounted on one surface,
An insulating layer disposed between the first substrate and the second substrate such that one surface faces one surface of the first substrate and the other surface faces one surface of the second substrate;
A plurality of first cavities open to the one side and containing the plurality of first electronic elements;
A plurality of second cavities open to the other surface and containing the plurality of second electronic elements;
A via penetrating from one surface of the insulating layer to the other surface and electrically connecting the first substrate and the second substrate;
The insulating layer is composed of a plurality of layers,
The via may include a via conductor formed so as to be stacked vertically on each of the plurality of layers of the insulating layer. A first substrate having a plurality of first electronic elements mounted on one surface;
A second substrate having a plurality of second electronic elements mounted on one surface;
An interposer for connecting the first substrate and the second substrate;
The interposer is
An insulating layer disposed between the first substrate and the second substrate such that one surface faces one surface of the first substrate and the other surface faces one surface of the second substrate;
A plurality of first cavities open to the one side and containing the plurality of first electronic elements;
A plurality of second cavities open to the other surface and containing the plurality of second electronic elements;
A via penetrating from one surface of the insulating layer to the other surface and electrically connecting the first substrate and the second substrate;
The via is a printed circuit board that passes between the plurality of first cavities and between the plurality of second cavities.   The printed circuit board according to claim 12, wherein the insulating layer includes a plurality of layers.   The printed circuit board according to claim 13, wherein the via includes a via conductor formed so as to be stacked up and down in the plurality of layers. The insulating layer is composed of three layers,
The printed circuit board according to claim 14, wherein the cross-sectional areas of via conductors formed in two layers located outside the three layers are smaller toward the inner side. A first pad is formed on one surface of the first substrate;
A second pad is formed on one surface of the second substrate;
Via pads are formed at both ends of the via,
The printed circuit board according to claim 12, wherein the via pad is bonded to the first pad and the second pad.   The printed circuit board according to claim 16, wherein solder is interposed between the via pad and the first pad and between the via pad and the second pad.   18. The semiconductor device according to claim 12, further comprising a second via penetrating from one surface of the insulating layer to the other surface, electrically connected to the first substrate and the second substrate, and formed at an edge of the insulating layer. A printed circuit board according to claim 1. A metal layer is formed on an inner surface of the plurality of first cavities and an inner surface of the plurality of second cavities;
The printed circuit board according to claim 18, wherein the metal layer is electrically connected to the second via.   The printed circuit board according to any one of claims 12 to 18, wherein a metal layer is formed on an inner surface of the plurality of first cavities and an inner surface of the plurality of second cavities.   21. The printed circuit board according to claim 20, wherein a heat dissipation member is interposed between the metal layer and the plurality of first electronic elements, and between the metal layer and the plurality of second electronic elements.   The printed circuit board according to claim 12, wherein at least one of the plurality of first cavities accommodates at least two of the plurality of first electronic elements.   23. The printed circuit board according to claim 12, wherein at least one of the plurality of first cavities is vertically merged with at least one of the plurality of second cavities.   The printed circuit board according to claim 12, further comprising a third electronic element mounted on the other surface of the first substrate. A first substrate having a plurality of first electronic elements mounted on one surface;
A second substrate having a plurality of second electronic elements mounted on one surface;
An interposer for connecting the first substrate and the second substrate;
The interposer is
An insulating layer disposed between the first substrate and the second substrate such that one surface faces one surface of the first substrate and the other surface faces one surface of the second substrate;
A plurality of first cavities open to the one side and containing the plurality of first electronic elements;
A plurality of second cavities open to the other surface and containing the plurality of second electronic elements;
A via penetrating from one surface of the insulating layer to the other surface and electrically connecting the first substrate and the second substrate;
The insulating layer is composed of a plurality of layers,
The via includes a via conductor formed so as to be stacked vertically on each of the plurality of layers of the insulating layer.