JP2019110938A - Game machine - Google Patents

Abstract

To suppress instability of light emission of light emitting means.SOLUTION: A game machine includes: light emitting means capable of emitting light in a prescribed mode; data storage means storing drive data corresponding to a light emission mode in which light is emitted by the light emitting means to a prescribed region; light emission driving means outputting a control signal based on the drive data stored to the data storage means to the light emitting means; and data setting means setting drive data to the prescribed region of the data storage means. The data setting means sets new drive data when a driving data number reaches a reference data number that the drive data set to the prescribed region of the data storage means can be stored in the prescribed region.SELECTED DRAWING: Figure 43

Description

  The present invention relates to a gaming machine such as a pachinko machine, for example.

  Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery.

  As this type of game machine, a game machine provided with a display device that emits light by backlight is disclosed (see, for example, Patent Document 1).

JP, 2016-159026, A

  However, for example, when the luminance of the light emitting means of the backlight is unstable, the display of the effect image on the display device may be unstable, which is not preferable.

  The present invention has been made in view of such a point, and an object thereof is to provide a gaming machine which can suppress the light emission of the light emitting means from becoming unstable.

The gaming machine according to the present invention is
Light emitting means (eg, backlight) capable of emitting light in a predetermined mode;
Data storage means (for example, data area of FIFO) for storing drive data (for example, luminance data) corresponding to the light emission mode emitted by the light emission means in a predetermined area;
A light emission drive unit (for example, an LSI) which outputs a control signal based on the drive data stored in the data storage unit to the light emission unit;
Data setting means (for example, host control circuit 210 for executing the process of step S346) for setting the drive data in a predetermined area of the data storage means;
Equipped with
The data setting means
The drive data set in the predetermined area of the data storage means is configured to set the new drive data when the number of drive data that can be set in the predetermined area becomes the reference data number. I assume.

  According to the above-mentioned gaming machine, when the number of drive data which can be stored in the predetermined area becomes equal to the reference data number, the drive data set in the predetermined data area is set with the new drive data. A control signal (for example, a signal corresponding to a PWM continuously output from the serial data output terminal of SPI) output by the means can be output, and the light emitting means emits light stably without passing through the driver Is possible.

  The above “reference data number” corresponds to 1 to 64 if the number of data that can be set in a predetermined area (for example, the data area of FIFO) of the data storage means is, for example, 64 or less. In view of the fact that it is necessary to prevent the number of data set in a predetermined area of the storage unit from becoming zero, it is preferable that the number is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more luminance data can be set. Thus, when there are two or more luminance data that can be set in the FIFO data area, for example, if the luminance data set in the FIFO data area falls below the first number (for example, two), the second number For example, one piece of luminance data may be replenished.

  According to the present invention, it is possible to prevent the light emission of the light emitting means from becoming unstable.

It is a figure showing a functional flow of a pachinko game machine concerning one embodiment of the present invention. It is an appearance perspective view of a pachinko game machine concerning one embodiment of the present invention. It is an exploded perspective view of a pachinko game machine concerning one embodiment of the present invention. It is a front view showing the composition of the game board of the pachinko game machine concerning one embodiment of the present invention. It is a block diagram showing the circuit composition of the pachinko game machine concerning one embodiment of the present invention. It is a block diagram which shows the internal structure of the subcontrol circuit of the pachinko game machine which concerns on one Embodiment of this invention. It is a block diagram showing an internal configuration of a voice and LED control circuit of a pachinko gaming machine according to an embodiment of the present invention. It is a figure for demonstrating an example of the output signal of the audio | voice / LED control circuit in the pachinko game machine which concerns on one Embodiment of this invention. It is a control block diagram for explaining an example of volume control by a host control circuit in a pachinko gaming machine according to an embodiment of the present invention. It is a schematic connection block diagram between the built-in relay board and speaker of a pachinko game machine concerning one embodiment of the present invention. It is a block diagram showing an internal configuration of a display control circuit of a pachinko gaming machine according to an embodiment of the present invention. It is a general | schematic connection block diagram between the sub board | substrate and CGROM board | substrate (NOR type | mold) of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a general | schematic connection block diagram between the sub board | substrate and CGROM board | substrate (NAND type | mold) of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a truth table for demonstrating the operation | movement of the AND circuit provided in the sub board | substrate of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a truth table for explaining the operation of the bidirectional balance transceiver provided on the sub substrate of the pachinko gaming machine according to an embodiment of the present invention. It is a figure which shows an example of the big hit random number determination table (at the time of 1st starting opening prize winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit random number determination table (at the time of 2nd starting opening prize winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the symbol determination table (at the time of 1st starting opening prize winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the symbol determination table (at the time of 2nd starting opening prize winning) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit type determination table (the 1) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit type determination table (the 2) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit type determination table (the 3) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit kind determination table (the 4) in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the presentation information determination table at the time of a prize in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the fluctuation production pattern determination table in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the fluctuation production table in the pachinko game machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the outline | summary of the drawing process in the pachinko game machine which concerns on one Embodiment of this invention. The pachinko game machine which concerns on one Embodiment of this invention WHEREIN: It is a flowchart which shows an example of the main-control main process performed by main CPU. It is a flow chart which shows an example of special symbol control processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of special symbol memory check processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of special symbol display time management processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of big hit end interval processing in a pachinko game machine concerning one embodiment of the present invention. In a pachinko gaming machine according to an embodiment of the present invention, it is a flowchart showing an example of a system timer interrupt process executed by the main CPU. It is a flowchart which shows an example of the switch input detection process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flow chart which shows an example of starting opening winning a prize detection processing in a pachinko game machine concerning one embodiment of the present invention. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows one example of the secondary control main processing which is executed by the host control circuit (the secondary control circuit). It is a flowchart which shows an example of the timer interrupt process performed by the host control circuit (sub control circuit) in the pachinko game machine which concerns on one Embodiment of this invention. The pachinko game machine which concerns on one Embodiment of this invention WHEREIN: It is a figure which shows an example for demonstrating the sub device input discrimination | determination information produced. It is a flowchart which shows an example of the sub device input process in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the sub device input ON edge information (with a repeat function) process in the pachinko gaming machine which concerns on one Embodiment of this invention. FIG. 40 is a flowchart continued from FIG. 40, showing an example of sub device input ON edge information (with repeat function) processing in a pachinko gaming machine according to an embodiment of the present invention. It is a figure for demonstrating notionally the backlight control processing in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the backlight control processing in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the timer interrupt process accompanying the modification of the backlight control processing in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows the modification of the backlight control processing in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the timer interrupt process which shows the backlight control process in the pachinko game machine which concerns on one Embodiment of this invention. In the pachinko game machine which relates to one execution form of this invention, it is the secondary control main processing (entire flow) which is executed by the host control circuit in order to explain the 1st example of processing of brightness adjustment of back light and various LEDs . In the pachinko game machine which relates to one execution form of this invention, it is the sub control main processing (entire flow) which is executed by the host control circuit in order to explain the 2nd example of processing of brightness adjustment of back light and various LEDs . In the pachinko game machine which relates to one execution form of this invention, it is the secondary control main processing (entire flow) which is executed by the host control circuit in order to explain the 3rd example of processing of brightness adjustment of back light and various LEDs . It is a flow chart which shows an example of RTC acquisition processing in a pachinko game machine concerning one embodiment of the present invention. It is a flow chart which shows an example of animation control main processing in a pachinko game machine concerning one embodiment of the present invention. It is a flowchart which shows an example of the composition reproduction | regeneration control processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the sound amplifier check process in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the amplifier check process for usual in the pachinko game machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the amplifier check process for super low tones in the pachinko game machine which concerns on one Embodiment of this invention. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows one example of the sound amplifier check processing which does the amplifier for the usual / the bass amplifier (collective) check processing. It is a flowchart which shows an example of the more preferable form of the sound amplifier check process in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the more preferable form of the amplifier check process for normal / bass in the pachinko gaming machine which concerns on one Embodiment of this invention. FIG. 59 is a flowchart continued from FIG. 58, showing an example of a more preferable form of the normal amplifier / bass amplifier check process in the pachinko gaming machine according to the embodiment of the present invention. In a pachinko game machine concerning one embodiment of the present invention, it is a flow chart which shows an example of sound request control processing when there are a plurality of sound requests to the same channel. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows the 1st execution example of the sound request control processing when volume adjustment is done. In the pachinko gaming machine which relates to one execution form of this invention, it is the flowchart which shows the 2nd execution example of the sound request control processing when volume adjustment is done. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows the 3rd execution example of the sound request control processing when volume adjustment is done. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows the 4th execution example of the sound request control processing when volume adjustment is done. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows the 5th example of sound request control processing when volume adjustment is done. The pachinko game machine which concerns on one Embodiment of this invention WHEREIN: It is an attenuation table which shows an example of the luminance attenuation value of each color (red, green, blue) according to the light emission intensity of strong, medium, and weak LED. The pachinko game machine which concerns on one Embodiment of this invention WHEREIN: It is a block diagram which shows an example of the connection state of LED port, LED, and a solenoid. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows one example of the data loading processing which is executed as one of various initialization processings with the host control circuit. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows one example of random number initialization processing which is executed as one of various initialization processings with the host control circuit. It is a flow chart which shows an example of random number regular updating processing in a pachinko game machine concerning one embodiment of the present invention. (A) A flowchart showing an example of random number 1 acquisition processing, (b) a flowchart showing an example of random number 2 acquisition processing, and (c) an example of random number 3 acquisition processing in a pachinko gaming machine according to an embodiment of the present invention 6 is a flowchart showing an example of (d) random number 4 acquisition processing. In a pachinko game machine concerning one embodiment of the present invention, it is a flow chart which shows an example of random number acquisition processing performed when random numbers are used. In the pachinko game machine which relates to one execution form of this invention, it is the secondary control main processing (entire flow) which is executed by the host control circuit in order to explain the modification of sub random number processing. In the pachinko game machine which relates to one execution form of this invention, it is the flowchart which shows one example of the reception interruption processing which is executed by the host control circuit.

  Hereinafter, the configuration and various operations of a pachinko gaming machine (game machine) according to an embodiment of the present invention will be described with reference to the drawings.

<Function flow>
First, with reference to FIG. 1, functions of the pachinko gaming machine according to the present embodiment will be described. FIG. 1 is a diagram showing a functional flow of the pachinko gaming machine according to the present embodiment.

  The pachinko game, as shown in FIG. 1, is a game in which a game ball is fired by the user's operation, and when the game ball wins various prizes, payout control processing of the game ball is performed. In addition, the pachinko game includes a special symbol game using a special symbol and an ordinary symbol game using an ordinary symbol. When a "big hit" in a special symbol game or a normal symbol game results in a "hit", the possibility that the game ball will win is relatively increased, and the game ball payout control processing is easily performed. Become.

  In addition, for various winnings, special symbol start winning which is one condition for performing variable display of special symbol in special symbol game, and one condition for performing variable display of normal symbol in normal symbol game It also includes a certain normal symbol start winning game.

  Note that "variable display" as used in the present specification is a concept that can be displayed in a variable manner, for example, "variation display" that is actually displayed as it is changed, or "stop display that is actually stopped and displayed. And so on. In "variable display", for example, "derivative display" can be performed in which a special symbol (identification information) is displayed as a result of the special symbol game. That is, in the present specification, the operation from the start of the “variable display” to the “derivative display” is referred to as one “variable display”. Furthermore, in the present specification, "identification information" refers to "patterns" used in pachinko games such as special symbols, normal symbols, decorative symbols, identification symbols, etc., and identification symbols or decorations used in pachislot or slot games It means that it may include a symbol used when displaying or suggesting the result of a game when a player plays a game, such as a symbol, and various symbols in the embodiment and various modifications described below are also included. May be included.

  Hereinafter, an outline of the processing flow of the special symbol game and the normal symbol game will be described.

(1) Special symbol game When there is a special symbol start winning in the special symbol game, random numbers (big hit determination random number and symbol determination random number) are extracted from the big hit determination counter and the symbol determination counter, respectively. The extracted random number values are stored (see the flow of the special symbol start winning process in the special symbol game shown in FIG. 1).

  Further, as shown in FIG. 1, in the special symbol control process during the special symbol game, it is first determined whether a condition for starting variable display of the special symbol is established. In this determination processing, it is referred to whether or not the random number value is stored by the special symbol start winning, and the condition to start the variable display of the special symbol is established with the random number value stored as one condition. judge.

  Next, when the variable display of the special symbol is started, the jackpot determination random number value extracted from the jackpot determination counter is referred to, and the jackpot determination of whether or not to make the "big hit" is performed. Thereafter, stop symbol determination processing is performed. In this processing, the symbol determination random number value extracted from the symbol determination counter and the result of the above-described big hit determination are referred to, and the special symbol to be displayed in a stopped state is determined.

  Next, a fluctuation pattern determination process is performed. In this process, a random number value is extracted from the fluctuation pattern determination counter, and the random pattern value, the result of the above-described big hit determination, and the special symbol to be displayed for stop described above are referenced to determine the fluctuation pattern of the special symbol.

  Next, an effect pattern determination process is performed. In this process, random number values are extracted from the effect pattern determination counter, and the random number values, the result of the above-described big hit determination, the special symbol to be displayed in the stop mentioned above, and the variation pattern of the special symbol mentioned above are referred to. The effect pattern to be executed along with the variable display of the special symbol is determined.

  Next, a variable display control process for controlling the variable display of the special symbol with reference to the special symbol to be stopped and displayed, the variation pattern of the special symbol, and the effect pattern accompanying the variable display of the special symbol as a result of the determined big hit determination. And, production control processing which performs specified production is executed.

  Then, when the variable display control process and the effect display control process are finished, it is determined whether or not the "big hit" is to be made. In this determination process, when it is determined that the "big hit" has been made, a big hit game control process for playing a big hit game is executed. In the big hit game, the possibility of the various winnings mentioned above increases. On the other hand, when it is determined that the "big hit" has not been made, the big hit game control process is not executed.

  If it is determined that the "big hit" has not been made, or if the big hit game control process has ended, a game state transition control process is performed to shift the game state. In this gaming state transition control process, management of the gaming state at the normal time which is different from the big hit gaming state is performed. As the gaming state at the normal time, for example, in the above-described jackpot determination, the gaming state in which the probability of being determined as a "big hit" increases (hereinafter referred to as "probability variation gaming state") or special symbol start winning is easily obtained The gaming state (hereinafter referred to as "time-saving gaming state") and the like can be mentioned. Thereafter, it is determined again whether or not to start the variable display of the special symbol, and thereafter, the various types of processing of the special symbol control processing described above are repeated.

  In the pachinko gaming machine of the present embodiment, when the game ball starts winning while displaying the special symbol, various data (big hit determination random number value, symbol determination random number value, etc.) acquired at the start winning combination ) Is put on hold. That is, when the game ball wins a starting prize during the variation display of the special symbol, the variable display (variation display) of the special symbol corresponding to the starting prize is suspended, and after the variation display of the special symbol currently being executed is ended. Variable display of the special symbol held is started. Below, the variable display of the special symbol held is also referred to as a "holding ball".

  In addition, in the pachinko gaming machine of this embodiment, as described later, two types of special symbol start winnings (first start opening winning and second starting opening winning) are provided, and a maximum of four for each special symbol starting winning You can get hold ball of. That is, in the present embodiment, a maximum of eight holding balls can be obtained.

  Furthermore, although the pachinko gaming machine of the present embodiment is not shown in FIG. 1, it determines the hit of the holding ball (presence or absence of “big hit” winning) based on the information of the holding ball described above, and further determines the judgment result. It also has a function to perform a predetermined effect based on it, that is, a pre-reading effect function.

(2) Normal symbol game If there is a normal symbol start winning in the normal symbol game, a random number value is extracted from the hit determination counter, and the random number value is stored (the normal symbol game shown in FIG. Refer to the flow of the symbol start winning process).

  Further, as shown in FIG. 1, in the normal symbol control process during the normal symbol game, first, it is determined whether or not a condition for starting variable display of the normal symbol is established. In this determination process, it is referred to whether or not the random number value is stored by the normal symbol starting winning, and the condition to start the variable display of the normal symbol is established with the random number value stored as one condition. judge.

  Then, when the variable display of the normal symbol is started, the random number value extracted from the hit determination counter is referred to, and a hit determination is made as to whether or not to make it a "hit". Thereafter, fluctuation pattern determination processing is performed. In this process, the result of the hit determination is referred to, and the variation pattern of the normal symbol is determined.

  Next, the variable display control process for controlling the variable display of the normal symbol and the effect control process for performing a predetermined effect are executed with reference to the determined result of the hit determination and the variation pattern of the normal symbol.

  When the variable display control process and the effect display control process are finished, it is determined whether or not a "hit" is to be made. In this determination process, when it is determined that "hit" is to be made, a hit game control process for performing a hit game is executed. In the hit game control process, the possibility of the various winnings mentioned above, in particular, the possibility of the special symbol starting winning of the gaming ball in the special symbol game is increased. On the other hand, if it is determined that "hit" is not made, the hit game control processing is not executed. Thereafter, determination processing as to whether or not to start variable symbol display of the normal symbol is performed again, and thereafter, various processing of the above-mentioned normal symbol control processing is repeated.

  As described above, in the pachinko game, the payout control of the game ball according to conditions such as whether or not the "big hit" in the special symbol game, the transition state of the gaming state, or the "hit" in the normal symbol game. The ease of treatment varies.

  In the present embodiment, a soft random number system that generates random number values by executing a program is used as a method of extracting various random number values. However, the present invention is not limited to this, and for example, when the pachinko gaming machine includes a random number generator in which random numbers are updated at a predetermined cycle, random number values from counters (so-called ring counters) in the random number generator. A hard random number system for extracting H may be adopted as an extraction system of various random number values described above. When the hard random number method is used, it is possible to prevent extraction of the same random value in a predetermined cycle by determining the initial value of the random number at a timing different from the predetermined cycle.

<Structure of Pachinko Machine>
Next, with reference to FIG. 2 and FIG. 3, the structure of the pachinko gaming machine in the present embodiment will be described. FIG. 2 is a perspective view showing the appearance of the pachinko gaming machine. FIG. 3 is an exploded perspective view of the pachinko gaming machine.

  As shown in FIGS. 2 and 3, the pachinko gaming machine 1 is a main body 2, a base door 3 attached to the main body 2 so as to be openable and closable, and a glass door attached to the base door 3 so as to be openable and closable. And 4.

[Body]
The main body 2 is formed of a frame-like member having a rectangular opening 2a (see FIG. 3). The main body 2 is formed of, for example, a material such as wood.

[Base door]
The base door 3 is formed of a plate-like member having a rectangular outer shape substantially equal to the outer shape of the main body 2. The base door 3 is disposed in front of the main body 2 (front side of the pachinko gaming machine 1), and the base door 3 is pivoted around one side edge of the main body 2 as an axis. The opening 2a is opened and closed. As shown in FIG. 3, the base door 3 is provided with a rectangular opening 3 a. The opening 3a is formed over a region from the substantially central portion of the base door 3 to the upper side, and is formed so as to occupy most of the region.

  Further, the speaker 11, the game board 12, the display device 13, the plate unit 14, the launcher 15, the payout device 16, and the substrate unit 17 are attached to the base door 3.

  The speaker 11 is disposed at the upper portion (near the upper end portion) of the base door 3. The game board 12 is disposed in front of the base door 3 (front side of the pachinko gaming machine 1), and is disposed to cover the opening 3a of the base door 3.

  The game board 12 is formed of a plate-shaped resin member having light transparency. In addition, as resin which has light transmittance, an acrylic resin, polycarbonate resin, methacryl resin etc. can be used, for example.

  Further, on the front surface of the game board 12 (the front surface of the pachinko gaming machine 1), a game area 12a is formed in which the game balls fired from the launch device 15 roll. The game area 12a is an area surrounded by the guide rails 41 (specifically, the outer rails 41a shown in FIG. 4 described later), and the outer peripheral shape thereof is substantially circular. Furthermore, in the game area 12a, a plurality of game nails (see FIG. 4 described later) are inserted. The structure of the game board 12 (game area 12a) will be described in detail later with reference to FIG. 4 described later.

  The display device 13 is attached to the back side of the game board 12 (opposite to the front side of the pachinko gaming machine 1). The display device 13 has a display area 13a for displaying an image. The size of the display area 13a is set so as to occupy the whole or a part of the surface of the game board 12. In the display area 13a of the display device 13, various images such as an identification symbol for effect, an effect image, and an image for decoration (decorative symbol) are displayed based on the result of the lottery process of the special symbol described later. The player can visually recognize various images displayed in the display area 13 a of the display device 13 through the game board 12.

  In the present embodiment, a liquid crystal display device is used as the display device 13. However, the present invention is not limited to this, and, for example, a display device such as a plasma display, a rear projection display, or a CRT (Cathode Ray Tube) display may be applied as the display device 13.

  Further, a spacer 19 is provided on the back side of the game board 12 (the side opposite to the front side of the pachinko gaming machine 1). The spacer 19 is provided between the back surface of the game board 12 (the front surface of the pachinko game machine 1) and the front surface of the display device 13 (the front surface of the pachinko game machine 1). A space to be a flow path of the game ball rolling on the area 12a is formed. The spacer 19 is formed of a light transmitting material. In addition, this invention is not limited to this, For example, one part may be formed with the material which has light transmittance, and may be formed with the material which does not have light transmittance. .

  The tray unit 14 is disposed below the gaming board 12. The tray unit 14 has an upper tray 21 and a lower tray 22 disposed below the upper tray 21. As shown in FIG. 2, the upper tray 21 and the lower tray 22 are respectively provided with a payout opening 21 a and a payout opening 22 a for lending the gaming balls and paying out the gaming balls (prize balls). When a predetermined payout condition is satisfied, gaming balls are discharged from the payout opening 21a and the payout opening 22a, and are stored in the upper tray 21 and the lower tray 22, respectively. In addition, the game balls stored in the upper tray 21 are fired by the launcher 15 to the game area 12 a.

  Further, the dish unit 14 is provided with an effect button 23. The effect button 23 is mounted on the upper tray 21. Further, a dial operation unit (jog dial) 24 is rotatably attached to the periphery of the effect button 23 with respect to the effect button 23. The pachinko gaming machine 1 of the present embodiment has a predetermined effect function performed using the effect button 23 and / or the dial operation unit 24, and when performing a predetermined effect, in the display area 13 a of the display device 13, An image prompting the user to operate the effect button 23 and / or the dial operation unit 24 is displayed.

  The launcher 15 is disposed in the lower right region (near the lower right corner) on the front surface of the base door 3. The launcher 15 includes a launch handle 25 operable by the player and a panel 26 engaged with the lower right portion of the tray unit 14. The firing handle 25 is disposed on the front side of the panel body 26 and is rotatably supported by the panel body 26.

  Although not shown in FIGS. 2 and 3, on the back side of the panel body 26, a solenoid actuator (drive device) for controlling the firing operation of the game balls is provided. Also, although not shown in FIGS. 2 and 3, a touch sensor is provided at the periphery of the firing handle 25, and a firing volume is provided inside the firing handle 25. The firing volume changes the resistance according to the amount of rotation of the firing handle 25 to change the power supplied to the solenoid actuator.

  In the pachinko gaming machine 1 of the present embodiment, when the player's hand contacts the touch sensor of the launch handle 25, the touch sensor outputs a detection signal. As a result, it is detected that the player grips the firing handle 25, and the firing of the gaming ball by the solenoid actuator is enabled. Then, when the player holds the firing handle 25 and rotates it clockwise (clockwise when viewed from the player), the resistance value of the firing volume changes in accordance with the pivot angle of the firing handle 25. Power corresponding to the resistance value is supplied to the solenoid actuator. As a result, the gaming balls stored in the upper tray 21 are sequentially fired, and the launched gaming balls are guided to the guide rails 41 (see FIG. 4 described later) and released to the gaming area 12 a of the gaming board 12.

  Also, although not shown in FIGS. 2 and 3, the side of the firing handle 25 is provided with a firing stop button. The firing stop button is a button provided to stop the firing of the game ball by the solenoid actuator. When the player depresses the release stop button, the release of the game ball is stopped even in a state in which the release handle 25 is held and turned.

  The dispensing device 16 and the substrate unit 17 are disposed on the back side of the base door 3. The game apparatus is supplied to the payout device 16 from a storage unit (not shown). The payout device 16 pays out a predetermined number of gaming balls to the upper tray 21 or the lower tray 22 from the gaming balls supplied from the storage unit based on the fulfillment of the payout conditions. The substrate unit 17 has various control substrates. The various control boards are provided with a main control circuit 70 and a sub control circuit 200 which will be described later (see FIG. 5 described later).

[Glass door]
The glass door 4 is comprised by the plate-shaped member whose surface is a substantially square shape. The glass door 4 is disposed on the front side of the game board 12 and has a size that covers the game board 12. A speaker cover 29 is provided in an upper region facing the speaker 11 on the front surface of the glass door 4.

  Further, in the central portion of the glass door 4, an opening 4a of a size that exposes at least the game area 12a is formed in the area facing the game area 12a of the game board 12. A light transmitting protective glass 28 is attached to the opening 4a of the glass door 4, whereby the opening 4a is closed. Therefore, when the glass door 4 is closed to the base door 3, the protective glass 28 is disposed to face at least the game area 12 a of the game board 12.

[Game board]
Next, the configuration of the game board 12 will be described with reference to FIG. FIG. 4 is a front view showing the configuration of the game board 12.

  On the front of the game board 12, as shown in FIG. 4, a guide rail 41, a ball passage detector 43, a first starting opening 44, a second starting opening 45 (starting area), and an ordinary electric role 46 And are provided. Also, on the front of the game board 12, there are a plurality of general winning openings 51 and 52, a first large winning opening 53 (variable winning device), a second large winning opening 54 (variable winning device), and a plurality of out-openings 55 Game nails 56 are provided. Furthermore, on the front of the game board 12, a special symbol display device 61, a normal symbol display device 62, and a normal symbol hold display device 63 are provided in the upper part of the display area 13a of the display device 13 disposed substantially in the center. A first special symbol hold display 64 and a second special symbol hold display 65 are provided.

  Although not shown in FIG. 4, a 7-segment counter for effect is also provided on the front of the game board 12. The 7-segment counter for effect is composed of a display counter capable of displaying two-digit numbers and two alphabets. Moreover, in the present embodiment, a notification LED (Light Emitting Diode) which lights up when the result of the stop display of the special symbol is "big hit", a round number display LED which displays the number of rounds in the big hit game, etc. It is also good.

[Various components of the game area]
The guide rail 41 is configured of an outer rail 41a extending in an arc shape partitioning the gaming area 12a, and an inner rail 41b extending in an arc shape disposed on the inner side (inner circumferential side) of the outer rail 41a. Be done. The game area 12a is formed inside the outer rail 41a. The outer rail 41a and the inner rail 41b are arranged to face each other near the left end of the game area 12a when viewed from the player side, whereby a launcher is provided between the outer rail 41a and the inner rail 41b. A guide path 41c is formed which guides the game ball fired by the camera 15 to the top of the game area 12a.

  Further, at the end of the inner rail 41b located on the upper left side of the game area 12a, a ball discharge port 41d is formed by the end of the inner rail 41b and a part of the outer rail 41a opposed thereto. A ball return prevention piece 42 is provided at the end of the inner rail 41b so as to close the ball outlet 41d. The ball return prevention piece 42 prevents the game balls discharged from the ball discharge opening 41d to the game area 12a from passing through the ball discharge opening 41d again and entering the guide path 41c.

  The game balls discharged from the ball discharge opening 41d flow downward from the top of the game area 12a. At this time, the game ball collides with various members provided in the game area 12a such as the plurality of game nails 56, the first starting opening 44, the second starting opening 45, etc., and changes the traveling direction of the game area 12a. Flow down from the top to the bottom.

  A display area 13a of the display device 13 is provided substantially at the center of the game area 12a. An obstacle 13 b is provided at the upper end of the display area 13 a. By providing the obstacle 13b, the gaming ball does not pass over the area overlapping the display area 13a in the gaming area 12a.

  The ball passing detector 43 is disposed near the right end of the display area 13a as viewed from the player. The ball passage detector 43 is provided with a passage ball sensor 43a (see FIG. 5 described later) for detecting gaming balls passing through the ball passage detector 43. Further, by the game ball passing through the ball passage detector 43, a lottery is performed to determine whether it is a "hit" or not, and the variation display of the normal symbol is started based on the result of the lottery.

  The first start opening 44 is disposed below the display area 13 a, and the second start opening 45 is disposed below the first start opening 44. The first starting opening 44 and the second starting opening 45 are made of members capable of receiving game balls. Hereinafter, that the game ball enters or passes through the first starting opening 44 or the second starting opening 45 is referred to as "winning". Then, when the gaming ball wins the first starting opening 44 or the second starting opening 45, a first predetermined number (three in the present embodiment) of gaming balls are paid out. In addition, by the game ball entering the first starting opening 44, the lottery whether or not it is either "big hit" and "small hit" is performed, the variation of the special symbol based on the result of the lottery Display starts. Further, by the game ball entering the second starting opening 45, a lottery for "big hit" is performed, and the variation display of the special symbol is started based on the result of the lottery.

  The first starting opening 44 is provided with a first starting opening winning ball sensor 44 a (see FIG. 5 described later) for detecting a game ball that has won a prize in the first starting opening 44. In addition, the second starting opening 45 is provided with a second starting opening winning ball sensor 45a (see FIG. 5 described later) for detecting a game ball winning a prize in the second starting opening 45. In addition, the game ball which has won the first start port 44 and the second start port 45 passes through the recovery port (not shown) provided on the game board 12 and is conveyed to the recovery section (not shown) of the game ball .

  The ordinary motor-operated part 46 is provided at the second start port 45. The common electric combination 46 includes a pair of blade members rotatably mounted on both sides of the second starting port 45, and a common combination electric solenoid 46a (see FIG. 5 described later) for driving the pair of blade members. Have. The ordinary electric character 46 is driven by the ordinary electric character solenoid 46a to expand the pair of wing members to facilitate winning of the game ball in the second starting opening 45 and to close the pair of wing members. The second starting port 45 generates one state of the closed state which makes it impossible to win the game ball. In the present embodiment, when the ordinary motorized character 46 is in the closed state, the opening form of the pair of wing members is not a form that makes winning impossible, but a form that makes winning of the game ball difficult. It is also good.

  The general winning opening 51 is disposed near the lower left portion of the game area 12a as viewed from the player. The general winning opening 52 is disposed below the ball passage detector 43, and is disposed near the lower right portion of the game area 12a as viewed from the player. The general winning opening 51 and the general winning opening 52 are made of members capable of receiving game balls. In the following, the game ball entering or passing through the general winning opening 51 or the general winning opening 52 is also referred to as "winning". When the game balls are won in the general winning opening 51 or the general winning opening 52, a second predetermined number (10 in the present embodiment) of game balls are paid out.

  In the general winning opening 51, a general winning ball sensor 51a (see FIG. 5 described later) for detecting a game ball that has won in the general winning opening 51 is provided. In addition, the general winning opening 52 is provided with a general winning ball sensor 52a (see FIG. 5 described later) for detecting the gaming ball that has won the general winning opening 52.

  The first large winning opening 53 and the second large winning opening 54 are disposed below the ball passage detector 43 and between the first starting opening 44 and the general winning opening 52. The first big winning opening 53 and the second big winning opening 54 are arranged vertically along the flow path of the game ball, and the first big winning opening 53 is arranged above the second big winning opening 54. Ru. The first large winning opening 53 and the second large winning opening 54 are both so-called attacking type opening and closing devices, and can be opened and closed shutters 53a and 54a and a solenoid actuator for driving the shutters (the first in FIG. A large winning opening solenoid 53b and a second large winning opening solenoid 54b).

  Each of the first large winning opening 53 and the second large winning opening 54 receives the game ball when the corresponding shutter is open (opened), and plays the game when the shutter is closed (closed) I do not accept the ball. Hereinafter, the game ball entering or passing through the first large winning opening 53 or the second large winning opening 54 is also referred to as a "winning". When the game ball is won in the first large winning opening 53, the game balls of the third predetermined number ball (10 in the present embodiment) are paid out. On the other hand, when the game ball is won in the second big winning opening 54, the game balls of the fourth predetermined number ball (15 in the present embodiment) are paid out.

  Further, a count sensor 53c (see FIG. 5 described later) for counting gaming balls having won a prize in the first large winning opening 53 is provided in the first large winning opening 53. Furthermore, a count sensor 54c (see FIG. 5 described later) for counting gaming balls that have won a prize in the second large winning opening 54 is provided in the second large winning opening 54.

  The out port 55 is provided at the bottom of the game area 12a. A game in which the out opening 55 does not win any of the first starting opening 44, the second starting opening 45, the general winning opening 51, the general winning opening 52, the first large winning opening 53, and the second large winning opening 54 I accept the ball.

  When the arrangement of various components in the game area 12a of this embodiment is arranged as shown in FIG. 4, when the game ball is hit in the area on the right side of the game area 12a by the player (when hit right) The game ball is guided to the second starting opening 45 by the game nail 56 or the like. In this case, there is almost no possibility of winning the first starting opening 44. In the present embodiment, as described later, it is easier for the player to receive the “big hit” lottery, which is advantageous for the player, than when winning in the second start opening 45 wins in the first start opening 44. Therefore, in the "time saving game state" described later in which winning to the second starting opening 45 is relatively easy, the possibility of winning to the first starting opening 44 (convenient to the player by hitting the right) The possibility of becoming a gaming state can be reduced.

[Special symbol display device]
As shown in FIG. 4, the special symbol display device 61 is disposed substantially at the center of the upper portion of the display area 13 a of the display device 13.

  The special symbol display device 61 is a display device that variably displays (variation display and stop display) the special symbol in the special symbol game. In the present embodiment, as shown in FIG. 4, the special symbol display device 61 is configured by a device that displays a special symbol by a symbol made up of numbers, symbols, and the like. In addition, this invention is not limited to this, You may comprise the special symbol display device 61 by several LED, for example. In this case, a display pattern configured by turning on / off a plurality of LEDs is represented as a special symbol.

  The special symbol display device 61 performs variation display of the special symbol (identification information), triggered by the game ball winning in the first starting opening 44 or the second starting opening 45 (special symbol starting winning). Then, the special symbol display device 61 performs the change display of the special symbol for a predetermined time, and then performs the stop display of the special symbol. Hereinafter, the special symbol variably displayed on the special symbol display device 61 when the gaming ball wins the first starting opening 44 is referred to as a first special symbol. Also, when the gaming ball wins the second starting opening 45, the special symbol that is variably displayed on the special symbol display device 61 is referred to as a second special symbol.

  In the special symbol display device 61, when the first special symbol or the second special symbol stopped and displayed is a specific mode (a mode of "big hit"), the gaming state is advantageous to the player from the normal gaming state It shifts to the big hit game state which is a state. That is, in the special symbol display device 61, it is a "big hit" that the first special symbol or the second special symbol is stopped and displayed in the mode of shifting to the big hit gaming state.

  In the big hit game state, the first large winning opening 53 or the second large winning opening 54 is opened. Specifically, in the present embodiment, when the gaming ball wins the first starting opening 44 and the first special symbol is stopped and displayed in a specific mode in the special symbol display device 61, the first big winning opening 53 is open. On the other hand, when the gaming ball wins the second starting opening 45 and the second special symbol is stopped and displayed in a specific mode in the special symbol display device 61, the second big winning opening 54 is in the open state.

  The open state of each big winning opening is maintained until a predetermined number of game balls are won, or until a predetermined period (for example, 30 seconds) elapses. Then, when the elapsed period of the open state of each big winning opening satisfies any one of these conditions, the big winning opening that was in the open state is closed.

  Hereinafter, a game in which the first large winning opening 53 or the second large winning opening 54 is in a state (opened state) in which the game ball can be easily received is referred to as a round game. During the round game, the big winning opening is closed. In addition, the round game is counted as the number of rounds such as one round and two rounds. For example, the first round game is referred to as a first round, and the second round game is referred to as a second round.

  In addition, in the special symbol display device 61, when the special symbol stopped and displayed is an aspect other than the specific aspect (an aspect of “loss”), the gaming state does not shift except in the case of winning the fall lottery. That is, the special symbol game is a game in which the special symbol is variably displayed by the special symbol display device 61 and then the special symbol is stopped and displayed, and as a result, the gaming state is shifted or maintained.

  Further, in the pachinko gaming machine 1 of the present embodiment, when the game ball wins the first starting opening 44 during the variable display of the first special symbol or the second special symbol, the variable of the first special symbol corresponding to the winning The display (hold ball) is suspended. Then, when the first special symbol or the second special symbol in the variation display is stopped and displayed, the variation display of the held first special symbol is started. In the present embodiment, the number of variable displays of the first special symbol to be suspended (so-called "number of suspended balls (number of balls for suspension)") is specified at a maximum of four times (pieces).

  Furthermore, in the present embodiment, when the gaming ball wins the second starting opening 45 during the variable display of the first special symbol or the second special symbol, the variable display of the second special symbol corresponding to the winning (holding ball) Is put on hold. Then, when the first special symbol or the second special symbol in the variation display is stopped and displayed, the variation display of the held second special symbol is started. In the present embodiment, the number of variable displays of the second special symbol to be suspended (the number of suspended units) is specified at a maximum of 4 times (pieces). Therefore, in the present embodiment, the maximum number of reserved variable designs for special symbols is eight in total.

  Moreover, in this embodiment, when the holding ball of the first special symbol and the holding ball of the second special symbol are mixed, the variable display of one of the special symbols is executed preferentially to the variable display of the other special symbol. . In addition, this invention is not limited to this, When the holding ball of a 1st special symbol and the holding ball of a 2nd special symbol are mixed, you may make it perform the fluctuation display of a special symbol in the held order.

[Normal symbol display device]
The normal symbol display device 62 is disposed substantially at the center of the upper portion of the display area 13a of the display device 13, as shown in FIG. And, in the present embodiment, the normal symbol display device 62 is disposed on the right side of the special symbol display device 61 as viewed from the player side.

  The normal symbol display device 62 is a display device that variably displays (variable display and stop display) a normal symbol in a normal symbol game. In the present embodiment, as shown in FIG. 4, the normal symbol display device 62 is configured by two LEDs (normal symbol display LEDs) arranged in the vertical direction. Then, in the normal symbol display device 62, a display pattern configured by turning on / off each normal symbol display LED is indicated as a normal symbol.

  The normal symbol display device 62 alternately turns on / off the two normal symbol display LEDs in response to the game ball passing through the ball passage detector 43, and performs the variation display of the normal symbol. Then, the normal symbol display device 62 performs the variable display of the normal symbol for a predetermined time, and then performs the stop display of the normal symbol.

  In the normal symbol display device 62, when the normal symbol stopped and displayed is in a predetermined mode (a mode of "hit"), the normal motorized role 46 is changed from the closed state to the open state only for a predetermined period. On the other hand, when the normal symbol stopped and displayed is a mode other than the predetermined mode (a mode of “losing”), the normal motorized role 46 maintains the closed state. That is, the normal symbol game is a game in which the normal symbol is variably displayed by the normal symbol display device 62, and then the normal symbol is stopped and displayed, and the normal electric character 46 operates according to the result.

  When the gaming ball passes the ball passage detector 43 during the variation display of the normal symbol, the variable display of the normal symbol is suspended. Then, when the normal symbol in the variation display is stopped and displayed, the variation display of the suspended normal symbol is started. In the present embodiment, the number of variable displays of normal symbols to be suspended (that is, the "number of suspended units") is specified to be at most four times (pieces).

[Normal symbol hold display device]
The normal symbol hold display device 63 is disposed substantially at the center of the upper portion of the display area 13a of the display device 13, as shown in FIG. And, in the present embodiment, the normal symbol hold display device 63 is disposed below the special symbol display device 61 and the normal symbol display device 62.

  The normal symbol holding display device 63 is a device for displaying the number of holdings of the variable display of the normal symbol. In the present embodiment, as shown in FIG. 4, the normal symbol hold display device 63 is configured by four LEDs (normal symbol hold display LEDs) arranged in the left-right direction. Then, in the normal symbol holding display device 63, the number of holdings of variable symbols of normal symbols is displayed by turning on / off each normal symbol holding display LED.

  Specifically, when the number of pending variable symbols of normal symbols is one, the normal symbol suspension indicator LED (the first ordinary symbol suspension indicator LED from the left) located at the leftmost position seen from the player side Lights up and the other normal symbol hold display LED goes out. In the case where the number of held variable display of the normal symbol is 2, the first and second normal symbol hold display LEDs from the left light, and the other normal symbol hold display LEDs turn off. In the case where the number of held variable display of normal symbols is 3, the first to third normal symbol hold display LEDs from the left light and the other normal symbol hold display LEDs are extinguished. And, in the case where the number of pending variable display of normal symbols is four, all the normal symbol holding display LEDs are lit.

[First special symbol hold display device]
The first special symbol holding display device 64 is disposed on the left side of the special symbol display device 61 when viewed from the player side in the upper part of the display area 13a of the display device 13 as shown in FIG.

  The first special symbol hold display device 64 is a device that displays information on the variable display of the first special symbol being held (the holding ball of the first special symbol). In the present embodiment, as shown in FIG. 4, the first special symbol hold display device 64 is configured of a first special symbol hold number display unit 64 a and a first special symbol hold information display unit 64 b. And the first special symbol hold information display unit 64b is disposed on the left side of the special symbol display device 61, and the first special symbol hold number display unit 64a is disposed on the left side of the first special symbol hold information display unit 64b .

  The first special symbol hold number display unit 64a has four LEDs (first special symbol hold indication LED) arranged in the left-right direction. In addition, the display mode of the 1st special symbol holding number display part 64a is the same as the display mode of the normal symbol holding display device 63. That is, when the variable display of the first special symbol is being held, the first special symbol holding indication LED from the first special symbol holding indication LED located from the first special symbol holding indication LED located from the player side to the number of holdings as seen from the player side Lights up.

  In addition, the first special symbol hold information display unit 64b displays information on the hold ball of the first special symbol. For example, the first special symbol holding information display unit 64b displays information (identification information) related to the holding ball of the first special symbol to be variably displayed next by a symbol made of numerals, symbols, and the like. In addition, the configuration of the first special symbol hold display device 64 is not limited to the example shown in FIG. 4 and can be arbitrarily configured as long as it can display at least the number of pending variable displays of the first special symbol. .

[Second special symbol hold display device]
As shown in FIG. 4, the second special symbol hold display device 65 is disposed on the right side of the normal symbol display device 62 as viewed from the player on the upper side of the display area 13 a of the display device 13.

  The second special symbol hold display device 65 is a device for displaying information on the variable display of the second special symbol being held (the holding ball of the second special symbol). In the present embodiment, as shown in FIG. 4, the second special symbol hold display device 65 is configured of a second special symbol hold number display unit 65a and a second special symbol hold information display unit 65b. The second special symbol hold information display unit 65b is disposed on the right side of the normal symbol display device 62, and the second special symbol hold number display unit 65a is disposed on the right side of the second special symbol hold information display unit 65b. .

  The 2nd special symbol reservation number display part 65a has 4 LED (2nd special symbol suspension display LED) arranged in the left-right direction. In addition, the display mode of the 2nd special symbol hold number display part 65a is the same as the display mode of the normal symbol hold display apparatus 63. FIG. That is, when the variable display of the second special symbol is being held, the second special symbol holding indication LED from the second special symbol holding indication LED located at the leftmost position to the number of holdings as seen from the player side Lights up.

  In addition, the second special symbol hold information display unit 65b displays information on the holding ball of the second special symbol. For example, the second special symbol hold information display unit 65b displays information (identification information) regarding the holding ball of the second special symbol to be variably displayed next by a symbol made of numerals, symbols, and the like. In addition, the configuration of the second special symbol hold display device 65 is not limited to the example shown in FIG. 4 and can be arbitrarily configured as long as it can display at least the number of pending variable displays of the second special symbol. .

[Display device]
The display device 13 is configured by the liquid crystal display device as described above, and performs various image display effects in the display area 13a.

  Specifically, in the present embodiment, an effect image associated with the special symbol displayed on the special symbol display device 61 is displayed in the display area 13a. Under the present circumstances, for example, when the special symbol is being variably displayed in the special symbol display device 61, a plurality of effect identification symbols (for example, decoration (decor The symbol is variably displayed in the display area 13a. When the special symbol is stopped and displayed in the special symbol display device 61, a plurality of decorative symbols (such as a jackpot symbol described later) corresponding to the special symbol are also stopped and displayed in the display area 13a.

  Then, if the special symbol displayed in the special symbol display device 61 in the stop display is a specific mode (the result of the stop display is "big hit"), the player is made to know that it is a "big hit". An effect image is displayed on the display area 13a. As an effect for making a player know that it is a "big hit", for example, first, a plurality of stop-displayed decorative symbols are in a specific mode (for example, a mode in which the same decorative symbols are arranged along a predetermined direction) Then, there is an effect such as displaying an image notifying "big hit".

  Further, in the present embodiment, an effect image associated with the display content of the first special symbol hold display device 64 and the second special symbol hold display device 65 is displayed in the display area 13a of the display device 13. For example, in the display area 13a, holding information (for example, a holding symbol having the same number as the holding number) for displaying the holding number of the variable display of the special symbol is displayed. Further, for example, in the pachinko gaming machine 1 of the present embodiment, the pre-reading effect is performed based on the information of the holding ball of the special symbol, but the advance notice at this time is also displayed in the display area 13a.

  In the present embodiment, when the normal symbol stopped and displayed on the normal symbol display device 62 is in the predetermined mode, the effect image for causing the player to grasp the information is displayed on the display area 13 a of the display device 13 A function may be further provided.

<Configuration of Circuits Provided in Pachinko Machine>
Next, with reference to FIG. 5, configurations of various circuits included in the pachinko gaming machine 1 of the present embodiment will be described. FIG. 5 is a block diagram showing a circuit configuration of the pachinko gaming machine 1.

  The pachinko gaming machine 1 is, as shown in FIG. 5, a main control circuit 70 mainly controlling the game operation, a payout / firing control circuit 123, and a sub control circuit controlling the rendering operation according to the progress of the game. And 200.

[Main control circuit]
The main control circuit 70 includes a one-chip microcomputer 77, a clock generation circuit 74, and an initial reset circuit 75. As described above, in the present embodiment, the lottery process of the special symbol is performed at the time of winning of the first starting opening 44 or the second starting opening 45, but this processing is controlled by the main control circuit 70. That is, the main control circuit 70 doubles as a means (lottery means) for performing a lottery process as to whether or not to shift the gaming state to a state advantageous to the player.

  The one-chip microcomputer 77 is configured by a main CPU (Central Processing Unit) 71, a main ROM (Read Only Memory) 72, a main RAM (Random Access Memory) 73, and a serial communication unit 76. The main CPU 71, the main ROM 72, the main RAM 73, and the serial communication unit 76 may be provided separately.

  Further, although the configuration in which the main ROM 72 is built in the substrate of the main control circuit 70 is described in the present embodiment, the present invention is not limited to this. For example, a ROM substrate on which the main ROM 72 is mounted may be connected to the substrate of the main control circuit 70. Furthermore, in the present embodiment, various circuits in the main control circuit 70 may be integrally formed or may be separately formed. Further, the main ROM 72 may not be installed in the gaming machine, and may be configured to be able to communicate with the gaming machine.

  A clock generation circuit 74 and an initial reset circuit 75 are connected to the one-chip microcomputer 77. The main ROM 72 stores various programs (see FIGS. 28 to 35 described later) for controlling the operation of the pachinko gaming machine 1 by the main CPU 71, various data tables (see FIGS. 16 to 26 described later), and the like. ing.

  The main CPU 71 executes various processes in accordance with the program stored in the main ROM 72. The main RAM 73 acts as a temporary storage area when the main CPU 71 executes various processes, and stores values of various flags and variables that the main CPU 71 needs for various processes. In the present embodiment, the main RAM 73 is used as a temporary storage area of the main CPU 71, but the present invention is not limited to this, and any recording medium can be used as a temporary storage area as long as it is a readable and writable storage medium. .

  The clock generation circuit 74 generates clock pulses at a predetermined cycle (for example, 2 msec) in order to execute a system timer interrupt process described later. The initial reset circuit 75 generates a reset signal when the power is turned on. Then, the serial communication unit 76 supplies a command to the sub control circuit 200.

  Further, as shown in FIG. 5, various devices that operate in accordance with the output signal sent from the main control circuit 70 are connected to the main control circuit 70.

  Specifically, the main control circuit 70 is connected to the special symbol display device 61, the normal symbol display device 62, the normal symbol hold display device 63, the first special symbol hold display device 64, and the second special symbol hold display device 65. Be done. Each of these devices performs a predetermined operation based on the output signal sent from the main control circuit 70. For example, when a predetermined output signal is transmitted from the main control circuit 70 to the special symbol display device 61, the special symbol display device 61 performs operation control of the variable display of the special symbol in the special symbol game based on the output signal. Do.

  Further, the main control circuit 70 is connected to a normal motorized product solenoid 46a, a first large winning opening solenoid 53b and a second large winning opening solenoid 54b. Then, the main control circuit 70 drives and controls the ordinary electric service combination solenoid 46 a to bring the pair of blade members of the ordinary electric combination 46 into an open state or a closed state. Further, the main control circuit 70 drives and controls the first large winning opening solenoid 53b and the second large winning opening solenoid 54b, respectively, to make the first large winning opening 53 and the second large winning opening 54 open or closed. Do.

  Further, as shown in FIG. 5, the main control circuit 70 is connected to various sensors, and receives output signals of various sensors. Specifically, the main control circuit 70 includes count sensors 53c and 54c, general winning ball sensors 51a and 52a, a passing ball sensor 43a, a first starting opening winning ball sensor 44a, a second starting opening winning ball sensor 45a, and a backup. The clear switch 121 or the like is connected.

  The count sensor 53c counts the game balls that have won the first large winning opening 53, and outputs a predetermined output signal indicating the result to the main control circuit 70. The count sensor 54c counts the gaming balls that have won the second big winning opening 54, and outputs a predetermined output signal indicating the result to the main control circuit 70. The general winning ball sensor 51a outputs a predetermined detection signal to the main control circuit 70 when the gaming ball has won in the general winning opening 51, and the general winning ball sensor 52a has the gaming ball in the general winning opening 52 In this case, a predetermined detection signal is output to the main control circuit 70.

  In addition, when the gaming ball passes the ball passage detector 43, the passage ball sensor 43a outputs a predetermined detection signal to the main control circuit 70. The first starting hole winning ball sensor 44 a outputs a predetermined detection signal to the main control circuit 70 when the gaming ball has won the first starting hole 44. The second starting opening winning ball sensor 45 a outputs a predetermined detection signal to the main control circuit 70 when the gaming ball has won the second starting opening 45. Also, the backup clear switch 121 sends a predetermined detection signal to the main control circuit 70 and the payout / fire control circuit 123 when the backup data is cleared according to the operation of the game arcade manager or the like at the time of power interruption or the like. Output.

  Further, a payout / firing control circuit 123 is connected to the main control circuit 70. The contents of the payout / emission control circuit 123 and the various peripheral devices connected thereto will be described in detail later.

[Payout and launch control circuit and its peripheral devices]
The payout / firing control circuit 123 is connected to the winning ball case unit 170, the payout status notification display 178, the lower tray full tank switch 179, the launcher 15, the external terminal board 140, and the card unit 150. Further, the external terminal board 140 is connected to the data display 141, and the card unit 150 is connected to the lending operation unit 151.

  The payout / firing control circuit 123 inputs / outputs signals etc. to / from these peripheral devices based on various commands etc. transmitted from the main control circuit 70, and controls the operation of each peripheral device. For example, the payout / firing control circuit 123 receives a prize ball control command transmitted from the main control circuit 70 and a rental ball control signal to be described later transmitted from the card unit 150, and sends a predetermined value to the prize ball case unit 170. Send a signal. Thereby, the winning ball case unit 170 pays out the gaming ball.

  The prize ball case unit 170 is a device for paying out game balls, and the first 15 ball security switch 172a, the second 15 ball security switch 172b, the first counting switch 181a, the second counting switch 181b, and the payout It has a motor 174. The components included in the winning ball case unit 170 are connected to the payout / emission control circuit 123, respectively.

  Further, although not shown here, two ball supply passages are provided inside the prize ball case unit 170. The first 15-ball collateral switch 172a detects the gaming ball supplied to one of the ball supply passages, and outputs a predetermined output signal indicating the detection result to the payout / firing control circuit 123. The second 15-ball collateral switch 172b detects the gaming ball supplied to the other ball supply passage, and outputs a predetermined output signal indicating the detection result to the payout / firing control circuit 123.

  Furthermore, although not shown here, two payout paths are provided inside the prize ball case unit 170. Then, the first counting switch 181a detects the gaming balls paid out to one of the payout paths, and outputs a predetermined output signal indicating the detection result to the payout / firing control circuit 123. The second counting switch 181 b detects the gaming balls paid out to the other payout passage, and outputs a predetermined output signal indicating the detection result to the payout / firing control circuit 123.

  The payout motor 174 is a stepping motor and is driven according to a control signal input from the payout / emission control circuit 123. The payout motor 174 rotationally drives a sprocket (rotating member) (not shown) provided in the winning ball case unit 170. Then, by the rotation operation of the sprocket, the game balls stored in each ball supply passage move one by one to the corresponding payout passage.

  The payout state notification display device 178 is a device for reporting the type of the abnormality when an abnormality occurs with regard to the payout of the gaming ball, and is constituted by a 7-segment display. The payout state notification display device 178 is attached at a position where only the manager of the game arcade (game arcade) can visually recognize, and is attached, for example, to a predetermined place on the back of the pachinko gaming machine 1.

  When the gaming balls stored in the lower tray 22 become full, the lower counter-full-tank switch 179 detects this and outputs the detection result to the payout / firing control circuit 123.

  The payout / firing control circuit 123 outputs the payout status notification display device 178 indicating that the lower tray full state is received when a signal indicating the lower tray full state is input from the lower plate full tank switch 179. A signal is output to the main control circuit 70 to indicate that it is full. After that, when the effect control command is transmitted from the main control circuit 70 to the sub control circuit 200, the sub control circuit 200 uses the speaker 11, the lamp group 18, the display device 13 or the like to make the lower tray 22 full. Inform that there is.

  The launcher 15 has a launch handle 25 that can be turned by the player when the gaming ball stored in the upper tray 21 is launched to the gaming area 12a. The payout / firing control circuit 123 controls the solenoid actuator (not shown) of the launching device 15 according to the turning angle when the firing handle 25 is held by the player and turned clockwise. Supply power. Thus, the launching device 15 launches the gaming ball. A motor may be used instead of the solenoid actuator as the drive unit of the launcher 15.

  The external terminal board 140 is used to transmit data to a hall computer that manages all the pachinko machines in the game arcade. The data display 141 is installed, for example, at the top of the pachinko gaming machine 1 as a subsidiary facility of a game arcade, and has a function of calling a hall clerk and a function of displaying the number of hits.

  When operated by the player, the lending operation unit 151 outputs a signal requesting the card unit 150 to lend a game ball. The card unit 150 determines the number of gaming balls to be paid out (the number of rental balls) via the prize ball case unit 170 based on the signal requesting for lending of the gaming balls output from the lending operation unit 151. Then, when the card unit 150 receives a signal requesting the game ball to be loaned from the lending operation unit 151, the card unit 150 transmits a loan ball control signal including information on the determined number of balls to the payout / firing control circuit 123.

[Sub control circuit]
The sub control circuit 200 is connected to the serial communication unit 76 of the main control circuit 70. Then, the sub control circuit 200 (host control circuit 210 described later) controls the entire sub control circuit 200 in accordance with various commands (information regarding the progress of the game) transmitted from the main control circuit 70. The sub control circuit 200 controls the sound reproduction operation by the speaker 11, controls the image display operation by the display device 13, and controls the lamp group 18 including the LED based on various commands transmitted from the main control circuit 70. Control of lighting / extinguishing operation, control of rendering operation by the character 20 (decorative member), and the like are performed. That is, the sub control circuit 200 controls various effect devices based on the command from the main control circuit 70, and executes various effects according to the progress of the game. In the present embodiment, the sub control circuit 200 can not supply a signal to the main control circuit 70. However, the present invention is not limited to this, and the sub control circuit 200 can transmit a signal to the main control circuit 70. May be provided.

  Next, the internal configuration of the sub control circuit 200 will be described in more detail with reference to FIG. FIG. 6 is a block diagram showing the circuit configuration inside the sub control circuit 200 and the connection between the sub control circuit 200 and its various peripheral devices.

  As shown in FIG. 6, the sub control circuit 200 includes a relay substrate 201, a sub substrate 202 (first substrate), a control ROM substrate 203, and a CGROM (character generator ROM) substrate 204 (second substrate). . The sub substrate 202 is connected to the relay substrate 201, the control ROM substrate 203, and the CGROM substrate 204. In the sub control circuit 200, the sub substrate 202 and various ROM substrates (the control ROM substrate 203 and the CGROM substrate 204) are connected via a board-to-board connector (not shown).

  The relay board 201 is a relay board for receiving a command transmitted from the main control circuit 70 and transmitting the received command to the sub board 202.

  The sub substrate 202 is provided with a host control circuit 210, an audio / LED control circuit 220, a display control circuit 230, an SDRAM (Synchronous Dynamic RAM) 250, and a built-in relay substrate 260. Among them, at least the host control circuit 210, the audio / LED control circuit 220, and the display control circuit 230 are configured as one board.

  The host control circuit 210 is a circuit that controls the overall operation of the sub control circuit 200 based on various commands transmitted from the main control circuit 70, and includes a CPU processor, sub work RAM 210a, SRAM 210b, RTC (real time clock), It is configured to include a watchdog timer. The host control circuit 210 is connected to the audio / LED control circuit 220, the display control circuit 230, and the built-in relay board 260 in the sub board 202. Also, the host control circuit 210 is connected to the control ROM substrate 203.

  The host control circuit 210 also includes a sub work RAM 210 a and an SRAM (Static RAM) 210 b. The subwork RAM 210a is a storage device which acts as a working temporary storage area when the host control circuit 210 executes various processes, and various flags and variables required when the host control circuit 210 executes various processes Memorize the value of. The SRAM 210 b is a storage device that backs up predetermined data in the sub work RAM 210 a. Although the RAM is used as a temporary storage area of the host control circuit 210 in this embodiment, the present invention is not limited to this, and any recording medium may be used as a temporary storage area as long as it is a readable and writable storage medium. .

  The audio / LED control circuit 220 is connected to the speaker 11 and the lamp group 18 via the built-in relay board 260, and based on the control signals (sound request and lamp request described later) input from the host control circuit 210, It is a circuit that controls the sound reproduction operation according to the above and the light emission operation by the lamp group 18. Thus, functionally, the audio and LED control circuit 220 comprises an audio controller 220a and a lamp controller 220b. The sound controller 220 a and the lamp controller 220 b are substantially included in a sound lamp control module 226 described later. The internal configuration of the voice / LED control circuit 220 will be described in detail later with reference to the drawings.

  In the present embodiment, when the control signal and data (for example, LED data described later, etc.) output from the audio / LED control circuit 220 are transmitted to the lamp group 18 via the built-in relay board 260, the audio / LED Communication between the control circuit 220 and the lamp group 18 is performed by a SPI (Serial Peripheral Interface) communication system (a type of serial communication system). In the embodiment, the lamp group 18 includes one or more LEDs and one or more LED drivers for controlling the respective LEDs.

  The display control circuit 230 is connected to the display device 13 and displays an image (decorative symbol image, background image, effect image, etc.) related to an effect based on a control signal (drawing request) input from the host control circuit 210. Is a circuit for controlling various processing operations at the time of displaying. The display control circuit 230 includes a display controller (a first display controller 238 and a second display controller 239 described later) and a built-in VRAM (Video RAM) 237.

  In addition, the display control circuit 230 is connected to the SDRAM 250 in the sub substrate 202. Further, the display control circuit 230 is connected to the CGROM substrate 204. Further, the display controller in the display control circuit 230 is directly connected to the display device 13 without passing through the relay substrate. The internal configuration of the display control circuit 230 will be described in detail later with reference to the drawings.

  The SDRAM 250 is configured by DDR2 (Double-Date Rate 2) SDRAM. Further, the SDRAM 250 is provided with various buffers for temporarily storing various image data in the drawing process of images (moving images and still images) displayed by the display device 13. Specifically, for example, the SDRAM 250 is provided with a texture buffer, a movie buffer, a blend buffer, two frame buffers (a first frame buffer and a second frame buffer), a motion buffer, and the like.

  The built-in relay board 260 receives various signals and various data outputted from the host control circuit 210 and the voice / LED control circuit 220, and receives the various signals and various data thus received to the speaker 11, the lamp group 18 and the article 20. It is a relay board to transmit.

  Further, the built-in relay board 260 includes an I 2 C (Inter-Integrated Circuit) controller 261 and a digital audio power amplifier 262 (amplifying means). Although the present embodiment shows an example in which the I2C controller 261 and the digital audio power amplifier 262 are mounted on the same relay board, the present invention is not limited to this, and the relay board on which the I2C controller 261 is mounted is The relay substrate on which the power amplifier 262 is mounted may be provided separately.

  The I2C controller 261 is connected to the host control circuit 210 and the motor controller 270 of the accessory 20. That is, the host control circuit 210 is connected to the accessory 20 via the I2C controller 261 and the motor controller 270. Then, control signals and data (for example, excitation data to be described later) output from the host control circuit 210 are input to the accessory 20 via the I2C controller 261 and the motor controller 270.

  In the present embodiment, communication between the I2C controller 261 and the motor controller 270 is performed by an I2C communication system (a type of serial communication system). Further, in the present embodiment, the accessory 20 includes one or more motors, and the motor controller 270 includes one or more motor drivers for driving the respective motors. Although FIG. 6 shows an example in which only one accessory 20 is provided, the present invention is not limited to this, and a plurality of accessories 20 may be provided.

  Further, in the configuration of the present embodiment, the host control circuit 210 may directly drive the motor of the accessory 20 without using the motor controller 270, or a control circuit for motor control may be separately provided. Good. Furthermore, in the present embodiment, a plurality of motor drivers (motors) are controlled by one control circuit, but the present invention is not limited to this. In this embodiment, one or more (one or more) control circuits may control one or more (one or more) motors (motor driver), or one or more (one or more) control circuits. One motor (motor driver) may be controlled, or one control circuit may control one motor (motor driver).

  Also, the digital audio power amplifier 262 is connected to the audio / LED control circuit 220 and the speaker 11. That is, the audio / LED control circuit 220 is connected to the speaker 11 via the digital audio power amplifier 262. Therefore, an audio signal or the like output from the audio / LED control circuit 220 is input to the speaker 11 via the digital audio power amplifier 262.

  The control ROM substrate 203 is provided with a sub main ROM 205. The sub main ROM 205 stores various programs for controlling the rendering operation of the pachinko gaming machine 1 by the host control circuit 210, and various data tables (see, for example, FIG. 26 described later). Then, the host control circuit 210 executes various processes in accordance with the program stored in the sub main ROM 205.

  In the present embodiment, the sub main ROM 205 is applied as a storage unit for storing a program used in the host control circuit 210 and various tables, but the present invention is not limited to this. As such storage means, a storage medium of another aspect may be used as long as it is a computer-readable storage medium provided with control means, for example, a hard disk device, a CD-ROM and a DVD-ROM, a ROM cartridge, etc. Storage media may be applied. Also, each of the programs may be recorded on separate storage media. Furthermore, the program may be recorded in advance in a recording medium, or may be downloaded from the outside after power on and recorded in the sub main ROM 205.

  The CGROM substrate 204 is provided with a CGROM 206. The CGROM 206 is configured by a NOR type or NAND type flash memory. Further, the CGROM 206 stores, for example, image data displayed on the display device 13, audio data reproduced by the speaker 11 (sometimes referred to as sound data in this specification), and the like. At this time, various types of data are compressed (coded) and stored in the CGROM 206, but the present invention is not limited to this, and various types of data may be stored in the CGROM 206 without being compressed.

  In the present embodiment, the configuration in which various ROM substrates (the control ROM substrate 203 and the CGROM substrate 204) and the sub substrate 202 are connected by the board-to-board connector in the sub control circuit 200 has been described. The invention is not limited to this. For example, various ROMs may be directly inserted into a port such as a socket provided on the sub substrate 202, and the sub substrate 202 may be formed of a single substrate having a ROM function or the ROM itself. That is, the sub substrate 202 and the various ROMs may be integrally configured. When sub substrate 202 is formed of a single substrate having a ROM function or a ROM itself, sub control circuit 200 uses the sub according to the type of memory used as a CGROM. The circuit may be provided with switching means for physically or electrically switching the circuit on the substrate, or switching means for switching information of the circuit on the sub-substrate to be used according to the type of memory.

  Further, in the present embodiment, the magnitude relationship of the communication speed of data between each of various storage means (sub main ROM 205, CGROM 206, built-in VRAM 237, SDRAM 250) and corresponding control circuit is as follows. ROM 205 ≒ CG ROM 206. That is, in the present embodiment, the communication speed between the built-in VRAM 237 and the various circuits in the display control circuit 230 is the fastest, and then the communication speed between the SDRAM 250 and the display control circuit 230 is faster. Then, the communication speed between the sub main ROM 205 and the host control circuit 210 and the communication speed between the CGROM 206 and the display control circuit 230 become the slowest. However, the present invention is not limited to this, and the magnitude relation of the communication speed between each of the various storage means and the corresponding control circuit can be set arbitrarily. For example, the magnitude relationship of the communication speed between each of the various storage means and the corresponding control circuit may be different from that of the present embodiment, or the communication speed between each storage means and the corresponding control circuit All may be the same.

  Here, possible configurations of the various storage means described above will be described. In the present embodiment, the storage unit of information related to image data (compressed (encoded) image data) includes information related to transparency data (alpha table described later) that can be used when setting transparency for the image data. The configuration example which is the same as the storage unit (CGROM 206) has been described. That is, the configuration example in which the “first information storage unit” is physically the same as the “second information storage unit” has been described. However, the present invention is not limited to this. For example, the "first information storage unit" may be configured by a storage unit (storage medium) physically different from the "second information storage unit".

  Further, "information storage means" in the present specification means not only storage means such as the CGROM 206 but also tables stored in the storage means, data storage areas in the storage means, etc. Good. Therefore, for example, the "first information storage means" and the "second information storage means" may be mutually different data storage areas in the same storage means, or may be different tables. In addition, it may be stored in different register addresses. That is, "the information storage means" in this specification is different not only when the storage means (storage medium) is physically different but also physically the same storage means (for example, ROM, RAM, etc.) Is a meaning that includes cases where data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) differ in the storage means.

  The meaning of the "information storage unit" in the present specification described above is also applicable to the "third information storage unit" (SDRAM 250) and the "fourth information storage unit" (internal VRAM 237). Therefore, for example, the "first information storage unit" to the "fourth information storage unit" may be configured by physically different storage units (storage media), or the "first information storage unit" to The "fourth information storage means" may be configured by mutually different data areas (storage areas distinguished by an address, a register, a table, a structure, etc.) in one storage means.

  Further, in the present embodiment, the “first information storage unit” and the “second information storage unit” are configured by mutually different data areas in one storage unit (CGROM 206), and the “third information storage unit” is A storage means (SDRAM 250) physically different from the storage means (CGROM 206) including the "first information storage means" and the "second information storage means", and the "fourth information storage means" A description will be given of an example configured by a storage unit (CGROM 206) including 1 information storage unit "and" second information storage unit ", and storage unit (internal VRAM 237) physically different from" third information storage unit "(SDRAM 250). However, the present invention is not limited to this. The combination of the "information storage means" defined as the data area and the "information storage means" defined as the storage means Whether to use this mode can be appropriately set according to, for example, the configuration (number, type, etc.) of the storage means provided in the gaming machine. For example, in the present embodiment, "first information storage means" to "third information storage means" are configured by mutually different data areas in one storage means, and "fourth information storage means" is The storage means may be physically different from the storage means including the (1) information storage means "to the" third information storage means ".

[Audio / LED control circuit]
Next, the internal configuration of the audio / LED control circuit 220 will be described with reference to FIG. FIG. 7 is a block diagram showing the internal circuit configuration of the audio / LED control circuit 220 and the connection between the audio / LED control circuit 220 and its various peripheral devices and peripheral circuits. In FIG. 7, in order to simplify the description, illustration of relay boards and the like provided between the audio / LED control circuit 220 and various peripheral devices and circuit units is omitted.

  As shown in FIG. 7, the audio / LED control circuit 220 includes an LSI (Large-Scale Integration) interface 221, a memory interface 222, a digital audio interface 223, a peripheral interface 224, a command register 225, and a sound lamp. A control module 226, a main generator 227, and a multi-effector 228 are provided. The connection relationship of each part in the voice / LED control circuit 220 is as follows.

  In the audio and LED control circuit 220, the sound and lamp control module 226 is connected to the memory interface 222, the peripheral interface 224, the command register 225, the main generator 227 and the multi-effector 228. The command register 225 is connected to the LSI interface 221 in addition to the sound and lamp control module 226. The main generator 227 is also connected to the memory interface 222 and the multi-effector 228 in addition to the sound and lamp control module 226. Furthermore, the multi-effector 228 is connected to the memory interface 222 and the digital audio interface 223 in addition to the sound lamp control module 226 and the main generator 227.

  Next, the configuration of each part in the audio / LED control circuit 220 will be described.

  The LSI interface 221 is an interface circuit used when performing input / output operations of control signals and the like (for example, a sound request, a lamp request and the like) between the host control circuit 210 and the command register 225. That is, the command register 225 is connected to the host control circuit 210 via the LSI interface 221.

  The memory interface 222 is an interface circuit used when performing input / output operations such as audio data between the sub main ROM 205 and the sound / lamp control module 226, the main generator 227, and the multi-effector 228.

  The digital audio interface 223 is an interface circuit used when outputting an audio signal or the like from the multi-effector 228 to the speaker 11. The digital audio interface 223 also outputs an audio input signal to the multi-effector 228.

  The peripheral interface 224 is an interface circuit used when performing input / output operations of a lamp signal and the like (LED data and the like described later) between the lamp group 18 and the sound / lamp control module 226. Further, in the peripheral interface 224, three physical systems are provided as physical systems (SPI channels) when performing data output to the LED drivers included in the lamp group 18. In the present embodiment, two physical systems (physical system 0 (SPI channel 0) and physical system 1 (SPI channel 1)) are used as described later.

  The command register 225 is composed of a large number of register groups (eg, a large number of voice control registers) accessed by the host control circuit 210. The command register 225 sets function control of the sound and lamp control module 226, the main generator 227 and the multi-effector 228. The command register 225 also sets the operating conditions of each interface (LSI interface 221, memory interface 222, digital audio interface 223, peripheral interface 224).

  An IC (Integrated Circuit) is mounted on each of the registers constituting the command register 225, and each of the registers is constituted by a memory chip whose operation is stabilized by memory access control. When registers of such a configuration are used, the load on the signal bus to which each register is connected is reduced. Therefore, the capacity per memory module can be easily increased by increasing the number of memory chips (registers). The capacity of the command register 225 can be increased.

  The sound and lamp control module 226 controls the sound reproduction operation and the like in an integrated manner, and controls the operation of each component (each block) in the sound and LED control circuit 220 according to the setting contents of the command register 225. . As shown in FIG. 7, the sound / lamp control module 226 includes a simple access controller 226a, a sequencer 226b, a lamp control unit 226c, and a peripheral control unit 226d.

  The simple access controller 226a is a circuit unit that collectively processes commands. The sequencer 226 b has various sequencers (automatic playback function unit) for controlling an automatic playback operation such as lamp lighting and sound. Then, each sequencer controls various operations in accordance with a timer and step conditions (for example, conditions set for each step processing during sequence reproduction such as LED animation and sound described later).

  The lamp control unit 226c calculates the luminance value to be set in all channels (eight channels) to which LED data described later can be set, and transmits the calculation result to the outside (LED driver). Also, the peripheral control unit 226d performs physical transmission control when transmitting the data of the calculation result output from the lamp control unit 226c to the LED driver.

  The main generator 227 is a circuit unit that generates an audio signal. Specifically, the main generator 227 acquires predetermined audio data stored in the CGROM 206 based on the control signal input from the sound / lamp control module 226, and acquires the acquired audio data as a predetermined audio signal. Convert to The main generator 227 is divided into reproduction channels CH1 to CH32, a decoder 227a for reproducing compressed data, a channel volume 227b (V1 to V4) for adjusting the volume, and a channel mix unit 227c for mixing reproduction sounds of the decoder 227a. And a remixing unit 227d that performs a final mixing operation.

  The multi-effector 228 has a mixer that synthesizes an audio signal input from the main generator 227 and an audio input signal input from the digital audio interface 223, and various effectors for applying various acoustic effects to audio. Then, the multi-effector 228 outputs an audio signal synthesized by the mixer, an output signal from the effector, and the like to the speaker 11 through the digital audio interface 223.

FIG. 8 is a diagram for explaining output signals of the audio / LED control circuit. The CGROM 206 stores up to 8192 types of sequence code groups and up to 8192 types of SAC data groups. Sequence code and SAC data, respectively, have been identified in the 13 bit long sequence code number or SAC number, a relationship of 8192 ^{= 2 13.}

  In the case of this embodiment, 16 sequences (SQ0 to SQ15) operating in parallel are provided as the sequencer 226b, and 4 sequences (SAC0 to SAC3) operating in parallel are provided as the simple accelerator controller 226a. There is. Corresponding to this configuration, the command register 225 is provided with an audio control register RGj2 for sequencer (SQ0 to SQ15) control and an audio control register RGj1 for SAC (SAC0 to SAC3) control.

  Then, when the host control circuit 210 configured by the CPU processor writes the SAC number and the additional information thereof in the predetermined voice control register RGj1 for SAC control based on the voice command transmission operation, the corresponding simple The access controller 226a starts the function, and the simple access controller 226a writes the group of setting data specified by the SAC number into the group of voice control registers indicated by the SAC data. In the present embodiment, the complicated setting operation can be completed by transmitting one SAC number and its associated information.

  On the other hand, based on the transmission operation of the voice command, the host control circuit 210 configured by the CPU processor determines the sequence code number and the attached information in a predetermined voice control register RGj2 for controlling the sequencer 226b (SQ0 to SQ7). When written, the corresponding sequencer SQi starts the function to write the group of setting data specified by the sequence code into the group of voice control registers indicated by the sequence code.

  Here, a predetermined voice control register RGj2 for controlling sequencers (SQ0 to SQ7) controls a plurality (up to eight) of sequence code numbers and loop information for the effects of the respective sequence code numbers for an arbitrary sequencer SQi. It is possible to fill in the Therefore, for example, when n + 1 sequence code numbers (X0, X1,..., Xn) are designated for sequencer SQi, setting operation of sequence code number X0 → setting operation of sequence code number X1 The setting operation of the sequence code number Xn is executed in order, and the sound effect corresponding to the setting operation is executed.

  In addition, since loop information such as the number of repetitions can be specified for each sequence code number, after repeating the sound effect specified by the sequence code number a predetermined number of times, the sound effect specified by the next sequence code number It can be migrated.

  As described above, there are various data to be set in the sequencer SQi, and it is necessary to appropriately set the sequence code number and the accompanying data in the voice control register RGj2 for sequencer control. Therefore, in the present embodiment, the entire sequence code number and the accompanying data are divided in 1-byte units, and the divided 1-byte data and the register address of sequencer control register RGj2 to which 1-byte data is to be set A group of SAC data to be a set is secured in the CGROM 206 (hereinafter, this is referred to as sequencer activation SAC data).

  Then, the host control circuit 210 activates the simple access controller 226a by designating a predetermined SAC number in the voice control register RGj1 for SAC control. Here, it goes without saying that the SAC number specifies SAC data for sequencer activation. Then, based on the operation of the SAC (Simple Access Controller), necessary data is expanded in the sequencer control register RGj2. Therefore, the setting operation of start data of sequencers SQ0 to SQ15 is easy.

  By the way, as described above with reference to FIG. 8, a plurality of operation units (sequence steps) divided by the step end code (FFFEH) are described in a group of sequence codes specified by one sequence code number. Eventually, after all of the plurality of sequence steps specified by one sequence code number are executed, the plurality of sequence steps specified by the next sequence code number will be executed.

  And since the waiting time can be set to each sequencer, the first sequence step (the writing operation of the group of setting data) is started after the waiting time indicated from the host control circuit 210 configured by the CPU processor. When the step end code (FFFEH) is executed, furthermore, after the waiting time, the next group of setting data is written to the group of voice control registers. In addition, although a single time information can be set for each sequencer (SQ0 to SQ7), for example, in the preceding sequence step, the waiting time applied to the subsequent sequence steps subsequent thereto is set. By doing this, the waiting time for each sequence step can be set arbitrarily.

  Further, to continue the description of the internal configuration of the audio / LED control circuit 220, as shown in FIG. 7, the output signals of six channels of the channel mix section 227c (mixture L0, mix R0, mix L1, mix R1, mix SUB0, The mixed SUB 1) is subjected to digital filter processing in the multi-effector 228 based on the operation parameter specified in the predetermined voice control register of the command register 225, and then supplied to the total volume 229 (TV 0 to TV 3). It is amplified based on TV.

  Although the total volume value TV is defined by an operation parameter written in the corresponding voice control register, this operation parameter is, in principle, a setting switch (hardware operation by an attendant in this embodiment) as described above. Defined based on the However, when the player operates the volume switch (screen operation) while the player is playing a game (while waiting for a sound effect), the total volume TV is defined (changed) based on the setting value. When the player operates the volume switch, the channel volume 227 b (V 1 to V 4) is defined (changed) instead of or in addition to the total volume TV being defined based on the setting value. You may

[Speaker volume control]
Next, volume control of each speaker 11 executed by the host control circuit 210 will be described with reference to FIG. FIG. 9 is a control block diagram for explaining an example of volume control by the host control circuit.

  Sounds such as game sounds outputted from the respective speakers 11 (L0 / R0 / L1 / R1, SUB0, SUB1) are the audio signals of the total volumes TV0 to 3 outputted to all the channels and the respective ones of all the channels. By multiplying the audio signal of each reproduction channel output to the channel with each other, the volume control is performed by the volume transition operation in which the volume value of the audio signal is transitioned stepwise.

  Note that "audio signal" has volume information (for example, information such as wattage), and can also be simply referred to as "volume". For example, in this specification, “audio signal for each reproduction channel” may be referred to as “volume for each reproduction channel”.

  The audio signals of the total volume TV0 to 3 are output by the audio signal by the volume control 281 by the hardware switch and the total value of the audio signal output by the user volume control 282 by the volume setting screen and by the debug volume control 283 at the time of debugging. And the specified audio signal. The host control circuit 210 that executes the volume control 281 by hardware switch, the user volume control 282 by volume setting screen, and the debug volume control 283 at the time of debugging corresponds to the "first volume control means" in the present invention.

  Further, the volume of each reproduction channel is obtained by multiplying the audio signal of the primary volume and the audio signal of the secondary volume. The audio signal of the primary volume is an audio signal outputted by the first reproduction channel primary control 284 affected by the volume adjustment and an audio signal outputted by the second reproduction channel primary control 285 not influenced by the volume adjustment. Specified by the overall value. In the first reproduction channel primary control 284, for example, a control for changing the volume of a normal game sound (that is, an audio signal (same in the following)) is performed based on the player or the like performing an operation to change the volume. It will be. The second playback channel primary control 285 controls to output a specific game sound (for example, an error sound or an alarm sound at the time of an illegal act) at a constant volume regardless of whether or not an operation to change the volume is performed. Is done. This constant volume may always be the maximum volume. As described above, in the second reproduction channel primary control 285 which is not affected by the volume adjustment, the specific gaming sound is controlled to be output at a constant volume, so that it is possible to specify only the specific reproduction channel instead of the whole. It is possible to execute control to make the volume of the game sound constant. Further, the audio signal of the secondary volume is a sound volume incorporated in the audio data specified by the SAC number, and is output by the volume control 286, 287, 288. The host control circuit 210 for executing the first reproduction channel primary control 284, the second reproduction channel primary control 285, and the volume control 286, 287, 288 incorporated in the audio data is the second volume of the present invention. It corresponds to "control means".

  As described above, the sound output from each of the speakers 11 (L0 / R0 / L1 / R1, SUB0, SUB1) is the volume of the total volume TV0 to 3 and the volume and secondary of the primary volume which is the volume for each reproduction channel. The volume of the game sound can be diversified because it is defined by multiplying the volume of the volume. In particular, since the volume of the total volume TV0 to 3 is also defined by the volume output by the debugging volume control 283 at the time of debugging, the gaming sound data used in the game can be used as it is at the time of debugging It is possible to improve the work efficiency of

  Also, with regard to the volume of the normal game sound, the volume can be changed based on the fact that the player or the like has performed an operation to change the volume. With regard to the game sound, a constant volume is output in the second reproduction channel primary control 285 regardless of whether or not an operation to change the volume has been performed. Therefore, it is not possible to hide the occurrence of an error or an illegal act, and security can be enhanced.

  In the pachinko gaming machine 1 of the present embodiment, volume control 281 by the hardware switch has, for example, three stages of large, medium, and small. Further, there are seven levels of user volume control 282 by the volume setting screen, and in conjunction with the hardware switch, [small] = [1], [medium] = “4”, [large] = “7”.

  As described above, in the pachinko gaming machine 1 according to the present embodiment, for example, with regard to a specific sound such as an error sound, the volume can be maintained only by the control by the second reproduction channel primary control 285. This makes it possible to easily perform volume control such as changing the volume according to volume adjustment for other normal sounds while maintaining the volume. The process by the host control circuit 210 when volume adjustment is performed will be described later with reference to FIGS. 61 to 65.

[Connection configuration between digital audio power amplifier and speaker]
Next, the connection configuration between the digital audio power amplifier 262 provided in the built-in relay board 260 and its peripheral circuits, and the speaker 11 will be described with reference to FIG. FIG. 10 is a connection configuration diagram between the built-in relay board 260 and the speaker 11. Note that FIG. 10 shows a state in which the speaker 11 is not connected to the built-in relay board 260 in order to clarify the configuration of the connection portion.

  In the pachinko gaming machine 1 of the present embodiment, as shown in FIG. 10, the speaker box 11a provided with the speakers 11 is connected to the built-in relay board 260 via the harness 300.

  The built-in relay board 260 includes a digital audio power amplifier 262, an LC circuit 263, a connection terminal group 264 including four connection terminals (first to fourth connection terminals), two resistors 265 and 266, and a capacitor. 267 and a NOT circuit (logic circuit) 268.

  The digital audio power amplifier 262 amplifies the input audio signal (audio data) and outputs the amplified audio signal to the speaker 11 to drive the speaker 11. The LC circuit 263 is configured of a resonant circuit including a coil and a capacitor. Also, the NOT circuit 268 is a logic circuit that inverts the level of the input signal and outputs it.

  The clock input terminal (MCK) and the data input terminal (SDATA) of the digital audio power amplifier 262 are connected to the audio / LED control circuit 220. The clock signal (master clock signal) output from the audio / LED control circuit 220 is input to the clock input terminal (MCK) of the digital audio power amplifier 262, and the audio / LED is input to the data input terminal (SDATA). An audio signal (audio data) output from the control circuit 220 is input.

  Further, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are respectively connected to the first connection terminal in the connection terminal group 264 of the built-in relay substrate 260 via the LC circuit 263 and It is connected to the second connection terminal. Although the present embodiment shows an example in which two output terminals of the digital audio power amplifier 262 are provided, the present invention is not limited to this. For example, the present invention is appropriately changed according to the function or the specification of the speaker 11 Can.

  Furthermore, the digital audio power amplifier 262 has a mute terminal (MUTE: audio output control terminal). When the level (amplitude value) of the voltage signal applied to the mute terminal is the LOW level, the digital audio power amplifier 262 outputs the audio signal from the first output terminal (OUTM1) and the second output terminal (OUTM2). It has a function (hereinafter referred to as a mute function) of stopping the output or setting the output terminal to a state of being grounded via a high resistance. That is, when the level of the voltage signal applied to the mute terminal is the LOW level, the digital audio power amplifier 262 receives the first signal from the first output terminal (OUTM1) and the second output terminal (OUTM2). It has a function of generating a state in which the output of the audio signal to the connection terminal and the second connection terminal is stopped.

  On the other hand, when the level (amplitude value) of the voltage signal applied to the mute terminal (MUTE) is at the HIGH level, the digital audio power amplifier 262 includes the first output terminal (OUTM1) and the second output terminal (OUTM2) Output an audio signal from

  The third connection terminal in the connection terminal group 264 of the built-in relay substrate 260 is connected to the input terminal of the NOT circuit 268 via the resistor 266. The output terminal of the NOT circuit 268 is connected to the mute terminal (MUTE) of the digital audio power amplifier 262. The signal connection between the third connection terminal of built-in relay substrate 260 and resistor 266 is connected to the power supply voltage (+5 V) terminal provided in built-in relay substrate 260 via resistor 265. In addition, the signal wiring between the input terminal of the NOT circuit 268 and the resistor 266 is connected (grounded) to a ground (GND) terminal provided in the built-in relay substrate 260 via the capacitor 267. Furthermore, the fourth connection terminal of the built-in relay substrate 260 is connected to the ground (GND) terminal.

  As shown in FIG. 10, the speaker 11 is attached to a speaker box 11a formed of a wooden frame. Further, the speaker box 11a is provided with a connection terminal group 11b including four connection terminals (first to fourth connection terminals). The first connection terminal and the second connection terminal of the speaker box 11a are connected to the speaker 11 through the signal wiring. Further, the third connection terminal (specific connection terminal) of the speaker box 11a is electrically connected to the fourth connection terminal by the signal wiring W1.

  As shown in FIG. 10, the harness 300 is configured by bundling four signal wires. Then, one of four connection terminals (first to fourth connection terminals) of the four signal wirings are connected to the first to fourth connection terminals of the built-in relay substrate 260, respectively. On the other hand, the other four connection terminals (fifth connection terminal to eighth connection terminal) of the four signal lines are respectively connected to the first connection terminal to the fourth connection terminal of the speaker box 11a. That is, the first connection terminal of the built-in relay substrate 260 and the first connection terminal of the speaker box 11 a are connected by the signal wiring between the first connection terminal and the fifth connection terminal in the harness 300, and the built-in relay substrate 260 The second connection terminal of the speaker box 11a and the second connection terminal of the speaker box 11a are connected by signal wiring between the second connection terminal and the sixth connection terminal in the harness 300. In addition, the third connection terminal of the built-in relay substrate 260 and the third connection terminal of the speaker box 11 a are connected by the signal wiring between the third connection terminal and the seventh connection terminal in the harness 300, and the built-in relay substrate 260 The fourth connection terminal of the speaker box 11a and the fourth connection terminal of the speaker box 11a are connected by signal wiring between the fourth connection terminal and the eighth connection terminal in the harness 300. Thus, the speaker 11 is connected to the built-in relay board 260 via the harness 300.

  The number of signal lines included in the harness 300 is not limited to four, and is appropriately changed according to, for example, the specifications of the digital audio power amplifier 262 and the speaker 11, the connection configuration between the two, and the like. In the harness 300, at least signal wiring for connecting the output terminal of the digital audio power amplifier 262 and the speaker 11, and signal wiring for grounding the mute terminal of the digital audio power amplifier 262 via the speaker box 11a. Should be included.

  As described above, when the built-in relay board 260 and the speaker 11 are connected via the harness 300, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected via the harness 300. And connected to the speaker 11. The mute terminal (MUTE) of the digital audio power amplifier 262 is grounded via the NOT circuit 268, the harness 300, and the signal wiring W1 between the third connection terminal and the fourth connection terminal of the speaker box 11a.

  As a result, when the speaker 11 is connected to the built-in relay board 260 (digital audio power amplifier 262) via the harness 300, the voltage signal of the LOW level is input to the NOT circuit 268. The level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the signal becomes a high level. In this case, an audio signal is output to the speaker 11 from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262.

  On the other hand, when the speaker 11 is not connected to the built-in relay board 260 (digital audio power amplifier 262), the third connection terminal of the built-in relay board 260 is in the open state. In this case, since the power supply voltage (+5 V) is input to the NOT circuit 268, the level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the digital audio power amplifier 262 becomes LOW, and the digital audio power amplifier The above-described mute function of 262 is activated.

  That is, when the speaker 11 is out of the built-in relay board 260 (digital audio power amplifier 262), the built-in relay board 260 is connected to the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262. A state is generated in which the output of the audio signal to the first connection terminal and the second connection terminal is stopped. As a result, the occurrence of a resonance phenomenon between the digital audio power amplifier 262 (output terminal) and the first and second connection terminals of the built-in relay substrate 260 is suppressed, and a failure such as a failure of the digital audio power amplifier 262 is generated. It can be prevented.

  As described above, in this embodiment, the mute function of the digital audio power amplifier 262 can be activated regardless of software control by the host control circuit 210 and the audio / LED control circuit 220. Therefore, for example, even when the host control circuit 210 and the audio / LED control circuit 220 recognize that the output stop control of the audio signal is performed in the situation where the speaker 11 is detached from the built-in relay board 260, In the pachinko gaming machine 1 of a structure in which the game board can not be replaced without removing the speaker 11 from the harness 300 or when the voice signal is erroneously output due to a bug (defect) or the like, after the game board is replaced Even when a door is closed by mistake without connecting the speaker 11 and the harness 300 and an audio output is started, the above-mentioned mute function of the digital audio power amplifier 262 operates as hardware. In this case, the digital audio power amplifier 262 can be surely protected, and the safety of the pachinko gaming machine 1 can be improved.

  Furthermore, in the present embodiment, as described above, the third connection terminal of the built-in relay board 260 is via the harness 300 and the signal wire W1 between the third connection terminal and the fourth connection terminal of the speaker box 11a. It is connected to the ground (GND) terminal provided in the built-in relay board 260. In such a configuration, when the signal level of the third connection terminal of the built-in relay board 260 is LOW, is this factor due to the fourth connection terminal of the built-in relay board 260 being grounded? Since it can be determined by measuring the signal level of the fourth connection terminal of the built-in relay board 260, the digital output operation from the digital audio power amplifier 262 can be managed more accurately.

[Display control circuit]
Next, the internal configuration of the display control circuit 230 will be described with reference to FIG. FIG. 11 is a block diagram showing the circuit configuration inside the display control circuit 230 and the connection between the display control circuit 230 and its various peripheral devices and peripheral circuit units.

  As shown in FIG. 11, the display control circuit 230 includes a memory controller 231, a command memory 232, a command parser 233, a moving image decoder 234, a still image decoder 235, an SDRAM controller 236, a built-in VRAM 237, and A display controller 238, a second display controller 239, a 3D (Dimension) geometry engine 240, and a rendering engine 241 are provided. The connection relationship of each part in the display control circuit 230, and the connection relationship between the display control circuit 230 and its various peripheral devices and peripheral circuits are as follows.

  In the display control circuit 230, the memory controller 231 is connected to the command parser 233, the moving picture decoder 234 and the still picture decoder 235. The command parser 233 is connected to the command memory 232, the moving image decoder 234, the still image decoder 235 and the 3D geometry engine 240 in addition to the memory controller 231. The video decoder 234 is connected to the SDRAM controller 236 in addition to the memory controller 231 and the command parser 233. The still image decoder 235 is connected to the built-in VRAM 237 in addition to the memory controller 231 and the command parser 233.

  Further, in the display control circuit 230, the SDRAM controller 236 is connected to the built-in VRAM 237, the first display controller 238 and the second display controller 239 in addition to the moving picture decoder 234. The built-in VRAM 237 is connected to the first display controller 238, the second display controller 239, and the rendering engine 241 in addition to the still image decoder 235 and the SDRAM controller 236. Furthermore, the 3D geometry engine 240 is connected to the rendering engine 241 in addition to the command parser 233.

  The SDRAM 250 is connected to the memory controller 231 and the SDRAM controller 236 in the display control circuit 230. The CGROM substrate 204 is also connected to the memory controller 231 in the display control circuit 230. The host control circuit 210 is also connected to the memory controller 231 and the command memory 232 in the display control circuit 230. Furthermore, the display device 13 is connected to a first display controller 238 and a second display controller 239 in the display control circuit 230.

  Next, the configuration of each part in the display control circuit 230 will be described.

  The memory controller 231 mainly performs communication control between various external memories (the CGROM substrate 204 and the SDRAM 250) and the display control circuit 230. For example, the memory controller 231 performs transmission / reception of an address designation signal of an external memory to be controlled, processing of memory ready, busy management, etc., and data stored in an address designated for various memories (effect data , Command data, etc.).

  The command memory 232 is a built-in memory for storing a command list. The command list may be stored in the SDRAM 250 and the CGROM substrate 204 (CGROM 206) in addition to the command memory 232.

  The command parser 233 obtains a command list from a designated memory (command memory 232, SDRAM 250 or CGROM 206). Specifically, in the present embodiment, the type (command memory 232, SDRAM 250 or CGROM 206) of the memory in which the command list is arranged in the system control register (not shown) in the display control circuit 230 by the host control circuit 210; The start address is set. Then, the command parser 233 accesses the start address in the memory designated by the system control register (not shown) to acquire the command list.

  Also, the command parser 233 analyzes the acquired command list to generate a specific control code, and outputs the control code to the moving picture decoder 234, the still picture decoder 235, and the 3D geometry engine 240. In the present embodiment, each image processing module in the display control circuit 230 operates based on the control code output by the command parser 233.

  The video decoder 234 decodes the video compression data acquired from the CGROM substrate 204 or the SDRAM 250. Then, the moving image decoder 234 outputs the decoded moving image data to the SDRAM 250 (external RAM). The moving image data (decoding result) output from the moving image decoder 234 is stored in a movie buffer provided in the SDRAM 250.

  The still image decoder 235 decodes the still image compressed data acquired from the CGROM substrate 204 or the SDRAM 250. Then, the still image decoder 235 outputs the decoded still image data to the built-in VRAM 237. The still image data (decoding result) output from the still image decoder 235 is temporarily stored in a sprite buffer described later provided in the built-in VRAM 237.

  The SDRAM controller 236 is a controller that controls operations such as storage processing of decoded moving image data and still image data in the RAM and transfer processing of image data between the built-in VRAM 237 and the CGROM substrate 204 or the SDRAM 250.

  The built-in VRAM 237 operates as a work RAM when executing various processing such as decoding processing and rendering processing in the drawing processing by the display control circuit 230. In addition, various image data are temporarily stored in the built-in VRAM 237 in the process of transferring image data between the built-in VRAM 237 and the CGROM substrate 204 or the SDRAM 250 which is performed in each process in the drawing process described later.

  Each of the first display controller 238 and the second display controller 239 obtains a rendering result (drawing result) generated by the rendering engine 241, and outputs the rendering result to the display device 13. Thereby, a predetermined image is displayed on the display screen of the display device 13. When two display controllers are provided as in the pachinko gaming machine 1 of the present embodiment, two screens are provided on the display device 13 by one display control circuit 230 (one chip), and each screen is displayed. It can be controlled independently.

  The 3D geometry engine 240 converts three-dimensional information into two-dimensional information based on the control code input from the command parser 233 (projective conversion processing), and affine transformations such as enlargement, reduction, rotation, and movement of figures. Perform (graphic conversion) processing. Then, the 3D geometry engine 240 outputs the result of the conversion process to the rendering engine 241.

  The rendering engine 241 performs rendering (drawing) processing on the image data with reference to the texture source (in this embodiment, the SDRAM 250) in which the decompressed still image data and moving image data are stored. Then, the rendering engine 241 writes the rendering result to the rendering target (in the present embodiment, the built-in VRAM 237 or the SDRAM 250).

  Note that “to render” as used in this specification refers to editing data decoded according to specified information (in the present embodiment, information output from the 3D geometry engine 240) such as scaling or rotation of a moving image. It is to be. Also, the “rendering engine” referred to here includes, for example, “rasterizer”, “pixel shader” and the like. Therefore, in the rendering engine 241, similar to the pixel shader, the ARGB values (A: alpha value indicating transparency (opacity), R: luminance value of red component, G: green component) for image data in pixel units Calculation processing of the luminance value of B, the luminance value of the blue component) is also performed.

[Connection configuration between display control circuit and CGROM]
The pachinko gaming machine 1 of the present embodiment has a configuration that can cope with different CGROM types (NOR type or NAND type) connected to the display control circuit 230. Here, the connection configuration between the display control circuit 230 provided in the sub substrate 202 and its peripheral circuits, and the CGROM mounted on the CGROM substrate will be described with reference to FIGS. 12 and 13.

  FIG. 12 is a connection configuration diagram between the sub substrate 202 and the CGROM substrate 204a when the CGROM is a NOR type CGROM 206a (NOR type flash memory). FIG. 13 is a connection configuration diagram between the sub substrate 202 and the CGROM substrate 204b in the case where the CGROM is a NAND type CGROM 206b (NAND type flash memory). 12 and 13 show a state in which the CGROM substrate is detached from the sub-substrate 202 in order to clarify the configuration of the connection portion, but in actuality, both substrates are via the board-to-board connector. Connected

(1) Configuration of Sub Substrate First, the internal configuration of the sub substrate 202 will be described. As apparent from the comparison between FIG. 12 and FIG. 13, the configuration of the sub substrate 202 when the NOR type CGROM 206a is mounted on the CGROM substrate 204a is the same as that of the NAND type CGROM 206b mounted on the CGROM substrate 204b. It is similar.

  As shown in FIGS. 12 and 13, the sub substrate 202 is provided with a display control circuit 230, and as a peripheral circuit thereof, a bidirectional balance transceiver 301 and an AND circuit 302 (AND gate) are provided. In addition, the sub substrate 202 is provided with various signal wirings (buses) and a terminal group 303 including a plurality of connection terminals directly or indirectly connected to the display control circuit 230 through the various buses.

  The bidirectional balance transceiver 301 has four other input / output terminals (terminals A0 to A3 in FIG. 12) and the other four input / output terminals (terminals A0 to A3) connected to one of the four input / output terminals. And one input / output terminal (terminal B0 to terminal B3 in FIG. 12). Further, the bidirectional balance transceiver 301 has two control terminals (terminals in FIG. 12) for switching control of the communication direction of the signals between the input / output terminal A0 to the input / output terminal A3 and the input / output terminal B0 to the input / output terminal B3. OE and terminal DIR).

  Bidirectional balance transceiver 301 is connected between input / output terminal A0 to input / output terminal A3 and input / output terminal B0 to input / output terminal B3 according to a combination of signal levels of voltage signals applied to control terminal OE and control terminal DIR. Switch the communication direction of the signal in. As a result, even when a mismatch occurs in the communication direction (communication operation) due to any cause, it is possible to secure the safety of the communication operation between the display control circuit 230 and the CGROM. The switching control operation of the communication direction in the bidirectional balance transceiver 301 will be described in detail later. In addition, the bidirectional balance transceiver 301 used in the present embodiment can also cope with a system having dual power supplies of 3.3V and 5V.

  The display control circuit 230 is provided with four input / output common terminals (terminals GMA31 / GRB3 to GMA28 / GRB0 in FIG. 12). The input / output common terminal GMA31 / GRB3 to the input / output common terminal GMA28 / GRB0 act as an output terminal of the address bus when the CGROM is a NOR type CGROM 206a, and a ready when the CGROM is a NAND type CGROM 206b. Acts as an input terminal for the / busy signal. Further, the display control circuit 230 is provided with 26 output terminals (terminal GMA 27 to terminal GMA 2 in FIG. 12) that act as output terminals of data (address specification data etc.) related to the address of the data storage area in the CGROM. Be

  Also, the display control circuit 230 is provided with two CG memory chip enable output terminals (terminal GCE_0 and terminal GCE_1 in FIG. 12). In the present embodiment, the display control circuit 230 has two memory spaces corresponding to two CG memory chip enable output terminals (GCE_0, GCE_1: specific output terminals), and each memory space contains a memory. Information such as type, bus width and access timing is set. However, in the present embodiment, the display control circuit 230 can not be used (used) when the ROM in the synchronous mode and the ROM in the asynchronous mode are mixed.

  Furthermore, the display control circuit 230 is provided with a plurality of data bus input terminals for acquiring image data (moving image / still image compressed data) from the CGROM via the data bus.

  The electrical connection relationship of the above-described components provided on the sub substrate 202 is as follows.

  As shown in FIG. 12 and FIG. 13, the input / output combined terminal GMA31 / GRB3 to the input / output combined terminal GMA28 / GRB0 of the display control circuit 230 are respectively connected to the input / output terminal B0 to the input / output terminal B3 of the bidirectional balance transceiver 301 Be done. The input / output terminals A0 to A3 of the bidirectional balance transceiver 301 are connected to the first to fourth connection terminals of the terminal group 303, respectively. That is, the input / output combined terminal GMA31 / GRB3 to the input / output combined terminal GMA28 / GRB0 of the display control circuit 230 are respectively connected to the first to fourth connection terminals of the terminal group 303 via the bidirectional balance transceiver 301. Ru.

  Further, the output terminal GMA27 to the output terminal GMA2 of the display control circuit 230 are respectively connected to the ninth connection terminal to the 34th connection terminal of the terminal group 303, and the CG memory chip enable output terminal GCE_0 and the CG memory chip enable output terminal GCE_1 are , 35th connection terminal of the terminal group 303 and 36th connection terminal. Furthermore, the plurality of data bus input terminals of the display control circuit 230 are connected to corresponding connection terminals after the 37th connection terminal of the terminal group 303, respectively.

  The control terminal DIR of the bidirectional balance transceiver 301 is connected to the fifth connection terminal of the terminal group 303, and the control terminal OE is connected to the output terminal of the AND circuit 302. One input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_0, and the other input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_1. Also, the sixth connection terminal and the seventh connection terminal of the terminal group 303 of the sub substrate 202 are connected to the power supply voltage (+3.3 V) terminal provided on the sub substrate 202, and the eighth connection terminal is connected to the sub substrate 202 It is connected to the provided ground (GND) terminal.

(2) Configuration of CGROM Substrate (NOR Type) Next, the internal configuration of the CGROM substrate 204a on which the NOR type CGROM 206a is mounted will be described with reference to FIG.

  When the NOR type CGROM 206a is mounted on the CGROM substrate 204a, the CGROM substrate 204a includes, together with the NOR type CGROM 206a, various signal wires (buses) and terminals including a plurality of connection terminals connected to the CGROM 206a via the various buses. A group 311 is provided.

  The connection terminals after the first to fourth connection terminals and the ninth connection terminal in the terminal group 311 provided on the CGROM substrate 204a are connected to the CGROM 206a.

  In the example shown in FIG. 12, since the CGROM 206a is a NOR type flash memory (random access flash memory), the first to fourth connection terminals and the ninth connection terminal to 34th in the terminal group 311 are used. The connection terminal is connected to the input terminal (not shown) of the address bus of the CGROM 206a. Further, the 35th connection terminal and the 36th connection terminal in the terminal group 311 are connected to the CG memory chip enable input terminal (not shown) of the CGROM 206a, and the connection control terminal after the 37th connection terminal is the CGROM 206a. Are connected to the data output terminal of the CGROM 206a used when acquiring image data (moving image / still image compressed data).

  The fifth connection terminal (predetermined connection terminal) in the terminal group 311 provided on the CGROM substrate 204a is connected to the eighth connection terminal via the signal wiring W2, and the eighth connection terminal is connected to the CGROM substrate 204a. It is connected to the provided ground (GND) terminal. That is, when the CGROM 206a is a NOR type flash memory, the fifth connection terminal is grounded via the signal wiring W2. Furthermore, the sixth connection terminal and the seventh connection terminal in the terminal group 311 are connected to the power supply voltage (+3.3 V) terminal provided on the CGROM substrate 204a.

  The number of connection terminals included in the terminal group 311 is the same as the number of connection terminals of the terminal group 303 for CGROM substrate connection provided on the sub substrate 202. When connecting (mounting) the CGROM substrate 204a to the sub substrate 202, both substrates are connected so that the connection terminal of the CGROM substrate 204a is connected to the connection terminal of the sub substrate 202 of the same terminal number. That is, as shown in FIG. 12, the first connection terminal, the second connection terminal,..., The 37 th connection terminal of the CGROM substrate 204a are the first connection terminal of the sub substrate 202, the second connection terminal,. 37 are respectively connected to the connection terminals.

(3) Configuration of CGROM Substrate (NAND Type) Next, the internal configuration of the CGROM substrate 204b on which the NAND type CGROM 206b is mounted will be described with reference to FIG. In the configuration of the CGROM substrate 204b shown in FIG. 13, the same components as those of the CGROM substrate 204a on which the NOR type CGROM 206a shown in FIG. 12 is mounted are denoted by the same reference numerals.

  When the NAND-type CGROM 206b is mounted on the CGROM substrate 204b, the CGROM substrate 204b is provided with a transistor circuit 312 as a peripheral circuit along with the NAND-type CGROM 206b. Further, the CGROM substrate 204b is provided with various signal wirings (buses) and a terminal group 311 including a plurality of connection terminals directly or indirectly connected to the CGROM 206b via the various buses.

  The first to fourth connection terminals in the terminal group 311 of the CGROM substrate 204 b are connected to the drain terminal of the transistor circuit 312. The gate terminal of the transistor circuit 312 is connected to the CGROM 206b, and the source terminal is connected to the ground (GND) terminal provided on the CGROM substrate 204b. That is, the first connection terminal to the fourth connection terminal are connected to the CGROM 206 b through the transistor circuit 312.

  In the example shown in FIG. 13, since the CGROM 206b is a NAND flash memory (sequential access flash memory), the gate terminals of the transistor circuit 312, that is, the first to fourth connection terminals in the terminal group 311. The terminal is connected to a ready / busy output terminal (not shown) provided in the CGROM 206b.

  Further, the fifth connection terminal (predetermined connection terminal) in the terminal group 311 of the CGROM substrate 204b is connected to the sixth connection terminal and the seventh connection terminal through the signal wiring W3, and the sixth connection terminal and the seventh connection are provided. The terminal is connected to a power supply voltage (+3.3 V) terminal provided on the CGROM substrate 204b. That is, when the CGROM 206 b is a NAND flash memory, the fifth connection terminal is connected to the power supply voltage (+3.3 V) terminal through the signal wiring W3.

  The eighth connection terminal in the terminal group 311 of the CGROM substrate 204b is connected to the ground (GND) terminal provided on the CGROM substrate 204b.

  Further, connection terminals after the ninth connection terminal in the terminal group 311 of the CGROM substrate 204b are connected to the CGROM 206b. At this time, the ninth to 34th connection terminals are connected to input terminals (not shown) of data related to an address provided on the CGROM 206b, and the 35th and 36th connection terminals are provided on the CGROM 206b. Connected to memory chip enable input terminal. Connection terminals after the 37th connection terminal are connected to a data output terminal (not shown) of the CGROM 206b used when the display control circuit 230 acquires image data (moving image / still image compressed data) from the CGROM 206b. Ru.

  Even when the NAND type CGROM 206b is mounted on the CGROM substrate 204b, the number of connection terminals included in the terminal group 311 of the CGROM substrate 204b is the same as that of the terminal group 303 for CGROM substrate connection provided on the sub substrate 202. The same as the number of connection terminals. When connecting (mounting) the CGROM substrate 204b to the sub substrate 202, both substrates are connected so that the connection terminal of the CGROM substrate 204b is connected to the connection terminal of the sub substrate 202 of the same terminal number. That is, as shown in FIG. 13, the first connection terminal, the second connection terminal,..., The 37th connection terminal,... Of the CGROM substrate 204b correspond to the first connection terminal, the second connection terminal,. 37 are respectively connected to the connection terminals.

[Communication operation between display control circuit and CGROM]
Next, an operation when the display control circuit 230 acquires image data (moving image / still image compressed data) from the CGROM will be described with reference to FIGS. 12 to 15. FIG. 14 is a truth table showing the correspondence between input signals and output signals in the AND circuit 302 provided on the sub substrate 202. FIG. 15 is a bidirectional balance transceiver 301 provided on the sub substrate 202. 6 is a truth table showing the correspondence between the signal levels applied to the control terminal OE and the control terminal DIR and the communication direction.

(1) Operation of AND Circuit and Bidirectional Balance Transceiver As shown in FIG. 14, the AND circuit 302 is bi-directional balance transceiver 301 only when a signal (voltage signal) of HIGH level is input to both input terminals. A high level signal is output to the control terminal OE of (1), and a low level signal is output to the control terminal OE under other input conditions.

  In the bidirectional balance transceiver 301, as shown in FIG. 15, when the signal (voltage signal) at the LOW level is input to the control terminal OE and the signal at the LOW level is input to the control terminal DIR, the bidirectional balance transceiver 301 The input / output terminal A0 to input / output terminal A3 of 301 function as output terminals, and the input / output terminal B0 to input / output terminal B3 function as input terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is from the display control circuit 230 toward the CGROM.

  Further, in the bidirectional balance transceiver 301, when a signal of LOW level is input to the control terminal OE and a signal of HIGH level is input to the control terminal DIR, input / output terminals A0 to I / O of the bidirectional balance transceiver 301 The terminal A3 functions as an input terminal, and the input / output terminal B0 to the input / output terminal B3 function as an output terminal. In this case, the communication direction between the display control circuit 230 and the CGROM is from the CGROM to the display control circuit 230.

  When the combination of the signal level input to the control terminal OE of the bidirectional balance transceiver 301 and the signal level input to the control terminal DIR is other than the above (a control terminal OE of the bidirectional balance transceiver 301 is HIGH) When a level signal is input), input / output terminal A0 to input / output terminal A3 and input / output terminal B0 to input / output terminal B3 of bidirectional balance transceiver 301 are in the HIGH impedance state ("Z" in FIG. 15). That is, the state is equivalent to the open state, and communication is not performed between the display control circuit 230 and the CGROM.

(2) Communication Operation Between Display Control Circuit and CGROM (NOR Type) First, consider the case where the CGROM substrate 204a on which the NOR type CGROM 206a is mounted is connected (mounted) to the sub substrate 202.

  In this case, in the present embodiment, a signal at the LOW level is output from at least one of the two CG memory chip enable output terminals GCE_0 and GCE_1 of the display control circuit 230. Therefore, the control terminal OE of the bidirectional balance transceiver 301 is LOW. A level signal is input. The signal levels of the CG memory chip enable output terminals GCE_0 and GCE_1 are set in the hardware initialization process (see FIG. 38 described later).

  In this embodiment, since the amplitude value of the output signal from the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals), which is preset by the sub control circuit 200, differs according to the type of CGROM, the display control circuit The amplitude value of the signal output from the CG memory chip enable output terminals GCE_0 and GCE_1 provided at 230 changes to be output according to the type of storage means. However, the aspect that "the amplitude value of the signal output is changed according to the type of CGROM" is not limited to this aspect. The display control circuit 230 detects the type of storage means connected, as described in Modification 7 to be described later, and based on the detection result, the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals) are used. The amplitude value of the signal to be output may be set.

  In addition, the fifth connection terminal of the sub substrate 202 to which the control terminal DIR of the bidirectional balance transceiver 301 is connected is grounded via the fifth connection terminal of the CGROM substrate 204a and the signal wiring W2, as shown in FIG. Therefore, a low level signal is input to the control terminal DIR.

  Therefore, when the CGROM substrate 204a on which the NOR type CGROM 206a is mounted is connected to the sub substrate 202, as shown in FIG. 15, the input / output terminal A0 to I / O terminal A3 of the bidirectional balance transceiver 301 serves as an output terminal. The input / output terminal B0 to the input / output terminal B3 act as input terminals. That is, the communication direction between the display control circuit 230 and the CGROM 206a in the bidirectional balance transceiver 301 is from the display control circuit 230 toward the CGROM 206a.

  In this case, signal lines connected through the first connection terminal to the fourth connection terminal of the sub substrate 202 and the first connection terminal to the fourth connection terminal of the CGROM substrate 204a can be used as an address bus, and display control The circuit 230 can perform the memory addressing operation normally on the NOR type CGROM 206a. As a result, the display control circuit 230 can directly perform addressing via the address bus to perform a data read operation.

(3) Communication Operation Between Display Control Circuit and CGROM (NAND Type) Next, consider the case where the CGROM substrate 204b on which the NAND type CGROM 206b is mounted is connected (mounted) to the sub substrate 202.

  Also in this case, in the present embodiment, a signal at the LOW level is output from at least one of the two CG memory chip enable output terminals CGE_0 and CGE_1 of the display control circuit 230. A low level signal is input. That is, in the present embodiment, the signal of the LOW level is input to the control terminal OE of the bidirectional balance transceiver 301 regardless of the type of the CGROM being either the NOR type or the NAND type. Also, as shown in FIG. 13, the fifth connection terminal of the sub substrate 202 to which the control terminal DIR of the bidirectional balance transceiver 301 is connected is connected to the power supply voltage (signal connection W3) through the fifth connection terminal of the CGROM substrate 204b. Since it is connected to the +3.3 V) terminal, a signal of HIGH level is inputted to the control terminal DIR.

  Therefore, when the CGROM substrate 204b on which the NAND type CGROM 206b is mounted is connected to the sub substrate 202, as shown in FIG. 15, input / output terminals A0 to input / output terminals A3 of the bidirectional balance transceiver 301 serve as input terminals. The input / output terminal B0 to the input / output terminal B3 act as an output terminal. That is, the communication direction between the display control circuit 230 and the CGROM 206b in the bidirectional balance transceiver 301 is from the CGROM 206b toward the display control circuit 230.

  In this case, use the signal wiring connected through the first connection terminal to the fourth connection terminal of the sub substrate 202 and the first connection terminal to the fourth connection terminal of the CGROM substrate 204b as the communication wiring of the ready / busy signal. Can. That is, in this case, when data is read from the NAND type CGROM 206b by the sequential access method, transmission processing from the CGROM 206 to the display control circuit 230 can be executed from the CGROM 206 of the ready / busy signal referred to by the display control circuit 230. As a result, the display control circuit 230 can properly execute the operation of acquiring the memory state (ready / busy state) with respect to the NAND type CGROM 206b.

  As described above, in the present embodiment, even if the type of CGROM changes, the communication operation between the display control circuit 230 and the CGROM can be normally performed without changing the configuration of the sub substrate 202. Therefore, in the present embodiment, an optimal CGROM can be selected in consideration of, for example, data capacity, communication speed, price and the like. Also, for example, when manufacturing a new pachinko gaming machine 1, the sub-substrate 202 used in the pachinko gaming machine manufactured in the past is diverted from the conditions such as data capacity, communication speed, etc., and only the type of CGROM is changed. Even if you do, you can easily cope with it. That is, in the pachinko gaming machine 1 of the present embodiment, it is possible to select the CGROM in accordance with the embodiment, and the extensibility of the pachinko gaming machine 1 can be secured.

  Furthermore, in the present embodiment, by using the bidirectional balance transceiver 301, the first connection terminal to the fourth connection terminal in the terminal group 303 of the sub substrate 202 and the first connection in the terminal group 311 of the CGROM substrate 204. The terminal to the fourth connection terminal can be used as data input / output terminals. In this case, there is no need to separately provide data input terminals and output terminals corresponding to the first to fourth connection terminals of the sub substrate 202 and the CGROM substrate 204, and space saving of the sub substrate 202 and the CGROM substrate 204 Can be implemented.

  As described above, in the present embodiment, the “communication form” between the display control circuit 230 and the CGROM can be switched by the bidirectional balance transceiver 301 according to the type of the CGROM. However, the “communication mode” between the display control circuit 230 and the CGROM in the present specification means the whole transmission / reception mode of various information between the display control circuit 230 and the CGROM.

  For example, in the “communication mode” between the display control circuit 230 and the CGROM as referred to in the present specification, data (image data (moving image / still image compressed data) necessary when displaying information on rendering operation on the display device 13 Not only the transmission / reception mode between the display control circuit 230 and the CGROM), but also the transmission / reception mode when the information for specifying the address of the data stored in the CGROM is communicated between the display control circuit 230 and the CGROM This means that the control circuit 230 also includes a transmission / reception mode when the ready / busy signal is received from the CGROM. The present invention is not limited to this, and the "communication form" referred to in the present specification may mean only the communication form of the portion in which the transmission / reception mode of information changes according to the type of CGROM.

<Type of gaming state>
Next, the types of gaming states controlled and managed by the main CPU 71 will be described.

  In the present embodiment, as the types of gaming states controlled and managed by the main CPU 71, “big hit gaming state” (special gaming state) and “small hit gaming state” (specific gaming state) in which expectations of prize balls are different from each other There is. The “big hit game state” is a game state in which a round game occurs (for example, 30 seconds) in which the open period (that is, the period of one round) of the shutter of the first large winning opening 53 or the second large winning opening 54 is long. It is a game state where a player can expect a big winning ball. That is, in the "big hit gaming state", the repetition mode of the open state and the closed state of the shutter of the big winning opening is advantageous by the player.

  On the other hand, "small hit gaming state" is a gaming state in which a round game occurs in which the period of one round is short (for example, 1.8 seconds etc.) compared to "big hit gaming state", and a player can not expect a big award ball It is a gaming state. That is, in the "small hit gaming state", the repetition mode of the open state and the closed state of the shutter of the big winning opening is disadvantageous to the player.

  Further, in the present embodiment, as the types of gaming states controlled and managed by the main CPU 71, “probability changing gaming states” (high probability gaming states) and “normal gaming states” (low) different in winning probability of “big hit” There is a probability game state).

  The "probable variation gaming state" is a gaming state in which the probability of winning the "big hit" (1/131 in the present embodiment) is high. On the other hand, the "normal game state" is a game state in which the probability of winning the "big hit" (in the present embodiment, 1/392) is lower than that in the "probability game state".

  Furthermore, in the present embodiment, as the type of gaming state controlled and managed by the main CPU 71, the “time saving game state” (high) in which the winning probability of the normal symbol (the probability that the normal symbol becomes the form of “hit”) mutually differs There are "winning game state" and "non-time short game state" (low winning game state).

  The "time-saving gaming state" in the present specification is a gaming state in which the probability of winning a normal symbol is high. That is, the "time saving game state" is a game state in which the normal motorized combination 46 (feather members) provided in the second start port 45 is likely to be in the open state (a game state in which the second start port winning is likely to occur) , It is a game state advantageous to the player. It should be noted that the "time saving gaming state" is ended when "big hit" is determined or when variation display of a special symbol for a predetermined number of time reductions to be described later is executed. In addition, in the time-saving game state, a fluctuation time shorter than the fluctuation time selected during the normal gaming state can be easily selected as the fluctuation time which is the time for performing the fluctuation display of the special symbol executed during the state. It may be controlled. By such control, the variation time may be shortened in the time saving gaming state than in the normal gaming state, and the gaming state advantageous to the player may be provided by increasing the number of games per unit time.

  On the other hand, "non-time-saving (no time-saving) gaming state" is a gaming state in which the probability of winning a normal symbol is lower than "time-saving gaming state". Therefore, the "non-time-saving gaming state" is a gaming state (a gaming state in which it is difficult for the second start opening winning to be generated) in which the ordinary electric character 46 (feather members) are not easily opened. It is a state.

  And in this embodiment, the game state of various combinations of the above-mentioned game state other than "big hit game state" and "small hit game state" is provided. Specifically, in the present embodiment, a gaming state (hereinafter referred to as a "high probability time shorting state") in which the "probable variation gaming state" and the "time reduction gaming state" occur simultaneously, and the "probability variation gaming state" A gaming state (hereinafter, referred to as a "high probability time short absence state") in which the "non-time saving gaming state" occurs simultaneously is provided. It should be noted that, in the state of "high probability time short absence", it is difficult for the player to determine whether or not the gaming state is the "probability changing gaming state", so here, such a gaming state is referred to as "latency gaming state It is also called. Further, in the present embodiment, a gaming state (hereinafter referred to as a "low probability time short absence state") in which the "normal gaming state" and the "non-short time gaming state" occur simultaneously, and the "normal gaming state" and the "short time gaming state" A game state (hereinafter referred to as a "low probability time short" state) in which the game state occurs simultaneously is also provided.

<Structure of data table stored in main ROM>
Next, the configuration of various data tables stored in the main ROM 72 of the main control circuit 70 will be described with reference to FIGS.

[Big hit random number judgment table (at the time of the first start mouth winning)]
First, with reference to FIG. 16, the big hit random number determination table (at the time of the first starting opening winning) will be described. The big hit random number judgment table (at the time of the first starting opening winning), "big hit", "small hit" based on the big hit judging random number value acquired when the game ball enters the first starting opening 44 (winning) And it is a table referred when determining any of "loss" by lottery.

  In addition, the random number value for big hit judgment is a random number value for judging the lottery result performed triggered by the starting opening winning combination, more specifically, the lottery of the special symbol (the first special symbol and the second special symbol) It is a random value indicating the result. Moreover, in the present embodiment, the jackpot determination random number value (the random number value for lottery of the special symbol) is selected from 0 to 65535 (65,536 types).

  In the present embodiment, when the game ball is won in the first starting opening 44, one of “big hit”, “small hit” and “loss” is determined by lottery. Therefore, as shown in FIG. 16, in the jackpot random number determination table (at the time of the first start-up winning), for each value (“0 (= off)” or “1 (= on)”) of the probability change flag The range of the jackpot judgment random number value for which the jackpot of "big hit", "small hit" and "lost" is determined, and the corresponding judgment value data ("big hit judgment value data", "small hit judgment value data") And the relationship with any one of “loss determination value data”. The definite change flag is one of the management flags stored in the main RAM 73, and is a flag for managing whether the gaming state is the "probable changing gaming state". When the gaming state is the "probable variation gaming state", the determination flag is "1".

  In the present embodiment, as shown in FIG. 16, when the first starting opening 44 is won, the probability change flag is “0”, and the jackpot determination random number value is any of “777” to “943”. , "Big hit" is won, "big hit judgment value data" is determined. That is, the winning probability of the “big hit” in this case (“selection rate” in FIG. 16) is 167/65536.

  In addition, when the first start opening 44 winning a prize, the probability change flag is "0" and the big hit judgment random number value is any of "1" to "300", "small hit" is won, and " The small hit judgment value data are determined. That is, the winning probability of "small hit" in this case is 300/65536.

  Furthermore, when the first start opening 44 winning, the probability change flag is "0" and the jackpot determination random number value is neither "1" to "300" nor "777" to "943", the "loss" Is won, and "loss determination value data" is determined.

  On the other hand, as shown in FIG. 16, when the first start opening 44 winning a prize, the probability change flag is “1” and the big hit determination random number value is any of “777” to “1277”, as shown in FIG. Is won, and "big hit judgment value data" is determined. That is, the winning probability of the "big hit" in this case ("selectivity" in FIG. 16) is 500/65536, which is higher than that when the probability change flag is "0".

  In addition, when the first start opening 44 winning a prize, the probability change flag is "1" and the big hit judgment random number value is any of "1" to "300", "small hit" is won, and " The small hit judgment value data are determined. That is, the winning probability of "small hit" in this case is 300/65536, which is the same as that when the probability change flag is "0".

  Furthermore, when the first start opening 44 winning, the probability change flag is "1" and the big hit determination random number value is neither "1" to "300" nor "777" to "1277" Is won, and "loss determination value data" is determined.

  As described above, in the present embodiment, when the game ball is won in the first starting opening 44, the selection rate (big hit probability) depends on whether or not the gaming state at the time of winning is "probable change gaming state". fluctuate. Specifically, the jackpot probability when the game ball is won in the first starting opening 44 when the gaming state is the "probability gaming state" is about three times that of the gaming state not being the "probability gaming state" Get higher.

[Big hit random number judgment table (at the time of the 2nd starting opening winning)]
Next, with reference to FIG. 17, the big hit random number determination table (at the time of second start opening winning) will be described. The big hit random number determination table (at the time of second start opening winning) is a lottery whether "big hit" or not based on the big hit determination random number value acquired when the game ball enters the second start opening 45 (winning) Is a table that is referred to when

  In the present embodiment, when the game ball is won in the second starting opening 45, either "big hit" or "loss" is determined by lottery. When the game ball is won in the second starting opening 45, the "small hit" is not won. Therefore, as shown in FIG. 17, in the jackpot random number determination table (at the time of second starting hole winning), every value (“0 (= off)” or “1 (= on)”) of the probability change flag “ The relationship between the range of the jackpot judgment random number values for which the jackpot of "big hit" and "loss" is determined, and the corresponding judgment value data (either "big hit judgment value data" or "loss judgment value data") Is defined.

  In the present embodiment, as shown in FIG. 17, when the second starting opening 45 is won, the probability change flag is “0”, and the jackpot determination random number value is any of “777” to “943”. , "Big hit" is won, "big hit judgment value data" is determined. That is, the winning probability of the “big hit” in this case (“selection rate” in FIG. 17) is 167/65536.

  Also, when the second start opening 45 winning, the probability change flag is "0" and the big hit determination random number value is neither "777"-"943", "loss" is won and "loss determination" Value data is determined.

  On the other hand, as shown in FIG. 17, when the probability change flag is “1” and the jackpot determination random number value is any of “777” to “1277” at the second start hole 45 winning, as shown in FIG. Is won, and "big hit judgment value data" is determined. That is, the winning probability (big hit probability) of “big hit” in this case is 500/65536, which is higher than that when the probability change flag is “0”.

  In addition, when the second start opening 45 winning a prize, the probability change flag is "1" and the big hit judgment random number value is neither "777" nor "1277", it becomes "loss" and "loss judgment value data" "Is determined.

  As described above, in the present embodiment, the selection rate (big hit probability) also depends on whether or not the gaming state at the time of winning is the "probability changing gaming state", even when the game ball is won in the second starting opening 45. Changes. Specifically, similarly to the first start opening 44 winning, also when the second start opening 45 winning, when the gaming state is "probability game state" when the game ball wins in the second start opening 45 The jackpot probability is about three times higher than that when the gaming state is not "probable gaming state".

[Symbol determination table (at the time of the first start mouth winning)]
Next, with reference to FIG. 18, the symbol determination table (at the time of winning at the first starting opening) will be described.

  In this embodiment, the winning types (“big hit”, “small hit” or “missing”) of the lottery based on the jackpot determination random number value performed when the game ball is won in the first starting opening 44, and the first start The special symbol is selected based on the symbol random number value (symbol determination random number value) acquired at the time of the mouth winning. The symbol determination table (at the time of winning at the first starting opening) is a table to be referred to when selecting the special symbol. The symbol random number value is a random number value for determining a special symbol, and is selected from 0 to 99 (100 types) regardless of the winning classification of the lottery based on the jackpot determination random number value.

  In the symbol determination table (at the time of winning the first starting opening), as shown in FIG. 18, a symbol designation command for designating a special symbol for each determination value data indicating the winning classification of the lottery based on the big hit determination random number value. A relation between ("zA1" to "zA3") and a symbol random number for which the symbol designation command is selected is defined.

  In addition, when the winning classification of the lottery based on the big hit judgment random number value is “small hit” (small hit judgment value data), the symbol designation command to be selected is one type (zA2), and the symbol designation is sure The command (zA2) is determined. In addition, even when the winning classification of the lottery based on the jackpot determination random number value is "loss" (loss determination value data), the symbol designation command to be selected is one type (zA3), and the symbol designation command (always) zA3) is determined.

  On the other hand, when the winning classification of the lottery based on the big hit judgment random number value is "big hit" (big hit judgment value data), as shown in FIG. 18, there are a plurality of types of special symbols to be selected, and "big hit" A plurality of kinds (“z0” to “z4”) of symbol designation commands (big hit selection symbol command in FIG. 18) are also prepared. And at the time of the "big hit", the big hit time selection symbol command determined also changes according to the symbol random number value acquired. For example, when the symbol random number value acquired at the time of "big hit" is any of "40" to "59", the big hit selection symbol command "z2" is selected, and the selection rate is 20/100 Become.

[Symbol determination table (at the second start opening winning)]
Next, with reference to FIG. 19, the symbol determination table (at the time of second start opening winning) will be described.

  In this embodiment, the winning type (“big hit” or “loss”) of the lottery based on the jackpot determination random number value performed when the game ball is won in the second starting opening 45 and the second starting opening winning is obtained The special symbol is selected based on the symbol random number value (random number value for symbol determination). The symbol determination table (at the time of second start opening winning) is a table to be referred to when selecting the special symbol.

  In the symbol determination table (at the time of second start opening winning), as shown in FIG. 19, a symbol designation command for designating a special symbol for each determination value data indicating the winning classification of the lottery based on the big hit determination random number value. The relationship between ("zA1" and "zA3") and the symbol random number for which the symbol designation command is selected is defined.

  In addition, even when the winning classification of the lottery based on the jackpot determination random number value is "loss" (loss determination value data), the symbol designation command to be selected is one type (zA3), and the symbol designation command (be sure to be selected) zA3) is determined.

  On the other hand, when the winning classification of the lottery based on the big hit judgment random number value is "big hit" (big hit judgment value data), as shown in FIG. 19, there are a plurality of types of special symbols to be selected, and "big hit" A plurality of kinds (“z0” and “z4”) of symbol designation commands (big hit selection symbol command in FIG. 19) are also prepared. And at the time of the "big hit", the big hit time selection symbol command determined also changes according to the symbol random number value acquired. For example, when the symbol random number value acquired at the time of "big hit" is any of "29" to "99", the big hit selection symbol command "z4" is selected, and the selection rate is 80/100 Become.

[Big hit type decision table]
Next, the big hit type determination table will be described with reference to FIGS. In this embodiment, when the jackpot selection symbol command (any one of “z0” to “z4”) is determined with reference to the symbol determination table (see FIGS. 18 and 19), the determined jackpot selection is performed. Based on the symbol command, the type of "big hit" (content of the big hit game) is determined. The big hit type determination table is a table that is referred to when deciding the type of “big hit” (content of the big hit game) based on the big hit time selection symbol command.

  Further, in the present embodiment, a big hit type determination table is provided for each gaming state at the time of the “big hit” winning. FIG. 20 shows a jackpot type determination table (part 1) to be referred to when the “big hit” is won when the gaming state is “no low probability time short”, and FIG. 21 shows the gaming state “low probability time short It is a jackpot type determination table (part 2) to be referred to when the "big hit" is won when "yes". Further, FIG. 22 is a big hit type determination table (part 3) to be referred to when the “big hit” is won when the gaming state is “high probability no time short”, and FIG. 23 is a gaming state “high It is a jackpot type determination table (part 4) to be referred to when the player wins the “big hit” when “when there is a short time”.

  In each big hit type determination table, the relationship between a big hit time selection symbol command ("z0" to "z4") and various parameters for determining the type of "big hit" is defined. As various parameters for determining the type of "big hit" (content of the big hit game), the value of the time reduction flag, the number of time reductions, the value of the probability change flag, and the number of rounds in the big hit game are defined.

  For example, in the case of winning the "big hit" in the "high probability time low" state, and "z1" is determined as the big hit time selection symbol command, as shown in FIG. As various parameters for determining the content of the jackpot game, a time saving flag “1”, a time saving count “100”, a probability change flag “0”, and a round number “10” are set.

  The “number of rounds” defined in each big hit type determination table is the number of rounds in which the opening time of the big winning opening is relatively long in the big hit game. The "time saving flag" is one of the management flags stored in the main RAM 73, and is a flag for managing whether or not the gaming state is the "time saving gaming state". When the gaming state is "time saving game state", the time saving flag is "1 (on)". In addition, "time reduction number" is the number of times of variation display of the special symbol given in "time reduction gaming state".

[Prize presentation information decision table]
Next, with reference to FIG. 24, the prize effect information determination table will be described.

  In the present embodiment, the main control circuit 70 (main CPU 71) selects the winning type ("big hit", "small hit" or "lost") determined at the time of winning (when starting opening) and symbol designation command or big hit. Based on the time selection symbol command, the sub control circuit 200 determines information to be used when determining the content of the effect. For example, in the sub control circuit 200, information to be used when determining the content regarding the color change presentation of the holding symbol indicating the holding ball of the special symbol, the content regarding the pre-reading presentation, etc. is determined. The prize effect information determination table is referred to when the outline of the effect contents to be executed by the sub control circuit 200 is determined based on the information acquired by the main control circuit 70 at the time of winning (when starting opening winning). It is a table.

  "At the time of winning effect information 1" showing an outline of the combination of various information determined at the time of winning (at the time of starting opening winning) and the contents of the effects executed by the sub control circuit 200 The relationship with the winning presentation information 2 is defined. In this embodiment, the type of starting opening, the type of determination value data, the type of big hit selection symbol command, and the type of symbol designation command are various types of information determined at the time of winning (at starting opening). It is specified in the time presentation information determination table.

  In the sub-control circuit 200, the effect data 1 for winning (“1A” to “1D”) defined in the effect information determining table for winning is mainly a color change effect of a holding symbol indicating a holding ball of a special symbol. This is presentation information that is used when determining the content regarding. When the sub control circuit 200 receives the prize effect information 1 determined based on the prize effect information determination table, the sub control circuit 200 changes the effect of the color change effect of the holding symbol included in the category of the prize effect information 1. One effect pattern is selected from a plurality of effect patterns regarding.

  In addition, the prize effect information 2 ("2A" to "2D") specified in the prize effect information determination table is a pre-reading effect (pre-reading continuous on the basis of the holding ball of the special symbol in the sub control circuit 200) Effect information used to determine the content of the effect). When the sub control circuit 200 receives the prize effect information 2 determined on the basis of the prize effect information determination table, the sub control circuit 200 generates a plurality of types of pre-read effects included in the category of the prize effect information 2. Select one effect pattern from the patterns.

  When the winning effect information determination table of this embodiment is referred to, for example, when “big hit” is won at the time of the first starting opening winning, “1A” as winning effect information 1 regardless of the type of big hit selection symbol command Is determined, and "2A" is determined as effect information 2 at the time of winning.

[Change production pattern determination table]
Next, with reference to FIG. 25, the variation presentation pattern determination table will be described.

  In the present embodiment, the main control circuit 70 (main CPU 71) selects a win type ("big hit", "small hit" or "lost"), a symbol designation command, a big hit selection symbol command, when the variation display of the special symbol starts. Based on the information such as the change time, the change effect pattern of the special symbol is determined. The variation presentation pattern determination table is a table referred to when determining the variation presentation pattern of this special symbol.

  In addition, the change effect pattern (information included in the special symbol effect start command described later) determined based on the change effect pattern determination table is transmitted from the main control circuit 70 to the sub control circuit 200 (host control circuit 210) . When the sub control circuit 200 receives the information on the change effect pattern, the sub control circuit 200 determines the type of effect based on the received information such as the change effect pattern and the game state.

  As shown in FIG. 25, in the fluctuation effect pattern determination table, the combination of the symbol designating command determined at the time of winning (starting opening winning), the combination of the big hit selection symbol command and the variation time of the special symbol, and the variation display of the special symbol A relationship with the type of effect (variation effect pattern) executed by the sub control circuit 200 is defined therein.

  In the present embodiment, the variation production pattern is represented by several characters of two digits, and the “upper” (first digit) parameter and the “lower” (second digit) described in the variation presentation pattern column in FIG. It is expressed in combination with parameters. For example, when the symbol designating command determined at the time of winning (when starting opening winning) is “zA1”, the big hit selection symbol command is “z0”, and the variation time of the special symbol is “15000 msec”. The parameter is “C1” (a combination of the upper “C” and the lower “1”).

  In addition, in this embodiment, the information of a fluctuation production parameter is contained in the below-mentioned special symbol production start command. At this time, the “upper” parameter and the “lower” parameter defined in the variation effect pattern column are stored in different parameter areas. Therefore, in the variation presentation pattern determination table, the “upper” parameter and the “lower” parameter of the variation presentation pattern are separately defined.

<Structure of data table stored in sub main ROM>
Next, the configuration of various data tables stored in the sub main ROM 205 of the sub control circuit 200 will be described with reference to FIG.

[Change production table]
First, the fluctuation presentation table will be described with reference to FIG.

  In the pachinko gaming machine 1 of the present embodiment, as described above, various effects are executed during the variable display of the special symbol by the control of the sub control circuit 200 (host control circuit 210). The contents (render pattern) of the effect performed at this time are the fluctuation symbols of the special symbol included in the special symbol effect start command described later transmitted from the main control circuit 70 to the sub control circuit 200 at the start of the fluctuation display of the special symbol. It is determined based on the information of the pattern and the like. The fluctuation presentation table is referred to when determining the contents of the presentation (rendering pattern) based on the information such as the fluctuation presentation pattern and the game state.

  As shown in FIG. 26, the variation effect table has a combination of various information (including information on variation effect patterns) determined at the time of winning (when starting opening) and an effect pattern determined by lottery (“EN00 “EN 44”) and the contents of the effect, and the correspondence between the random number value for selecting (determining) each effect pattern and the selection rate (wining probability). In the present embodiment, as the various information determined at the time of winning (when starting opening winning), the types (“A0” to “A4”, “B1” to “B3” and “C1”) of the variation effect pattern of the special symbol "-" CF "), variation time of special symbol, winning classification (" big hit "," small hit "or" loss "), symbol designation command and big hit selection symbol command are defined in the variation effect table.

  In this embodiment, it is assumed that the fluctuation time of the special symbol specified in the fluctuation presentation table is substantially the same as the presentation time of the corresponding presentation pattern. Further, the random number value defined in the fluctuation presentation table is a random number value acquired in the sub lottery process, and is any one of “0” to “999” (1000 types).

  When determining the effect pattern with reference to the change effect table of the present embodiment, for example, when the change pattern of the special symbol determined at the start of the change display of the special symbol is "C1" and when the effect pattern is selected When the random number value acquired in step S is any one of “0” to “499”, “EN 15” is selected as the effect pattern. In this case, an effect called "normal reach effect A" is performed in the variable symbol display period (15000 msec) of the special symbol. And with the completion | finish of "normal reach production A", the display of a "big hit" aspect is performed on the display area 13a of the display apparatus 13, and a special symbol changes and stops.

<Overview of drawing control method>
Next, the outline of the drawing process executed by the display control circuit 230 when the drawing request is output from the host control circuit 210 to the display control circuit 230 will be described with reference to FIG. FIG. 27 is a diagram showing a flow of image data (moving image data and still image data) at the time of drawing processing.

  In the present embodiment, data (compressed data) of an image (moving image and / or still image) to be displayed on the liquid crystal screen of the display device 13 is stored in the CGROM 206 in the CGROM substrate 204. Then, when the drawing request is input to the display control circuit 230, the display control circuit 230 first reads out the compressed image data from the CGROM 206 and decodes (expands). At this time, when the moving picture compressed data is read, the moving picture compressed data is decoded by the moving picture decoder 234 in the display control circuit 230, and when the still picture compressed data is read, the inside of the display control circuit 230 is Still image compressed data is decoded by the still image decoder 235 of FIG.

  Next, the display control circuit 230 writes the decoding result (image expansion data) of the image data into a predetermined buffer designated as the texture source. In the present embodiment, a movie buffer, a texture buffer, and a sprite buffer in the built-in VRAM 237 provided in the SDRAM 250 (external RAM) are specified as texture sources. For example, when one moving image is displayed, the expanded moving image data (decoding result) is written out to the movie buffer in the SDRAM 250. Also, for example, when displaying one still image, the expanded still image data is written out to the sprite buffer in the built-in VRAM 237.

  Next, the display control circuit 230 specifies a rendering target to which the rendering (drawing) result of the image data is written. As a rendering target, for example, a frame buffer provided in the SDRAM 250 (external RAM), a frame buffer provided in the built-in VRAM 237, or the like can be specified.

  Next, the display control circuit 230 operates the rendering engine 241 to perform a rendering process on the decoding result of the image data written to the texture source, and writes the rendering result to the rendering target. Note that in this processing, rendering processing is performed according to specification information (various pieces of information input from the 3D geometry engine 240) such as scaling or rotation of a moving image.

  Next, the display control circuit 230 displays the rendering result (display output data) written out to the rendering target on the display screen of the display device 13.

  In the present embodiment, two frame buffers are prepared as rendering targets. Then, when the rendering result is written from the rendering engine 241 to the frame buffer, the frame buffer to which the rendering result is written is switched for each frame. For example, when rendering results are written to one frame buffer in a predetermined frame, rendering results are written to the other frame buffer in the next frame, and rendering results are written to one frame buffer in the next frame. That is, in the present embodiment, the process of writing rendering results to one frame buffer and the process of writing rendering results to the other frame buffer are alternately switched frame by frame and executed.

  In addition, in the flow of the writing process and the display process of the rendering result described above, the rendering result written out to one frame buffer in a predetermined frame is displayed on the display screen of the display device 13 in the next frame (one Function of the frame buffer is switched from the drawing function to the display function). Also, the rendering result written out to the other frame buffer in the next frame is displayed on the display screen of the display device 13 in the next frame (the function of the other frame buffer is switched from the drawing function to the display function). That is, in the present embodiment, the display processing of the rendering result in one frame buffer and the display processing of the rendering result in the other frame buffer are alternately switched and executed for each frame.

<Overview of voice reproduction control method>
Next, when the sound request is output from the host control circuit 210 to the audio / LED control circuit 220, the outline of the audio reproduction process executed by the audio / LED control circuit 220 will be described returning to FIG.

  In the present embodiment, audio data to be output to the speaker 11 is stored in the CGROM 206. The audio data stored in the CGROM 206 is phrase compressed data specified by a 13-bit phrase number NUM (000H to 1FFFH), and one set of background music (BGM) or a group of Up to 8192 types (= 213) of effect sound (precaution sound) and the like are stored corresponding to the phrase number NUM. The phrase number NUM is identified by the setting value (operation parameter) of the voice command transmitted from the host control circuit 210 to the command register 225 of the voice / LED control circuit 220.

  The voice command is an Individual Write application that transmits a set value of 1 byte length to any one voice control register of a large number of voice control registers built in the voice / LED control circuit 220, or N continuous series Is used in Block Write application to transmit a group of N set values to the voice control register group of

  In any case, the voice control register to be accessed is specified by a 1-byte register address, and the storage capacity of each voice control register is 1 byte. Further, in the present embodiment, a large number of voice control registers are secured by dividing into seven register banks. That is, since the register bank is divided into seven, the total number of voice control registers is, in principle, up to 7 × 256.

  In this embodiment, in all the register banks, a specific register address is a voice control register for setting the register bank. Therefore, in order to specify any one of 7 × 256 voice control registers, the register bank is written to the voice control register for bank setting by the preceding voice command, and then voice control belonging to the register bank is performed. The register is specified by a 1-byte register address.

  By the way, the setting operation of the setting value to the voice control register does not necessarily need to directly designate the register address of the voice control register to be set, and SAC data (Simple Access Code Data) stored in the CGROM 206 or A sequence code can also be specified to complete a series of setting operations for a group of voice control registers. Then, in order to realize such an operation, the voice / LED control circuit 220 incorporates four simple access controllers 226a (simple access controllers) shown in FIG. 8 and 16 sequencers 226b (Sequencer). .

  From the SAC (Simple Access Code) data for causing the simple access controller 226a to function, the SAC data includes the register address (1 byte) of the voice control register and the setting value (1 byte) to the voice control register. This means a group of up to 512 data sets (= 1024 bytes) corresponding to each other and terminated at the SAC end code (FFFFH) (see FIG. 8).

  In the case of the present embodiment, such SAC data can be provided up to 8192 types (= 213), and the host control circuit 210 sets the SAC number of 13 bit length to the voice control register for SAC control (see FIG. 8). The simple access controller 226a can be made to function by writing in. The simple access controller 226a having started the function reads the group of SAC data specified by the SAC number sequentially from the CGROM 206, and sets the setting value indicated by the SAC data in the voice control register indicated by the SAC data.

  Therefore, the host control circuit 210 only needs to write (register) the SAC number in the voice control register for SAC control, and does not designate the register address of the voice control register individually, but performs a series of setting operations. Can be instructed. In addition, in the voice control register for SAC control, a standby time (wait information as attached data) that defines the start timing of a series of setting operations can be set, and the SAC number to the voice control register for SAC control The setting start timing to the voice control register by the simple access controller 226a can also be delayed from the write timing of.

  Subsequently, a sequence code (Sequence Code) for causing the sequencer 226b to function will be described. Similarly to the SAC data, the sequence code is also a plurality of sets of data in which the register address (1 byte) of the voice control register and the setting value (1 byte) to the voice control register correspond to each other (see FIG. 8). However, unlike the SAC data, the sequence code can define a plurality of operation steps (a plurality of sequence steps) which can be intermittently executed after a predetermined waiting time.

  Also, in the voice control register for sequencer (Sequencer) control, for each sequencer SQ0 to SQ15, a waiting time (waiting information) defining the start timing of the setting operation, presence or absence of repetitive operation, and the number of repetitions thereof (loop information Can be included. Therefore, the sequence code specifies a series of voice effects to be executed in a predetermined time.

  As shown in FIG. 8, the plurality of operation steps are separated by a step end code (FFFEH), and the end of the plurality of operation steps is terminated by a sequence end code (FFFFH). In the case of this embodiment, up to 8192 types (= 213) of sequence codes can be provided, and the host control circuit 210 arranges the sequence code numbers of 13 bit length and the attached data defining the operation of the sequencer A series of setting operations can be instructed to the sequencer 226b by writing in the voice control register for control.

  In the present embodiment, such SAC data and sequence code are stored in advance in the CGROM 206 only for the necessary sets, and a group of SAC data and a group of sequence codes are specified by the SAC number and the sequence code number. Therefore, in the case of this embodiment, the voice command for the Write application not only defines the setting operation directly to the voice control register, but also defines the indirect setting operation via the simple access controller 226a and the sequencer 226b. The case is also included.

  In order to realize the above operation, the host control circuit 210 and the voice / LED control circuit 220 have a parallel signal line (data bus) capable of transmitting and receiving 1-byte data, and a 2-bit operation management capable of transmitting operation management data. A data line (address bus), a control signal line having a 2-bit length capable of controlling a read / write operation, and a chip select signal line for selecting the audio / LED control circuit 220 are connected.

  The parallel signal lines are realized by the data bus of the host control circuit 210, and the operation management data lines are realized by the address bus of the host control circuit 210. The voice / LED control circuit 220 is provided with three port numbers PORT having the upper 6 bits in common and the lower 2 bits of 00, 01, 10, and the host control circuit 210 has these ports. When an I / O READ instruction or an I / O WRITE instruction for the number PORT is executed, the circuit is configured such that the chip select signal CS is at the active level in any case.

  The data output to the lower 2 bits A0 to A1 of the address bus when the I / O READ instruction or I / O WRITE instruction is executed becomes operation management data A0 to A1 for the audio / LED control circuit 220, and this 2 bits A0 Whether 1-byte data of the data bus at that time is a register address or write data or read data is specified on the basis of A1.

  That is, if the address data is [00], the data on the data bus at that timing is evaluated as a register address, while if the address data is [01], the data on the data bus at that timing is write data or read It becomes data. The case where the I / O READ instruction is executed is read data, and the case where the I / O WRITE instruction is executed is write data.

  Therefore, the voice command transmission operation of writing a predetermined setting value into a predetermined voice control register changes the lower 2 bits A0 and A1 of the port number PORT of the voice / LED control circuit 220 while carrying out the I / O WRITE instruction. It is realized by executing continuously. Specifically, while the lower 2 bits A0 to A1 of the address data are transitioned from [00] to [01], 1 byte data of the data bus is read from [register address of voice control register] to [voice control register] By switching to [write data], a transmission operation of a predetermined voice command is realized.

  As in the case of transmitting the SAC number (13 bits), the sequence code number (13 bits), and the control data (wait information, loop information, etc.) accompanying this, the write data has a plurality of bytes, When the register address of the register is continuous, write data of a plurality of bytes are transmitted while repeating the operation management data A0 to A1 of [01] from [00] → [01] → [01] → [01]. .

  The voice command transmitted in this manner is then effective inside the voice / LED control circuit 220 unless there is a communication error. However, when a communication error is recognized, such as when data of a plurality of bytes do not match each other, the voice command is not made effective. Then, an error flag of the voice control register is set, and this error flag (status information STS) is an I / O READ instruction which shifts the operation management data A0 to A1 of the address bus from [01] to [10]. Can be received by

  As described above, in this embodiment, error information with a plurality of bit lengths (abnormality in the final cycle of causing the operation management data A0 to A1 to transition from [00] → [01] → ... [01] → [10] Time can get FFH). Then, by retransmitting the voice command that could not be properly parallel-transmitted, the voice presentation can be appropriately progressed. Therefore, according to the configuration of the present embodiment, it is possible to eliminate the unnaturalness in which the sound effect is suddenly interrupted.

  On the other hand, in the data read operation by the I / O READ operation, the I / O WRITE instruction and the I / O READ instruction are continuously executed while transitioning the lower 2 bits A0 and A1 of the port number PORT of the audio / LED control circuit 220. To be realized. When the read data has a plurality of bytes, the I / O READ instruction is continued by the required number of bytes.

  Specifically, first, as an I / O WRITE operation, the register address of the voice control register storing the operation status etc. for the port number PORT where the lower 2 bits A0 to A1 of the address data becomes [00]. 1 byte long)] is output. Next, if an I / O READ instruction is executed for a port number PORT where the lower 2 bits A0 to A1 of the address data is [01], necessary data such as operation status is acquired from a predetermined voice control register. Can.

  The audio reproduced by the audio / LED control circuit 220 having the above configuration is digital audio signals in the form of 5-bit signals (SCLK, LRO, SD0, SD1, SD2) as digital audio signals of the audio / LED control circuit 220. It is transmitted to the power amplifier 262, is class D amplified by the digital audio power amplifier 262, and is supplied to each speaker as an analog audio signal. Specifically, the amplified output (analog audio signal) of the digital audio power amplifier 262 is supplied to the lower speaker for bass, and the amplified output (analog audio signal) of the digital audio power amplifier 262 is Four regular speakers (for example, see FIG. 9 (L0, R0, L1, R1) and two deep bass speakers (for vibration) (for example, see FIG. 9 (SUB0, It is supplied to SUB1).

<Description of operation of main control circuit>
Next, contents of various processes executed by the main CPU 71 of the main control circuit 70 will be described with reference to FIGS. 28 to 35.

[Main control main processing]
First, main control main processing under control of the main CPU 71 will be described with reference to FIG. FIG. 28 is a flowchart showing the procedure of the main control main process in the present embodiment.

  When the pachinko gaming machine 1 is powered on, first, the main CPU 71 performs an initial setting process (S1). In this processing, the main CPU 71 performs processing such as, for example, access permission to the main RAM 73, backup restoration, initialization of a work area, and the like. Next, the main CPU 71 executes an update process of the initial value random number (S2). In this process, the main CPU 71 updates the initial random number counter value.

  Next, the main CPU 71 conducts special symbol control processing (S3). In this process, the main CPU 71 conducts predetermined control processes regarding the progress of the special symbol game and the special symbols (first special symbol and second special symbol) displayed on the special symbol display device 61. In addition, the details of the special symbol control process will be described later with reference to FIG. 29 described later.

  Next, the main CPU 71 performs normal symbol control processing (S4). In this processing, the main CPU 71 conducts predetermined control processing regarding the progress of the normal symbol game and the normal symbol displayed on the normal symbol display device 62.

  Next, the main CPU 71 executes control processing of the symbol display device (S5). In this process, the main CPU 71 changes the special symbol (first special symbol and second special symbol) and the ordinary symbol based on the execution result of the special symbol control processing (S3) and the normal symbol control processing (S4). Control display of display.

  Next, the main CPU 71 executes game information data generation processing (S6). In this process, the main CPU 71 generates game information data to be transmitted to the payout / fire control circuit 123, the sub control circuit 200, the hall computer of the game shop, etc., and stores the game information data in the main RAM 73.

  Next, the main CPU 71 executes storage and gaming state data generation processing (S7). In this process, the main CPU 71 generates storage / playing state data to be transmitted to the sub control circuit 200 based on the value of the probability change flag and the value of the time saving flag, and stores the storage / playing state data in the main RAM 73.

  Then, after the process of S7, the main CPU 71 returns the process to the process of S2, and repeats the processes after S2 described above.

[Special symbol control process]
Next, with reference to FIG. 29, the special symbol control process performed in S3 in the main control main process (see FIG. 28) will be described. FIG. 29 is a flow chart showing a procedure of special symbol control processing in the present embodiment. Numerical values ("00" to "08") in parentheses in parallel with the reference numerals of the respective processing steps shown in FIG. 29 indicate the value of the control state flag, and this control state flag is stored in a predetermined storage in the main RAM 73. It is stored in the area. The main CPU 71 advances the special symbol game by executing each processing step corresponding to the numerical value of the control state flag.

  First, the main CPU 71 loads a control state flag (S11). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

  The main CPU 71 determines whether to execute various processes of S12 to S20 described later based on the value of the control state flag loaded in S11. The control state flag indicates the game state of the special symbol game, and enables one of the processes in S12 to S20 to be performed.

  Further, the main CPU 71 executes the processing of each step at a predetermined timing determined in accordance with the waiting time or the like set for each processing of S12 to S20. In the period before reaching the predetermined timing, other subroutine processing is executed without executing the processing of each step. Further, a system timer interrupt process (see FIG. 33 described later) is also executed at a predetermined cycle.

  When the process of S11 is completed, the main CPU 71 conducts special symbol storage check process (S12).

  In this process, the main CPU 71 checks the number of pending display of the variable display of the special symbol when the control status flag is the value ("00") indicating the special symbol storage check process, and the number of pending objects is not "0". (When there is a holding ball), processing such as determination of a hit, determination of a special symbol, determination of a variation pattern of a special symbol, etc. is performed. Further, in this process, the main CPU 71 sets a control state flag to a value (“01”) indicating a special symbol fluctuation time management process (S13) described later, and corresponds to the fluctuation pattern determined in the current process. The variation time of the special symbol is set to the waiting time timer. That is, by this process, after the variation time of the special symbol corresponding to the variation pattern determined in the process of S12 has elapsed, it is set so that the below-mentioned special symbol variation time management process is executed.

  On the other hand, when the number of held items is “0” (when there is no holding ball), the main CPU 71 executes a demonstration display process for displaying a demonstration screen. The details of the special symbol storage check process will be described later with reference to FIG. 30 described later.

  Next, the main CPU 71 conducts special symbol variation time management processing (S13). In this process, the main CPU 71 determines that the control status flag is a value ("01") indicating the special symbol variation time management process, and when the variation time of the special symbol has passed, the control symbol indicates the special symbol described later. A value ("02") indicating the time management process (S14) is set, and the wait time after decision is set in the wait time timer. That is, by this process, after the waiting time after the determination set in the process of S13 has elapsed, it is set so that the later-described special symbol display time management process is executed.

  Next, the main CPU 71 conducts special symbol display time management processing (S14). In this process, the main CPU 71 determines that the control state flag is a value indicating the special symbol display time management process ("02"), and the waiting time after determination set in the process of S13 has passed, the result of the hit determination. It is determined whether or not "big hit" or "small hit". Then, when the result of the hit determination is "big hit" or "small hit", the main CPU 71 sets a value ("03") indicating the big hit start interval management process (S15) described later in the control state flag, The time corresponding to the big hit start interval is set in the waiting time timer. That is, by this processing, after the time corresponding to the jackpot start interval set in the processing of S14 has elapsed, it is set so that the jackpot start interval management processing described later is executed.

  On the other hand, when the result of the hit determination is not "big hit" or "small hit", the main CPU 71 sets a value ("08") indicating the special symbol game end process (S20) described later in the control state flag. That is, in this case, it is set to execute a special symbol game end process described later. In addition, the details of the special symbol display time management process will be described later with reference to FIG. 31 described later.

  Next, when the main CPU 71 determines in S14 that the result of the hit determination is "big hit" or "small hit", it performs a big hit start interval management process (S15). In this process, the main CPU 71 determines that the control state flag is a value (“03”) indicating the big hit start interval management process, and the first CPU 71 receives the time corresponding to the big hit start interval set in the process of S14. In order to open the special winning opening 53 or the second large winning opening 54, the variable positioned in the main RAM 73 is updated based on the data read from the main ROM 72.

  Further, in this process, the main CPU 71 sets a value ("04") indicating the in-progress opening process (S16) described later in the control state flag, and the upper opening time limit of the in-progress opening (for example, 30 sec). Set to the special winning opening open time timer. That is, it is set by this process that a special winning opening open processing described later is executed.

  Next, the main CPU 71 executes a special winning opening open process (S16). In this process, the main CPU 71 first opens the condition that the number of big winning opening winning counters is equal to or more than the predetermined number when the control status flag is a value ("04") indicating the big winning opening opening processing. It is determined whether one of the conditions that the upper limit time has elapsed (the special winning opening open time timer is “0”) is satisfied (a predetermined closing condition is satisfied).

  In S16, when one of the conditions is satisfied, the main CPU 71 updates the variable located in the main RAM 73 in order to close the predetermined large winning opening (the first large winning opening or the second large winning opening). Do. Then, the main CPU 71 sets a value ("05") indicating the big winning opening residual ball monitoring process (S17) described later in the control status flag, and sets the big winning opening residual ball monitoring time in the waiting time timer . That is, by this process, it is set so that the below-mentioned in-game winning hole in-house residual ball monitoring process is executed after the in-game winning hole in-game remaining ball monitoring time set in S17 has elapsed.

  Further, at S16, the main CPU 71 transmits an inter-round display command to the sub control circuit 200 immediately before the end of the special winning opening open processing.

  Next, the main CPU 71 executes a special winning opening residual ball monitoring process (S17). In this process, the main CPU 71 determines that the control status flag is a value ("05") indicating the residual ball monitoring process in the special winning opening, and when the residual ball monitoring time in the special winning opening has elapsed, It is determined whether the condition that the value is equal to or more than the maximum value of the number of times of opening of the special winning opening (the final round) is satisfied.

  When the main CPU 71 determines in S17 that the above condition is not satisfied, the main CPU 71 sets a value (“06”) indicating the special winning opening reopening waiting time management process in the control state flag. Further, the main CPU 71 sets a time corresponding to the inter-round interval in the waiting time timer. That is, by this processing, after the time corresponding to the inter-round interval has elapsed, it is set so that the waiting time management processing before the special winning opening reopening described later is executed.

  On the other hand, when the main CPU 71 determines that the above condition is satisfied in S17, the main CPU 71 sets a value ("07") indicating the big hit end interval processing in the control state flag, and the time corresponding to the big hit end interval. (Big win end interval time) is set to the waiting time timer. That is, by this processing, after the time corresponding to the big hit end interval set in S17 has elapsed, it is set so that the big hit end interval process described later is executed.

  Next, in S17, when the main CPU 71 determines that the value of the special winning opening open frequency counter is not greater than or equal to the maximum value of the special winning opening opening frequency, the main CPU 71 executes waiting time management processing before the special winning opening reopening ( S18). In this process, the main CPU 71 determines that the control status flag is a value ("06") indicating the waiting time management process before the big winning opening reopening, and the time corresponding to the interval between rounds has passed, the big winning opening opening. The value of the number counter is updated so as to increase "1". Further, the main CPU 71 sets a value (“04”) indicating the special winning opening open processing to the control state flag. Then, the main CPU 71 sets the open upper limit time (for example, 30 seconds) in the special winning opening open time timer. That is, this process is set to execute the above-mentioned process for opening a special winning opening (S16) again after the process of S18.

  Furthermore, the main CPU 71 transmits a special winning opening open display command to the sub control circuit 200 immediately before the end of the special winning opening pre-reopening waiting time management process in S18.

  When the main CPU 71 determines in S17 that the value of the special winning opening open frequency counter is greater than or equal to the maximum value of the special winning opening opening frequency, it performs a big hit end interval process (S19). In this process, the main CPU 71 determines that the control state flag is a value indicating the big hit end interval process ("07") and the special symbol game end process is executed when the time corresponding to the big hit end interval has elapsed (" Set 08 ") in the control status flag. That is, it is set by this process that the special symbol game end process described later is executed after the process of S19. The details of the big hit end interval process will be described later with reference to FIG. 32 described later.

  Then, the main CPU 71 performs control to shift the gaming state to the probability variation gaming state when the jackpot symbol is the odd symbol, and shifts the gaming state to the normal gaming status when the jackpot symbol is the non-probability symbol Control. If the big hit symbol is a symbol corresponding to "small hit", the main CPU 71 controls the gaming state after the "small hit" game is over when the small hit is controlled. Also control to prevent transition to the advantageous gaming state.

  Next, the main CPU 71 conducts special symbol game end processing when the big hit gaming state or the small hit gaming state ends, or when the player loses the winning game (S20).

  In this process, the main CPU 71 updates and stores data (starting storage information) indicating the number of held pieces by 1 when the control status flag is the value ("08") indicating the special symbol game end processing. Do. In addition, the main CPU 71 updates the special symbol storage area in order to perform the next variable display of the special symbol. Furthermore, the main CPU 71 sets a value (“00”) indicating the special symbol storage check process in the control state flag. That is, by this process, the special symbol storage check process (S12) described above is set to be performed after the process of S20.

  Then, after the processing of S20, the main CPU 71 ends the special symbol control processing, and shifts the processing to S4 of the main control main processing (see FIG. 28).

  As described above, in the pachinko gaming machine 1 of the present embodiment, the special symbol game is advanced by sequentially setting various values in the control state flag. Specifically, when the gaming state is neither the big hit gaming state nor the small hit gaming state, and the result of the hit determination is “loss”, the main CPU 71 sets the control status flag to “00”, “01”. , "02", "08" in the order. Thus, the main CPU 71 checks the special symbol storage check process (S12), the special symbol variation time management process (S13), the special symbol display time management process (S14) and the special symbol game end process (S20) in this order. Execute at a predetermined timing.

  Further, when the gaming state is neither the big hit gaming state nor the small hit gaming state, and the result of the hit determination is the "big hit" or the "small hit", the main CPU 71 sets the control status flag to "00", " Set in the order of 01 "," 02 "and" 03 ". Thus, the main CPU 71 checks the special symbol storage check process (S12), the special symbol variation time management process (S13), the special symbol display time management process (S14) and the big hit start interval management process (S15) in this order. It executes at a predetermined timing, and executes transition control to the big hit gaming state or the small hit gaming state.

  Furthermore, when transition control to the big hit gaming state or the small hit gaming state is executed, the main CPU 71 sets the control state flag in the order of “04”, “05”, and “06”. As a result, the main CPU 71 executes the above-mentioned special winning opening open processing (S16), the special winning opening residual ball monitoring processing (S17) and the special winning opening reopening waiting time management processing (S18) in this order at a predetermined timing. Run in and run a big hit game or a small hit game.

  When the big hit gaming state ending condition is satisfied during the big hit game, the main CPU 71 sets the control state flag in the order of “04”, “05”, “07”, and “08”. As a result, the main CPU 71 executes the above-mentioned big winning opening open processing (S16), big winning opening residual ball monitoring processing (S17), big hit end interval processing (S19) and special symbol game ending processing (S20) in this order. The game is executed at a predetermined timing, and the big hit gaming state is ended.

  As described above, in the special symbol control process, the processing flow is branched according to the status. Also, the normal symbol control process of S4 in the main control main process shown in FIG. 28 also branches the process flow according to the status, as described later, as in the special symbol control process.

  The processing program of this embodiment is programmed so that a pure return processing from the small module to the parent module can be performed by a call instruction when the processing is branched according to the status. As a result, in the present embodiment, the capacity of the program can be reduced as compared with the case where the jump table is arranged to execute the above process.

[Special symbol memory check process]
Next, with reference to FIG. 30, the special symbol storage check process performed in S12 in the special symbol control process (see FIG. 29) will be described. In addition, FIG. 30 is a flowchart which shows the procedure of the special symbol memory check process in this embodiment.

  First, the main CPU 71 loads a control state flag (S31). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

  Next, the main CPU 71 determines whether or not the control state flag is a value ("00") indicating a special symbol storage check process (S32). In S32, when the main CPU 71 determines that the control status flag is not "00" (when the determination in S32 is NO), the main CPU 71 ends the special symbol storage check processing, and the processing is the special symbol control processing (FIG. 29) See).

  On the other hand, when the main CPU 71 determines that the control status flag is "00" (when the determination in S32 is YES) in S32, the main CPU 71 wins the second starting opening (variable display of the second special symbol) It is determined whether the number of reservations (the second start memory number) is "0" (S33).

  In S33, when the main CPU 71 determines that the hold number of the second starting opening winning is not “0” (when the determination in S33 is NO), the main CPU 71 corresponds to the second holding number corresponding to the second starting opening winning. The value of the starting memory number is decremented by "1" (S34).

  In the present embodiment, the main CPU 71 determines whether data is stored in the second special symbol start storage area (0) to the second special symbol start storage area (4) provided in the main RAM 73, It is determined whether or not there is a start-up memory of a special symbol game corresponding to the variable display of the second special symbol being changed or pending. In the second special symbol start storage area (0), data (information) of the special symbol game corresponding to the variable display of the second special symbol in change is stored as start storage. And, in the second special symbol starting memory area (1) ~ the second special symbol starting memory area (4), a special symbol game corresponding to the variable display (holding ball) of the second special symbol for 4 times being held Data (information) is stored as a starting memory. The data contained in the start memory stored in each second special symbol start storage area is, for example, data such as a jackpot determination random number value and a jackpot symbol random number value acquired at the time of winning of the second start port 45 .

  After the processing of S34, the main CPU 71 conducts special symbol storage transfer processing based on the second start hole winning (S35). In this process, the main CPU 71 transfers (stores) data of the second special symbol start storage areas (1) to (4) to the second special symbol start storage areas (0) to (3), respectively. Then, after the process of S35, the main CPU 71 performs the process of S40 described later.

  Here, if the main CPU 71 determines that the number of held second starting hole wins is "0" (S33 is YES), the main CPU 71 returns to the process of S33 again. It is determined whether or not the number of held first start opening winnings (variable display of the first special symbol) (first start stored number) is "0" (S36).

  In S36, when the main CPU 71 determines that the number of held first starting hole wins is “0” (when the determination in S36 is YES), the main CPU 71 performs a demonstration display process (S37). Then, after the process of S37, the main CPU 71 ends the special symbol storage check process, and returns the process to the special symbol control process (see FIG. 29).

  In the demonstration display process of S37, the main CPU 71 sets a demonstration display permission value in the main RAM 73. That is, the main CPU 71 causes a state in which the number of reserved first start hole wins and the number of reserved second start hole wins is “0” (state in which the special symbol game start memory is “0”) is a predetermined time (for example, When maintained for 30 seconds, a predetermined value is set as a demonstration display permission value. When the demonstration display permission value is a predetermined value in the demonstration display process of S37, the main CPU 71 sets demonstration display command data in the main RAM 73. Then, the demonstration display command data is transmitted from the main CPU 71 of the main control circuit 70 to the host control circuit 210 in the sub control circuit 200. When receiving the demonstration display command data, the sub control circuit 200 causes the display area 13a of the display device 13 to display a demonstration screen.

  On the other hand, when the main CPU 71 determines in S36 that the number of pending positions for the first starting hole winning is not "0" (when the determination in S36 is NO), the main CPU 71 corresponds to the number of pending first starting holes for winning. The value of the first starting memory number is decremented by "1" (S38).

  In the present embodiment, the main CPU 71 determines whether data is stored in the first special symbol start storage area (0) to the first special symbol start storage area (4) provided in the main RAM 73, It is determined whether or not there is a start-up memory of a special symbol game corresponding to the variable display of the first special symbol being changed or suspended. In the first special symbol start storage area (0), data (information) of the special symbol game corresponding to the variable display of the first special symbol in change is stored as start storage. And, in the first special symbol starting memory area (1) ~ the first special symbol starting memory area (4), a special symbol game corresponding to the variable display (holding ball) of the first special symbol for 4 times being held Data (information) is stored as a starting memory. The data contained in the start memory stored in each first special symbol start storage area is, for example, data such as a jackpot determination random number value and a jackpot symbol random number value acquired at the time of winning of the first start port 44 .

  After the processing of S38, the main CPU 71 conducts special symbol storage transfer processing based on the first start hole winning (S39). In this process, the main CPU 71 transfers (stores) data of the first special symbol start storage areas (1) to (4) to the first special symbol start storage areas (0) to (3), respectively. Then, after the process of S39, the main CPU 71 performs the process of S40 described later.

  Next, after the processing of S35 or S39, the main CPU 71 determines whether or not the value of the time saving state change number counter is “0” (S40).

  In S40, when the main CPU 71 determines that the value of the hour reduction state fluctuation number counter is “0” (when the determination in S40 is YES), the main CPU 71 performs the processing of S44 described later. On the other hand, when the main CPU 71 determines in S40 that the value of the time saving state variation counter is not "0" (when the determination in S40 is NO), the main CPU 71 subtracts "1" from the value of the time saving status change counter. To do (S41).

  After the processing of S41, the main CPU 71 determines whether or not the value of the time saving state fluctuation number counter is “0” (S42).

  In S42, when the main CPU 71 determines that the value of the time saving state fluctuation number counter is not “0” (when the determination in S42 is NO), the main CPU 71 performs the processing of S44 described later. On the other hand, when the main CPU 71 determines that the value of the time saving state variation counter is “0” in S42 (when the determination in S42 is YES), the main CPU 71 sets “0” in the time saving flag (S43). ).

  After the processing of S43, if S40 is a YES determination, or if S42 is a NO determination, the main CPU 71 sets a value (“01”) indicating a special symbol variation time management process in the control state flag (S44). Further, in this process, the main CPU 71 transmits the hold subtraction command and the special symbol effect start command to the sub control circuit 200.

  Next, the main CPU 71 conducts big hit determination processing (S45). In this process, the main CPU 71 determines (determines) which of “big hit”, “small hit”, and “losing” has been won by lottery based on the jackpot determination random number value acquired at the starting opening winning combination.

  Next, the main CPU 71 clears information (data) of the storage area used for the previous variable display (S46). Next, the main CPU 71 sets a variation time corresponding to the determined variation pattern of the special symbol in the waiting time timer (S47). Then, after the process of S47, the main CPU 71 ends the special symbol storage check process, and returns the process to the special symbol control process (see FIG. 29).

[Special symbol display time management process]
Next, with reference to FIG. 31, the special symbol display time management process performed at S14 in the special symbol control process (see FIG. 29) will be described. In addition, FIG. 31 is a flowchart which shows the procedure of the special symbol display time management process in this embodiment.

  First, the main CPU 71 determines whether or not the control state flag is a value (“02”) indicating a special symbol display time management process (S51). In S51, when the main CPU 71 determines that the control status flag is not the value ("02") indicating the special symbol display time management process (when the determination of S51 is NO), the main CPU 71 conducts special symbol display time management process The process is returned to the special symbol control process (see FIG. 29).

  On the other hand, when the main CPU 71 determines that the control status flag is the value indicating the special symbol display time management process ("02") in S51 (when the determination of S51 is YES), the main CPU 71 determines that the waiting time timer is It is determined whether the value (waiting time) is "0" (S52). In this process, the main CPU 71 determines whether or not the waiting time (variation start waiting time) set in the waiting time timer has been settled.

  In S52, when the main CPU 71 determines that the value of the waiting time timer is not "0" (when the determination in S52 is NO), the main CPU 71 ends the special symbol display time management processing, and the processing is a special symbol control processing. Return to (see FIG. 29). On the other hand, when the main CPU 71 determines in S52 that the value of the waiting time timer is "0" (when the determination in S52 is YES), the main CPU 71 determines whether the special symbol game is "big hit" or not. It discriminates (S53). Also, in this process, the main CPU 71 simultaneously transmits a special effect stop command to the sub control circuit 200.

  If the main CPU 71 determines in S53 that the special symbol game is not a "big hit" (if the determination in S53 is NO), the main CPU 71 sets a value ("08") indicating the special symbol game end processing in the control status flag. Set (S54). Then, after the process of S54, the main CPU 71 ends the special symbol display time management process and returns the process to the special symbol control process (see FIG. 29).

  On the other hand, when the main CPU 71 determines in S53 that the special symbol game is a "big hit" (when the determination in S53 is YES), the main CPU 71 sets a big hit flag to an on state (S55). The big hit flag is a flag indicating whether or not to play a big hit game.

  Next, the main CPU 71 clears the value of the time saving state change frequency counter, the value of the time saving flag, and the value of the probability change flag (S56). Next, the main CPU 71 sets a value (“03”) indicating a big hit start interval management process in the control state flag (S57).

  Next, the main CPU 71 sets the jackpot start interval time (for example, 5000 msec) corresponding to the special symbol (first special symbol or second special symbol) in the waiting time timer (S58). Next, the main CPU 71 sets a big hit start command (special symbol start display command) corresponding to the special symbol in the main RAM 73 (S59). Further, in this process, the main CPU 71 simultaneously transmits a special symbol hit start display command to the sub control circuit 200.

  Next, the main CPU 71 sets the round number display LED pattern flag to the on state (S60). The number-of-rounds display LED pattern flag is a flag indicating whether or not to display the number of remaining rounds in a predetermined pattern. Then, after the process of S60, the main CPU 71 ends the special symbol display time management process, and returns the process to the special symbol control process (see FIG. 29).

[Big hit end interval processing]
Next, with reference to FIG. 32, the big hit end interval process performed in S19 in the special symbol control process (see FIG. 29) will be described. FIG. 32 is a flowchart showing the procedure of the big hit end interval process according to the present embodiment.

  First, the main CPU 71 determines whether or not the control state flag is a value (“07”) indicating the big hit end interval process (S71).

  In S71, when the main CPU 71 determines that the control state flag is not a value (“07”) indicating the big hit end interval processing (when S71 is NO determination), the main CPU 71 ends the big hit end interval processing, and processing Is returned to the special symbol control process (see FIG. 29). On the other hand, when the main CPU 71 determines in S71 that the control status flag is the value indicating the big hit end interval processing ("07") (when S71 is YES determination), the main CPU 71 determines that the value of the waiting time timer is It is determined whether it is "0" (S72). In this process, the main CPU 71 determines whether or not the big hit end interval time set in the waiting time timer has been consumed.

  In S72, when the main CPU 71 determines that the value of the waiting time timer is not “0” (when the determination in S 72 is NO), the main CPU 71 ends the big hit end interval processing, and the processing is a special symbol control processing (FIG. Return to 29). On the other hand, when the main CPU 71 determines in S72 that the value of the waiting time timer is "0" (when the determination in S72 is YES), the main CPU 71 clears the special winning opening open number display LED pattern flag ( S73).

  Next, the main CPU 71 clears the round number distribution flag (sets it to "0") (S74).

  Next, the main CPU 71 sets a value (“08”) indicating the special symbol game end process in the control state flag (S75). Further, in this processing, the main CPU 71 simultaneously transmits a special symbol hit end display command to the sub control circuit 200. Next, the main CPU 71 clears the big hit flag (S76).

  Next, the main CPU 71 refers to the big hit type determination table (see FIGS. 20 to 23) and sets the value of the probability change flag based on the gaming state at the time of big hit and the type of big hit selection symbol command (S77) . Next, the main CPU 71 refers to the big hit type determination table (see FIGS. 20 to 23) and sets the value of the time saving flag based on the gaming state at the big hit and the type of big hit selection symbol command (S78) .

  Next, the main CPU 71 determines whether the value of the time saving flag is “1” (the time saving flag is in the on state) (S79). In S79, when the main CPU 71 determines that the value of the time saving flag is not “1” (when the determination in S 79 is NO), the main CPU 71 ends the big hit end interval processing, and the processing is a special symbol control processing (FIG. See).

  On the other hand, when the main CPU 71 determines in S79 that the value of the time saving flag is "1" (when the determination in S79 is YES), the main CPU 71 refers to the big hit type determination table (see FIGS. 20 to 23). Then, based on the gaming state at the time of big hit winning and the type of big hit selection symbol command, the value of the corresponding time saving number is set in the time saving state variation number counter (S80). Then, after the process of S80, the main CPU 71 ends the big hit end interval process, and returns the process to the special symbol control process (see FIG. 29).

[System timer interrupt processing]
In the pachinko gaming machine 1 of the present embodiment, the main CPU 71 interrupts the main processing at a predetermined cycle and executes the system timer interrupt processing even while the main processing is being performed. Specifically, the main CPU 71 executes system timer interrupt processing in response to a clock pulse generated from the clock generation circuit 74 in a predetermined cycle (for example, 2 msec). Here, the system timer interrupt process executed by the main CPU 71 will be described with reference to FIG. FIG. 33 is a flowchart showing the procedure of the system timer interrupt process in this embodiment.

  First, the main CPU 71 saves data (information) of each register (S121). Next, the main CPU 71 performs random number update processing (S122). In this process, the main CPU 71 updates various random number values extracted from the big hit determination counter, the symbol determination counter, the hit determination counter, the fall determination counter, the variation pattern determination counter, the effect pattern determination counter, etc. . The jackpot determination counter and the symbol determination counter lack fairness when the update timing of the counter value is indefinite. Therefore, the jackpot determination counter and the symbol determination counter are updated at a timing determined in a cycle of 2 msec in order to secure fairness.

  Next, the main CPU 71 performs switch input detection processing (S123). In this process, the main CPU 71 detects winning or passing to the various starting openings, various winning openings, and the ball passing detector 43. The details of the switch input detection process will be described later with reference to FIG. 34 described later.

  Next, the main CPU 71 conducts timer update processing (S124). Specifically, the main CPU 71 controls various timers such as a waiting time timer for synchronizing the main control circuit 70 and the sub control circuit 200, and a special winning opening opening time timer for measuring the opening time of the special winning opening. Update process of

  Next, the main CPU 71 executes command output processing (S125). In this process, the main CPU 71 outputs various commands such as a winning command and a fluctuation command to the host control circuit 210 of the sub control circuit 200.

  Next, the main CPU 71 conducts game information output processing (S126). In this process, the main CPU 71 outputs various information relating to the game processed by the main control circuit 70, the sub control circuit 200, the payout / fire control circuit 123 and the like to the hall computer of the game arcade.

  Next, the main CPU 71 restores the data of each register saved in S121 (S127). Then, after the process of S127, the main CPU 71 ends the system timer interrupt process.

[Switch input detection processing]
Next, with reference to FIG. 34, the switch input detection process performed in S123 in the system timer interrupt process (see FIG. 33) will be described. FIG. 34 is a flowchart showing the procedure of the switch input detection process according to this embodiment.

  First, the main CPU 71 executes a starting opening winning detection process (S131). In this process, the main CPU 71 determines whether the gaming ball has entered (passed) the first starting opening 44 or the second starting opening 45. That is, the main CPU 71 detects whether or not the winning of the gaming ball has been detected by the first starting opening winning ball sensor 44a or the second starting opening winning ball sensor 45a. The details of the starting opening winning detection process will be described later with reference to FIG. 35 described later.

  Next, the main CPU 71 conducts a general winning opening passage detection process (S132). In this process, the main CPU 71 determines whether the game ball has entered the general winning opening 51 or 52. That is, the main CPU 71 detects whether or not the winning of the gaming ball has been detected by the general winning ball sensor 51a or 52a. Then, when a winning of the gaming ball to the general winning opening 51 or 52 is detected, the main CPU 71 performs various predetermined processing corresponding to the winning.

  Next, the main CPU 71 conducts a special winning opening passage detection process (S133). In this process, the main CPU 71 determines whether the game ball has entered the first large winning opening 53 or the second large winning opening 54. That is, the main CPU 71 detects whether or not the winning of the game ball has been detected by the first large winning opening solenoid 53b or the second large winning opening solenoid 54b. Then, when a winning of the gaming ball to the first big winning opening 53 or the second big winning opening 54 is detected, the main CPU 71 performs various predetermined processing corresponding to the winning.

  Next, the main CPU 71 conducts gate passage detection processing (S134). In this process, the main CPU 71 determines whether the gaming ball has passed the ball passage detector 43 or not. That is, the main CPU 71 detects whether or not passage of the game ball is detected by the passage ball sensor 43a. Next, when it is detected that the gaming ball has passed the ball passage detector 43, the main CPU 71 executes various predetermined processes corresponding to the passage. Then, after the processing of S134, the main CPU 71 ends the switch input detection processing, and shifts the processing to S124 of the system timer interrupt processing (see FIG. 33).

[Starting mouth winning detection process]
Next, with reference to FIG. 35, the starting opening winning detection process performed in S131 in the switch input detection process (see FIG. 34) will be described. FIG. 34 is a flowchart showing the procedure of the starting hole winning detection process in the present embodiment.

  First, the main CPU 71 determines whether or not the winning of the game ball to the first starting opening 44 has been detected based on the output signal of the first starting opening winning ball sensor 44a (S141).

  In S141, when the main CPU 71 determines that the winning of the gaming ball to the first starting opening 44 is not detected (when the determination of S141 is NO), the main CPU 71 performs the processing of S149 described later. On the other hand, when the main CPU 71 determines that the winning of the game ball to the first starting opening 44 has been detected in S141 (when the determination of S141 is YES), the main CPU 71 pays out information corresponding to the first starting opening winning Are set in the main RAM 73 (S142). In the present embodiment, when the gaming ball wins the first starting opening 44, a predetermined number of gaming balls are paid out. Therefore, in the process of S142, payout information of a predetermined number of gaming balls is set.

  After the processing of S142, the main CPU 71 determines whether or not the number of reserved first winning opening winnings (variable display of the first special symbol) (number of holding balls) is less than "4" (S143).

  In S143, when the main CPU 71 determines that the number of held first starting hole wins is not less than “4” (when the determination of S 143 is NO), the main CPU 71 performs the processing of S 149 described later. On the other hand, when the main CPU 71 determines in S143 that the number of first start hole winnings held is less than "4" (when S143 is YES), the main CPU 71 determines the number of first starting holes winnings. A process of adding "1" is performed (S144).

  After the processing of S144, the main CPU 71 acquires various random number values used for the lottery, and stores the acquired various random number values in a predetermined area of the main RAM 73 (S145). Specifically, the main CPU 71 acquires various random number values such as a jackpot determination random number value, a symbol random number value, and a fall determination random number value.

  Next, the main CPU 71 conducts a first special stop symbol determination process (S146). In this process, the main CPU 71 refers to the big hit random number determination table (first start port) (see FIG. 16) and the symbol determination table (first start port) (see FIG. 18), and determines the big hit determination obtained in S145. Based on the numerical value and the symbol random number value, it is determined whether or not "big hit", and in the case of "big hit", the big hit symbol (identification symbol for effect) to be displayed on the display screen of the display device 13. Make a selection (judgment).

  Next, the main CPU 71 conducts determination processing of the presence or absence of a fall (S147). In this process, the main CPU 71 conducts a fall lottery based on the fall determination random number value acquired in S145, and determines whether or not there is a fall. As a result, the main CPU 71 acquires falling lottery information (“0”: no falling or “1”: falling).

  Next, the main CPU 71 sets hold addition command data at the time of the first start-up winning in the main RAM 73 (S148).

  In this process, the main CPU 71 determines the big hit random number determination table (first start port) (see FIG. 16), the symbol determination table (first start port) (see FIG. 18), and the big hit type determination table (see FIGS. ) And the winning time effect information determination table (see FIG. 24), the gaming state (“normal”, “certain change”, “time reduction”), winning classification (“big hit”, “small hit”, “loss”) "), Number of starting memory (number of first special symbol held), symbol designation command, jackpot selection symbol command, winning presentation effect information, jackpot determination result information, information such as fall lottery information, hold addition command Determine the information (transmission content) to be included in.

  In this case, the gaming state is acquired with reference to the values of the probability change flag and the time saving flag, and the winning type is acquired by referring to the big hit random number determination table (first start port) (see FIG. 16), The symbol designation command and the jackpot selection symbol command are acquired by referring to the symbol determination table (first starting opening) (see FIG. 18), and the prize effect information is a prize effect information determination table (see FIG. 24). It is acquired by referring to. Further, the result information of the jackpot determination is acquired in the process of S146, and the fall lottery information is acquired in the process of S147.

  Further, in the present embodiment, in the process of S148, the main CPU 71 sends a suspension addition command at the time of winning the first starting opening to the sub control circuit 200 (host control circuit 210). Then, based on the hold addition command at the time of the first start hole winning, the sub control circuit 200 selects the effect pattern of the hold effect and the prefetch effect.

  After the processing of S148, or if S141 or S143 is NO, the main CPU 71 detects a winning of the gaming ball to the second starting opening 45 based on the output signal of the second starting opening winning ball sensor 45a It is determined whether or not it is (S149).

  In S149, when the main CPU 71 determines that the winning of the game ball to the second starting opening 45 is not detected (when the S149 is NO determination), the main CPU 71 ends the starting opening winning detection processing, and processing Is transferred to S132 of the switch input detection process (see FIG. 34). On the other hand, when the main CPU 71 determines in S149 that the game ball has been detected to win the second starting opening 45 (when the determination in S149 is YES), the main CPU 71 pays out information corresponding to the second starting opening winning Are set in the main RAM 73 (S150). In the present embodiment, when the gaming ball wins the second starting opening 45, a predetermined number of gaming balls are paid out. Therefore, in the process of S150, payout information of a predetermined number of gaming balls is set.

  After the processing of S150, the main CPU 71 determines whether or not the number of holdings (the number of holding balls) of the second starting opening winning (variable display of the second special symbol) is less than "4" (S151).

  In S151, when the main CPU 71 determines that the number of held second starting hole winnings is not less than “4” (when S151 is NO), the main CPU 71 ends the starting opening winning detection process and switches the processing. The process moves to S132 in the input detection process (see FIG. 34). On the other hand, when the main CPU 71 determines in S151 that the number of reserved second start hole winnings is less than “4” (when the determination of S151 is “YES”), the main CPU 71 determines the number of reserved second starting port winnings. A process of adding "1" is performed (S152). After the processing of S152, the main CPU 71 acquires various random number values used for the lottery, and stores the acquired various random number values in a predetermined area of the main RAM 73 (S153). Specifically, the main CPU 71 acquires various random number values such as a jackpot determination random number value, a symbol random number value, and a fall determination random number value.

  Next, the main CPU 71 conducts a second special stop symbol determination process (S154). In this process, the main CPU 71 refers to the big hit random number determination table (second start opening) (see FIG. 17) and the symbol determination table (second start opening) (see FIG. 19), and the big hit determination randomness obtained in S153. Based on the numerical value and the symbol random number value, it is determined whether or not "big hit", and in the case of big hit, selection of the big hit symbol (identification symbol for effect) to be displayed on the display screen of the display device 13 Make a judgment).

  Next, the main CPU 71 conducts determination processing of the presence or absence of a fall (S155). In this process, the main CPU 71 conducts a fall lottery based on the fall determination random number value acquired in S153, and determines whether or not a fall occurs. As a result, the main CPU 71 acquires falling lottery information (“0”: no falling or “1”: falling).

  Next, the main CPU 71 sets hold addition command data at the time of the second starting opening winning combination in the main RAM 73 (S156).

  In this process, the main CPU 71 determines the big hit random number determination table (second start opening) (see FIG. 17), the symbol determination table (second start opening) (see FIG. 19), and the big hit type determination table (see FIGS. 20 to 23). ) And the winning time effect information determination table (see FIG. 24), the gaming state (“normal”, “certain change”, “time reduction”), winning classification (“big hit”, “missing”), start memory Information to be included in the pending addition command based on information such as number (second special symbol pending number), symbol specifying command, jackpot selection symbol command, winning presentation information, jackpot determination result information, falling lottery information and so on Determine the transmission content).

  At this time, the gaming state is acquired by referring to the values of the probability change flag and the time saving flag, and the winning type is acquired by referring to the big hit random number determination table (second starting port) (see FIG. 17), The symbol designation command and the jackpot selection symbol command are obtained by referring to the symbol determination table (second starting opening) (see FIG. 19), and the prize effect information is a prize effect information determination table (see FIG. 24) It is acquired by referring to. Further, the result information of the jackpot determination is acquired in the process of S154, and the fall lottery information is acquired in the process of S155.

  Further, in the present embodiment, in the process of S156, the main CPU 71 sends a hold addition command at the time of winning the second starting opening to the sub control circuit 200 (host control circuit 210). The sub control circuit 200 selects the effect pattern of the on-hold effect and the pre-read effect on the basis of the on-hold addition command at the time of winning at the second starting opening. Then, after the process of S156, the main CPU 71 ends the starting opening winning a prize detection process, and shifts the process to S132 of the switch input detection process (see FIG. 34).

<Description of operation of sub control circuit>
Next, with reference to FIGS. 36 to 74, contents of various processes executed by various control circuits in the sub substrate 202 (for example, refer to FIG. 6) of the sub control circuit 200 will be described. The sub control circuit 200 receives various commands transmitted from the main control circuit 70 (see, for example, FIG. 6), and performs various processing based on the various commands.

[Sub control main processing]
First, with reference to FIG. 36, the sub control main process executed by the host control circuit 210 (see, for example, FIG. 6, the same applies hereinafter) will be described. FIG. 36 is a flow chart showing an example of the sub control main process in the present embodiment. The sub control main process is a process that is started when the power is turned on. In the sub control main processing described with reference to FIG. 36 and the sub control main processing described later (refer to FIG. 47, FIG. 48, and FIG. 49), different reference numerals are given for convenience of description even if the processing is the same. ing. For example, when various initialization processes are described as an example, various initialization processes (step S201) in FIG. 36, various initialization processes (step S381) in FIG. 47, and various initialization processes (step S391) in FIG. The various initialization processes (step S401) in FIG. 48 are substantially the same processes but different reference numerals are attached.

  First, the host control circuit 210 performs various initialization processing (step S201). In this processing, the host control circuit 210 performs various initialization processing such as hardware initialization processing, device initialization processing, various application initialization processing, backup data recovery initialization processing, RTC acquisition processing, etc. Do. When game data is erased by clearing the RAM, random number initialization processing is also performed. Also, the host control circuit 210 clears the watchdog timer counter each time each initialization process is completed. At the time of start-up, the reset time of the watchdog timer is set, and thereafter, when the writing of the service pulse is not performed (at time-out), the power-off process is performed. Further, the timing for clearing the watchdog timer is at the start of each processing in the main loop in the sub control main processing, at the start of each initialization processing, and at the transition to the power failure processing.

  Next, the host control circuit 210 enters the main loop, and performs RTC acquisition processing, that is, processing for acquiring the current time based on the RTC time (step S202).

  The host control circuit 210 performs random number initialization processing in step S203. The random number initialization process will be described later.

  The host control circuit 210 acquires the control code of the item in step S204, and performs synchronization processing of the item and the solenoid (step S205). These processes will be described in the later-described "feature solenoid control process".

  The host control circuit 210 performs sub device input processing in step S206. In this process, the host control circuit 210 acquires information on the operation contents based on the input state of the operation means (determination process as to whether or not the player has operated the operation means such as a button, for example). Etc. The sub device input process (step S206) includes, for example, adjustment of the brightness of the LED or the like by the operation of the player or the like.

  The host control circuit 210 performs various request control processes in step S207. In this process, the host control circuit 210 performs various request control processes such as, for example, a sound request control process, an LED request control process, and a feature request control process. The sound request, the LED request, the feature request, and the like are stored in a buffer and are output to each device after bank flipping in step S213 described later. Thereby, synchronization with drawing can be achieved. The bank flip is processing for switching the function of one frame buffer from the drawing function to the display function and switching the function of the other frame buffer from the display function to the drawing function.

  Next, the host control circuit 210 enters a packet reception loop in the main loop and performs main-sub command control processing (step S208). In this process, the host control circuit 210 performs a process of reading command data (command reception process) when command data is received from the main CPU 71 and a process of storing command data to the sub work RAM 210a (reception data storage process).

  The host control circuit 210 performs game data backup processing in step S209. In the pachinko gaming machine 1 of the present embodiment, the first data (magic code, program version and SUM value) and the second data (all are information set in the hall menu) as game data used for the RAM clear determination. And prepare the SUM value). Then, in the game data backup process, after the first data is stored in the game data, it is backed up in the SRAM 210b (see FIG. 6). The game data is also backed up (mirrored) to another area of the SRAM 210b. After the power is turned on, game data is restored from the data backed up in the SRAM 210b. At this time, the first data is used to check whether or not the backed up data is corrupted. If there is corruption in the backed up data, check if there is corruption in the second data. At this time, data stored in all the SRAMs 210b such as hall menu information is also initialized.

  Next, the host control circuit 210 performs an animation request construction process (step S210). In this processing, the host control circuit 210 performs command analysis / state setting / lottery processing, receives these, and generates an animation request necessary for performing effect control using the display device 13, and this animation request In response to the effect control (display) in the display device 13 executed based on the above, various requests (a sound request, a lamp request and a feature request) for operating the various effect devices are generated.

  The host control circuit 210 executes the processing of the above-described steps S202 to S05 until the number of received commands is executed, and when the number of received commands is executed, the packet reception loop is left. Thereafter, the host control circuit 210 passes through animation update processing (step S211), drawing processing (step S212), and bank flip / bank flip end waiting (step S213), and each processing in the main loop is repeated.

  The host control circuit 210 repeatedly executes the process (main loop process) of one example of steps S202 to S213 described above at a predetermined FPS cycle. The FPS cycle is set to, for example, about 16.7 msec (60 FPS) or about 33.3 msec (30 FPS). The predetermined FPS cycle is timed in step S213.

  Below are timer interrupt processing, sub device input processing, backlight control processing, brightness adjustment of backlight and various LEDs, RTC acquisition processing, composition reproduction control, sound amplifier control processing, sound request control processing (for the same channel (for the same channel) The sound request control process (when there is a plurality of sound requests) (when the volume adjustment is performed), the LED brightness adjustment process, the feature solenoid control process, the data loading process, and the sub random number process will be described in this order. The order of the above-described processes is different from the order of processes for the convenience of description.

[Timer interrupt processing]
In the pachinko gaming machine 1 of the present embodiment, the host control circuit 210 performs interrupt processing in a cycle of 1 msec. The interrupt process will also be described in each process to be described later, but here, an example of a typical interrupt process will be briefly described with reference to FIG. FIG. 37 is a flow chart showing an example of the timer interrupt process executed by the host control circuit (sub control circuit). In the timer interrupt process briefly described with reference to FIG. 37 and the timer interrupt process (see FIGS. 44 and 46) to be described later, different symbols are attached for convenience of explanation even if the process is the same. For example, to describe the product motor control as an example, the product motor control of FIG. 37 (step S251), the product motor control of FIG. 44 (step S352), and the product motor control of FIG. 46 (step S371). Are substantially the same process but with different signs.

  Referring to FIG. 37, in the timer interrupt process, first, host control circuit 210 performs feature motor control (step S251). Next, the host control circuit 210 performs input state determination processing based on the input information of the sub device (step S252). Next, the host control circuit 210 performs control processing such as backlighting of a liquid crystal display device used as the display device 13 based on the luminance value (step S253). Next, the host control circuit 210 performs a sound amplifier check process (step S254).

Sub device input processing
In the present embodiment, the host control circuit 210 creates sub device input discrimination information in the main processing every 33.3 msec based on the input state of the sub device detected by the timer interrupt every 1 msec, and this is created Control the sub device based on the sub device input discrimination information.

  When the host control circuit 210 detects the input state of the sub device by a timer interrupt every 1 msec, the sub device input information and the sub device as the above-mentioned sub device input discrimination information created in the main processing based on the detection result. Input ON edge information, sub device input ON edge information (with repeat function), and sub device input OFF edge information are created.

  The sub device input processing shown in FIG. 36 will be described below with reference to FIGS. 38 to 41. The sub device is controlled by the host control circuit 210 based on input (e.g. operation) information, such as a push button, for example. FIG. 38 is a diagram showing an example for explaining the sub device input discrimination information to be created, (a) a diagram showing the input state of the sub device detected by the timer interrupt, (b) created by the main processing (C) shows the sub device input ON edge information created in the main processing, (c) the sub device input ON edge information (with a repeat function) created in the main processing FIG. 6D is a diagram showing sub device OFF edge information created in the main processing. FIG. 39 is a flowchart illustrating an example of the sub device input process. FIG. 40 is a flowchart of an example of sub device input ON edge information (with repeat function) processing. FIG. 41 illustrates an example of sub device input ON edge information (with repeat function) processing, and is a flowchart continued from FIG.

  The sub device input information created in the main processing is created according to the sub device input state (see FIG. 38A) detected by the timer interrupt, as shown in FIG. That is, 1 is set when the sub device input state detected by the timer interrupt is ON. When the sub device input state detected by the timer interrupt is OFF, 0 is set.

  As shown in FIG. 38C, the sub device input ON edge information detects that the sub device input state detected by the timer interrupt is switched from OFF to ON, and only one frame is displayed in the main process. Is set.

  The sub device input ON edge information (with a repeat function) is information used for control, for example, at the time of debugging or when the operation button is pressed for a long time, and as shown in FIG. When it is detected that the sub device input state changed from OFF to ON, 1 is set for one frame in the main processing. Then, when the ON state of the input state of the sub device continues thereafter, for example, 1 is set to one frame after 10 frames have elapsed in the main processing as a predetermined time until the key repeat start, and thereafter, for example, in the main processing. One is set every four frames. Thus, the reason why the first frame is extended to 10 frames is to be able to determine whether or not the sub device is pressed for a long time, and it is determined that the first frame is not for a long time if it is short. Can.

  As shown in FIG. 38 (e), the sub device input OFF edge information detects that the sub device input state detected by the timer interrupt has been turned from ON to OFF, and only one frame is selected by the main processing. Is set.

  In the present embodiment, assuming that there are a plurality of subdevices, the host control circuit 210 manages subdevice input discrimination information in bit units. For example, sub-device input determination information on up to, for example, 32 devices can be managed such that bit 0 is a main button, bit 1 is a left button, and bit 2 is a right button.

  Next, sub device input processing (see, for example, step S206 in FIG. 36) will be described with reference to FIG. The sub device input processing includes, for example, sub device input information, sub device input ON edge information, sub device input ON edge information (with repeat function), and sub device input OFF edge information as input determination information of the sub device. It is a process of creating type information.

  The host control circuit 210 first creates input information of the current subdevice based on the current input state of the subdevice (step S301). Specifically, 1 is set if the sub device is in the ON state, and 0 is set if the sub device is in the OFF state.

  Next, the host control circuit 210 updates the sub device input information in accordance with the current sub device input information, that is, the sub device input information created in step S301 (step S302).

  Next, the host control circuit 210 determines whether the previous sub device input information is 0 and the current sub device input information is 1 (step S303). If the previous sub device input information is 0 and the current sub device input information is 1 (YES in step S303), the host control circuit 210 sets the sub device input ON edge information to 1 (step S304), and Move to S306. On the other hand, if the previous sub device input information is 0 and the current sub device input information is not 1 (that is, the previous sub device input information is 1 or / and the current sub device input information is 0), the host The control circuit 210 sets the sub device input ON edge information to 0 (step S305), and proceeds to step S306.

  In step S306, the host control circuit 210 determines whether the previous sub device input information is 1 and the current sub device input information is 0. If the previous sub device input information is 1 and the current sub device input information is 0 (YES in step S306), the host control circuit 210 sets the sub device input OFF edge information to 1 (step S307), and step Move to S309. On the other hand, if the previous sub device input information is 1 and the current sub device input information is not 0 (that is, the previous sub device input information is 0 or / and the current sub device input information is 1), the host The control circuit 210 sets the sub device input OFF edge information to 0 (step S308), and proceeds to step S309.

  In step S309, the host control circuit 210 performs sub device input ON edge information (with repeat function) processing. Details of this sub device input ON edge information (with repeat function) processing will be described later.

  When the sub device input ON edge information (with repeat function) processing in step S309 ends, the host control circuit 210 sets the current sub device input information to the previous sub device input information (step S310), and the sub device input End the process.

  Next, with reference to FIGS. 40 and 41, processing of sub device input ON edge information (with a repeat function) will be described.

  As shown in FIG. 40, in the sub device input ON edge information (with repeat function) processing, the host control circuit 210 first determines whether the previous sub device input information is 0 (step S321). . If the previous sub device input information is 0 (YES in step S321), the process moves to step S322.

  In step S322, the host control circuit 210 determines whether the current sub device input information is one. If the current sub-device input information is 1 (YES in step S322), that is, if the previous sub-device input information is 0 and the current sub-device input information is 1, the process proceeds to step S323. On the other hand, if the current sub device input information is not 1 (NO in step S322), that is, if the previous sub device input information is 0 and the current sub device input information is 0, the sub device input is ON. End the edge information (with repeat function) processing.

  Next, the host control circuit 210 sets the sub device input ON edge information (with the repeat function) to 1 (step S323), and sets 10 frames as an elapsed frame (step S324), and the sub device input ON edge information End processing (with repeat function).

  In step S321, if the previous sub device input information is 1 (NO in step S321), the host control circuit 210 proceeds to step S325 in FIG.

  Referring to FIG. 41, in step S325, host control circuit 210 determines whether or not the current sub-device input information is one. If the current sub device input information is 1 (YES in step S 325), that is, if the previous sub device input information is 1 and the current sub device input information is 1, 1 is subtracted from the elapsed frame. (Step S326) Move on to step S327.

  In step S327, the host control circuit 210 determines whether the elapsed frame is 0 or not. If the elapsed frame is 0 (YES in step S327), the sub device input ON edge information (with a repeat function) is set to 1 (step S328), and the elapsed frame is set to 4 (step S329). The input ON edge information (with repeat function) processing ends.

  In step S325, if the current sub device input information is not 1 (NO in step S325), that is, if the previous sub device input information is 1 and the current sub device input information is 0, host control The circuit 210 sets an elapsed frame to 0 (step S330), and proceeds to step S331.

  When the sub device input ON edge information (with repeat function) is set to 0 in step S331, the host control circuit 210 ends the processing of the sub device input ON edge information (with repeat function).

  As described above, the host control circuit 210 creates the above four types of sub device input discrimination information in the main processing every 33.3 msec, based on the input state of the sub device detected by the timer interrupt every 1 msec, By controlling the sub device based on the four types of sub device input discrimination information, control of the continuous hit production of the sub device, control of long press effect, control of time setting, control of other operations, etc. are easily performed. It becomes possible.

[Backlight control process]
Next, a backlight control process (for example, a backlight control process for controlling a backlight of a liquid crystal display or the like) will be described with reference to FIGS. 42 and 43. FIG. 42 is a diagram showing an example for conceptually explaining the backlight control process. FIG. 43 is a flowchart illustrating an example of the backlight control process.

  The backlight control process of this embodiment uses the function of SPI asynchronous data write (SPI + DMA) to continuously and continuously from the serial output terminal of, for example, a serial peripheral interface (hereinafter referred to as "SPI"). A signal corresponding to pulse width modulation (hereinafter referred to as "PWM") is output, and the duty (brightness) can be changed. This makes it possible to perform backlight control without intervention of a driver for backlight control.

  In this embodiment, for example, SPI clock frequency 100 kHz, SPI1 clock is 0.01 msec, time required for data transmission of 16 bits (one data of luminance data is 16 bits) by SPI is 0.16 msec. The interrupt is 1 msec, and the number of luminance data transmitted from the SPI between scheduled interrupts of the host control circuit 210 is 100 bits. Therefore, the number of pieces of luminance data transmitted between scheduled interrupts of the host control circuit 210 is 6.25 (100/16) (see FIG. 42). Therefore, for example, the number of scheduled interrupts executed until 32 luminance data are replenished in a FIFO (First In First Out) data area that can set (store) 64 16-bit luminance data is 5 to 6 it is conceivable that. The number of times differs depending on the time of the scheduled interrupt of the host control circuit 210.

  For example, when the luminance data set (stored) in the FIFO (First In First Out) data area that can set (store) 64 luminance data of 16 bits is less than 32 data, the callback function is called, The area is not always filled. Therefore, if processing for setting (storing) luminance data in the data area of the FIFO takes time in other processes in the main process executed in a cycle of 33.3 msec, the data area of the FIFO becomes empty. There is a possibility that the backlight will be dark.

  Therefore, in the present embodiment, after power-on, first, 64 pieces of luminance data of 1 data 16 bits are first set to fill the data area of FIFO, and thereafter, 32 pieces of luminance data set in the data area of FIFO If less than, the callback function is called to set 32 pieces of data in the callback function so that the FIFO data area is not emptied.

  As shown in FIG. 43, in the backlight control process, the host control circuit 210 first determines whether it is a process at the time of initial setting (step S341). When host control circuit 210 determines that the processing at the time of initial setting (that is, one of steps 201 of FIG. 36) (YES in step S341), 64 pieces of luminance data of luminance 0 are stored in the data area of FIFO It sets (step S342) and moves to step S343. On the other hand, if it is determined that the process is not at the time of initial setting (that is, the process of step S253 in FIG. 37) (NO in step S341), the process of step S342 is skipped, and the process proceeds to step S343.

  At step S343, host control circuit 210 determines whether the luminance value has been changed. When the host control circuit 210 determines that the luminance value has been changed (YES in step S343), the host control circuit 210 changes the luminance data to be set in the data area of the FIFO (step S344), and proceeds to step S345. On the other hand, when it is determined that the luminance value is not changed (NO in step S343), the process of step S344 is skipped, and the process proceeds to step S345.

  In step S345, the host control circuit 210 determines whether the number of luminance data set in the FIFO data area is smaller than 32 and the number of luminance data set in the FIFO data area is 32. If the number is smaller than the number (YES in step S345), 32 luminance data are set in the data area of the FIFO, ie, replenished (step S346), and the backlight control process is ended. On the other hand, if the number of luminance data set in the data area of the FIFO is greater than 32 (NO in step S345), the host control circuit 210 ends the backlight processing.

  In this way, by processing so that the luminance data set in the FIFO data area is not emptied, it is possible to continuously output a signal corresponding to PWM continuously from the SPI serial data output terminal. It becomes possible to perform backlight control without passing through a driver for write control.

  In addition, the process of step S343-step S346 of the backlight control process of this embodiment can also be substituted as follows. That is, after 64 sets of luminance 0 data (see step S 342), processing is performed to determine whether the number of luminance data set in the data area of the FIFO is smaller than 32 or not. Thereafter, it is determined whether or not the luminance value is changed, and when it is determined that the luminance value is changed, 32 pieces of luminance data according to the setting are set in the data area of the FIFO, and when it is determined that the luminance value is not changed Set the same 32 luminance data in the FIFO data area. In this manner, luminance data may be set in the data area of the FIFO, and the backlight control process may be ended.

  Further, in the present embodiment, when luminance data set in the data area of the FIFO falls below 32 (half of the number of data that can be set in the FIFO), 32 luminance data are replenished. The timing of replenishing the image data and the number of luminance data to be replenished are not limited to this, and the predetermined number of luminance data may be replenished when the luminance data set in the data area of the FIFO falls below the predetermined number. Further, the luminance data to be replenished in the data area of the FIFO does not have to be the predetermined number described above. For example, when the luminance data set in the data area of the FIFO falls below the first number, the second number The luminance data may be supplemented. However, from the viewpoint of preventing the luminance data set in the FIFO data area from becoming empty without frequently setting the luminance data in the FIFO data area too much, the above-mentioned predetermined number or the first The number is preferably the number of luminance data that is about half the number of data that can be set in the FIFO data area, but as described above, the number is not limited to this. The above “about half” may be any range as long as the frequency of setting the luminance data in the FIFO data area is not too high and the luminance data set in the FIFO data area does not become empty. There are various judgment methods, such as half or less, according to the consumption speed of the luminance data set in the data area of the above. For example, since the FIFO data area in this embodiment can set up to 64 16-bit luminance data, when the luminance data set in the FIFO data area is 1 to 64, one or more are newly added. Although the luminance data may be set, from the viewpoint of preventing the backlight from becoming dark (the luminance data set in the data area of the FIFO becomes 0), the data of the FIFO can be set. It is preferable to newly set one or more luminance data when there are two or more luminance data set in the area. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more luminance data can be set. Thus, when there are two or more luminance data that can be set in the FIFO data area, for example, if the luminance data set in the FIFO data area falls below the first number (for example, two), the second number For example, one piece of luminance data may be replenished.

[Modification of backlight control process]
Next, a modified example of the backlight control process will be described with reference to FIGS. 44 and 45. FIG. 44 is a flowchart showing an example of timer interrupt processing according to the modification of the backlight control processing. FIG. 45 is a flowchart showing a modification of the backlight control process.

  In the modified example of the backlight control process, when there is a possibility that the process may take time in the timer interrupt process of 1 msec, whether or not a predetermined time or more has elapsed since data was set in the FIFO data area in the backlight control process. If a predetermined time or more has elapsed, data is set in the data area of the FIFO.

  In the timer interrupt processing of FIG. 44, the host control circuit 210 first performs backlight control processing (step S351). Hereinafter, for convenience of description, the backlight control process of step S351 will be described with reference to FIG. 45 before the processes of step S352 and subsequent steps are described.

  As shown in FIG. 45, in the backlight control process, the host control circuit 210 first determines whether it is a process at the time of initial setting (step S361). When host control circuit 210 determines that the processing at the time of initial setting (that is, one of steps 201 of FIG. 36) (YES in step S 361), 64 pieces of luminance data of luminance 0 are stored in the data area of FIFO After setting (step S362), the process proceeds to step S366. On the other hand, if it is determined that the process is not at the time of initial setting (that is, the process of step S351) (NO in step S361), the process proceeds to step S363.

  In step S 363, the host control circuit 210 determines whether the number of luminance data set in the FIFO data area is smaller than 32 and the number of luminance data set in the FIFO data area is 32. If the number is smaller than the number (YES in step S363), 32 luminance data are set or supplemented in the data area of the FIFO (step S364), and the process moves to step S365. On the other hand, if the number of luminance data set in the data area of the FIFO is larger than 32 (NO in step S363), the process moves to step S366. The above 32 are half of the number of data that can be set in the FIFO as described above.

  The host control circuit 210 resets the elapsed time in step S365 (step S365), and starts counting the elapsed time (step S366). When counting of elapsed time is started in step S366, the host control circuit 210 ends the backlight control process.

  Referring back to FIG. 44, the host control circuit 210 performs the bonus motor control after ending the backlight control process of step S351 (step S352).

  In this modified example, after the host control circuit 210 performs processing that may require time for processing, such as a bonus motor control, whether the elapsed time from which time counting was started in step S366 has exceeded a predetermined time or not It is determined (step S353). If the predetermined time or more has elapsed (YES in step S353), 32 luminance data are set in the data area of the FIFO (step S354). On the other hand, if the predetermined time or more has not elapsed (NO in step S353), it is not necessary to replenish the data area of the FIFO with the luminance data, and thus the process proceeds to step S357.

  As described above, since it takes 0.16 msec to transmit 16-bit SPI data (16 bits of luminance data) data, it is considered that 5.12 msec is required to transmit 32 luminance data. Be Therefore, in this modification, in step S353, it is determined whether or not 5.12 msec or more has elapsed as the predetermined time.

  After performing the process of step S354, the host control circuit 210 resets the elapsed time (step S355), and restarts counting of the elapsed time (step S356). Then, when clocking of the elapsed time is started in step S356, the host control circuit 210 performs an input state determination process (step S357), and ends the timer interrupt process.

  As described above, timing is started when luminance data is set in the data area of the FIFO, and after processing which may take time, if the above-mentioned time has elapsed for a predetermined time or more, luminance data is replenished. By doing this, it becomes possible to prevent the luminance data in the data area of the FIFO from becoming empty.

  In this modification, although the example which performs processing of Step S353-Step S357 after character product motor control (Step S352) was explained, this is an example to the last. That is, from the viewpoint of preventing the luminance data set in the data area of the FIFO from becoming empty, if the processing of step S 353 to step S 357 is performed after the processing that may take time for processing. Well, such a process is not limited to a specific process.

[Brightness adjustment of backlight and various LEDs]
Next, variations of the brightness adjustment of the backlight and various LEDs will be described. The various LEDs correspond to a board-side LED (for example, an LED disposed on the game board 12), a frame-side LED, and the like, and in the present specification, a lamp group 18 and the like including the LED (for example, see FIG. 5) corresponds thereto. . Furthermore, in this specification, three variations of the first embodiment to the third embodiment will be described as variations of brightness adjustment of the backlight and the various LEDs with reference to FIGS. 46 to 49, respectively. FIG. 46 is a flow chart showing an example of timer interrupt processing showing backlight control processing. FIG. 47 shows a sub control main process (overall flow) executed by the host control circuit 210 for describing the first embodiment of the process of adjusting the brightness of the backlight and various LEDs. FIG. 48 shows a sub control main process (overall flow) executed by the host control circuit 210 for explaining a second embodiment of the process of adjusting the brightness of the backlight and various LEDs. FIG. 49 shows a sub control main process (overall flow) executed by the host control circuit 210 for explaining the third embodiment of the process of adjusting the brightness of the backlight and various LEDs. However, in FIG. 47 to FIG. 49, only the processing necessary for explanation is shown, and the other processing is omitted. Also in the first to third embodiments described below, as described above, when the luminance data set in the data area of the FIFO becomes about half, the host control circuit 210 enters the data area of the FIFO as well. Replenish the luminance data.

  The timing for replenishing the luminance data in the data area of the FIFO is not limited to when the luminance data set in the data area of the FIFO becomes about half. In the FIFO data area in this embodiment, for example, up to 64 16-bit luminance data can be set. Therefore, when the luminance data set in the FIFO data area is 1 to 64, one or more are newly added. It suffices to set the luminance data. However, from the viewpoint of preventing the backlight from becoming dark (the luminance data set in the FIFO data area becomes 0), the luminance data set in the FIFO data area is 2 It is preferable to newly set one or more luminance data when the number is one or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more luminance data can be set. Thus, when there are two or more luminance data that can be set in the FIFO data area, for example, if the luminance data set in the FIFO data area falls below the first number (for example, two), the second number For example, one piece of luminance data may be replenished.

(First embodiment)
For example, when the brightness adjustment of the backlight (for example, backlight such as a liquid crystal display) is performed by the operation of the player or the like, the brightness of the backlight is changed. At this time, control of the panel side LED and the frame side LED It may affect the In this case, in this case, the brightness setting of the backlight and the brightness setting of the panel-side LED and the frame-side LED are common settings, and the backlight, the panel-side LED and the frame-side LED It is intended to perform control. Thereby, even if the update timing of the backlight control and the update timing of the control of the panel-side LED and the frame-side LED are different, the process can be facilitated.

  In the timer interrupt process of FIG. 46, the host control circuit 210 performs the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order.

  As shown in FIG. 47, after performing the initialization process (step S381), the host control circuit 210 moves on to the main loop and performs the LED request control process (step S382). The LED request performed in step S382 is generated in the animation construction process (step S386 described later) one frame before.

  After performing the process of step S382, the host control circuit 210 performs the above-described process of generating sub device (button) input discrimination information (step S383) based on the input state of the sub device, and proceeds to step S384.

  In step S384, the host control circuit 210 controls the brightness of the backlight based on the input state of the sub device (for example, the player or the like operates the brightness setting screen displayed on the liquid crystal display device used as the display device 13). Set The brightness of the backlight is, for example, set to three levels of high, middle and low.

  After performing the process of step S 384, the host control circuit 210 moves to the packet reception loop, and first, sets the brightness values of the panel-side LED and the frame-side LED according to the rendering mode and the setting of the brightness value to be executed. (Step S385). Similarly to the backlight, the brightness of the panel-side LED and the frame-side LED is, for example, set to three levels of high, middle and low.

  Here, by setting the setting of the brightness of the panel side LED and the frame side LED and setting the brightness of the backlight in common, the increase of the control load is suppressed and the brightness of the panel side LED and the frame side LED is reduced. Both the setting and the setting of the brightness of the backlight can be changed by the operation of the player or the like. For example, the host control circuit 210 changes the luminance value of the backlight based on the player or the like operating the luminance setting screen displayed on the liquid crystal display device used as the display device 13 (step S384). The brightness values of the panel-side LED and the frame-side LED are also changed (step S 385). At this time, the stage of the luminance value of the backlight and the stage of the luminance values of the panel-side LED and the frame-side LED are common. For example, if the stage of the brightness value of the backlight is middle, then the stages of the brightness values of the panel side LED and the frame side LED are also middle. As shown in FIG. 47, since the backlight luminance update timing and the panel side LED and frame side LED luminance update timings are different, after the backlight luminance is updated, the panel side LED and the frame side LED The brightness of the is to be updated. However, control may be performed so that the brightness update timing of the backlight and the brightness update timing of the panel-side LED and the frame-side LED become the same.

  The brightness of the backlight and the brightness of the panel-side LED and the frame-side LED are changed based on the player or the like operating the brightness setting screen displayed on the liquid crystal display device used as the display device 13. Although the present invention is not limited to this, for example, the brightness of the backlight, the brightness of the panel-side LED and the brightness of the frame-side LED may be changed based on the operation of the push button for effect. In this case, it is necessary to determine whether or not it is a period (function period of the push button) that functions as a push button for effect, so adjust the brightness of the panel side LED and the frame side LED in the main flow The backlight needs to be controlled according to the brightness of the LED.

  The host control circuit 210 performs animation construction processing in step S386. In the animation construction process of step S386, an LED request is created. The created LED request is queued in the buffer and then output in the LED request control process (see step S 382) of the next frame.

  The host control circuit 210 repeatedly performs the processes of step S385 and step S386 in accordance with the received packet.

  When leaving the packet reception loop, the host control circuit 210 performs animation update processing (step S387), and then waits for bank flip / bank flip completion (step S388).

  The host control circuit 210 repeatedly performs each process of steps S382 to S388 in the main loop at a cycle of 33.3 msec.

Second Embodiment
For example, when the brightness adjustment operation is performed by the player or the like, as described above, the control of the board-side LED and the frame-side LED may be affected. In this case, in this case, for example, when the brightness adjustment operation is performed by the player or the like, although the brightness value of the backlight is immediately changed, the control of the panel side LED and the frame side LED is a special symbol It is something which is executed after the end of fluctuation or between bank flips.

  As described above, in the timer interrupt process of FIG. 46, the host control circuit 210 controls the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order. Do.

  As shown in FIG. 48, after performing the initialization process (step S391), the host control circuit 210 moves to the main loop and performs the LED request control process (step S392). The LED request performed in step S392 is generated in the animation construction process (step S395 described later) one frame before.

  When the host control circuit 210 performs the process of step S392, the process of generating the sub device (button) input discrimination information described above is performed (step S393) based on the input state of the sub device (for example, the brightness adjustment operation by the player or the like). ) And moves to step S394.

  In step S394, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub device (for example, the brightness adjustment operation by the player or the like). The brightness of the backlight is, for example, set to three levels of high, middle and low.

  When the process of step S394 is performed, the host control circuit 210 moves to a packet reception loop and performs an animation construction process (step S395). In the animation construction process of step S395, an LED request is created. The created LED request is queued in the buffer and then output in the LED request control process (see step S392) of the next frame.

  The host control circuit 210 repeatedly performs the process of step S395 according to the received packet.

  When leaving the packet reception loop, the host control circuit 210 performs animation update processing (step S396), and then waits for bank flip / bank flip completion (step S397), and proceeds to step S398.

  In step S398, the host control circuit 210 determines whether or not the variation of the effect identification displayed on the liquid crystal display device as the display device 13 has ended, that is, whether or not the variation time of the effect identification symbol has elapsed. (Step S398). If the variation of the effect identification symbol has ended (YES in step S398), the host control circuit 210 changes the brightness of the panel-side LED and the frame-side LED according to the setting value at that time (step S399). On the other hand, if the variation of the special symbol has not ended (NO in step S398), the processing of steps S392 to S399 in the main loop of 33.3 msec cycle is repeated. The process of step S 399 may be performed during the bank flip of step S 397 instead of or in addition to when the variation of the special symbol is finished.

  As described above, in the second embodiment, the host control circuit 210 controls the brightness of the backlight directly affecting the eyes of the player based on the input state of the sub device (for example, the brightness adjustment operation by the player or the like). Is controlled to be changed immediately, but the brightness of the panel side LED and the frame side LED is changed after the brightness of the backlight is changed and after the variation of the identification symbol for effect is finished To control. In addition, when the brightness adjustment operation is performed by the player or the like during the fluctuation of the identification symbol for effect, the brightness of the panel-side LED and the frame-side LED needs to be changed by the LED request control process. Can be changed immediately. Therefore, based on the input state of the sub device, control is performed so that the brightness of the backlight is changed immediately, but the control load is changed by changing the brightness of the panel side LED and the frame side LED by the LED request control process. Can be minimized. That is, for example, the brightness of the backlight and the brightness of the panel-side LED and the frame-side LED can be changed while minimizing the control load only by performing the brightness adjustment operation once by the player or the like.

  When the brightness of the backlight is changed based on the input state of the sub device (for example, the brightness adjustment operation by the player or the like), the host control circuit 210 converts the brightness data related to the brightness after the change into FIFO. Set in the data area.

Third Embodiment
For example, when the brightness adjustment operation is performed by the player or the like, as described above, the control of the board-side LED and the frame-side LED may be affected. In this case, in such a case, for example, when a brightness adjustment operation is performed by a player or the like, the brightness value of the backlight is changed, and the effects of the panel-side LED and the frame-side LED are limited. It is something like that. To perform limitedly corresponds to, for example, limiting the number of LEDs emitting light in the effects of the panel-side LED and the frame-side LED, limiting the number of effects performed by the panel-side LED and the frame-side LED, etc. . To limit the number of effects is, for example, originally performing effects 1 to effect 5, performing effects 1 to 3 only, and omitting effect 4 and effect 5 and the like, etc. are equivalent. As a result, the effects of the panel-side LED and the frame-side LED are limited without directly changing the luminance value, and hence the intensity of light received by the player from the panel-side LED and the frame-side LED is suppressed. Become. Moreover, even if the update timing of the backlight control and the update timing of the control of the panel-side LED and the frame-side LED are different, the process can be facilitated.

  As described above, in the timer interrupt process of FIG. 46, the host control circuit 210 controls the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order. Do.

  As shown in FIG. 49, after performing the initialization process (step S401), the host control circuit 210 moves on to the main loop and performs the LED request control process (step S402). The LED request performed in step S402 is generated in the animation construction process (step S407 described later) one frame before.

  After performing the process of step S402, the host control circuit 210 performs the above-described process of generating sub device (button) input discrimination information (step S403) based on the input state of the sub device, and proceeds to step S404.

  In step S404, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub device (for example, the brightness adjustment operation by the player or the like). The brightness of the backlight is, for example, set to three levels of high, middle and low.

  When the process of step S404 is performed, the host control circuit 210 determines whether or not there is a change in setting of luminance (step S405). If there is a setting change of the luminance (YES in step S405), the host control circuit 210 limits the luminance of the panel-side LED and the frame-side LED according to the setting time (step S406), and moves to the packet reception loop. On the other hand, if there is no change in setting of the luminance value (NO in step S405), the host control circuit 210 proceeds to the packet reception loop without performing the process of step S406.

  In the packet reception loop, the host control circuit 210 performs animation construction processing (step S407). In the animation construction process of step S407, an LED request is created. The created LED request is queued in the buffer and then output in the LED request control process (see step S402) of the next frame.

  The host control circuit 210 repeatedly performs the process of step S407 according to the received packet.

  When leaving the packet reception loop, the host control circuit 210 performs animation update processing (step S408), and then waits for bank flip / bank flip completion (step S409).

  The host control circuit 210 repeatedly performs the processing of steps S402 to S409 in the main loop of 33.3 msec cycle.

  The backlight control process of this embodiment uses the function of SPI asynchronous data write (SPI + DMA) as described above for the above-described backlight and luminance adjustment of the various LEDs (first to third examples). For example, a signal corresponding to PWM is continuously output continuously from the serial output terminal of SPI. On the other hand, for the panel-side LED and the frame-side LED, for example, as shown in step S 382 of FIG. 47, the LEDs are controlled based on the LED request created one frame before the main loop. Therefore, even if the brightness adjustment of the backlight and various LEDs is performed, the timing at which the brightness of the backlight is changed is different from the timing at which the brightness of the panel-side LED or the frame-side LED is changed.

[RTC acquisition processing]
Next, RTC acquisition processing will be described with reference to FIG. As described above, the RTC acquisition process is performed both in various initialization processes (see step S201 in FIG. 36) and in the main loop (see step S201 in FIG. 36). FIG. 50 is a flowchart showing an example of the RTC acquisition process.

  For example, when an accurate time can not be acquired due to an RTC abnormality, such as when communication with the RTC can not be performed or when an abnormality occurs in the RTC itself, the time is not updated and remains at the previous time. Therefore, when an RTC effect (for example, an effect related to Christmas at Christmas time, etc.) is performed based on the RTC time, there is a possibility that the RTC effect can not be performed when an RTC abnormality occurs. Furthermore, when the RTC or more occurs, the RTC time is not updated, and there is a possibility that the RTC effect may be performed or the RTC effect may be performed when it is not expected.

  Therefore, in the RTC acquisition process of this embodiment, when the RTC is abnormal, that is, when the previous RTC time and the current RTC time are different, the RTC effect is executed based on the current time. Note that a secondary battery is provided in the RTC, and it is possible to manage time even when the host control circuit 210 is powered off. Also, the host control circuit 210 acquires time from the RTC, and manages an error occurrence time and the like.

  As shown in FIG. 50, in the RTC acquisition process, the host control circuit 210 first acquires an RTC time (step S412), and then proceeds to step S413.

  The host control circuit 210 updates the previous time in step S413. In the update of the previous time, the current time updated in step S416 described later is updated as the previous time. Thereafter, the host control circuit 210 determines whether the RTC is abnormal (step S414). If the RTC is abnormal (YES in step S414), the current time is maintained (step S415), and the process proceeds to step S417. On the other hand, if the RTC is not abnormal (NO in step S414), the current time is updated (step S416), and the process proceeds to step S417.

  In the RTC acquisition process of this embodiment, it is determined whether or not the RTC is abnormal after updating the time last time (step S413) (step S414), but instead, the previous time is updated It may be determined in advance whether or not the RTC is abnormal, and if the RTC is not abnormal, control may be performed so that the previous time is updated and the current time is not maintained.

  In step S417, the host control circuit 210 determines whether or not the current time is a designated time (for example, a time to execute an RTC effect). If the current time is a designated time (YES in step S417), the process moves to step S418, and if the current time is not a designated time (NO in step S417), the process moves to step S420.

  In step S418, the host control circuit 210 determines whether the previous time and the current time do not match. If the RTC is abnormal, the previous time and the current time do not match (YES in step S418). If the previous time and the current time do not match (YES in step S418), the RTC effect execution flag is set to 1 (step S419). That is, when the RTC is abnormal, the RTC effect is executed when the current time reaches the designated time. Then, when the process of step S419 is performed, the host control circuit 210 ends the RTC acquisition process. On the other hand, if the previous time and the current time do not match (NO in step S418), the process moves to step S420.

  The host control circuit 210 sets an RTC effect execution flag to 0 in step S420. Then, when the process of step S420 is performed, the host control circuit 210 ends the RTC acquisition process.

  As described above, in this embodiment, even when the RTC is abnormal, it is possible to avoid the situation where the RTC effect is not executed by executing the RTC effect when the current time reaches the designated time. .

[Composition playback control]
Next, composition reproduction control will be described with reference to FIGS. 51 and 52.

  The composition is, for example, scene data in which material data for forming an image (movie) displayed on a liquid crystal display device used as the display device 13 is combined, and is generally composed of a plurality of layers. Layers include animation, vector graphics, still images, lights, and so on.

  FIG. 51 is a flowchart showing an example of animation control main processing executed by the display control circuit 230. As shown in FIG. 51, the display control circuit 230 first clears the composition reproduction information (step S431). Then, the display control circuit 230 executes composition reproduction control processing (step S432). The composition reproduction control process will be described later. Thereafter, the display control circuit 230 executes the top direct drawing function (step S433), and ends the animation control main process.

  FIG. 52 is a flowchart showing an example of the composition reproduction control process executed by the display control circuit 230. As shown in FIG. 52, the display control circuit 230 first determines whether the determined number of priorities is less than (or less than or equal to) the upper limit of the number of priorities (step S441). If the determined number of priorities is less than (or less than) the upper limit of the number of priorities (YES in step S441), the process moves to step S442. The number of priorities is the number of layers of the composition to be reproduced simultaneously, and the upper limit of the number of priorities is predetermined based on the composition to be reproduced. Therefore, as long as the processing by the host control circuit 210 is normal, the determined number of priorities does not exceed the upper limit of the number of priorities. Therefore, when the determined number of priorities exceeds the upper limit of the number of priorities (NO in step S441), the display control circuit 230 ends the composition reproduction control process.

  In step S 442, the display control circuit 230 determines whether or not the determined number of displays is less than (or less than) the available number of displays, that is, the determined number of displays can be used on the system (for example, mounted) It is determined whether the number is less than (or less than) the number (step S442). If the determined number of displays is less than (or less than) the number of usable displays (YES in step S442), the process moves to step S443.

  In step S443, the display control circuit 230 determines whether the used display number is not 0, that is, whether or not the usable display number exists. If the used display number is not 0 (YES in step S443), that is, if there is a usable display number, the display control circuit 230 proceeds to step S444. On the other hand, if the used display number is 0 (NO in step S443), that is, if there is no usable display number, the display control circuit 230 proceeds to step S459.

  By the way, in the pachinko gaming machine 1 of the present embodiment, two frame buffers are provided as a frame buffer in which a composition is registered. These two frame buffers are used by switching the function of one frame buffer from the drawing function to the display function and switching the function of the other frame buffer from the display function to the drawing function by bank flip. Hereinafter, in this specification, a frame buffer having a display function is simply referred to as a "frame buffer", and a frame buffer having a drawing function is referred to as a "drawing result output destination buffer".

  In step S444, the display control circuit 230 determines whether a composition is registered in the drawing result output destination buffer. In the determination process of step S444, it is determined whether or not all the compositions are registered (that is, there is an unregistered one). If all the compositions are registered in the drawing result output destination buffer (YES in step S444), the display control circuit 230 sets a drawing target (step S445). Setting a drawing target is processing for setting a display to which drawing is to be performed. If the composition is not registered in the drawing result output destination buffer (NO in step S444), that is, if there is an unregistered composition, the display control circuit 230 proceeds to step S450.

  In step S446, the display control circuit 230 sets a drawing result output destination buffer as a frame buffer. That is, the process of step S446 is a process in which the drawing result output destination buffer is switched to the frame buffer by the bank flip. At this time, the composition registered in the drawing result output destination buffer switched from the frame buffer is cleared. After that, the display control circuit 230 determines whether or not there is a pause flag in the composition registered in the frame buffer switched from the drawing output destination buffer by the bank flip in step S446 (step S447). The pause flag is a flag of the debugging function for temporarily stopping the image, and when the pause flag is present (YES in step S447), the display control circuit 230 switches the drawing output destination buffer switched from the frame buffer by the bank flip of step S446. Then, the composition reproduction information is registered (step S448) and the composition is reproduced (step S449). On the other hand, if there is no pause flag (NO in step S447), the process moves to step S459. The playback information of the composition includes, for example, the size of the frame buffer, the size of the composition, the coordinates of the four vertices of the image to be played back, the composition registration information, the loop composition to be played back, the composition length, and the start frame setting. , Loop reproduction flag, etc. Further, registration of reproduction information of a composition means collecting reproduction information of the composition, and composition reproduction means registering reproduction information of the collected composition. When composition playback information is registered, previous playback information is cleared.

  In step S450, the display control circuit 230 determines whether the number of frames reproduced in the drawing result output destination buffer is equal to or more than the upper limit (that is, whether the number of reproduced frames exceeds the number of frames included in the composition). Determine. If the number of frames reproduced in the drawing result output destination buffer is not more than the upper limit (NO in step S450), the display control circuit 230 moves to step S457 and registers composition reproduction information in the drawing result output destination buffer (step S457) At step S457, the composition is reproduced (step S458).

  If the display control circuit 230 determines in step S450 that the number of frames reproduced in the drawing result output destination buffer is equal to or more than the upper limit (YES in step S450), the display control circuit 230 proceeds to step S451.

  In step S451, the display control circuit 230 determines whether the reproduction mode of the composition registered in the frame buffer is loop reproduction. If the reproduction mode of the composition registered in the frame buffer is loop reproduction (YES in step S451), the display control circuit 230 performs reproduction from the beginning during loop reproduction (step S452), and then proceeds to step S457. . If the reproduction mode of the composition registered in the frame buffer is not loop reproduction (NO in step S451), the display control circuit 230 proceeds to step S453.

  In step S453, the display control circuit 230 determines whether the reproduction mode of the composition registered in the frame buffer is the frame continuation display. If the reproduction mode of the composition registered in the frame buffer is the frame continuation display (YES in step S453), the display control circuit 230 reproduces the final frame during the frame continuation display (step S454), and then step S457. Move to If the reproduction mode of the composition registered in the frame buffer is not the frame continuous display (NO in step S453), the display control circuit 230 proceeds to step S455.

  In step S455, the display control circuit 230 determines whether the reproduction mode of the composition registered in the frame buffer is shot reproduction. If the reproduction mode is shot reproduction (YES in step S455), the display control circuit 230 clears the composition during shot reproduction (step S456), and then proceeds to step S459. If the reproduction mode of the composition registered in the frame buffer is not shot reproduction (NO in step S455), the display control circuit 230 proceeds to step S457.

  Note that the composition reproduction information registration in step S457 is, in principle, a process that is performed when a composition is not registered in the drawing result output destination buffer (when it is determined NO in step S444). However, as described above, even when there is a pause flag in the frame buffer switched from the drawing output destination buffer at the bank flip in step S446 as described above (YES in step S447), the frame flip at the frame flip in step S446 The composition reproduction information is registered in the drawing output destination buffer switched from the buffer (step S448) and the composition is reproduced (step S449). As described above, when there is a pause flag in the frame buffer switched from the drawing output destination buffer in the bank flip of step S446 (YES in step S447), composition reproduction information is immediately registered in the drawing output destination buffer ( Since the composition is reproduced at the same time as step S448) (step S449), rapid processing can be performed.

  In step S459, the display control circuit 230 adds 1 to the determined number of displays, and the process returns to step S442.

  If the display control circuit 230 determines in step S442 that the determined number of displays exceeds the upper limit of the number of usable displays (NO in step S442), the direct drawing function is executed if there is data to be directly drawn. (Step S460). Thereafter, the display control circuit 230 adds 1 to the determined number of priorities (step S461), and returns to step S441.

  As described above, in the composition reproduction control of this embodiment, in a state where the composition is registered in the drawing output destination buffer, in principle, reproduction information of a new composition is not registered. However, the composition is not registered only when the specific condition is satisfied (when it is determined as YES in step S447, that is, when the composition registered in the drawing output destination buffer has a pause flag) It becomes possible to perform processing (composition reproduction information registration) at the time. That is, in the state where the composition is registered in the drawing output destination buffer, the composition can be registered again at any timing, so it depends on the content of the composition newly (newly) registered. It is possible to overwrite the effect, skip the effect, and stop the effect.

  Also, the process of step S 441 is a process of determining whether the determined number of priorities is less than (or less than the upper limit of the number of priorities) (whether the determined number of displays is less than (or less than the number of usable displays) Is a process higher than the process of step S 442. Therefore, the process returns to step S 442 from the process of step S 459 to process the number of priorities determined in step S 441 on a plurality of displays. Therefore, the processing load can be reduced.

[Sound amplifier check process]
Next, the sound amplifier check process shown in FIG. 37 will be described with reference to FIGS. In this sound amplifier check process, it is determined whether the digital audio power amplifier 262 (hereinafter referred to as “sound amplifier”) is not in an abnormal state (for example, overcurrent abnormality, high temperature abnormality, DC detection abnormality in which audio signal does not change, etc.) Also, confirmation of setting information of the sound amplifier is performed. FIG. 53 is a flowchart showing an example of the sound amplifier check process. FIG. 54 is a flowchart showing an example of the normal amplifier check process. FIG. 55 is a flow chart showing an example of the bass check process.

  The pachinko gaming machine 1 of the present embodiment includes, as a sound amplifier, a normal amplifier for amplifying normal audio data and a bass amplifier for amplifying bass sound data.

  As shown in FIG. 53, the host control circuit 210 performs a normal amplifier check process (step S471) and a deep bass amplifier check process (step S472).

  As shown in FIG. 54, in the normal amplifier check process, the host control circuit 210 first determines whether setting has been performed from the binary file (step S481). If there is a binary file at initialization time, the setting is done from the binary file. In addition, the process at the time of initialization is executed not only at the time of power-on but also at the time of finding a problem in the amplifier check and resetting. Further, in the present embodiment, the setting is performed from the binary file. However, the present invention is not limited to this, and it may be a storage area different from the setting read like a binary file.

  When host control circuit 210 determines that the setting has been performed from the binary file (YES in step S481), it determines whether the register serving as the reference of the register value to be checked is normal (step S482). , And move on to step S483. In the determination process of step S 482, the values of the registers are checked in order of the address, so it is determined whether there is a value of the register that starts the check and whether the value is normal.

  In step S483, the host control circuit 210 rearranges the received data from the binary file. Thereafter, the host control circuit 210 compares the value of the register RAM with the received data (step S 484), and determines whether the value of the normal amplifier is normal (step S 485). When the host control circuit 210 performs the determination process of step S485, it ends the normal amplifier check process.

  On the other hand, if the setting from the binary file is not performed in step S481 (NO in step S481), host control circuit 210 performs a process (step S486) for comparing the default value and the set value, and performs the normal amplifier check process. Finish. When the normal amplifier check process ends, the host control circuit 210 performs a deep bass amplifier check process.

  As shown in FIG. 55, in the bass amplifier check process, the host control circuit 210 first determines whether the setting has been performed from the binary file (step S491).

  When host control circuit 210 determines that the setting has been performed from the binary file (YES in step S491), processing is performed to determine whether the register to be checked is normal (step S492), and then the process proceeds to step S493. .

  In step S493, the host control circuit 210 clears the register 0x17-0x25 with an appropriate value (binary file information) in consideration of the case where the value can not be read due to a hardware failure.

  In step S494, the host control circuit 210 rearranges the received data from the binary file. Thereafter, the host control circuit 210 compares the value of the RAM in the register with the received data (step S495), and performs the process of updating the RAM address (step S496). When the host control circuit 210 performs the update process of step S 496, the host bass amplifier check process ends.

  On the other hand, if the setting from the binary file is not performed in step S491 (NO in step S491), the host control circuit 210 performs a process (step S497) to compare the default value and the setting value. End the process.

  As described above, in the present embodiment, the host control circuit 210 performs the sound amplifier check process in the interrupt process of 1 msec. By the way, such sound amplifier check processing can also be performed in the main loop. However, when the sound amplifier check process is performed in the main loop, if it takes time for the sound amplifier check process, other processes may be stressed. Therefore, by performing the sound amplifier check process in the interrupt process as in the present embodiment, it is possible to perform the sound amplifier check process without stressing other processes in the main loop.

  Further, in the sound amplifier check process shown in the timer interrupt process (see FIG. 37), for example, as shown in FIG. 56, the normal amplifier / heavy bass amplifier (collective) check process (step S497) in the 1 msec interrupt process. ) May be performed. The normal amplifier / heavy-duty amplifier (collective) check process (step S 497) is a process for collectively performing the normal amplifier check process (see FIG. 54) and the deep bass amplifier check process (see FIG. 55).

  However, if the sound amplifier check process is performed in the 1 msec interrupt process, there may be cases where the entire sound amplifier check process can not be executed. Therefore, a more preferable embodiment of the sound amplifier check process will be described with reference to FIGS. FIG. 57 is a flowchart showing an example of a more preferable mode of the sound amplifier check process. FIG. 58 is a flow chart showing an example of a more preferable form of the normal amplifier / heavy bass amplifier check process. FIG. 59 shows an example of a more preferable form of the normal amplifier / heavy bass amplifier check process, and is a flowchart continued from FIG.

  In a more preferable embodiment of the sound amplifier check process, as shown in FIG. 57, the host control circuit 210 performs a normal amplifier / heavy bass amplifier (division) check process (step S 498). The normal amplifier / heavy bass amplifier (division) check process will be described later in detail, but each check process of the regular amplifier and each check process of the heavy bass amplifier can be divided into a range within 1 msec of interrupt processing. The check processing is performed inside, and the subsequent processing is performed in the subsequent frames. In other words, among the full check process of the normal amplifier and the full check process of the bass amplifier, only a part of the check process is performed in the one-time interrupt process, but all the check is performed across multiple interrupt processes. The In this way, in the interrupt processing, it is possible to execute the entire check processing of the normal amplifier and the check processing of the deep bass amplifier without being terminated halfway.

  As shown in FIG. 58, in the normal amplifier / bass amplifier (division) check process, the host control circuit 210 first determines whether the setting is performed from the binary file (step S501).

  When the host control circuit 210 determines that the setting has been performed from the binary file (YES in step S501), it determines whether the check status is 0 (step S502). If the check status is 0 (YES in step S502), the host control circuit 210 determines whether the register value checked by the normal amplifier is normal (step S503). After performing the process of step S503, the host control circuit 210 sets the check status to 1 (step S504), and ends the normal amplifier / heavy bass amplifier (division) check process. When the host control circuit 210 determines that the check status is not 0 in step S502 (NO in step S502), the process proceeds to step S505. In the process of step S503, whether or not each register value of the plurality of registers is normal may be divided and further divided for each register.

  In step S505, the host control circuit 210 determines whether the check status is "1". If the check status is 1 (YES in step S505), the host control circuit 210 rearranges received data from the binary file (step S506). Thereafter, the host control circuit 210 compares the value of the RAM of the register of the normal amplifier with the received data (step S507), and determines whether or not the processing for the number of divisions of the normal amplifier has been executed (step S508). ). If the processing for the division number of the normal amplifier has been executed (YES in step S508), the host control circuit 210 sets the check status to 2 (step S509), and the normal amplifier / heavy bass amplifier (division ) End the check process. On the other hand, when the processing for the division number of the normal amplifier is not executed (NO in step S508), the host control circuit 210 does not update the check status, and the normal amplifier / heavy bass amplifier (division) check processing Finish. That is, since the check status is maintained at 1 without being updated, the host control circuit 210 performs again the process in the case where the check status is 1 in the frames after the next time. When the host control circuit 210 determines that the check status is not 1 in step S505 (NO in step S505), the process proceeds to step S510. In the process of step S508, the process of comparing the value of the RAM of each register among the plurality of registers with the received data may be further divided and performed for each register.

  The host control circuit 210 determines whether the check status is 2 or not in step S510. If the check status is 2 (YES in step S510), the host control circuit 210 determines whether the value of the normal amplifier is normal (step S511). Thereafter, the host control circuit 210 determines whether or not processing for the number of divisions of the normal amplifier has been executed (step S512). If the processing for the division number of the normal amplifier has been executed (YES in step S512), the host control circuit 210 sets the check status to 3 (step S513), and the normal amplifier / heavy bass amplifier (division ) End the check process. On the other hand, when the processing for the division number of the normal amplifier is not executed (NO in step S512), the host control circuit 210 does not update the check status, and the normal amplifier / heavy bass amplifier (division) check processing Finish. That is, since the check status is maintained at 2 without being updated, the host control circuit 210 performs again the process in the case where the check status is 2 in the frames after the next time. When host control circuit 210 determines that the check status is not 2 in step S510 (NO in step S510), the process proceeds to step S514 (see FIG. 59).

  Referring to FIG. 59, host control circuit 210 determines whether the check status is 3 or not in step S514. If the check status is 3 (YES in step S514), the host control circuit 210 determines whether the register value checked by the high tone amplifier is normal (step S515). Thereafter, the host control circuit 210 determines whether or not the processing for the number of divisions of the deep bass amplifier has been performed (step S516). If the processing for the number of divisions of the bass amplifier has been executed (YES in step S516), the host control circuit 210 sets the check status to 4 (step S517), and the ordinary amplifier / bass amplifier ( The division processing ends. On the other hand, if processing for the number of divisions of the bass amplifier is not executed (NO in step S516), the host control circuit 210 checks the normal amplifier / bass amplifier (division) check without updating the check status. End the process. That is, since the check status is maintained at 3 without being updated, the host control circuit 210 performs again the process in the case where the check status is 3 in the frames after the next time. When the host control circuit 210 determines that the check status is not 3 in step S514 (NO in step S514), the process proceeds to step S518.

  The host control circuit 210 determines whether the check status is 4 or not in step S518. If the check status is 4 (YES in step S518), the host control circuit 210 clears the value of the register of the deep bass amplifier with an appropriate value (step S519). Thereafter, the host control circuit 210 sets the check status to 5 (step S520), and ends the normal amplifier / heavy bass amplifier (division) check process. When the host control circuit 210 determines that the check status is not 4 in step S518 (NO in step S518), the process proceeds to step S521.

  The host control circuit 210 determines whether the check status is 5 or not in step S521. If the check status is 5 (YES in step S521), the host control circuit 210 performs a rearrangement process of received data from the binary file (step S522). Thereafter, the host control circuit 210 compares the value of the RAM of the register of the bass amplifier with the received data (step S523), and updates the RAM address (step S524). Thereafter, the host control circuit 210 determines whether or not the processing for the number of divisions of the deep bass amplifier has been performed (step S525). If processing for the number of divisions of the bass amplifier has been executed (YES in step S525), host control circuit 210 determines whether or not updating of the RAM address is completed (step S526), and the check status is It is set to 0 (step S527), and the normal amplifier / heavy bass amplifier (division) check process is ended. When processing for the number of divisions of the bass amplifier is not executed in step S525 (NO in step S525), and when it is determined that updating of the RAM address is not completed in step S526 (NO in step S526) The host control circuit 210 ends the normal amplifier / heavy bass amplifier (division) check process without updating the check status. That is, since the check status is maintained at 5 without being updated, the host control circuit 210 performs again the process in the case where the check status is 5 in the frames after the next time. If the host control circuit 210 determines in step S521 that the check status is not 5 (NO in step S521), the normal amplifier / bass amplifier (division) check process ends.

  As described above, in a preferred embodiment of the sound amplifier check process, each check process of the normal amplifier and each check process of the bass amplifier can be divided and performed within 1 msec of interrupt process (that is, within one frame). The check processing is performed within the range, and the subsequent processing is performed in the subsequent frames. As described above, since a part of each of the check processing of the normal amplifier and the check processing of the bass amplifier is performed over a plurality of frames in one frame, the entire check processing of each amplifier can be performed over a plurality of frames. It becomes possible.

  When the check status is 4, the host control circuit 210 determines whether or not the processing for the number of divisions has been performed (for example, if the check status is 3, the processing in step S516 corresponds). Absent. This is because the process of step S519 performed when the check status is 4 can be performed as short as possible without affecting the 1 msec interrupt process. In other words, the process performed when the check status is 4 (step S519) is the process performed when the check status is 0 (step S503), and the process performed when the check status is 1 (step S506). And step S507), processing performed when the check status is 2 (step S511), processing performed when the check status is 3 (step S515), processing performed when the check status is 5 (step S515) This is because the time required for the process is shorter than that in S522 to step S524), and the interrupt process of 1 msec is not affected. As described above, in the pachinko gaming machine 1 of the present embodiment, in consideration of the time required for processing (whether or not to affect the interrupt processing of 1 msec), it is determined whether processing for the number of divisions has been performed. It is decided whether or not. However, even if the processing does not affect the interrupt processing of 1 msec (for example, processing such as step S519 performed when the check status is 4), whether or not processing for the number of divisions has been performed The determination may be made.

  In the processes of step S503, step S511, and step S515, the determination as to whether or not each register value among the plurality of registers is normal may be further divided and performed for each register. In this case, the progress of the divided determination may be managed by the second check status. That is, the check status (first check status) according to the process of major classification shown in FIGS. 58 and 59, and the check status (second check status) according to the process of minor classification into which the process of major classification is further divided. And manage the progress of the process. Similarly, in each of steps S506 to S507 and steps S522 to S523, the process of comparing the value of the RAM of each register among the plurality of registers with the received data is further divided for each register and performed. It is good. In this case, the progress of the further divided processing may be managed by the second check status. That is, the check status (first check status) according to the process of major classification shown in FIGS. 58 and 59, and the check status (second check status) according to the process of minor classification into which the process of major classification is further divided. And manage the progress of the process. For example, even if a power failure occurs in the middle of the small classification processing or determination, the progress status of the small classification processing or determination is checked by the first check status and the second check status after power recovery. You may control so that each process and each determination may be restarted.

  The check status is 0 when the power is turned on, and can be set in various ways, such as starting from the check status at the previous time of power failure after power recovery, when power failure occurs. Needless to say, when a power failure occurs, when the power is turned on, or when backup clear (ram clear) processing is performed, the check status is set to 0 after power recovery, and all processing and determination are performed again ( Alternatively, as one process of the initialization process, all the processes or determinations or some processes or determinations may be performed again.

[Sound request control process (when there are multiple sound requests for the same channel)]
Next, with regard to the sound request control process shown in FIG. 36, the sound request control process when there are a plurality of sound requests (also referred to as SAC request) for the same channel will be described with reference to FIG. FIG. 60 is a flowchart showing an example of the sound request control process when there are a plurality of sound requests for the same channel.

  In the pachinko gaming machine 1 of this embodiment, when a plurality of SAC requests are made to the same reproduction channel in the same frame of the main loop performed in a cycle of 33.3 msec, a mute command of 2 msec, for example, between the SAC request and the SAC request. Is registered. Thereby, it is possible to prevent the game sound output based on the SAC request from being covered by another game sound, and it is possible to output a game sound with high accuracy. However, in this case, there is a merit that the game sound is not overwritten, but there is a possibility that it takes time for processing. Therefore, in the pachinko gaming machine 1 of the present embodiment, when a plurality of SAC numbers are designated (registered) in the same virtual track in the same frame of the main loop, the SACs of the second arrival are spaced apart from the first SAC request. A case of making a request and a case of making a second-arrival SAC request without an interval between the first-arrival SAC number are provided. The details will be described below.

  As shown in FIG. 60, in the sound request control process (when there are a plurality of sound requests for the same channel), the host control circuit 210 first confirms the SAC number and the reproduction channel (step S 541). Thereafter, the process proceeds to step S542.

  In step S 542, the host control circuit 210 determines whether there are a plurality of SAC requests for the same reproduction channel. For example, since SAC numbers are different between SHOT reproduction and LOOP reproduction, a plurality of SAC numbers may be designated to the same reproduction channel without an interval. If there are a plurality of SAC requests for the same reproduction channel (YES in step S542), the host control circuit 210 proceeds to step S543. On the other hand, if there are a plurality of SAC requests for the same reproduction channel (NO in step S 542), the sound request control process is ended. In the present embodiment, since one virtual track corresponds to one reproduction channel, the determination process of step S542 is synonymous with the determination of whether or not there is a SAC request for the same virtual track. It is. That is, "track" is an interface for decoding and reproducing "phrase", and "reproduction channel" is a concept for reproducing "phrase". That is, when the "play channel" is specified and the "phrase" is requested to be played back, the phrase is assigned to the corresponding "track" and the phrase is played back. Also, "virtual track" is an "interface for phrase reproduction control". The virtual track has 128 channels and can be automatically distributed to the phrase reproduction channel of 32 channels. However, in this embodiment, since this function is not used, “virtual track” = “reproduction channel”.

  In step S543, the host control circuit 210 determines whether it is chain reproduction of SHOT reproduction and LOOP reproduction. In the case of chain reproduction of SHOT reproduction and LOOP reproduction (YES in step S543), the host control circuit 210 executes the SAC request of LOOP reproduction one frame later (33.3 msec later) (step S544) to control the sound request control. End the process. In the case of chain playback of SHOT playback and LOOP playback, the SAC request for LOOP playback is delayed by one frame and executed so that the sound of SHOT playback is not overwritten, and the sound of SHOT playback is prevented from being difficult to hear It becomes possible. On the other hand, if it is not chain reproduction of SHOT reproduction and LOOP reproduction (NO in step S543), the host control circuit 210 proceeds to step S545.

  In step S545, the host control circuit 210 determines whether the mute command between the SACs is the mute setting of all the reproduction channels. For example, when the variable display of the special symbol or the decorative symbol is finished, the mute command is uniformly set between the SACs for all the reproduction channels. Then, if the mute command between the SACs is the mute setting of all the reproduction channels (YES in step S545), the host control circuit 210 performs SAC data corresponding to the first SAC request so that the mute is executed. The SAC data corresponding to the late SAC request is set without overwriting the mute command (step S546), and the sound request control process is ended. On the other hand, when the mute command between the SACs is not the mute setting of all the playback channels (NO in step S545), the mute command of each playback channel corresponds to the SAC request of the second arrival so that quick processing is performed. The SAC data is overwritten and set (step S547), and the sound request control process ends.

  As described above, in the pachinko gaming machine 1 according to the present embodiment, when a plurality of SAC requests are made to the same reproduction channel in the same frame of the main loop, the plurality of SAC requests are chain reproduction of SHOT reproduction and LOOP reproduction. The SAC number of the LOOP playback is delayed by one frame (for example, 33.3 msec) so that the sound of the LOOP playback is not covered with the SHOT playback. The SHOT reproduction is, for example, one reproduction of a phrase, and the LOOP reproduction is, for example, LOOP reproduction (reproduction of a plurality of times) of a phrase.

  If the mute command between SACs is set to mute all playback channels, the mute command is not executed after overwriting the last SAC data, and the SAC data corresponding to the SAC number is not overwritten. sign up. Thus, for example, when the variation display of the special symbol is finished, it is possible to secure the period until the next variation display of the special symbol is started. Furthermore, when the mute command between the SACs is not the mute setting of all playback channels, the mute command of each playback channel is overwritten with the SAC data corresponding to the subsequent SAC request so that the mute is not performed. As described above, by executing or not executing the mute according to the situation, it is possible to secure the rapidity of the process (the promptness due to the overwrite of the mute) while taking advantage of the game sound effect by the mute. ing.

[Sound request control process (when volume adjustment is performed)]
Next, regarding the sound request control process shown in FIG. 36, a variation of the sound request control process when the volume adjustment is performed will be described. In this specification, five variations of the first to fifth embodiments will be described as variations of the sound request control process when the volume adjustment is performed, with reference to FIGS. 61 to 65, respectively. FIG. 61 is a flowchart showing a first example of the sound request control process when the volume adjustment is performed. FIG. 62 is a flow chart showing a second embodiment of the sound request control process when the volume adjustment is performed. FIG. 63 is a flowchart showing a third example of the sound request control process when the volume adjustment is performed. FIG. 64 is a flowchart showing a fourth example of the sound request control process when the volume adjustment is performed. FIG. 65 is a flowchart showing a fifth example of the sound request control process when the volume adjustment is performed.

(First embodiment)
As shown in FIG. 61, in the first embodiment of the sound request control process (when volume adjustment is performed), the host control circuit 210 first performs an input process of audio data designated by the SAC number ( Step S551). Thereafter, the process proceeds to step S552. The SAC number is registered in each channel by the host control circuit 210.

  In step S552, the host control circuit 210 designates the speaker of the output destination based on the audio data designated by the SAC number, and proceeds to step S553. In the first embodiment, the audio data designated by the SAC number incorporates information on which speaker to output. The speaker is, for example, a general-purpose speaker (used for outputting a normal sound other than a specific sound) and a dedicated speaker used for outputting a specific sound (error sound, warning sound, etc.) And a speaker (for example, a speaker for deep bass). The host control circuit 210 performs setting of which one of the plurality of speakers is to be a dedicated speaker in various initialization processes (for example, refer to various initialization processes (step S201 in FIG. 36)).

  In step S553, the host control circuit 210 determines whether volume control is performed by the hardware switch. If volume control is performed by the hardware switch (YES in step S553), volume control (see reference numeral 281 in FIG. 9) by the hardware switch is performed (step S554), and the process proceeds to step S556. On the other hand, if it is not volume control by the hardware switch (NO in step S553), user volume control (see reference numeral 282 in FIG. 9) is performed (step S555), and the process moves to step S556.

  In step S556, the host control circuit 210 performs debug volume control (see reference numeral 283 in FIG. 9) at the time of debugging, and then proceeds to step S557.

  In step S557, the host control circuit 210 determines whether or not volume control of a specific sound is performed. The specific sound corresponds to, for example, a sound that does not want to be affected by volume adjustment, such as an error sound. Further, in the audio data instructed by the SAC number, information indicating that the output destination of the normal sound is the shared speaker is incorporated, and information indicating that the output destination of the specific sound is the dedicated speaker is incorporated. There is.

  If it is determined in step S558 that volume control of a specific sound is not performed (NO in step S557), the host control circuit 210 performs volume control (see symbol 284 in FIG. 9) for normal sound set in the channel (step S558). ), Go to step S560. In the volume control of step S558, control is performed to change the volume according to the volume adjustment.

  On the other hand, when it is determined in step S557 that volume control of a specific sound is performed (YES in step S557), the host control circuit 210 performs volume control (symbol 285 in FIG. 9) for the specific sound set in the channel ( The process proceeds to step S560). In the volume control in step S559, control to output a constant volume without being affected by volume adjustment regardless of whether or not volume adjustment is performed (that is, even if a volume change operation is performed, the operation Control is performed before and after a constant volume is output.

  In step S560, the host control circuit 210 determines whether or not volume control for the number of channels (32 channels of 1CH to 32CH in this embodiment) has been performed.

  If volume setting for the number of channels has been performed in step S560 (YES in step S560), volume control incorporated in the audio data designated by the SAC number is performed (step S561), and the sound request control process ends Do.

  If volume control for the number of channels is not performed in step S560 (NO in step S560), the host control circuit 210 returns to step S557, and determines volume control for the number of channels (YES in step S560) Until the process is performed, the processes of steps S557 to S560 are performed. Although not shown in FIG. 61, in view of the designation of the SAC number corresponding to each channel, volume control corresponding to the number of channels is performed also in the processing of step S561. good.

Second Embodiment
As shown in FIG. 62, in the second embodiment of the sound request control process (when volume adjustment is performed), the host control circuit 210 first performs an input process of audio data designated by the SAC number ( Step S571). Thereafter, the process proceeds to step S572. The SAC number is registered in each channel by the host control circuit 210.

  In this second embodiment, for example, a common channel (used for outputting a normal sound other than a specific sound) used for general purpose and a specific sound (error sound, warning sound, etc.) A dedicated channel used for output is provided. The host control circuit 210 includes a dedicated channel (CH31, CH32) used to output a specific sound among a plurality of channels (1 to 32 CH) and a shared channel (CH1) used for sounds other than the specific sound. .About.CH30 are set in various initialization processes (for example, refer to various initialization processes (step S201) in FIG. 36).

  In step S572, the host control circuit 210 determines whether or not volume control is performed by a hardware switch. If volume control is performed by the hardware switch (YES in step S572), volume control (see reference numeral 281 in FIG. 9) by the hardware switch is performed (step S573), and the process proceeds to step S575. On the other hand, if it is not volume control by the hardware switch (NO in step S572), user volume control (see reference numeral 282 in FIG. 9) is performed (step S574), and the process proceeds to step S575.

  In step S576, the host control circuit 210 performs debug volume control (see reference numeral 283 in FIG. 9) at the time of debugging, and then proceeds to step S576.

  In step S576, the host control circuit 210 determines whether it is volume control of a specific sound. Also in the second embodiment, the specific sound corresponds to a sound such as an error sound which is not desired to be affected by the volume adjustment.

  If it is determined in step S576 that volume control of a specific sound is not performed (NO in step S576), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for normal sound set in the channel (step S577). ), Go to step S578. In the volume control of step S577, control is performed to change the volume according to the volume adjustment.

  On the other hand, when it is determined in step S576 that volume control of a specific sound is performed (YES in step S576), the host control circuit 210 performs volume control (symbol 285 in FIG. 9) for the specific sound set in the channel ((2) in FIG. The process moves to step S 582). In the volume control in step S579, a control that outputs a constant volume without being affected by the volume adjustment regardless of whether or not the volume adjustment is performed (that is, even if the volume change operation is performed, the operation is performed Control is performed before and after a constant volume is output.

  In step S578, the host control circuit 210 determines whether reproduction is performed on a reproduction channel which is not affected by volume adjustment. In the case of reproduction on a reproduction channel (for example, CH31 and CH32) which is not affected by volume adjustment (YES in step S578), a constant volume is designated (step S580). If it is the reproduction on the reproduction channel (for example, CH1 to CH30) to be subjected to the volume adjustment (NO in step S578), the volume according to the user volume is set (step S581). When the process of step S580 ends or the process of step S581 ends, the host control circuit 210 proceeds to step S582.

  In step S 582, the host control circuit 210 determines whether volume control has been performed for the number of channels (in this embodiment, 32 channels of 1 CH to 32 CH).

  If volume setting for the number of channels is performed in step S632 (YES in step S582), volume control incorporated in the audio data designated by the SAC number is performed (step S583), and the sound request control process is ended. Do.

  If volume control for the number of channels is not performed in step S582 (NO in step S582), the host control circuit 210 returns to step S576, and determines volume control for the number of channels (YES in step S582) The processing of steps S576 to S582 is performed until Although not shown in FIG. 62, volume control for the number of channels may be performed in the process of step S583.

Third Embodiment
As shown in FIG. 63, in the third embodiment of the sound request control process (when volume adjustment is performed), the host control circuit 210 first performs an input process of audio data specified by the SAC number ( Step S591). Thereafter, the process proceeds to step S592.

  In step S592, the host control circuit 210 determines whether volume control is performed by the hardware switch. If volume control is performed by the hardware switch (YES in step S592), volume control (see reference numeral 281 in FIG. 9) by the hardware switch is performed (step S593), and the process proceeds to step S595. On the other hand, if it is not volume control by the hardware switch (NO in step S592), user volume control (see reference numeral 282 in FIG. 9) is performed (step S594), and the process proceeds to step S595.

  In step S595, the host control circuit 210 performs debug volume control (see reference numeral 283 in FIG. 9) at the time of debugging, and then proceeds to step S596.

  In step S596, the host control circuit 210 determines whether volume control of a specific sound is performed. Also in the third embodiment, the specific sound corresponds to a sound such as an error sound which is not desired to be affected by the volume adjustment.

  If it is determined in step S596 that volume control of a specific sound is not performed (NO in step S596), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for normal sound set in the channel (step S597). ), Go to step S599. In the volume control of step S597, control is performed to change the volume according to the volume adjustment.

  On the other hand, when it is determined in step S596 that volume control of a specific sound is performed (YES in step S596), the host control circuit 210 performs volume control (symbol 285 in FIG. 9) for the specific sound set in the channel ((2) in FIG. It moves to step S599) and step S599. In the volume control in step S598, control is performed such that a constant volume is output regardless of whether or not volume adjustment is performed (that is, even if a volume change operation is performed, the operation is performed Control is performed before and after a constant volume is output.

  In step S599, the host control circuit 210 determines whether the data currently being reproduced (data being reproduced) is data that is not affected by the volume adjustment. If the data in the reproduction channel is data which is not affected by the volume adjustment (YES in step S599), a constant volume is designated as the reproduction channel next time (step S600). If the data in the reproduction channel is data to be subjected to volume adjustment (NO in step S599), next, the volume according to the volume adjustment is set in the reproduction channel (step S601). When the process of step S600 ends or the process of step S601 ends, the host control circuit 210 proceeds to step S602.

  In step S602, the host control circuit 210 determines whether volume control has been performed for the number of channels (in this embodiment, 32 channels of 1CH to 32CH).

  If volume setting for the number of channels has been performed in step S602 (YES in step S602), volume control incorporated in the audio data specified by the SAC number is performed (step S603), and the sound request control process ends Do.

  If volume control for the number of channels has not been performed in step S602 (NO in step S602), the host control circuit 210 returns to step S599, and determines volume control for the number of channels (YES in step S602) Until the process is performed, the processes of steps S599 to S602 are performed. Although not shown in FIG. 63, volume control for the number of channels may be performed in the process of step S603.

  In the third embodiment, it is determined in step S599 whether the data currently being reproduced (data being reproduced) is data not affected by the volume adjustment, and the determination result in step S599 is If YES, the next playback channel is set to a constant volume (step S600), and if the determination result in step S599 is NO, the next playback channel is set to a volume according to the volume adjustment. Instead, it may be a modification as described below. That is, in this modification, as processing of the step following step S597 and step S598, the audio data set this time and the audio data already reproduced on the reproduction channel to which the audio data is set are volume-adjusted. After performing processing to check whether or not the data is not affected, it is determined whether or not the setting of volume adjustment of the current audio data and the setting of volume adjustment of the previous audio data are the same. I do. If the setting of the volume adjustment of the audio data this time and the setting of the volume adjustment of the previous audio data are the same, it is determined whether the data is not affected by the volume adjustment. If the volume adjustment setting of the audio data and the volume adjustment setting of the previous audio data are not the same, the volume adjustment setting of the audio data set this time is not affected by the volume adjustment. It moves on to processing to determine whether it is data or not. The process moves to a process of determining whether the data is not affected by the volume adjustment. Then, when the data is not affected by the volume adjustment, a process of setting a fixed volume to the reproduction channel is performed, and when the data is affected by the volume adjustment, the volume adjustment is performed according to the volume adjustment. Perform processing to set the volume. Thereafter, as in step S602, it is preferable to shift to a process of determining whether or not the number of channels has been set. The process different from the third embodiment in this modification is only the process described above, and the other processes are the processes of the third embodiment (the processes of steps S592 to S598 shown in FIG. 63, the process of step S602, And the process of step S603).

Fourth Embodiment
As shown in FIG. 64, in the fourth embodiment of the sound request control process (when volume adjustment is performed), the host control circuit 210 first determines whether the SAC number is a SAC number affected by volume adjustment Whether or not it is confirmed (step S611). Thereafter, the process proceeds to step S612.

  In step S612, the host control circuit 210 updates a flag indicating whether the SAC number is affected by volume adjustment, and performs input of audio data specified by the SAC number (step S613). Specifically, if the SAC number is affected by volume adjustment, the flag is set to ON (if the SAC number is not affected by volume adjustment, the flag is OFF).

  In step S614, the host control circuit 210 determines whether volume control is performed by a hardware switch. If volume control is performed by the hardware switch (YES in step S614), volume control (see reference numeral 281 in FIG. 9) by the hardware switch is performed (step S615), and the process proceeds to step S617. On the other hand, if it is not volume control by the hardware switch (NO in step S614), user volume control (see reference numeral 282 in FIG. 9) is performed (step S610), and the process proceeds to step S617.

  In step S617, the host control circuit 210 performs debug volume control (see reference numeral 283 in FIG. 9) at the time of debugging, and then proceeds to step S618.

  In step S618, the host control circuit 210 determines whether it is volume control of a specific sound. Also in the fourth embodiment, the specific sound corresponds to, for example, a sound that does not want to be affected by the volume adjustment, such as an error sound.

  If it is determined in step S618 that volume control of a specific sound is not performed (NO in step S618), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for normal sound set in the channel (step S619). ), Go to step S620. In the volume control of step S619, control is performed to change the volume according to the volume adjustment.

  On the other hand, when it is determined in step S618 that volume control of a specific sound is performed (YES in step S618), the host control circuit 210 performs volume control (symbol 285 in FIG. 9) for the specific sound set in the channel ((2) in FIG. Step S622) Move on to step S624. In the volume control of step S 622, a control that outputs a constant volume without being affected by the volume adjustment regardless of whether or not the volume adjustment is performed (that is, even if a volume change operation is performed, the operation Control is performed before and after a constant volume is output.

  In step S620, the host control circuit 210 determines whether or not reproduction is performed on a reproduction channel not affected by volume adjustment. That is, in step S612, it is determined whether the flag is set to ON. When the reproduction is performed on the reproduction channel not affected by the volume adjustment (YES in step S620), a constant volume is designated for the reproduction channel (step S621), and the process proceeds to step S624. When the reproduction is not performed on the reproduction channel not affected by the volume adjustment (NO in step S620), the volume according to the volume adjustment is set to the reproduction channel (step S623), and the process proceeds to step S624.

  In step S624, the host control circuit 210 determines whether volume control has been performed for the number of channels (in this embodiment, 32 channels of 1CH to 32CH).

  If volume setting for the number of channels is performed in step S624 (YES in step S624), volume control incorporated in the audio data designated by the SAC number is performed (step S625), and the sound request control process is ended. Do.

  If volume control for the number of channels has not been performed in step S624 (NO in step S624), the host control circuit 210 returns to step S618, and determines volume control for the number of channels (YES in step S624) Until the process is performed, the processes of steps S618 to S624 are performed. Although not shown in FIG. 64, volume control for the number of channels may be performed in the process of step S625.

Fifth Embodiment
As shown in FIG. 65, in the fifth embodiment of the sound request control process (when volume adjustment is performed), the host control circuit 210 first performs an input process of audio data designated by the SAC number ( Step S631). Thereafter, the process proceeds to step S632.

  The host control circuit 210 confirms whether the audio data is audio data to which each channel is subjected to volume adjustment (step S633). Specifically, when the audio data specified by the SAC number is the audio data affected by the volume adjustment, the flag is set to ON (the audio data specified by the SAC number is not affected by the volume adjustment If it is voice data, the flag is OFF).

  In step S633, the host control circuit 210 determines whether volume control is performed by a hardware switch. If volume control is performed by the hardware switch (YES in step S633), volume control (see reference numeral 281 in FIG. 9) by the hardware switch is performed (step S634), and the process proceeds to step S636. On the other hand, if it is not volume control by the hardware switch (NO in step S633), user volume control (see reference numeral 282 in FIG. 9) is performed (step S635), and the process proceeds to step S636.

  In step S636, the host control circuit 210 performs debug volume control (see reference numeral 283 in FIG. 9) at the time of debugging, and then proceeds to step S637.

  In step S637, the host control circuit 210 determines whether it is volume control of a specific sound. Also in the fifth embodiment, the specific sound corresponds to a sound such as an error sound which is not desired to be affected by the volume adjustment.

  If it is determined in step S637 that volume control of a specific sound is not performed (NO in step S637), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for normal sound set in the channel (step S638). ), Go to step S639. In the volume control of step S638, control is performed to change the volume according to the volume adjustment.

  On the other hand, when it is determined in step S637 that volume control of a specific sound is performed (YES in step S637), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (FIG. 9). It moves to step S643) and step S640. In the volume control in step S640, control is performed such that a constant volume is output without being affected by volume adjustment regardless of whether or not volume adjustment has been performed (that is, even if a volume change operation has been performed, the operation Before and after a constant volume is output).

  In step S639, the host control circuit 210 determines whether the channel is not affected by the volume adjustment. That is, it is determined in step S632 whether the flag is set to ON. If the channel is not affected by the volume adjustment (YES in step S639), a constant volume is set to the reproduction channel (step S641). If the channel is affected by the volume adjustment (NO in step S639), the volume according to the volume adjustment is set to the reproduction channel (step S642). When the process of step S641 ends or the process of step S642 ends, the host control circuit 210 proceeds to step S643.

  In step S643, the host control circuit 210 determines whether volume control has been performed for the number of channels (in this embodiment, 32 channels of 1CH to 32CH).

  If volume setting for the number of channels has been performed in step S643 (YES in step S643), volume control incorporated in the audio data specified by the SAC number is performed (step S644), and the sound request control process ends Do.

  If volume control for the number of channels is not performed in step S643 (NO in step S643), the host control circuit 210 returns to step S637, and determines volume control for the number of channels (YES in step S643) The processing of steps S637 to S643 is performed. Although not shown in FIG. 65, volume control for the number of channels may be performed in the process of step S644.

  According to the sound request control process (the first to fifth embodiments) when the above-described volume adjustment is performed, when the volume adjustment is performed, the volume corresponding to the volume adjustment is output for the normal sound. On the other hand, for a critical specific sound such as an error sound, for example, it is possible to easily perform voice control such as outputting a constant volume from the speaker even if the volume adjustment is performed.

[LED brightness adjustment processing]
Next, the adjustment of the brightness of the LED will be described with reference to FIGS. 36 and 66. FIG. 66 is an attenuation table showing an example of the luminance attenuation value of each color (red, green, blue) according to the emission intensity of the strong, medium and weak LEDs. The attenuation table is stored in the sub main ROM 205 (see, for example, FIG. 6).

  In the pachinko gaming machine 1 of the present embodiment, for example, the brightness of the LED can be adjusted in three steps by the operation of the player or the like. Specifically, when the operation of adjusting the luminance is performed on the luminance setting screen displayed on the liquid crystal display device used as the display device 13, the host control circuit 210 performs the switching process of the attenuation table shown in FIG. For example, when an operation of changing from high intensity to low intensity among three levels of brightness is performed, the host control circuit 210 performs processing of switching the reference table into high intensity to low in the attenuation table of FIG.

  The LED whose luminance can be adjusted by the operation of the player or the like may be, for example, an LED provided on the glass door 4 (for example, see FIG. 3). For example, a backlight of a liquid crystal display device used as the display device 13 It may be The brightness adjustment of the LED is not limited to three stages, and may be configured to be adjustable in more stages, for example.

The output value of the LED is represented by the following equation (1).
LED output value = brightness value by LED data × (100−brightness attenuation value) / 100 equation (1)
The output value of the LED of the above equation (1) can also be set for each reproduction channel of the LED. The parameter changed by the operation of the player is the luminance attenuation value. For example, when the luminance attenuation value is 0, the luminance is the highest, and when the luminance attenuation value is 100, the luminance is the weakest. Also, calculation of the output value of the LED is performed inside the sequencer 226 b (see FIG. 7).

  The LED data table that defines LED data and playback patterns etc. creates a BLD file (LED animation) using tools such as ActiveLED (UE) and LEDMaker (UE), and adds information to this created BLD file While converting, it is created by LED list (Excel macro) (UE).

  By the way, in the case of a three-primary color full color LED, when the luminance attenuation values of red, green and blue are uniformly made the same, the white balance may be lost, and for example, the white one may become yellow. For example, when the luminance of the LED is reduced, it is necessary to maximize the luminance attenuation value of blue among red, green and blue, and it is preferable to minimize the luminance attenuation value of red.

  Therefore, in the pachinko gaming machine 1 of the present embodiment, for example, even when the brightness of the LED is changed by the operation of the player or the like, white is set by setting the brightness attenuation value for each of 1024 ports. It is configured to be able to maintain balance as much as possible.

  Specifically, when the brightness of the LED is adjusted to one of strong, medium and weak by the operation of the player or the like, the voice / LED control circuit 220 refers to the attenuation table of FIG. Control the brightness of the LED based on the brightness attenuation value set for each of green and blue. The attenuation table is prepared, for example, for every 1024 ports (for each LED), so that attenuation values can be set for each port.

  For example, when the brightness of the LED is set to a high level by the operation of the player or the like, the sequencer 226b of the voice / LED control circuit 220 determines that the red brightness decay value 0, the green brightness decay value 5 and the blue brightness decay value 25 Is substituted into the above equation (1) to calculate the output value of the LED. Similarly, the sequencer 226b of the voice / LED control circuit 220 sets the red brightness decay value 50, the green brightness decay value 53, and the blue brightness decay value when the brightness of the LED is set by the player or the like. Substituting 63 into the above equation (1), when the brightness of the LED is set to be weak by the operation of the player etc., the red brightness decay value 80, the green brightness decay value 81 and the blue brightness falloff value Substituting the above equation (1), the LED output value is calculated. Then, the audio / LED control circuit 220 controls the light emission of the LED based on the output value of the LED calculated in this way.

  Thus, the voice / LED control circuit 220 calculates the output value of the LED based on the luminance attenuation value set corresponding to each of red, green and blue, and based on the calculated output value of the LED By controlling the light emission of the LED, for example, even if the brightness of the LED is changed by the operation of the player or the like, it is possible to maintain the white balance as much as possible.

[Item solenoid control process]
Next, the accessory solenoid control process will be described with reference to FIGS. 36, 37 and 67. FIG. FIG. 67 is a block diagram showing an example of the connection between the LED port and the LED and the solenoid.

  In the pachinko gaming machine 1 of the present embodiment, for example, the movement of the movable body (feature) provided in the game area is diversified, and the control of the movable body is complicated accordingly. Therefore, with regard to simple movements among various movements of the movable body, the control load of the movable body can be suppressed by operating the member that constitutes the character with the solenoid or providing a mechanism for locking the character with the solenoid. I am trying to When receiving the request for the motor operation, the feature driver sequentially outputs the contents of the motor operation data. The output of the motor driver and the determination of the end of the motor operation are performed by a timer interrupt process of 1 msec as shown in FIG. In the timer interrupt process, output determination and end determination (that is, determination of start and end) of the product motor are performed, and synchronous control of a plurality of motors is also performed.

  Further, as shown in FIG. 67, the voice / LED control circuit 220 of the pachinko gaming machine 1 according to the present embodiment has the frame side LEDs connected to the respective LED ports and the LEDs on the basis of the command from the host control circuit 210. The light emission of an LED on the board side (for example, an LED disposed on the game board 12 or a backlight of a liquid crystal display device used as the display device 13) is controlled via an LED driver. Then, among the LED ports (Port 0 to Port 23) controlled by the LED driver, the solenoid is connected to Port 6 and the LEDs are connected to the other ports.

  The voice / LED control circuit 220 receives the command from the host control circuit 210 and executes the light emission of the LED connected to each port of the frame side LED and the panel side LED via the LED driver, for example. By connecting the solenoid to the port 6, actuation of the solenoid can also be performed via the LED driver. As a result, even if the number of solenoids is increased due to diversification of the movement of the goods, it is possible to suppress the control load for operating the goods while maintaining the diversity of the movement of the goods. .

  By the way, when performing the above-mentioned operation of the solenoid via the LED driver as shown in FIG. 67, it is necessary to synchronously control the motor for operating the item and the operation of the above-mentioned solenoid. In addition, the operation of the prize is performed by an interruption process of 1 msec including synchronous control of a plurality of motors.

  Therefore, in the pachinko gaming machine 1 of the present embodiment, a control code is added to the item sequence table, and when it is desired to synchronously control the solenoid and a plurality of motors for operating the item, the control code has a value larger than 0. I am trying to set it. Then, in the processing of the main loop, the host control circuit 210 acquires the control code of the item being reproduced by the accessory device (see step S204 in FIG. 36), and the acquired control code has a value larger than 0. In this case, control of the LED port (for example, Port 6 to which the above-described solenoid is connected) corresponding to the control code is executed (see step S205 in FIG. 36). As a result, it becomes possible to execute synchronous control of the solenoid and a plurality of motors for operating the item.

  The control of the LED port corresponding to the control code is executed in the main loop so as not to affect the normal LED control executed in the 1 msec interrupt process.

  Further, in the pachinko gaming machine 1 of the present embodiment, since the solenoid is connected to a part of the LED ports (Port 0 to Port 23), for example, the brightness adjustment of the LED described above is performed by the operation of the player or the like. Also, although the voltage to the solenoid is also reset, the influence on the solenoid is considered to be small since the operation of the solenoid is only ON / OFF. In addition, in the case of executing the synchronization effect for synchronizing the light emission of the LED and the operation of the solenoid, it is also possible to easily execute the synchronization effect.

[Data loading process]
In the pachinko gaming machine 1 of the present embodiment, data loading processing is performed as one of various initialization processing (refer to step S201 in FIG. 36) executed when the power is turned on. Also, data loading processing may be performed during the game. These data loading processes are data transfer from ROM to RAM or buffer (for example, data transfer from sub main ROM 205 to SRAM 210b, data transfer from CGROM 206 to built-in VRAM 237, etc. (for example, all refer to FIG. 6), , And a process of loading data stored in the ROM into a RAM or a buffer (data loading process).

  In the above data loading process, if the amount of data to be transferred is large, it takes time to load, and the watchdog may be reset and the data loading process may end. When the watchdog is reset, it is difficult to determine whether the reset is caused simply because the data amount is large and time is required or because an error occurs at the time of data loading. In addition, when the data loading process is completed, the host control circuit 210 can not determine whether the loading is completed or the loading is not completed and continues waiting for the loading completion, so that the automatic recovery can not be performed. May be

  Therefore, in the present embodiment, when the time required for the data loading process exceeds the predetermined upper limit value, the data loading process is ended as an error and reloaded. Hereinafter, the data loading process will be described with reference to FIG. FIG. 68 is a flowchart showing an example of the data loading process executed by the host control circuit 210 as one of various initialization processes.

As shown in FIG. 68, the host control circuit 210 first sets the upper limit of the transfer time (step S651). The transfer time is the time required to load data from the ROM to the RAM. The upper limit of the transfer time varies depending on the amount of data to be transferred, but in the present embodiment, it is determined by the following equation (2).
Upper limit value of transfer time = (transfer data amount per unit time) × (transfer time standard + α) formula (2)
The transfer data amount per unit time in the above equation (2) and the transfer time standard may be preset based on the transferred data amount, or may be set based on the transferred data amount, for example, the host control circuit 210. It may be calculated by Here, α is a time for giving a margin for data loading.

  When the process of step S651 is completed, the host control circuit 210 proceeds to step S652 and starts data loading from the ROM to the RAM.

  After starting data loading (step S652), the host control circuit 210 determines whether data loading has been completed (step S653). If the data loading has not been completed (NO in step S653), the host control circuit 210 proceeds to step S654. On the other hand, if the data loading has been completed (YES in step S653), the host control circuit 210 ends the data loading process.

  In step S 654, host control circuit 210 determines whether the data transfer time has exceeded the upper limit value. If the data transfer time exceeds the upper limit value (YES in step S654), the watchdog timer is cleared every fixed time (step S655). On the other hand, if the data transfer time exceeds the upper limit (NO in step S654), the host control circuit 210 determines that an error has occurred and executes error processing. The error process executed here is a process of resetting the load data by watchdog reset (step S656) without clearing the watchdog timer (step S656). Thereafter, the host control circuit 210 returns to step S654. That is, when the data transfer time exceeds the upper limit value (NO in step S654), it is reloaded as an error process.

  As described above, when data loading processing is performed, the host control circuit 210 keeps clearing the watchdog timer at regular intervals while waiting for loading completion so that watchdog reset does not occur during normal loading. I have to. However, when the data loading process exceeds a predetermined upper limit value, the host control circuit 210 resets and reloads the load data. As a result, even if it takes time for the data loading process, it is automatically returned by reloading.

Sub random number processing
Next, sub-random number processing performed in the main loop by the host control circuit 210 will be described.

  The sub random number processing includes random number initialization processing executed as one of various initialization processing (see step S201 in FIG. 36) when the power is turned on, and random number periodic update processing executed periodically. And a random number acquisition process that is executed when the random number is used. The sub random number process is a process for a random number used for determining, for example, a presentation mode which does not affect the balls, unlike the lottery of the special symbol by the main CPU 71 (see, for example, FIG. 5). However, the sub random number processing described below may be applied to the random number processing executed by the main CPU 71. The above-described sub random number processing will be described with reference to FIGS. 69 to 72. FIG. 69 is a flowchart showing an example of random number initialization processing executed by the host control circuit 210 as one of various initialization processing. FIG. 70 is a flowchart of an example of the random number regular update process. 71 is a flowchart showing an example of (a) random number 1 acquisition processing, (b) a flowchart showing an example of random number 2 acquisition processing, (c) a flowchart showing an example of random number 3 acquisition processing, (d) random number 4 acquisition processing It is a flowchart which shows an example. FIG. 72 is a flow chart showing an example of random number acquisition processing executed when a random number is used.

  In the pachinko gaming machine 1 of this embodiment, four random numbers are used (random number 1 to random number 4), and the initialization process for these four random numbers is as shown in FIG. It is executed at the same timing.

  As shown in FIG. 69, in the random number initialization process, the host control circuit 210 first acquires an RTC time (minute / second) (step S 671), and then enters a loop for the number of random numbers.

In the loop for the number of random numbers, the host control circuit 210 first creates a random number SEED (step S672). The creation of the random number SEED in the random number initialization process is performed based on the following equation (3).
SEED (random number 1 to 4) = (RTC time (seconds) + (RTC time (minutes) x 60) + random number numbers (random numbers 1 to 4)) x prime number at the initial time (3)

  After creating the random number SEED in step S672, the host control circuit 210 saves the random number SEED created in step S672 in the random number backup, ie, the SRAM 210b (see, for example, FIG. 6) (step S673). The random number SEED backed up here is the random number SEED created this time, but the information backed up by the previous time may be deleted or may be stored continuously.

  When the host control circuit 210 executes the processing of step S672 and step S673 for the number of random numbers (four for random number 1 to random number 4 in this embodiment), the host control circuit 210 exits the loop for the number of random numbers and ends the random number initialization processing.

  Thus, in the random number initialization process, minutes and seconds of the RTC time are used. Therefore, the time for which the power is turned on is involved in the random number SEED at the time of initialization up to the unit of minutes and seconds.

  Next, random number regular update processing will be described with reference to FIG. The random number regular update process is a process for periodically updating the random numbers 1 to 4 even if none of the random numbers 1 to 4 is used in waiting for the bank flip end shown in FIG.

  As shown in FIG. 70, in the random number regular update process, the host control circuit 210 performs random number 1 acquisition process (step S681), random number 2 acquisition process (step S682), random number 3 acquisition process (step S683), and random number 4 acquisition. The process (step S684) is performed in this order. The random number regular update process is always executed while waiting for the bank flip end. In addition, even when waiting for bank flip completion does not occur due to any processing drop in the main loop, the host control circuit 210 performs the random number periodic update processing once in one frame.

  As shown in FIG. 71A, in the random number 1 acquisition process, the random number 1 is updated (step S685), that is, the random number 1 is updated after the random number 1 is acquired. Thereafter, the acquired random number 1 is stored in the random number 1 backup, that is, the SRAM 210b (see, for example, FIG. 6) (step S686). Similarly, as shown in FIG. 71 (b), the random number 2 acquisition process updates random number 2 (step S687) and backs up random number 2 (step S688). Similarly, as shown in FIG. 71C, the random number 3 acquisition process updates the random number 3 (step S689) and backs up the random number 3 (step S690). Similarly, as shown in FIG. 71 (d), the random number 4 acquisition process updates the random number 4 (step S691) and backs up the random number 4 (step S692). The random numbers backed up in step S686, step S688, step S690 and step S692 are the random numbers acquired this time, but the information backed up by the previous time may be deleted or may be stored continuously. .

  Although any one of the random numbers 1 to 4 is obtained from random numbers generated in the range of 0 to 32767, the range of the generated random numbers is not limited to this.

  As shown in FIG. 72, in the random number acquisition process executed when the random number is used, the host control circuit 210 first performs random number 3 acquisition process (step S693). The random number 3 acquisition process is a process of acquiring a random number to be used for determination of a random number to be used among random number 1, random number 2 and random number 4. When the random number 3 acquisition process of step S693 is executed, the host control circuit 210 proceeds to step S694.

  In step S694, the host control circuit 210 determines whether the remainder number (hereinafter simply referred to as the "remainder number") obtained by dividing the random number acquired in random number 3 acquisition processing in step S693 by 4 is 0 or 1 or not. Determine if If the remainder is 0 or 1 (YES in step S694), random number 1 acquisition processing is performed (step S695). On the other hand, if the remainder is neither 0 nor 1 (NO in step S694), the process moves to step S696.

  In step S696, the host control circuit 210 determines whether the number of remainders is two. If the number of remainders is 2 (YES in step S 696), random number 2 acquisition processing is performed (step S 697). On the other hand, if the remainder is not 2 (NO in step S 696), the process moves to step S 698.

  In step S698, the host control circuit 210 determines whether the remainder is three. If the number of remainders is 3 (YES in step S698), random number 4 acquisition processing is performed (step S699). On the other hand, if the number of remainders is not 3 (NO in step S698), this means that none of the numbers of remainders 0 to 3 is, so the process is repeated from step S693.

  The random number 1 acquisition process (step S695), the random number 2 acquisition process (step S697), the random number 3 acquisition process (step S693), and the random number 4 acquisition process (step S699) are all as shown in FIG. .

  As described above, in the random number acquisition process executed when the random number is used, although the selected random number among the random number 1, the random number 2 and the random number 4 is updated, the update is performed for the unselected random number. It does not happen.

  In the pachinko gaming machine 1 of this embodiment, random number initialization processing is performed when the power is turned on, and random number acquisition processing is performed for the selected random number when using random numbers, and bank flip end wait or bank flip end Even when waiting does not occur, random number regular update processing is performed.

The calculation formula at the time of updating the random number is as shown in the following formula (4).
This time updated value = (previous time updated value × prime number of each random number) + 1 ··· Formula (4)
Here, the return value of the random number acquisition processing is a value of 0 to 32767 in which right shift return is performed from 32 bits to 16 bits. That is, the current update value calculated based on the above equation (4) is represented by 32 bits, and the 32-bit current update value is right-shift-returned from 32 bits to 16 bits. Then, the 16th bit is masked, and the value (one of 0 to 32767) shown in 1 to 15 bits is determined as the update value this time.

  By performing the above-described sub random number processing, the acquired random numbers can be made random, and it is possible to suppress the occurrence of bias in the acquired random numbers. In particular, since the time during which the power is turned on is involved in the random number SEED during initialization up to the unit of minutes and seconds, it is possible to make the initial value different each time.

[Modification of sub random number processing]
Although the sub random number processing in the present embodiment has been described above, sub random number processing (modification) described below may be performed instead of or in combination with the above-described sub random number processing. Further, the sub random number processing (modification) described below may be applied to the random number processing executed by the main CPU 71. A modification of the sub random number processing will be described with reference to FIGS. 73 and 74. FIG. 73 shows a subcontrol main process (entire flow) executed by the host control circuit 210 for explaining a modification of the subrandom number process. However, FIG. 73 shows only the process necessary for the description, and the other processes are omitted. FIG. 74 is a flow chart showing an example of the reception interrupt process executed by the host control circuit 210.

  The host control circuit 210 first performs random number initialization processing which is executed as one of various initialization processing (see step S201 in FIG. 36) (step S701). In this random number initialization process, for example, a random number seed of a power of two (power multiplier) and a current random number seed number are prepared, and a predetermined initial value is set in the stack pointer.

  When the random number initialization process of step S701 is performed, the host control circuit 210 enters the main loop, performs the input process of the sub device (step S702), and then performs various request control processes (step S703). In the various request control processing (step S703), the request is output to various devices based on the request created in step S705 to be described later, which is one frame earlier.

When the sub device input process (step S702) and various request control processes (step S703) are performed, the host control circuit 210 performs a random number table creation process (step S704). In the random number table creating process of step S704, a new random number table is created by updating the random numbers registered in the random number table having the size of the power of 2 at the drawing timing. For obtaining the random numbers registered in the random number table, for example, among the random number seeds of the power of 2, a random number seed determined based on the current random number seed number is used. For example, when 2 ³ (8) random number seeds a to h are prepared, if the current random number seed number is 4, a random number seed of d is used.

The host control circuit 210 can create a random number table having a size of, for example, 2 ⁵ (32) in step S704, and 32 random numbers are registered in this random number table. When the random number is registered in the random number table, the host control circuit 210 updates the value of the random number seed. The update of the random number seed is performed by adding 1 after multiplying by the previous update value × the prime number, as in the above-mentioned equation (4). Note that the size of the random number table may be a power of 2 (pieces) in this modification, and 2 ⁵ (32) is adopted, but any power of 2 (pieces) may be adopted. good.

  As shown in FIG. 74, the random number seed used to create the random number table in step S704 is, for example, the value of the CPU counter by the CPU processor of the host control circuit 210 at the time of serial command reception (step S801). It is updated using (step S802). In the random number seed update process of step S802, the random number seed number is incremented, and the incremented random number seed number is used as the current random number seed number, thereby updating the random number seed used for creating the random number table.

  Referring back to FIG. 73, when the random number table creating process of step S704 is performed, the host control circuit 210 enters a packet reception loop.

  In the packet reception loop, the host control circuit 210 performs animation construction processing (step S705) for creating a request for animation for moving image effect, and performs random number acquisition processing when using random numbers (step S706). The request created in step S705 is output in the next frame after waiting in the buffer.

  The host control circuit 210 acquires a random number from the random number table generated in step S704 in the random number acquisition process of step S706. The random number acquired here is used for a lottery relating to the effect executed by the host control circuit 210 (for example, a lottery for determining an animation for moving image effect). When acquiring the random number from the random number table in step S706, the host control circuit 210 updates (increments) the reference position of the random number table. Note that the reference position of the random number table is only performed when the random number is acquired from the random number table, and is not performed in the random number table creating process of step S704.

  The host control circuit 210 repeats the processes of steps S705 and S706 for the packet reception. When the host control circuit 210 performs the processes of steps S705 and S706 for the packet reception, the host control circuit 210 exits the packet reception loop.

  When the packet reception loop is exited, the host control circuit 210 performs animation update processing (step S 707), and then waits for bank flip / bank flip completion (step S 708).

  The host control circuit 210 repeatedly performs the processing of steps S702 to S708 in the main loop of 33.3 msec cycle.

  According to the variation of the above-described sub-random number processing, even if random number acquisition opportunities occur multiple times in the packet reception loop, it is only necessary to change the reference position and acquire random numbers using the same random number table already created. Thus, it is possible to reduce the control load of the host control circuit 210 while imparting irregularity to the acquired random numbers.

[Other extension example]
The pachinko gaming machine 1 of the present embodiment can play a game using a game medium, and the present invention can be applied to all types of gaming machines in which benefits are provided based on the result of the game. That is, the game is played by the game medium being fired or inserted by the action of a physical player, and the main control circuit 100 itself is not only the form in which the game medium is paid out based on the result of the game. The game medium held by the player may be electromagnetically managed, and a game played by circulating the enclosed game balls or a game played without medals may be enabled. Further, the game medium management device which is attached to (connected to) the main control circuit 100 and manages game media may be used to electromagnetically manage game media held by the player.

  When managed by the gaming media management device connected to the main control circuit 100, the gaming media management device is a device having a ROM and RWM (or RAM) and provided in the gaming machine, which is an external gaming machine (not shown). It is connected to a two-way communication function through a medium handling device and a predetermined interface, and provides a gaming medium lending operation (that is, providing a necessary gaming medium for the player to perform a game medium insertion operation) Operation) or a payout operation of gaming media (ie, the player is required to pay out gaming media on a line, and acquire necessary gaming media on the line) when winning (combination of the above winnings) is achieved for a winning combination Operation), or an operation of electromagnetically recording a game medium to be provided for a game may be performed. In addition, the gaming media management device displays not only the management of the actual number of gaming media but also, for example, the number of gaming media held on the front of the pachinko gaming machine 1 based on the management result of the number of gaming media. A game medium number display device (not shown) may be provided, and the number of game media displayed on the owned game medium number display device may be managed. That is, the gaming media management device may be capable of recording and displaying the total number of gaming media that the player can use for gaming by an electromagnetic method.

  Also, in this case, the gaming media management device has the capability of allowing the player to freely transmit a signal indicating the number of gaming media recorded to the external gaming media handling device, and also playing a game. In addition to the case where the player directly operates, it has the ability not to reduce the number of recorded game media, and an external connection terminal board (not shown) is provided between it and an external game medium handling device. In such a case, it is desirable that the player can not transmit a signal indicating the number of game media recorded unless the external connection terminal board is used.

  In addition to the above, the gaming machine is provided with a lending operation means operable by the player, a return (settlement) operation means, and an external connection terminal board, and the gaming medium handling device is a slot for inserting valuable values such as bills, a recording medium (For example, an IC card) insertion slot, a non-contact communication antenna for receiving electronic money etc. from a portable terminal, etc., other operation means such as lending operation means, return operation means, game medium handling device side external connection terminal board It may be provided (all not shown).

  As the flow of the game at that time, for example, the player deposits a valuable value to the game medium handling device by any method, and subtracts a predetermined number of valuable values based on the operation of any one of the lending operation means described above. The game media corresponding to the valuable value subtracted from the game media handling device to the game media management device is increased. Then, the player plays a game, and when the game medium is required, the above operation is repeated. Thereafter, a predetermined number of game media are obtained as a result of the game, and the game media management device transmits the number of game media from the game media management device to the game media handling device by operating any return operation means when ending the game. The medium handling device ejects a recording medium recording the number of game media. The gaming media management device clears the number of gaming media stored by itself when transmitting the number of gaming media. The player brings the ejected recording medium to a prize counter or the like to exchange prizes, or moves the game platform to play a game based on the game medium recorded on another platform.

  In the above example, all game media are sent to the game media handling apparatus, but the game machine or game media handling apparatus sends only the number of game media desired by the player and the game media possessed by the player It may be divided and processed. In addition to discharging the recording medium, cash or cash equivalents may be discharged, or may be stored in a portable terminal or the like. Further, the gaming medium handling device may insert a member recording medium of the game arcade, and store the member recording medium in the member recording medium so as to be able to play again later.

  Further, in the gaming machine or game medium handling apparatus, it is possible to execute a lock operation for locking the data communication of the game medium or the valuable value to the game medium handling apparatus or the game medium management apparatus by operating predetermined operation means not shown. It is also good. At that time, the player may be recorded by setting information which can be known only to the player such as a one-time password or by an imaging means provided in the game medium handling apparatus.

  Also, although the above describes the case where the gaming media management device is applied to a pachinko gaming machine, the gaming media management device is similarly applied to pachislot machines, slot machines using gaming balls, and enclosed game machines as well. It is also possible to provide a game medium for the player to be managed.

  As described above, by providing the above-described gaming medium management device, it is possible to reduce the number of parts inside the gaming machine compared to when the gaming medium is physically provided for gaming, and the cost and manufacturing cost of the gaming machine As well as being able to reduce the number of players, it is also possible to prevent the player from coming into direct contact with the game media, the gaming environment is improved, noise can be reduced, and the power consumption of the gaming machine is reduced by reducing parts. It will also be. In addition, it is possible to prevent fraudulent acts through the insertion slot and the payout opening of the game media and the game media. That is, it is possible to provide a gaming machine capable of improving various environments surrounding the gaming machine.

  In addition, an enclosed type gaming machine configured to be playable without gaming media being discharged to the outside, and data relating to increase and decrease of gaming media accompanying consumption, lending and payout of gaming media to the gaming machine, and communication cable When the present invention is applied to a gaming system having a gaming medium management device connected via an optical signal to enable transmission and reception, the gaming system may be configured as follows.

  The outline of the enclosed game machine will be described below. In the enclosed type game machine, the launcher is located above the game area and shoots a game ball as a game medium from above the game area. When the player operates the handle, the payout control circuit causes the ball feed solenoid to be driven, and the ball feed rod pushes the waiting game ball toward the launch pad. Thereby, the game ball moves to the launch pad. In addition, a subtractive sensor is provided on the path from the standby position to the launch pad to detect gaming balls moving to the launch pad. When the gaming ball is detected by the subtraction sensor, the number of holding balls is decremented by one. As described above, since the game ball as the game medium is fired from above the game area, a so-called return ball (fall ball) can be avoided in the enclosed game machine. Then, the game balls discharged from the game area after rolling the game area are polished by the ball polishing apparatus. The game balls polished by the ball-shine device are transported upward by the transport device and guided to the launch device. The game balls are not discharged to the outside of the enclosed game machine, and a predetermined number (for example, 50) of game balls circulate in a series of paths in the game machine.

  In the enclosed type game machine, since the game balls are not discharged to the outside of the game machine, the upper plate and the lower plate for temporarily holding the game balls are not provided. In the enclosed type game machine, since the game ball is not discharged to the outside, the game ball is not actually present at the hand of the player, and the game ball does not actually increase or decrease by playing a game. In the enclosed type game machine, the player starts holding a game after obtaining a ball by lending from the game medium management device. Here, to obtain a holding ball means that the player obtains a game medium in data management. Then, the ball is consumed by the game ball being fired from the launcher, and the number of balls decreases. In addition, as the game balls pass through the respective winning openings and the like provided in the gaming area, the payout is performed by the number according to the conditions set according to the winning openings, and the number of balls increases. Furthermore, the number of balls held is also increased by lending from the gaming media management device. Note that "consumption, lending and payout of game media" indicates that balls are consumed, borrowed and dispensed. Also, "increase or decrease in game media" indicates that the number of balls increases or decreases due to consumption, lending, and payout. Further, "data relating to the increase or decrease of game media accompanying consumption, lending and payout of game media" is data relating to a decrease in balls due to the game ball being fired and an increase in balls due to lending and payout.

  An enclosed type game machine has a payout control circuit and a liquid crystal display device which is a touch panel type. The payout control circuit is connected to various sensors that detect the passage of the game balls such as each winning opening. The payout control circuit manages the number of balls held. For example, when the game ball passes each winning opening, the number of game balls paid out due to that is added to the number of balls held. In addition, when the game ball is fired, the number of balls is subtracted. The payout control circuit transmits data on the number of balls held to the gaming media management device according to the operation of the player. The liquid crystal display device described above is located at the top of the gaming machine, and receives requests for conversion from game value to balls held by a game medium management device (ball lending) and counting (returning) of balls. Then, these requests are transmitted to the payout control circuit via the gaming media management device, and the payout control circuit instructs the gaming media management device to transmit data on the current number of balls held. Here, “game value” refers to money, bills, prepaid media, tokens, electronic money, tickets, etc., and can be converted into balls by the game media management device. In the present embodiment, the gaming media management device is a so-called CR unit, and is configured to be able to receive bills, prepaid media, and the like. In addition, the balls possessed by counting can be used for prize exchange or the like in a game arcade or the like in which a gaming system is installed.

  In addition, the enclosed game machine has a backup power supply. As a result, even when the power is turned off at night or the like, data immediately before turning off can be held. In addition, with this backup power supply, for example, detection of the door frame opening by the door opening sensor may be continuously performed. In this way, it is also possible to prevent fraudulent acts at night. In this case, information such as the number of times the door frame is opened may be stored. Furthermore, when the power is turned on, information such as the number of times the door frame is opened may be output to a liquid crystal display device or the like of the gaming machine.

  The gaming medium management device has a gaming machine connection board. The gaming medium management device is configured to transmit and receive data (transmission signal) with the gaming machine via the gaming machine connection board. The data to be transmitted / received is the unique ID of the CPU provided in the main control circuit, the unique ID of the CPU provided in the payout control circuit, the game machine manufacturer code stored in the game machine, the manufacturer code of the security chip, the game Information such as the machine model code. Then, when one of the gaming machine and the gaming medium management device is the transmission source and the other is the transmission destination, when the transmission source transmits the transmission signal, the transmission destination having received the transmission signal is the same signal as the transmission signal. The confirmation signal is transmitted to the transmission source, and the transmission source compares the transmission signal with the confirmation signal to determine whether they are the same or not.

  As described above, by comparing the confirmation signal transmitted from the transmission destination with the transmission signal at the transmission source and determining whether they are the same, the signal transmitted from the transmission source is not falsified, It can be confirmed that it has been sent to the sender. In this way, it is possible to suppress fraudulent acts such as falsifying transmission / reception signals between the gaming machine and the gaming media management device.

  Further, in the gaming system, the transmission source has a modulation unit that modulates a signal, transmits the signal modulated by the modulation unit as the transmission signal, and the transmission destination is the signal modulated by the modulation unit. It is possible to have a demodulation unit that demodulates.

  Thus, even if the transmission / reception signal between the gaming machine and the gaming media management device is read, it is difficult to decipher this signal, and the transmission / reception signal between the gaming machine and the gaming media management device is It is possible to suppress fraudulent acts such as falsification.

  Further, in the gaming system, when the transmission destination receives the transmission signal from the transmission source, the transmission destination receives an approval signal indicating that the transmission signal has been received, separately from the confirmation signal. It may be transmitted to the transmission source.

  Thus, by comparing the transmission signal with the confirmation signal, not only confirmation that the transmission and reception of the normal signal has been performed but also confirmation that the transmission and reception of the normal signal has been performed based on the approval signal It is possible to further strengthen the control of fraud since it is possible.

[Supplementary note]
[First game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when the gaming ball is won in the starting opening, and a big hit game is played when the result of the lottery is a big hit.

  As this type of gaming machine, a long press effect to change the execution mode of the specific game effect is performed on the operation means on the condition that the player performs a predetermined long press operation, and the shorting is shorter than the long press operation. There is known a gaming machine capable of executing a continuous hitting effect on the condition that a continuous hitting operation of performing a pressing operation a plurality of times is performed (see, for example, JP-A-2015-065977). In the gaming machine disclosed in JP-A-2015-065977, when the long press operation is performed within the long press operation acceptance effective period for determining whether the long press operation is performed, the long press effect is executed.

(First issue)
As in the gaming machine described in JP-A-2015-065977, if it is judged and controlled whether long press operation or continuous hit effect is performed to the operation means, the control load becomes large, which is not preferable. .

  However, in recent years, a game machine capable of enhancing interest by performing effects capable of giving a further visual impact is desired.

  In order to solve the said 1st subject, the 1st game machine of the following structures is provided.

The first gaming machine is
A gaming machine capable of executing main processing (for example, processing of a main loop) in which various processing (for example, various request control processing) is performed every predetermined time (for example, 33.3 msec).
Predetermined operation means (for example, main button);
An interrupt process is performed every time (for example, 1 msec) shorter than the predetermined time, and control capable of generating input information in the main process based on the input state of the operation means detected by the interrupt process Means (eg, host control circuit 210);
Equipped with
The control means
As the input information, after the input state of the operating means is switched from the OFF state to the ON state, after the input state of the operating means is switched from the OFF state to the ON state as the input information After the ON state is determined to have continued (for example, 10 frames), the ON state is generated periodically as long as the ON state continues for a time (for example, 4 frames) shorter than the predetermined time (for example, 4 frames). Input information generation means (for example, host control circuit 210 for executing the process of step S309) for generating information (for example, ON edge information with repeat function) that can be determined;
Device control means (for example, host control circuit 210) capable of executing control of a predetermined device based on the information (for example, the ON edge information with repeat function) generated by the input information generation means It features.

  According to the first gaming machine, after the input state of the operation means changes from the OFF state to the ON state based on the input state of the operation means (for example, the input information of the sub device), the ON state continues for a fixed time The sub device is generated by periodically generating information that can be determined to be generated as long as the input state of the operation means continues to be ON in a shorter time than a predetermined time after it is determined that It is possible to easily perform control such as control of continuous hit production and control of long press production.

  Further, according to the first gaming machine, it is possible to execute control according to the mode of the operation means while reducing the control load.

[Second game machine, third game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery.

  As this type of game machine, a game machine provided with a display device which emits light by backlight is disclosed (see, for example, JP-A-2016-159026).

(Second issue)
However, for example, when the luminance of the light emitting means of the backlight is unstable, the display of the effect image on the display device may be unstable, which is not preferable.

  In order to solve the said 2nd subject, the 2nd game machine and the 3rd game machine of the following composition are provided.

The second gaming machine is
Light emitting means (eg, backlight) capable of emitting light in a predetermined mode;
Data storage means (for example, data area of FIFO) for storing drive data (for example, luminance data) corresponding to the light emission mode emitted by the light emission means in a predetermined area;
A light emission drive unit (for example, an LSI) which outputs a control signal based on the drive data stored in the data storage unit to the light emission unit;
Data setting means (for example, host control circuit 210 for executing the process of step S346) for setting the drive data in a predetermined area of the data storage means;
Equipped with
The data setting means
The drive data set in the predetermined area of the data storage means is configured to set the new drive data when the number of drive data that can be set in the predetermined area becomes the reference data number. I assume.

  According to the second gaming machine, new drive data is set when the number of drive data that can be stored in the predetermined area becomes equal to the number of drive data that can be stored in the predetermined area. A control signal (for example, a signal corresponding to PWM continuously output from the serial data output terminal of SPI) output by the drive unit can be output, and the light emission unit emits light stably without passing through the driver. It becomes possible.

  The above “reference data number” corresponds to 1 to 64 if the number of data that can be set in a predetermined area (for example, the data area of FIFO) of the data storage means is, for example, 64 or less. In view of the fact that it is necessary to prevent the number of data set in a predetermined area of the storage unit from becoming zero, it is preferable that the number is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more luminance data can be set. Thus, when there are two or more luminance data that can be set in the FIFO data area, for example, if the luminance data set in the FIFO data area falls below the first number (for example, two), the second number For example, one piece of luminance data may be replenished.

The third gaming machine is
Light emitting means (eg, backlight) capable of emitting light in a predetermined mode;
Data storage means (for example, FIFO data area) for storing drive data (for example, luminance data) corresponding to the light emission mode emitted by the light emission means in a predetermined area (for example, FIFO data area);
A light emission drive unit (for example, an LSI) which outputs a control signal based on the drive data stored in a predetermined area of the data storage unit to the light emission unit;
Data setting means (for example, host control circuit 210 for executing the process of step S346) for setting the drive data in a predetermined area of the data storage means;
Clocking means capable of measuring an elapsed time after the drive data is set in a predetermined area of the data storage means (for example, host control circuit 210 which executes the process of step S356);
Equipped with
The data setting means
The drive data can be set in a predetermined area of the data storage unit (the processing of step S354 can be executed) based on the fact that the time counted by the clock unit has exceeded a predetermined time or more. I assume.

  According to the third gaming machine, the drive data is stored in the predetermined area of the data storage unit based on the lapse of a predetermined time or more after the drive data is set in the predetermined area of the data storage unit. It is set. For example, if time is required for some processing, the drive data set in the predetermined area of the data storage means disappears until the drive data is set to the predetermined area of the data storage means There is a risk of In this respect, according to this gaming machine, even if it is not the timing to set the drive data in the predetermined area of the data storage means, the drive data is determined based on the passage of the predetermined time or more. Because the drive data set in the predetermined data area can be prevented from becoming empty. Therefore, it is possible to output a control signal (for example, a signal corresponding to PWM continuously output from the serial data output terminal of SPI) output by the light emission drive means, and the light emission means can be stabilized without passing through the driver. It becomes possible to make it emit light.

  Further, according to the second gaming machine and the third gaming machine, it becomes possible to suppress the light emission of the light emitting means from becoming unstable.

[Fourth game machine, fifth game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and a rendering image is displayed on a liquid crystal display or the like based on the result of the lottery.

  As this type of game machine, there is known a game machine to be used for effect and decoration by causing a light emitting device composed of light emitters such as a plurality of LEDs provided on the front side to emit light in a predetermined mode. . Further, a gaming machine is disclosed that allows a player or the like to adjust the luminance of these light emitting devices within a preset range (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(Third task)
By the way, in recent years, the effects have become bright including the light emitting devices including light emitting bodies such as a plurality of LEDs provided on the front side. Therefore, some players may feel stress when the luminance of the light emitting device is high. If the player or the like can operate the luminance of the light emitting device, the player can adjust the luminance to a desired luminance, but that may not be sufficient.

  In order to solve the said 3rd subject, the 4th game machine of the following structures and a 5th game machine are provided.

(1) The fourth game machine is
First light emitting means (for example, backlight) capable of emitting light in a predetermined mode;
Operation means capable of changing the luminance of the first light emitting means to any one of a plurality of levels (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13);
First light emission control means capable of changing the luminance of the first light emitting means to any one of a plurality of stages based on the operation of the operation means (for example, a host control circuit that executes the processing of step S384 210) and
Second light emitting means (for example, panel side LED or frame side LED) provided separately from the first light emitting means;
Second light emission control means capable of changing the luminance of the second light emission means (for example, the host control circuit 210 which executes the process of step S385);
Equipped with
The second light emission control means
The luminance of the second light emitting means is changed to any one of the plurality of stages at a timing different from the timing when the luminance of the first light emitting means is changed based on the operation of the operation means. It is characterized in that it is configured as possible.

  According to the fourth gaming machine of the above (1), when the operation means capable of changing the luminance of the first light emitting means is operated, the timing different from the timing at which the luminance of the first light emitting means is changed Since the brightness of the second light emitting means is also changed to any of a plurality of levels while the brightness of the second light emitting means is also changed, it is possible to further increase the degree of freedom for changing the brightness by the player. It becomes possible.

(2) In the fourth gaming machine according to (1),
Data storage means (for example, data area of FIFO) for storing drive data corresponding to the light emission mode emitted by the first light emission means in a predetermined area;
A light emission drive unit (for example, an LSI) which outputs a control signal based on the drive data stored in the data storage unit to the first light emission unit;
Data setting means (for example, host control circuit 210 for executing the process of step S346) for setting the drive data in a predetermined area of the data storage means;
Equipped with
The data setting means
The drive data set in the predetermined area of the data storage means sets the new drive data when the number of drive data storable in the predetermined area reaches a reference data number.
When the operation means is operated, the new drive data is configured to set the drive data after the change of the luminance.

  According to the fourth gaming machine of (2), when the number of drive data which can be stored in the predetermined area becomes equal to the number of reference data, the new drive data is set. Therefore, it is possible to output a control signal (for example, a signal corresponding to PWM continuously output from the serial data output terminal of SPI) output by the light emission drive means, and the light emission means is stabilized without passing through the driver. It becomes possible to emit light. Moreover, when the brightness is changed, the drive data after the change is set as new drive data, so that it is possible to cause the first light emitting means to emit light stably according to the set brightness.

  The above “reference data number” corresponds to 1 to 64 if the number of data that can be set in a predetermined area (for example, the data area of FIFO) of the data storage means is, for example, 64 or less. In view of the fact that it is necessary to prevent the number of data set in a predetermined area of the storage unit from becoming zero, it is preferable that the number is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more luminance data can be set. Thus, when there are two or more luminance data that can be set in the FIFO data area, for example, if the luminance data set in the FIFO data area falls below the first number (for example, two), the second number For example, one piece of luminance data may be replenished.

(1) The fifth gaming machine is
Lottery means (for example, the main CPU 71 that executes the process of step S45) that performs a lottery based on the establishment of a predetermined condition;
Display means (for example, a liquid crystal display device used as the display device 13) on which a predetermined effect image is displayed;
Variation display control means (for example, display control circuit 230) for performing variation display of symbols (for example, identification symbols for effects) in the display means based on the result of the lottery;
First light emitting means (for example, backlight) capable of emitting light in a predetermined mode;
Operation means capable of changing the luminance of the first light emitting means to any one of a plurality of levels (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13);
First light emission control means capable of changing the luminance of the first light emitting means to any one of a plurality of stages based on the operation of the operation means (for example, host control for executing the process of step S394) Circuit 210),
Second light emitting means (for example, panel side LED or frame side LED) provided separately from the first light emitting means;
Second light emission control means (host control circuit 210 for executing the process of step S392) for controlling the light emission mode of the second light emission means based on a predetermined request;
Equipped with
The second light emission control means
The luminance of the second light emitting means is changed after the luminance of the first light emitting means is changed and after the variation display of the symbol is finished based on the operation of the operation means. (For example, the processing of step S 399 is performed).

  According to the fifth gaming machine of the above (1), when the operation means is operated, the luminance of the first light emitting means can be changed. Further, the luminance of the second light emitting means is changed after the luminance of the first light emitting means is changed and after the fluctuation display of the symbol is completed. Here, since the light emission mode of the second light emitting means is controlled based on a predetermined request, the control load is minimized by changing the luminance of the second light emitting means after the variation display of the symbol is finished. It is possible to change the luminances of the first light emitting means and the second light emitting means while limiting as much as possible.

(2) In the fifth gaming machine according to (1),
Data storage means (for example, data area of FIFO) for storing drive data corresponding to the light emission mode emitted by the first light emission means in a predetermined area;
A light emission drive unit (for example, an LSI) which outputs a control signal based on the drive data stored in the data storage unit to the first light emission unit;
Data setting means (for example, host control circuit 210 for executing the process of step S346) for setting the drive data in a predetermined area of the data storage means;
Equipped with
The data setting means
The drive data set in the predetermined area of the data storage means sets the new drive data when the number of drive data storable in the predetermined area reaches a reference data number.
When the operation means is operated, the new drive data is configured to set the drive data after the change of the luminance.

  According to the fourth gaming machine of (2), when the number of drive data which can be stored in the predetermined area becomes equal to the number of reference data, the new drive data is set. Therefore, it is possible to output a control signal (for example, a signal corresponding to PWM continuously output from the serial data output terminal of SPI) output by the light emission drive means, and the light emission means is stabilized without passing through the driver. It becomes possible to emit light. Moreover, when the brightness is changed, the drive data after the change is set as new drive data, so that it is possible to cause the first light emitting means to emit light stably according to the set brightness.

  The above “reference data number” corresponds to 1 to 64 if the number of data that can be set in a predetermined area (for example, the data area of FIFO) of the data storage means is, for example, 64 or less. In view of the fact that it is necessary to prevent the number of data set in a predetermined area of the storage unit from becoming zero, it is preferable that the number is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more luminance data can be set. Thus, when there are two or more luminance data that can be set in the FIFO data area, for example, if the luminance data set in the FIFO data area falls below the first number (for example, two), the second number For example, one piece of luminance data may be replenished.

  Further, according to the fourth gaming machine and the fifth gaming machine, it is possible to provide a gaming machine capable of more suitably adjusting the luminance of the light emitting device.

[Sixth game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and a rendering image is displayed on a liquid crystal display or the like based on the result of the lottery.

  As this type of game machine, there is known a game machine to be used for effect and decoration by causing a light emitting device composed of light emitters such as a plurality of LEDs provided on the front side to emit light in a predetermined mode. . Further, a gaming machine is disclosed that allows a player or the like to adjust the luminance of these light emitting devices within a preset range (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(Fourth issue)
By the way, in recent years, the effects have become bright including the light emitting devices including light emitting bodies such as a plurality of LEDs provided on the front side. Therefore, if the intensity of light received from the light emitting device is high, some players may feel stress.

  In order to solve the fourth problem, a sixth gaming machine having the following configuration is provided.

(1) The sixth gaming machine is
The gaming machine according to the present invention is
First light emitting means (for example, backlight) capable of emitting light in a predetermined mode;
Operation means capable of changing the luminance of the first light emitting means to any one of a plurality of levels (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13);
First light emission control means capable of changing the luminance of the first light emitting means to any one of a plurality of stages based on the operation of the operation means (for example, host control circuit for executing the process of step S394) 210) and
Second light emitting means (for example, panel side LED or frame side LED) provided separately from the first light emitting means;
Second light emission control means capable of changing the light emission mode of the second light emission means (for example, a host control circuit 210 which executes the process of step S406);
Equipped with
The second light emission control means
Based on the operation of the operation means, at a timing different from the timing when the brightness of the first light emission means is changed, the aspect of the light emission effect performed by the second light emission means is limited and executed It is characterized in that it is configured as possible.

  According to the sixth gaming machine of the above (1), when the operation means capable of changing the luminance of the first light emitting means is operated, the aspect of the light emission effect executed by the second light emitting means is limited. . Therefore, it is possible to suppress the intensity of light received from the second light emitting means by simple processing.

(2) In the sixth gaming machine according to (1),
Data storage means (for example, data area of FIFO) for storing drive data corresponding to the light emission mode emitted by the first light emission means in a predetermined area;
A light emission drive unit (for example, an LSI) which outputs a control signal based on the drive data stored in the data storage unit to the first light emission unit;
Data setting means (for example, host control circuit 210 for executing the process of step S346) for setting the drive data in a predetermined area of the data storage means;
Equipped with
The data setting means
The drive data set in the predetermined area of the data storage means sets the new drive data when the number of drive data storable in the predetermined area reaches a reference data number.
When the operation means is operated, the new drive data is configured to set the drive data after the change of the luminance.

  According to the fifth gaming machine of the above (2), when the number of drive data which can be stored in the predetermined area becomes equal to the reference data number, the new drive data is set. Therefore, it is possible to output a control signal (for example, a signal corresponding to PWM continuously output from the serial data output terminal of SPI) output by the light emission drive means, and the light emission means is stabilized without passing through the driver. It becomes possible to emit light. Moreover, when the brightness is changed, the drive data after the change is set as new drive data, so that it is possible to cause the first light emitting means to emit light stably according to the set brightness.

  The above “reference data number” corresponds to 1 to 64 if the number of data that can be set in a predetermined area (for example, the data area of FIFO) of the data storage means is, for example, 64 or less. In view of the fact that it is necessary to prevent the number of data set in a predetermined area of the storage unit from becoming zero, it is preferable that the number is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, as long as at least two or more luminance data can be set. Thus, when there are two or more luminance data that can be set in the FIFO data area, for example, if the luminance data set in the FIFO data area falls below the first number (for example, two), the second number For example, one piece of luminance data may be replenished.

  Thus, according to the sixth gaming machine, it is possible to provide a gaming machine capable of suitably adjusting the intensity of light received from the light-emitting device by a player or the like.

[Seventh game machine]
BACKGROUND Conventionally, in a gaming machine such as a pachinko machine, a gaming machine is known in which an effect depending on an RTC (Real Time Clock) is performed.

  In this type of gaming machine, the RTC is determined to be abnormal when the power is turned on, etc., and if there is an abnormality, the date and time are notified, and if an abnormality in the RTC is recognized, the gaming machine can quickly cope with this. It is known (for example, refer to JP-A-2017-51853 (for example, paragraph [0094])).

(Fifth issue)
According to the gaming machine described in JP-A-2017-51853, if there is an abnormality in the RTC, the notification of the date and time is performed, but there is a possibility that it can be dealt with quickly. There is a risk that it will not be possible to

  In order to solve the 5th subject of the above, the 7th game machine of the following composition is provided.

The seventh gaming machine is
A real time clock (eg, RTC) capable of outputting time information;
Time information management means capable of acquiring time information from the real-time clock and updating the acquired time to current time information (for example, the host control circuit 210 that executes the processing of step S413);
An effect execution unit (for example, a host control circuit 210) capable of executing a specific effect (for example, an RTC effect) based on that the current time information is a specific time information (for example, a specified time);
Abnormality determination means (for example, a host control circuit 210 that executes the process of step S414) that determines an abnormality of the real-time clock;
Equipped with
The time information management means
If it is determined that the real time clock is abnormal, the time information management means maintains the previous time information acquired last time as current time information (for example, step S415), and the real time clock is determined to be normal. Then, the previous time information can be updated to the current time information (for example, the process of step S416).
The effect executing means is
The specific effect is executed on the condition that the current time information is the specific time information (YES in step S417) and the previous time information does not match the current time information (YES in step S418) (step S419). It is characterized in that it is configured.

  According to the seventh gaming machine, even if the RTC is abnormal, it is possible to preferably perform an effect depending on the RTC.

[The eighth game machine, the ninth game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on a display device or the like based on the result of the lottery. If the result of the lottery is a big hit, a big hit game is started.

  As this type of gaming machine, there is known a gaming machine in which compressed image data is decoded, the decoded image data is appropriately converted, stored in a frame buffer, and output to a display device. (For example, Unexamined-Japanese-Patent No. 2014-87402 (for example, refer to stage [0100])).

(The sixth task)
In recent years, variations of the effect image displayed on the display device are increasing, and control of the effect image tends to be complicated. In such a case, it is desirable to efficiently perform control of the effect image.

  In order to solve the sixth problem, an eighth gaming machine and a ninth gaming machine having the following configuration are provided.

The eighth gaming machine is
A gaming machine capable of executing processing (for example, bank flipping) for switching functions between a drawing output destination buffer having a drawing function and a frame buffer having a display function,
Registration means capable of registering image information (for example, composition) related to a rendering image displayed on a predetermined display means in the drawing output destination buffer (for example, display control circuit 230 capable of executing step S449 or step S458) When,
After the drawing output destination buffer is switched to the frame buffer (for example, after the process of step S446 is performed), the effect image is displayed on the predetermined display unit based on the image information registered by the registration unit. Effect image display control means (for example, display control circuit 230) for controlling to be displayed;
Equipped with
The registration means is
When the image information registered in the frame buffer switched from the drawing output destination buffer includes image information for pausing the image (for example, when it is determined YES in step S447), First registration means (for example, a display control circuit 230 which executes the process of step S449) for registering image information in the drawing output destination buffer;
Even if there is no image information registered in the drawing output destination buffer (for example, even if it is determined NO in step S444), the effect image displayed on the predetermined display means is registered in the frame buffer A second registration unit (for example, step S458 can be executed) for registering the image information in the drawing output destination buffer when the upper limit of the image information being processed is reached (for example, when it is determined YES in step S450) Display control circuit 230).

  According to the eighth gaming machine, even if the image information is registered while the image information is registered under the condition that the image information is not registered, the image information specific to the registered image information Since the image information is registered when the image information is included, it is possible to efficiently perform the control related to the effect image.

The ninth gaming machine is
A plurality of display means (for example, displays) capable of reproducing a predetermined effect image;
Display control means (for example, display control circuit 230) capable of controlling image information related to effect images reproduced by the plurality of display means;
Equipped with
The display control means
Layer number determination means (for example, a display control circuit 230 which executes the processing of step S441) which determines the appropriateness of the number of layers relating to the image information reproduced simultaneously in the display means;
When the number of layers is appropriate (for example, when it is determined as YES in step S441), the number of display means determination means (for example, step for determining the appropriateness of the number of display means used for reproducing the effect image) A display control circuit 230) that executes the processing of S442;
When the number of display means used for reproducing the effect image is appropriate (for example, when it is determined YES in step S442), display means for determining the presence of the display means to be the registration object of the image information is present A determination unit (for example, a display control circuit 230 that executes the process of step S443);
Image information registration means (e.g., step S449) for registering image information to be reproduced on the display means when there is a display means for registering the image information (e.g., when it is determined YES in step S443) And a display control circuit 230) that executes the processing of step S458.
After the image information to be reproduced by one display unit of the plurality of display units is registered by the image information registration unit, the image information is registered in another display unit different from the one display unit. It is characterized in that the determination by the display means number determination means and the determination by the display means presence determination means are performed (the process of step S459 is performed and then the process of returning to step S442 is performed).

  According to the ninth gaming machine, when there are a plurality of display means and the number of layers concerning the image information is appropriate, after the image information related to the effect image displayed on one display means is registered, Since the image information related to the effect image displayed on the other display means different from the display means is registered, it is possible to efficiently register the image information determined that the number of layers is appropriate.

  Thus, according to the eighth gaming machine and the ninth gaming machine, it is possible to provide a gaming machine capable of efficiently performing control relating to the effect image.

[10th game machine, 11th game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery. In addition to such effect images, sound effects are also output.

  As this type of gaming machine, it is determined whether or not the timing for determining an abnormality of the digital amplifier has been reached, for example, from the input port Pi2 when the operation determination timing determined at time intervals of several seconds has been reached. There is known a gaming machine which acquires an abnormality notification signal ERR and determines whether the digital amplifier is at an abnormal level (see, for example, JP-A-2016-209723 (for example, paragraphs [0178] and [0179])).

(The seventh problem)
In recent years, with the increase of variations of effect images displayed on a liquid crystal display or the like, the contents of effects are advanced and the interest is improved. However, along with the sophistication of the contents of the presentation, the contents of the presentation of the game sound also tend to be advanced, and in order to output the normal game sound, it is necessary to appropriately perform the determination processing of the amplification device for amplifying the game sound. There is.

  In order to solve the seventh problem, a tenth gaming machine and an eleventh gaming machine having the following configuration are provided.

(1) The tenth game machine is
A gaming machine capable of executing predetermined processing (for example, main processing and interrupt processing) each time a predetermined time has elapsed,
An output unit capable of outputting a game sound (for example, the speaker 11);
Amplification means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
Abnormality determination means (for example, a host control circuit 210 that executes processing of step S503, step S511, step S515, etc.) that performs abnormality determination processing of whether the amplifier is normal or not;
Equipped with
The abnormality determination means
The abnormality determination process can be divided into multiple abnormality determination processes (for example, processes of step S503, step S511, step S515, etc.) and can be executed.
Performing part of the abnormality determination process (for example, step S503, step S511, and step S515) divided into the plurality of times in one predetermined process (for example, one frame) performed within the predetermined time, A part or all of the remaining abnormality determination processing can be performed in the predetermined processing after the next time.

  According to the tenth gaming machine of the above (1), part of abnormality determination processing of the amplification means (for example, the normal amplifier and the bass amplifier) is performed over a plurality of frames within the predetermined processing (for example, one frame) As it is performed, it becomes possible to execute all the abnormality determination processing of each amplification means over a plurality of frames.

(2) Another example of the tenth gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing and interrupt processing) each time a predetermined time has elapsed,
An output unit capable of outputting a game sound (for example, the speaker 11);
Amplification means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
Setting information confirmation unit (for example, host control circuit 210 that executes processing of steps S506 to S507, steps S522 to S523, etc.) for confirming the setting information of the amplification unit;
Equipped with
The setting information confirmation unit
The confirmation process can be divided into a plurality of confirmation processes and can be executed.
A part of the confirmation process (for example, the host control circuit 210 that executes the processes of steps S506 to S507 and steps S522 to S523) divided into a plurality of times in one predetermined process performed within the predetermined time Is executed, and part or all of the remaining confirmation processing can be executed in the predetermined processing from the next time onward.

  According to another example of the tenth gaming machine of (2), part of the confirmation processing of the setting information of the amplification means (for example, the normal amplifier and the bass amplifier) within the predetermined processing (for example, one frame) Since each step is performed over a plurality of frames, it is possible to execute the entire confirmation processing of the setting information of each amplification means over a plurality of frames.

(1) The eleventh gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing and interrupt processing) each time a predetermined time has elapsed,
An output unit capable of outputting a game sound (for example, the speaker 11);
Amplification means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
The abnormality determination processing as to whether or not the amplification means is normal can be divided into a plurality of abnormality determination processing (for example, processing of check status = 0, 2 and 3) and can be executed. Abnormality determination means (for example, a host control circuit 210 that executes the processing of step S503, step S511, step S515, etc.) that performs the determination processing over a plurality of times of the predetermined processing;
Progress management means (for example, a host control circuit 210 for managing a check status) that manages the progress of the abnormality determination process;
Equipped with
The progress management means is
It is possible to determine whether or not one of the plurality of abnormality determination processes (for example, processes of check status = 0, 2 and 3) is completed in one predetermined process,
The abnormality determination means
When the one abnormality determination process (for example, the process of the check status 0) is completed in the one predetermined process, another process different from the one abnormality determination process in the predetermined process of the next and subsequent steps (for example, the subsequent frame). When abnormality determination processing (for example, processing of check status 2) is executed and the one abnormality determination processing (for example, processing of check status 0) is not completed in the one predetermined processing, in predetermined processing after the next time The one abnormality determination process (for example, the process of the check status 0) can be performed again.

  According to the eleventh gaming machine of the above (1), part of abnormality determination processing of the amplification means (for example, the normal amplifier and the bass amplifier) is performed over a plurality of frames within a predetermined process (for example, one frame) As it is performed, it becomes possible to execute all the abnormality determination processing of each amplification means over a plurality of frames. In addition, when one abnormality determination process is not completed in one predetermined process (for example, main process or interrupt process of one frame), the one abnormality determination in the predetermined process after the next (for example, subsequent frame) Since the process is executed again, any abnormality determination process is executed until completion.

(2) Another example of the eleventh gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing and interrupt processing) each time a predetermined time has elapsed,
An output unit capable of outputting a game sound (for example, the speaker 11);
Amplification means (for example, digital audio power amplifier 262) capable of amplifying the game sound output from the output means;
The confirmation process of the setting information about the amplification means can be divided into a plurality of confirmation processes (for example, processes of check status = 1, 5) and can be executed, and the plurality of confirmation processes can be performed a plurality of times of the predetermined process Setting information confirmation means (for example, the host control circuit 210 that executes the processing of steps S506 to S507, steps S522 to S523, etc.)
Progress management means (for example, a host control circuit 210 for managing a check status) for managing the progress of the confirmation process of the setting information;
Equipped with
The progress management means is
It is possible to determine whether or not one confirmation process of the plurality of confirmation processes (for example, the processes of check status = 1 and 5) is completed in one predetermined process,
The setting information confirmation unit
When the one confirmation process (for example, the process of the check status = 1) is completed in the one predetermined process, another confirmation process (for example, the check status = different from the one confirmation process in the next and subsequent predetermined processes) When step 5) is executed and the one confirmation process is not completed in the one predetermined process, the one confirmation process is configured to be executable again in the next and subsequent predetermined processes. .

  According to another example of the eleventh gaming machine of (2), part of the confirmation processing of the setting information of the amplification means (for example, the normal amplifier and the bass amplifier) within the predetermined processing (for example, one frame) Since each step is performed over a plurality of frames, it is possible to execute the entire confirmation processing of the setting information of each amplification means over a plurality of frames. In addition, when one confirmation process is not completed in one predetermined process (for example, main process or interrupt process of one frame), the one confirmation process is performed in the predetermined process of the next time (for example, the next frame and subsequent ones). Since it is executed again, any confirmation process will be executed until completion.

  Thus, according to the tenth gaming machine and the eleventh gaming machine, it is possible to provide a gaming machine capable of appropriately performing the determination process of the amplification device.

[12th game machine, 13th game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery. In addition to such effect images, game sounds are also output from the speakers.

  As this type of gaming machine, a gaming machine is disclosed that outputs a voice data such as a game sound from a voice memory by causing a simple access controller to function by writing an SAC number into a voice control register (e.g. See 2017-79971).

(The eighth task)
In recent years, the variation of game sounds has also increased along with the increase of variations of effect images. However, for example, when a plurality of game sounds overlap, there is a possibility that the effect of such game sounds may be halved.

  In order to solve the eighth problem, a twelfth gaming machine and a thirteenth gaming machine having the following configuration are provided.

(1) The twelfth game machine is
Setting means (for example, host control circuit 210) capable of assigning and setting sound information (for example, SAC number) related to game sound data to a channel;
Sound output means (for example, voice / LED control circuit) capable of outputting game sound based on the sound information assigned to the channel;
Equipped with
The setting means is
When sound information is assigned to one channel, a plurality of pieces of sound information are set to the one channel (for example, when it is determined YES in the process of step S 542),
When the plurality of pieces of sound information is a specific piece of sound information (for example, chain reproduction of SHOT reproduction and LOOP reproduction), one of the plurality of pieces of sound information (for example, loop reproduction) is stored for at least a predetermined time (E.g., one frame) or a first setting unit configured to delay and set (e.g., a host control circuit 210 that executes the process of step S544);
Under the condition that the plurality of sound information is non-specific sound information different from the specific sound information (for example, NO in the process of step S543), without delaying for a predetermined time or more For example, a second setting unit (for example, a host control circuit 210 that executes the processing of step S546 or step S547) for setting the plurality of pieces of sound information in the frame is characterized.

  According to the twelfth gaming machine of the above (1), when a plurality of pieces of sound information are set in one channel, when the plurality of pieces of sound information are specific sound information, any one of the pieces of sound information is Since the delay is set, it is possible to enjoy the sound effect by delaying (for example, the sound effect by muffling). On the other hand, if the plurality of pieces of sound information are non-specific sound information, the plurality of pieces of sound information are set without being delayed, so that the processing can be performed quickly. That is, by not delaying or delaying according to the situation, it is possible to secure the promptness of processing while taking advantage of the game sound effect due to the delay.

(2) In the twelfth gaming machine according to (1),
The specific sound information is
At least the first sound information (for example, SHOT reproduction) reproduced only once, and the second sound information (LOOP reproduction) reproduced for a plurality of times,
The first setting means is
It is characterized in that the second sound information can be set by delaying for a predetermined time or more after setting the first sound information.

  According to the twelfth gaming machine of the above (2), after the first sound information to be reproduced only once is set and delayed for a predetermined time or more, the second sound information to be reproduced plural times is set Therefore, it becomes possible to prevent the first sound information reproduced only once from becoming difficult to hear.

The thirteenth gaming machine is
Setting means (for example, voice / LED control circuit) which can be set by assigning sound information (for example, SAC number) related to game sound data to a channel;
Sound output means capable of outputting a game sound based on the sound information assigned to the channel;
Equipped with
The setting means is
When sound information is assigned to one channel, a plurality of pieces of sound information are set to the one channel (for example, when it is determined YES in the process of step S 542),
When the plurality of pieces of sound information are specific sound information (for example, chain reproduction of SHOT + loop), any one piece of sound information (for example, loop reproduction) of the plurality of pieces of sound information is stored for at least a predetermined time (for example, First setting means (for example, the host control circuit 210 which executes the process of step S544) configured to delay and set one frame or more;
Under the condition that the plurality of sound information is non-specific sound information different from the specific sound information (for example, NO in the process of step S543), without delaying for a predetermined time or more For example, a second setting unit (for example, a host control circuit 210 that executes the processing of step S546 or step S547) that sets the plurality of pieces of sound information in the frame);
Have
The second setting unit is
When the mute setting is performed for all the channels (for example, when it is determined YES in the process of step S545), the sound information is set without overwriting the mute setting (for example, the process of step S546 is performed) On the other hand, when the mute setting is not for all channels but the mute setting for one channel (for example, when it is determined NO in step S545), the mute setting is overwritten and the sound information is set (for example, step S547). Perform the processing of (a).

  According to the thirteenth gaming machine, when a plurality of pieces of sound information are set in one channel, when the plurality of pieces of sound information are specific sound information, any one piece of sound information is delayed and set. Therefore, it is possible to enjoy the sound effect by delaying (for example, the sound effect by muffling). On the other hand, if the plurality of pieces of sound information are non-specific sound information, the plurality of pieces of sound information are set without being delayed, so that the processing can be performed quickly. That is, by not delaying or delaying according to the situation, it is possible to secure the promptness of processing while taking advantage of the game sound effect due to the delay. Furthermore, when a plurality of sound information is non-specific sound information, the sound information is set without overwriting the muffling setting when muttering is set for all channels, and the sound information is set instead of the mutter setting for all channels. When the mute setting for the channel is set, the mute setting is overwritten and sound information is set, so for example, until the variation display of the next special symbol is started when the variation display of the special symbol is finished ) Can be secured.

  Thus, according to the twelfth gaming machine and the thirteenth gaming machine, it is possible to provide a gaming machine capable of suitably outputting game sound.

[14th game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery. In addition to such effect images, game sounds are also output from the speakers.

  As a game machine of this type, a game machine is disclosed that outputs a sound that boosts a game in conjunction with an effect image displayed on a liquid crystal display or the like (see, for example, JP-A-2014-144066).

(The ninth task)
However, in the gaming machine described in JP-A-2014-144066, the secondary volume is maintained at a fixed value, and the primary volume controls the volume of the effect sound, so to increase the variation of the effect sound volume There is a limit.

  In order to solve the ninth problem, a fourteenth gaming machine having the following configuration is provided.

(1) The fourteenth game machine is
An output unit (for example, the speaker 11) capable of outputting a predetermined game sound;
Sound data setting means (e.g., host control circuit 210) capable of setting sound data (e.g., voice data) related to game sound output from the output means;
A volume control unit (for example, a host control circuit 210 that executes a sound request) having a plurality of reproduction channels (for example, CH1 to CH31) and capable of controlling the volume output from the output unit;
Equipped with
The volume control means
A first volume control unit (for example, a first volume control unit capable of changing information related to the volume for all of the plurality of reproduction channels based on a predetermined operation (for example, a hardware switch operation or a screen operation by a user) being performed. A host control circuit 210) for executing volume control 281 by hardware switch, user volume control 282 by volume setting screen, and debug volume control 283 at the time of debugging;
Second volume control means (for example, first reproduction channel primary control 284, second reproduction channel primary control 285, and second volume control means) capable of changing information related to the volume for each reproduction channel among the plurality of reproduction channels. A host control circuit 210)) which executes volume control 286, 287, 288 embedded in voice data;
And the information related to the volume by the first volume control unit and the information related to the volume by the second volume control unit are multiplied to change the volume output from the output unit. ,
The second volume control means
Volume control (first reproduction channel primary control 284) for controlling so that information related to the volume is changed when the predetermined operation is performed for each reproduction channel;
Even if the predetermined operation is performed for each reproduction channel, a volume is controlled to output information (for example, an error sound and an alarm sound at the time of illegal activity) related to a certain volume before and after the operation is performed. The control (second reproduction channel primary control 285) is configured to be executable.

  According to the fourteenth gaming machine of (1), the game sound output from the output means is the product of the information on the volume by the first volume control means and the information on the volume by the second volume control means Therefore, it is possible to provide diversity in the volume of the game sound. In addition, the second volume control means performs control such that, even if a predetermined operation is performed for each reproduction channel, information relating to a certain volume is output before and after the operation is performed. Thereby, even if a predetermined operation is performed, it is possible to execute control for outputting information related to a certain volume before and after the operation is performed only on a specific reproduction channel, not on the entire channel. .

(2) In the fourteenth gaming machine according to (1),
The first volume control means
It is characterized in that information related to volume can be controlled by debugging volume control at the time of debugging.

  According to the fourteenth gaming machine of (2) above, gaming sound data used in the game can be used as it is at the time of debugging, and work efficiency at the time of debugging can be improved.

  Also, according to the fourteenth gaming machine, it is possible to provide a gaming machine capable of providing variety in variations of the volume of the effect sound.

[Fifteenth to nineteenth gaming machines]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery. In addition to such effect images, game sounds are also output from the speakers.

  As this type of game machine, a game machine capable of adjusting the volume of the game sound output from the speaker by the operation of the player is disclosed (see, for example, JP-A-2011-229766).

(The tenth task)
However, if it is possible to adjust the volume of the game sound output from the speaker by the operation of the game sound, there is a possibility that the sound may not be changed, such as an error sound or a warning sound, for example. Not desirable.

  In order to solve the tenth problem, the following fifteenth to nineteenth gaming machines are provided.

(1) The fifteenth game machine is
A plurality of output means (for example, speakers 11) capable of outputting a predetermined game sound;
Operation means (for example, volume setting screen) capable of operating the volume output from the output means;
Sound control means (for example, a host control circuit 210 that executes a sound request control process) capable of controlling the sound volume based on the operation means being operated;
Equipped with
The volume outputted from the output means is at least a first information (for example, the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated Audio signal) and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information of volume changed based on operation of the operation means And
The plurality of output means include dedicated output means (for example, dedicated speakers) used for outputting a specific sound, and shared output means (for example, shared speaker) used for outputting a sound other than the specific sound. And at least
The sound control means is
With regard to the dedicated output means, a specific sound control means (for example, a step capable of executing control to output the first information so that a constant volume is outputted before and after the operation is performed even if the operation means is operated) A host control circuit 210) that executes S559;
Non-specific sound control means capable of executing control to output the second information so that the volume is changed based on the operation means being operated (for example, a host executing step S558) And a control circuit 210).

  According to the fifteenth game machine of the above (1), the dedicated output means used for outputting a specific sound is constant before and after the operation is performed even if the operator capable of operating the volume is operated It is controlled to output the volume. That is, although the volume can be operated, a constant volume is output without changing the volume before and after the operation of the operation means. Further, as for the common output means used for outputting a sound other than the specific sound, the second information is outputted in which the volume information is changed based on the operation of the operator capable of operating the volume. It is possible to suitably adjust the volume.

(2) In the fifteenth game machine according to (1),
The dedicated output means is a speaker for vibration.

  According to the fifteenth game machine of (2), it is possible to output a specific sound (for example, an error sound or a warning sound) from the speaker for vibration at a constant volume.

(3) In the gaming machine of (1) or (2) above,
Dedicated output setting means (for example, the process of step S201 is executed to set which one of the plurality of output means is to be the dedicated output means at the time of power-on (for example, at the time of various initialization processing of step S201) Host control circuit 210), and
The data relating to the specific sound (for example, voice data relating to the specific sound designated by the SAC number) is defined as that the output destination of the specific sound is the dedicated output means. I assume.

  According to the above-mentioned gaming machine (3), since the output destination of data relating to a specific sound is defined in the dedicated output unit when the power is turned on, which output unit can be set as the dedicated output unit can be set. In addition, since it is defined that voice data relating to a specific sound from which a constant volume is output is output from the dedicated output means, it is possible to enhance versatility.

(1) The sixteenth gaming machine
An output unit (for example, the speaker 11) capable of outputting a predetermined game sound;
Operation means (for example, volume setting screen) capable of operating the volume output from the output means;
Sound control means (for example, a host control circuit 210 that executes a sound request control process) having a plurality of reproduction channels and capable of controlling the volume based on the operation of the operation means;
Equipped with
The volume outputted from the output means is at least a first information (for example, the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated Audio signal) and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information of volume changed based on operation of the operation means And
The plurality of reproduction channels include at least a dedicated channel used to output a specific sound, and a shared channel used to output a sound other than the specific sound.
The sound control means is
With regard to the dedicated channel, even if the operation means is operated, a specific sound control means capable of executing control to output the first information so as to output a constant volume before and after the operation is performed (for example, step S580) Host control circuit 210) that executes
Non-specific sound control means (for example, host control for executing step S581) capable of executing control for outputting the second information so that the volume is changed based on the operation of the operation means for the shared channel And the circuit 210).

  According to the sixteenth gaming machine of the above (1), even if the operation means is operated for a dedicated channel used to output a specific sound, a constant volume is output before and after the operation is performed It is controlled. That is, although the volume can be operated, constant volume information is output without changing the volume before and after the operation of the operation means. In addition, for shared channels used to output sounds other than a specific sound, the volume is controlled to be changed based on the operation of an operator capable of operating the volume, so it is preferable to adjust the volume. It is possible to do

(2) In the sixteenth game machine according to (1),
Set the dedicated channel (for example, CH31, CH32) used to output the specific sound when the power is turned on, and the shared channel (for example, CH1 to CH30) used for the output of sounds other than the specific sound Channel setting means (for example, host control circuit 210 which executes the process of step S201);
Sound information registration means (for example, a host for registering a SAC number) for registering sound information (for example, SAC number) applied to data of each of the specific sound and sounds other than the specific sound in the dedicated channel or the shared channel Control circuit 210),
And the like.

  According to the sixteenth gaming machine of the above (2), when the power is turned on, a dedicated channel used for outputting a specific sound and a shared channel used for outputting a sound other than the specific sound are set. In addition, since the sound information applied to the data of each of the specific sound and the sounds other than the specific sound is registered in each channel, it is possible to enhance versatility.

The seventeenth gaming machine is
An output unit (for example, the speaker 11) capable of outputting a predetermined game sound;
Operation means (for example, volume setting screen) capable of operating the volume output from the output means;
Sound control means (for example, a host control circuit 210 that executes a sound request control process) having a reproduction channel and capable of controlling the volume based on the operation of the operation means;
Equipped with
The volume outputted from the output means is at least a first information (for example, the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated Audio signal) and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information of volume changed based on operation of the operation means And
The sound control means is
Data determination means (for example, a host control circuit 210 executing step S599) for determining whether or not the game sound data being reproduced on the reproduction channel is specific data of a specific sound;
When the data discrimination means determines that the game sound data being reproduced on the reproduction channel is the specific data, a constant volume is output before and after the operation is performed even if the operation means is operated. Specific sound control means (for example, host control circuit 210 which executes step S600) capable of executing control to output the first information;
When it is determined by the data determination unit that the game sound data being reproduced on the reproduction channel is non-specific data, the second information is changed so that the volume is changed based on the operation of the operation unit. And a non-specific sound control unit capable of executing control to output (for example, a host control circuit 210 that executes step S601).

  According to the seventeenth gaming machine, when it is determined that the data of the game sound being reproduced is the specific data, control is performed so that a constant volume is output before and after the operation is performed even if the operation means is operated. When it is determined that the game sound data being played back is non-specific data, the volume is controlled to be changed based on the operation of the operation means, so the volume adjustment is preferably made. It will be possible to do.

The eighteenth game machine is
An output unit (for example, the speaker 11) capable of outputting a predetermined game sound;
Operation means (for example, volume setting screen) capable of operating the volume output from the output means;
Sound control means (for example, a host control circuit 210 that executes a sound request control process) having a reproduction channel and capable of controlling the volume based on the operation of the operation means;
Equipped with
The volume outputted from the output means is at least a first information (for example, the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated Audio signal) and second information (for example, an audio signal output by the first reproduction channel primary control 284) having information of volume changed based on operation of the operation means And
The sound control means is
When sound information (for example, SAC number) corresponding to sound output reproduced on the reproduction channel is specific sound information, a constant volume is output before and after the operation is performed even if the operation means is operated Specific sound control means (for example, host control circuit 210 which executes step S621) capable of setting the first information to the reproduction channel,
When sound information (for example, SAC number) corresponding to a game sound reproduced on the reproduction channel is non-specific sound information, the reproduction is changed such that the volume is changed based on the operation of the operation means. A non-specific sound control unit capable of setting the second information in a channel (for example, the host control circuit 210 that executes step S623) is characterized.

  According to the eighteenth game machine, if the sound information (for example, SAC number) corresponding to the sound output reproduced on the reproduction channel is specific sound information, a constant volume is output even if the operation means is operated. If the sound information (for example, SAC number) corresponding to the game sound reproduced on the reproduction channel is non-specific sound information, the volume is changed based on the operation of the operation means. Therefore, it is possible to suitably adjust the volume.

The nineteenth gaming machine is
An output unit (for example, the speaker 11) capable of outputting a predetermined game sound;
Operation means (for example, volume setting screen) capable of operating the volume output from the output means;
Sound control means (for example, a host control circuit 210 that executes a sound request control process) having a reproduction channel and capable of controlling the volume based on the operation of the operation means;
Equipped with
The volume outputted from the output means is at least a first information (for example, the second reproduction channel primary control 285) having information of a constant volume before and after the operation is performed even if the operation means is operated Audio signal), second information (for example, an audio signal output by the first reproduction channel primary control 284) having information of volume changed based on the operation of the operation means; Third information (for example, audio signal output by volume control 286, 287, 288 incorporated in audio data) having information of volume incorporated in audio data specified from audio information registered in playback channel Specified by) and
The sound control means is
When sound data specified from sound information (for example, SAC number) registered in the reproduction channel is specific sound data (for example, sound data not affected by volume adjustment), the specific sound data Identification information setting means (for example, host control circuit 210 for executing the process of step S632) for setting in advance identification information (for example, a flag indicating whether each channel is affected by volume adjustment) capable of identifying a certain thing ,
In setting the volume to the reproduction channel, when the sound data specified from the sound information (for example, SAC number) can be identified by the identification information as the specified sound data (for example, it is determined as YES in step S637) First volume setting means (for example, step) capable of setting the first information to the reproduction channel so that a constant volume is output before and after the operation is performed even if the operation means is operated). A host control circuit 210) capable of executing the process of S641;
In setting the volume to the reproduction channel, when the sound data specified from the sound information can be identified by the identification information that the sound data is not the specific sound data (for example, when determined as NO in step S637), the operation A second volume setting unit (for example, a host control circuit 210 capable of executing the process of step S638) capable of setting the second information to the reproduction channel so that the volume is changed based on the operation of the unit;
A third volume setting unit (for example, a host control circuit 210 capable of executing the process of step S644) for setting third information to the reproduction channel is provided for setting the volume to the reproduction channel.

  According to the nineteenth gaming machine, identification information capable of identifying that the sound data specified from the sound information registered in the reproduction channel is the specific sound data is set in advance, and the sound information specified from the sound information When it can be identified by the identification information that the sound data is specific sound data, a constant sound volume is set to be output even if the operation means is operated. Further, the sound volume is set to be changed based on the sound data specified from the sound information registered in the reproduction channel. Further, third information having volume information incorporated in sound data specified from sound information registered in the reproduction channel is set in the reproduction channel. In this way, it is possible to suitably adjust the volume.

  In the above-mentioned gaming machine, when the sound data specified from the sound information (for example, SAC number) registered in the reproduction channel can be identified by the identification information as the specific sound data (for example, YES in step S637) Even when the operation means is operated, a constant sound volume is output before and after the operation is performed, but the constant sound volume in this case is always information relating to the maximum sound volume. Also good. However, even if sound data specified from sound information registered in the reproduction channel is specific sound data (first information related to a certain volume), sound information (for example, SAC number registered in the reproduction channel) The output volume may not be a constant volume because it is multiplied with the volume incorporated in the sound data specified from.

  Thus, according to the fifteenth to nineteenth gaming machines, it is possible to provide a gaming machine capable of suitably adjusting the volume.

[Twentieth game machine]
Conventionally, in a gaming machine such as a pachinko machine, a game is known in which a light emitting means including a light emitting body such as an LED is provided on the front side of the gaming machine and this light emitting means is lighted or blinked in a predetermined manner. ing.

  As this type of game machine, there is known a game machine capable of adjusting the brightness of the light emitting means by an operation by a player or the like (see, for example, JP-A-2008-295551).

(The eleventh problem)
According to the gaming machine described in JP-A-2008-295551, although the luminance of the light emitting means can be challenged by the operation of the player etc., when the light emitting means can emit light in full color, the light emission occurs when the luminance is changed. The color may change significantly.

  In order to solve the eleventh problem, a twentieth gaming machine having the following configuration is provided.

The twentieth game machine is
A predetermined light emitting means (for example, a lamp (LED) group 18);
Operation means operable to select the luminance of the light emitting means (for example, a luminance setting screen displayed on a liquid crystal display device used as the display device 13);
A storage unit (for example, a luminance information table (for example, attenuation table) in which luminance information is set for each of a plurality of colors (for example, RGB) as luminance information (for example, luminance attenuation factor) related to the luminance of the light emitting unit. Sub main ROM 205),
Brightness control means (for example, host control circuit 210) capable of controlling the brightness of the light emitting means based on the brightness information table when the brightness is selected by the operation means;
Equipped with
The storage means is
A luminance information table in which the luminance information is set for each of the plurality of colors is stored corresponding to the luminance selectable by the operation means.
The brightness control means
Based on the brightness information table corresponding to the brightness selected by the operation means, the brightness of the light emitting means can be controlled so that the attenuation factor of blue among the plurality of colors is the largest and the attenuation factor of red is the smallest. It is characterized in that

  According to the twentieth game machine, light emission of the light emitting means is performed so that the attenuation factor of blue among the plurality of colors is the largest and the attenuation factor of the red is the smallest based on the luminance information set for each of the plurality of colors. Therefore, even if the brightness of the light emitting means is changed by the operation of the player or the like, for example, it is possible to suppress the change of the light emission color, that is, maintain the white balance.

  As described above, according to the twentieth game machine, it is possible to provide a game machine capable of changing the luminance while suppressing the change of the luminescent color.

[The 21st game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery.

  As this type of gaming machine, there has been proposed a gaming machine in which a movable body is disposed on a gaming board and the movable body exerts an impact by operating the movable body to increase the motivation for the game. (For example, refer Unexamined-Japanese-Patent No. 2006-288694).

(The 12th subject)
For example, in the gaming machine in which the movable body is operated as disclosed in Japanese Patent Application Laid-Open No. 2006-286894, the movement of the movable body is diversified in recent years, and the control for operating the movable body is complicated accordingly. Therefore, in recent years, there has been a demand for a gaming machine capable of suppressing a control load while giving diversity to the movement of a movable body.

  In order to solve the above-mentioned twenty-first problem, a twenty-first game machine having the following configuration is provided.

The 21st game machine is
The predetermined features,
Control means (for example, host control circuit 210) capable of controlling the operation of the predetermined item;
An actuating member (e.g., a solenoid) capable of actuating a member constituting the accessory;
A plurality of light emitting means (for example, LEDs);
A plurality of connection parts (for example, Port 0 to Port 23) capable of transmitting signals to the connected light emitting means by being connected to any of the plurality of light emitting means;
A light emission control unit (for example, an audio / LED control circuit 220) capable of controlling the light emitting unit by transmitting a signal to the light emitting unit through the connection unit;
Equipped with
The actuating member is
It is configured to be connected to any one of the plurality of connection parts, and to operate a member that constitutes the item according to a signal from the light emission control means,
The control means
The actuating member connected to any one of the plurality of connection portions can be operated in synchronization with the predetermined accessory.

  According to the twenty-first gaming machine, even if the number of operating members increases due to diversification of the movement of the item, the control load for operating the item is maintained while maintaining the diversity of the movement of the item. While suppressing, it becomes possible to synchronize an accessory and an operation member.

  Thus, according to the twenty-first gaming machine, it is possible to provide a gaming machine capable of suppressing a control load.

[The 22nd game machine]
Conventionally, in a gaming machine such as a pachinko machine, when a game ball is won in the starting opening, a lottery is performed, and an effect image is displayed on, for example, a liquid crystal display based on the result of the lottery.

  As this type of gaming machine, compressed data is read out from a CGROM storing compressed data of still images and moving images displayed on a liquid crystal display, and the read out compressed data is expanded and image data to be output to the liquid crystal display There is known a gaming machine which generates a game machine (for example, see JP-A-2016-159026).

(The thirteenth task)
However, as described in JP-A-2016-159026, for example, when generating compressed image data to be output by reading compressed data from a CGROM, load processing takes time if there is a large amount of data. . In this case, although the loading process proceeds normally, watchdog reset may be performed, which is not preferable.

  In order to solve the thirteenth problem, a twenty-second game machine having the following configuration is provided.

(1) The twenty-second game machine is
A read-only storage area (for example, sub main 205 or CGROM 206) in which game data relating to a game is stored;
Volatile storage area (for example, SRAM 210b or built-in VRAM 237) capable of reading and writing game data related to the game;
Transfer executing means (for example, a host control circuit 210 for executing the data loading process of FIG. 68) for executing a loading process for reading the gaming data stored in the read only storage area and writing the same to the volatile storage area;
Watchdog timer,
Clearing means (for example, a host control circuit 210 having a CPU processor) which clears the clocking of the watchdog timer when a predetermined time has elapsed;
Equipped with
The transfer execution means is
When the loading process exceeds a predetermined time, the watchdog timer is reset, and a load reprocessing unit (a host control circuit 210 that executes the process of step S656) that executes the loading process again is provided.

  According to the twenty-second gaming machine of (1), the loading process is ended when the time required for the loading process by the transfer execution means exceeds the predetermined upper limit, and the loading process is executed again. Even when the loading process takes time, it is possible to automatically return.

  As described above, according to the twenty-second gaming machine, even when the loading process takes time, the loading process can be suitably progressed.

(2) In the twenty-second gaming machine according to (1),
The clearing means is
If the loading process does not exceed the predetermined time, the watchdog timer is cleared (for example, the process of step S655), and only when the loading process exceeds the predetermined time, the watchdog timer counts time. The error processing (for example, the processing of step S656) is configured to be executed without being cleared,
The transfer execution means is
The load processing is executed again as the error processing.

  According to the twenty-second gaming machine of the above (2), while the watchdog timer is cleared when the loading process does not exceed the predetermined time, the watchdog timer is set only when the loading process exceeds the predetermined time. Since the error processing is executed without being cleared, it is possible to grasp that the loading processing could not be completed due to the occurrence of an error.

[23rd game machine, 24th game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when the gaming ball is won in the starting opening, and a big hit game is played when the result of the drawing is a big hit. Further, for example, a liquid crystal display is provided on which the effect image is displayed, and the effect image determined by the lottery is displayed on the liquid crystal display.

  In this type of gaming machine, lottery is performed in various scenes, and such lottery is performed by generating and acquiring random numbers. For example, in JP-A-2017-023629, the number of digits of the newly acquired random number is determined, and the number of one digit determined from the reference random number is calculated, and the calculated value is used as each digit. A method of arranging and acquiring new numerical values is described.

(The 14th task)
In random number acquisition processing for acquiring a random number, it is required that regularity is unlikely to occur in the acquired random number. However, if the process is complicated, the control load becomes large, which is not preferable. Therefore, it is preferable to perform random number acquisition processing in which regularity is less likely to occur while suppressing an increase in control load.

  In order to solve the fourteenth problem, a twenty-third game machine and a twenty-fourth game machine having the following configurations are provided.

The twenty-third game machine is
It is a gaming machine that performs lottery using a predetermined random number,
A real time clock (eg, RTC) capable of outputting time information;
Random number generation means (for example, a host control circuit 210 for executing the processing of FIG. 70 and FIG. 71) for generating random numbers used for a predetermined lottery;
Equipped with
The random number generation means
Initialization means for acquiring time information from the real-time clock and generating an initial value of random numbers using the acquired time information (for example, host control circuit 210 for executing random number initialization processing);
Non-stationary updating means (host control circuit 210 for executing the processing of FIG. 71) for updating the random numbers when the generated random numbers are used for the lottery;
Stationary update means (host control circuit 210 for executing the processing of FIG. 70) for periodically updating the random numbers even if the generated random numbers are not used in the lottery;
It is characterized by

  According to the twenty-third game machine, since the initial value of the random number is generated using the time information acquired from the real time clock, the acquired random number can be made random, and the acquired random number is biased. Can be suppressed. In particular, the initial value of the random number can be varied each time since the time when the power is turned on is involved up to the minute / second unit.

The 24th game machine is
It is a gaming machine that performs lottery using a predetermined random number,
Random number table creating means (for example, step S704 is executed) which creates a random number table in which a plurality of random numbers are registered, using any one of a plurality of random number seeds (for example, random number seeds a to h). Host control circuit 210),
Random number acquisition means for acquiring random numbers to be provided for a predetermined lottery with reference to the random number table generated by the random number table generation means (for example, in the random number acquisition process of step S706, from the random number table generated in step S704) A host control circuit 210) for acquiring random numbers;
Reference position updating means for updating the reference position of the random number table at a timing different from the timing when the random number table is created (a host control circuit for updating the reference position of the random number table when random numbers are obtained from the random number table in step S706) 210) and
Equipped with
The random number acquisition unit
After obtaining a random number with reference to the random number table, it is possible to obtain a random number to be provided for the predetermined lottery with reference to the same random number table in which the reference position is updated without creating the random number table (for example, It is characterized in that the packet reception loop of FIG. 73 can be performed to execute the random number acquisition process of step S706).

  According to the twenty-fourth gaming machine, even if random number acquisition opportunities occur multiple times, only the reference position is updated and random numbers are acquired using the same random number table that has already been created. It is possible to lighten the control load while providing irregularity.

  Thus, according to the twelfth gaming machine and the thirteenth gaming machine, it is possible to provide a gaming machine capable of suitably outputting game sound.

  As described above, according to the twenty-third and twenty-fourth game machines, it is possible to provide a game machine capable of executing processing in which regularity is unlikely to occur while suppressing an increase in control load.

  Further, according to the first to twenty-fourth game machines, it is possible to preferably provide a game machine capable of suppressing the decrease in interest.

1 Pachinko machine (game machine)
Reference Signs List 2 main body 3 base door 4 glass door 11 speaker 11a speaker box 11b connection terminal group 12 game board 13 display device 15 launcher 16 dispensing device 18 lamp (LED) group 20 role 43 ball passing detector 44 first starting port 45 2 Start-up opening 46 ordinary electric role 51, 52 general winning opening 53 first large winning opening 54 second large winning opening 55 out opening 56 game nail 61 special symbol display device 62 normal symbol display device 63 normal symbol hold display device 64 1 special symbol hold display device 65 second special symbol hold display device 70 main control circuit 71 main CPU
72 Main ROM
73 Main RAM
77 One-chip microcomputer 123 Dispensing and firing control circuit 200 Sub control circuit 201 Relay board 202 Sub board 203 Control ROM board 204, 204a, 204b CGROM board 205 Sub main ROM
206, 206a, 206b CGROM
210 host control circuit 210a sub work RAM
210b SRAM
220 Audio / LED Control Circuit 230 Display Control Circuit 262 Digital Audio Power Amplifier

Claims (1)

Light emitting means capable of emitting light in a predetermined manner;
Data storage means for storing drive data corresponding to a light emission mode emitted by the light emission means in a predetermined area;
A light emission drive means for outputting a control signal based on the drive data stored in the data storage means to the light emission means;
Data setting means for setting the drive data in a predetermined area of the data storage means;
Equipped with
The data setting means
The drive data set in the predetermined area of the data storage means is configured to set the new drive data when the number of drive data that can be set in the predetermined area becomes the reference data number. A gaming machine to be.

Images