JP2019106830A - Resonance type inverter device, electric power supply, control apparatus, and control program - Google Patents

Abstract

To provide a resonance type inverter device capable of achieving a correct zero-volt switching while correctly operating a soft-switching by preventing a hard switching in an inverter circuit, and accurately reducing a switching loss and a noise as a result.SOLUTION: An electric power supply 1 is structured so as to detect an output current output from an inverter circuit 21, detect a potential difference between drain-source of each of semiconductor switching elements Qa to Qd, control a turn-off operation of each of the semiconductor switching elements Qa to Qd on the basis of positive and negative polarities of the output current detected and control a turn-on operation of each of the semiconductor switching elements Qa to Qd on the basis of the positive and negative polarities of the output current detected and the potential difference between the drain-source in each of the semiconductor switching elements detected.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a resonant inverter device or the like in which a resonant circuit is connected in series to an output end of an inverter circuit.

  Conventionally, in order to prevent the turn-on loss in the series resonant inverter device, a method of adjusting the switching timing of the full bridge inverter circuit has been proposed (for example, Patent Document 1).

  For example, a conventional resonance type inverter device includes an inverter circuit forming a full bridge inverter that alternately outputs voltage pulses whose positive and negative polarities change periodically, and an inductor (reactor) and a capacitor at its output end. ing.

  Then, this resonance type inverter device detects the output current value of the inverter circuit by a current detector, and adjusts the turn-on / turn-off timing of the semiconductor switching element constituting the full bridge inverter based on the detected current value. have.

  In addition, such an inverter device can prevent turn-on or turn-off loss by realizing the zero cross timing of the output current of the inverter circuit.

JP 2002-171766 A

  However, in the resonance type inverter device described in Patent Document 1 above, the frequency of the output voltage pulse from the inverter circuit is adjusted in order to correct the zero cross timing. For this reason, in the case of the resonance type inverter device, when the load value changes rapidly, such as occurrence of a short circuit state caused by arc discharge generated on the load side, the inverter circuit operates by hard switching, and as a result, Problems such as increased power loss, abnormal heat generation, and increased noise may occur.

  The present invention has been made to solve the above-mentioned problems, and its object is to prevent hard switching in an inverter circuit to operate soft switching properly and to realize accurate zero volt switching. As a result, it is an object of the present invention to provide a resonant inverter device and the like capable of reliably reducing switching loss and noise.

In order to solve the above problems, the present invention is
A full bridge type inverter circuit having a plurality of semiconductor switching elements, and alternately outputting voltage pulses whose positive and negative polarities periodically change by controlling the semiconductor switching elements;
A resonant circuit comprising an inductor and a capacitor connected in series to an output end of the inverter circuit;
Current detection means for detecting an output current output from the inverter circuit;
Potential difference detection means for detecting the potential difference between the drain and the source of each of the plurality of semiconductor switching elements;
Control means for controlling the on operation and the off operation of each of the semiconductor switching elements based on the positive / negative polarity of the detected output current and the potential difference between the drain and source of each of the detected semiconductor switching elements;
Have a configuration.

  In addition to the above, the present invention may further include a step-down converter connected to the input end of the inverter circuit.

Furthermore, the present invention
A full bridge type inverter circuit having a plurality of semiconductor switching elements and alternately outputting voltage pulses whose positive and negative polarities change periodically by controlling the semiconductor switching elements, and a series connected to the output terminal of the inverter circuit And a resonant circuit including an inductor and a capacitor connected to the
A resonant circuit comprising an inductor and a capacitor connected in series to an output end of the inverter circuit;
Current detection means for detecting an output current output from the inverter circuit;
Potential difference detection means for detecting the potential difference between the drain and the source of each of the plurality of semiconductor switching elements;
Control means for controlling the on operation and the off operation of each of the semiconductor switching elements based on the positive / negative polarity of the detected output current and the potential difference between the drain and source of each of the detected semiconductor switching elements;
And may have a configuration.

  Note that the present invention may be realized by a control program installed in a computer.

  With this configuration, the present invention corrects the variation of the positive / negative polarity even when the positive / negative polarity of the output current output from the inverter circuit is varied due to an external factor such as a load variation. In other words, by controlling the operation of each semiconductor switching element based on the voltage between the source and the drain of each semiconductor switching element, zero volt switching can be accurately realized.

  Therefore, the present invention can prevent soft switching caused by an external factor to allow soft switching to operate normally, and also causes switching loss, abnormal heat generation, and spike generated in a full bridge inverter circuit or the like. The generation of current or high frequency noise can be reliably reduced or prevented.

It is a figure which shows one structural example of the circuit structure in the power supply device of one Embodiment which concerns on this invention. It is a circuit diagram (the 1) for explaining basic operation of an inverter circuit of one embodiment. It is a circuit diagram (the 2) for demonstrating the basic operation | movement of the inverter circuit of one Embodiment. It is a circuit diagram (the 3) for demonstrating the basic operation | movement of the inverter circuit of one Embodiment. It is a timing chart which shows the operation of each switching element which constitutes the inverter circuit of one embodiment, and the timing of the output voltage pulse and output current which are outputted from the inverter circuit concerned. It is a circuit diagram (the 1) for explaining an abnormal state in operation of an inverter circuit of one embodiment. It is a circuit diagram (the 2) for demonstrating an abnormal condition in operation | movement of the inverter circuit of one Embodiment. In one embodiment, the operation of each switching element forming the inverter circuit, the timing of the output voltage pulse and the output current output from the inverter circuit, the D-S voltage detection signal of each switching element, and each switching element 4 is a timing chart showing the relationship between the on-operation permission signal for permitting the turn-on operation of In one embodiment, the operation of each switching element forming the inverter circuit, the timing of the output voltage pulse and the output current output from the inverter circuit, the D-S voltage detection signal of each switching element, and each switching element And FIG. 16 is another example of a timing chart showing the relationship between the on-operation permission signal for permitting the turn-on operation of the circuit of FIG.

  Hereinafter, the present embodiment will be described. Note that the embodiments described below do not unduly limit the contents of the present invention described in the claims. In addition, not all of the configurations described in the present embodiment are necessarily essential configuration requirements of the present invention.

[1] Power Supply Device First, the circuit configuration of the power supply device 1 of the present embodiment will be described with reference to FIG. FIG. 1 is a diagram showing a circuit configuration of the power supply device 1 in the present embodiment.

  The power supply device 1 of the present embodiment applies a DC voltage to the converter input unit, converts the DC output of the converter into an AC (square wave) voltage by a PWM (pulse wide modulation) type inverter with phase shift full bridge, The inverter is a series resonance inverter that converts a rectangular wave to a sine wave by a series resonance tank including an inductor and a capacitor.

  In addition, the power supply device 1 of the present embodiment includes, for example, sputtering devices, various electron microscopes such as transmission electron microscopes and scanning electron microscopes, magnetic resonance devices and various measurement devices, illumination using high frequency induction heating devices and discharge tubes. It is for supplying alternating current power to the appliance.

  Then, as shown in FIG. 1, the power supply device 1 of the present embodiment is a step-down converter 10 that steps down DC voltage and supplies it to the series resonant inverter device 20, and an inverter circuit 21 that converts DC voltage to AC voltage. And a control circuit 30 for controlling the series resonant inverter device 20.

  The step-down converter 10 supplies a DC voltage to the input end of the series resonant inverter device 20 connected to the output end 12. In particular, the step-down converter 10 includes an input-side capacitor C1 and an output-side capacitor C2, a diode D1, a semiconductor switching element for the converter (hereinafter referred to as "converter switching element") Q1, and an inductor L1. There is. For example, the step-down converter 10 of the present embodiment constitutes a step-down converter of the present invention.

  Specifically, the input side capacitor C1 and the output side capacitor C2 respectively have the input end 11 (the first input end 11a and the second input end 11b) and the output end 12 (the first output end 12a and the second end). Are connected in parallel to the output end 12b) of the.

The anode of the diode D1 is connected to the drain of the converter switching element Q1 and one end of the inductor L1, and the cathode of the diode D1 is connected to one end of the input side capacitor C1 and the output side capacitor C2.

  The converter switching element Q1 is configured of an N-type MOSFET (Metal-Oxide-Semiconductor-Field-Effect Transistor).

  The converter switching element Q1 has a source electrode (hereinafter also referred to as a "source") connected to one end of the input-side capacitor C1 and the second input terminal 11b, and a drain electrode (hereinafter referred to as "anode") , Also referred to as “drain”.

  The inductor L1 is connected to the anode of the diode D1, one end of the output side capacitor C2, and the second output end 12b.

  The series resonance type inverter device 20 converts the DC voltage supplied by the step-down converter 10 into an AC voltage and outputs a voltage pulse whose positive and negative polarities periodically change, and the inverter circuit And a resonant circuit 22 for reducing switching loss in voltage pulses having positive and negative polarities output from V.21.

  For example, the inverter circuit 21 of the present embodiment constitutes the inverter circuit of the present invention, and the resonant circuit 22 constitutes the resonant circuit of the present invention.

  The inverter circuit 21 includes four self-extinguishing N-type switching elements Q such as MOSFETs (hereinafter referred to as “first switching element Qa”, “second switching element Qb”, “third switching element Qc” and It has "the 4th switching element Qd."

  Each of the switching elements Qa to Qd has a configuration in which a parasitic diode (hereinafter referred to as a "body diode") BD is built in between the drain and the source. Each body diode BD is connected in parallel between the drain and source of each switching element Qa to Qd.

  Specifically, the drain of the first switching element Qa is connected to the drains of the first input end 23a connected to the first output end 12a of the step-down converter 10 and the drain of the third switching element Qc. The source of the first switching element Qa is connected to the drain of the second switching element Qb.

  The drain of the second switching element Qb is connected to the source of the first switching element Qa and the second output end 24b. Further, the source of the second switching element Qb is connected to the sources of the second input end 23b connected to the second output end 12b of the step-down converter 10 and the fourth switching element Qd.

  Then, a first connection point CP1 which is an input end of the resonant circuit 22 is formed between the source of the first switching element Qa and the drain of the second switching element Qb.

  On the other hand, the drain of the third switching element Qc is connected to the first input terminal 23a and the drain of the first switching element Qa. The source of the third switching element Qc is connected to the drain of the fourth switching element Qd.

The drain of the fourth switching element Qd is the source of the third switching element Qc and the first
Are connected to the output end 24a of. The source of the fourth switching element Qd is connected to the second input terminal 23b and the source of the second switching element Qb.

  Then, a second connection point CP2 serving as an input end of the resonance circuit 22 is formed between the source of the third switching element Qc and the drain of the fourth switching element Qd.

  The first connection point CP1 and the second connection point CP2 constitute an output end of the inverter circuit 21. Then, the potential difference (voltage between (Vsw1 and Vsw2)) between both connection points CP1 and CP2 is supplied to the resonance circuit 22 as an output voltage pulse of the inverter circuit 21.

  On the other hand, a control circuit 30 (specifically, a drive circuit unit 37 described later) is connected to a base electrode (hereinafter referred to as "base") of each of the switching elements Qa to Qd, and the first switching is performed. A signal Vga, a second switching signal Vgb, a third switching signal Vgc and a fourth switching signal Vgd are provided.

  In particular, in each of the switching elements Qa to Qd, the corresponding switching signals Vga to Vgd are changed from "Low" level (hereinafter referred to as "L level") to "Hi" level (hereinafter referred to as "H level"). When it rises, it turns on (on operation). Each of switching elements Qa to Qd maintains the on state while corresponding switching signals Vga to Vgd are maintained at the “H” level.

  Each of switching elements Qa to Qd is turned off (turned off) when corresponding switching signals Vga to Vgd are lowered from the “H” level to the “L” level. Each switching element Qa to Qd maintains the off state while the corresponding switching signals Vga to Vgd are maintained at the “L” level.

  In the present embodiment, the soft switching operation is realized by adjusting the on timing and the off timing of each of the switching elements Qa to Qd, and the switching loss in the power supply device 1 (specifically, the inverter circuit 21) is It can be reduced.

  The resonant circuit 22 is configured to output a desired AC voltage or AC current output from the inverter circuit 21 from the output terminal 24 to the outside. Specifically, the resonant circuit 22 includes an inductor L2 connected in series to the first connection point CP1, a capacitor C3 connected in series to the second connection point CP2, and an output side of the capacitor C3 on the primary side. And a transformer T1 connected to the output side of the inductor L2 and whose secondary side is connected to the output end 24.

  In particular, one end of the inductor L2 is connected to a first connection point CP1 formed between the first switching element Qa and the second switching element Qb, and the other end of the inductor L2 is connected to the primary winding Lp of the transformer T1. Connected to one end.

  Further, one end of the capacitor C3 is connected to a second connection point CP2 formed between the third switching element Qc and the fourth switching element Qd, and the other end of the capacitor C3 is connected to the primary winding Lp of the transformer T1. Connected to the other end.

The control circuit 30 controls on / off of each of the switching elements Qa to Qd constituting the inverter circuit 21.
(1) The voltage of the capacitor C3 constituting the resonant circuit 22 is detected to calculate the current flowing through the capacitor C3,
(2) detecting an output voltage Vo and an output current Io of the series resonant inverter device 20 (that is, an output current of the power supply device 1);
(3) The voltage between the drain and source of each of the switching elements Qa to Qd (hereinafter referred to as "drain-source voltage") is detected;
(4) Based on the detection results of (1) to (3), execute predetermined operations to drive and control the switching elements Qa to Qd.
It has a configuration. The details of the configuration of the control circuit 30 and the operation thereof in the present embodiment will be described later.

[2] Drive Control of Inverter Circuit [2.1] Basic Operation of Inverter Circuit Next, the basic operation of the inverter circuit 21 in the series resonant inverter device 20 of the present embodiment will be described with reference to FIGS. . 2 to 4 are circuit diagrams for explaining the basic operation of the inverter circuit 21 of the present embodiment. FIG. 5 is a timing chart for explaining the operation of each of the switching elements Qa to Qd in the inverter circuit 21 of the present embodiment and the timing of the output voltage pulse and the output current output from the inverter circuit 21. is there.

The inverter circuit 21 of the present embodiment is
(1) A first set of switches (hereinafter, also referred to as "first semiconductor switching element group") configured of the first switching element Qa and the fourth switching element Qd and turned on simultaneously.
(2) A second set of switches (hereinafter, also referred to as "second semiconductor switching element group") configured of the second switching element Qb and the third switching element Qc and turned on simultaneously.
It consists of

  Then, when the switching signals Vga to Vgd generated in the drive circuit unit 37 are respectively supplied to the gates of the switching elements Qa to Qd, the switching elements Qa to Qd are driven.

  In particular, as shown in FIGS. 2 to 4, the inverter circuit 21 repeats the operation modes m1 to m6 described below based on the switching signals Vga to Vgd, and outputs the output voltage pulse (Vsw1−) having positive and negative polarities. Output Vsw2) and output current (Isw).

  For example, when the switching signals Vga to Vgd shown in FIGS. 5A to 5D are supplied to the gates of the switching elements Qa to Qd, the inverter circuit 21 performs the first connection point CP1 and the second connection point CP1. The output voltage pulse (Vsw1−Vsw2) having positive and negative polarities shown in FIG. 5E and the output current Isw shown in FIG. 5F are output to the resonance circuit 22 via the connection point CP2.

(1) Operation mode m1 (FIG. 2 (A))
First, as shown in FIG. 5, when the first switching element Qa is turned on at timing t12 and the fourth switching element Qd is turned on at timing t14, the inverter circuit 21 is set to the operation mode "m1". A transition is made, and the output voltage pulse (Vsw1-Vsw2) becomes a positive output voltage pulse having an amplitude level Vm (FIG. 5 (E)).

  At this time, as shown in FIG. 2A, the output current output from step-down converter 10 flows in the forward direction between the drain and source of switching element Qa, and resonant circuit 22 via first connection point CP1. Output current Isw (positive (rightward with respect to the drawing)).

  Then, the current returned from the resonant circuit 22 through the second connection point CP2 flows in the forward direction between the drain and source of the fourth switching element Qd as shown in FIG. Reflux to 10 (specifically, the output side capacitor C2).

  At this time, the second switching element Qb and the third switching element Qc are in the off state.

(2) Operation mode m2 (FIG. 2 (B))
Next, as shown in FIG. 5, when the first switching element Qa is turned off at timing t21 in the operation mode m1, the forward current flowing through the first switching element Qa is the current of the second switching element Qb. It flows to the body diode.

  Then, as shown in FIG. 5, when the second switching element Qb is turned on at timing t22 after a predetermined period (dead time period) has elapsed, the operation mode transitions to “m2”, and the output voltage pulse ( Vsw1−Vsw2) becomes “0” (FIG. 5E).

  At this time, as shown in FIG. 2B, the current flowing in the body diode of the fourth switching element Qd flows in the reverse direction between the drain and source of the second switching element Qb, and the first connection point CP1 , And is output to the resonance circuit 22 as an output current Isw (positive).

  Then, the current returned from the resonant circuit 22 through the second connection point CP2 flows in the forward direction between the drain and source of the fourth switching element Qd as shown in FIG. 2 Reflux to the switching element Qb.

  At this time, the first switching element Qa and the third switching element Qc are in the off state.

(3) Operation mode m3 (FIG. 3 (A))
Then, as shown in FIG. 5, when the fourth switching element Qd is turned off at timing t23 in the operation mode m2, the forward current flowing between the drain and source of the fourth switching element Qd is: It flows to the body diode of the third switching element Qc.

  Then, as shown in FIG. 5, when the third switching element Qc is turned on at a timing t24 after a predetermined period (dead time period) has elapsed, the current has flowed to the body diode of the third switching element Qc. A current flows between the drain and source of the third switching element Qc.

  At this time, the operation mode changes from “m2” to “m3”, and the output voltage pulse (Vsw1−Vsw2) becomes a negative output voltage pulse having the amplitude level Vm (FIG. 5 (E)).

  At this time, as shown in FIG. 3A, a current flows from the step-down converter 10 (specifically, the output-side capacitor C2) in the reverse direction between the drain and source of the second switching element Qb. Is output to the resonance circuit 22 as the output current Isw (positive) through the first connection point CP1.

  Then, the current returned from the resonant circuit 22 through the second connection point CP2 flows in the reverse direction between the drain and source of the third switching element Qc as shown in FIG. Reflux to 10 (specifically, the output side capacitor C2).

  Further, the dead time period in this mode is provided to prevent a through current between the third switching element Qc and the fourth switching element Qd.

(4) Operation mode m4 (FIG. 3 (B))
Then, as shown in FIG. 5, the output current Isw flowing at the time of the operation mode m3 passes the operation of the resonance circuit 22 (that is, the resonance between Vsw1 and Vsw2) after elapse of a predetermined period after transition to the operation mode m3. The operation mode is switched to "m4" by reversing by the function of the tank). However, at this time, as shown in FIG. 5E, the output voltage pulse (Vsw1-Vsw2) maintains a negative output voltage pulse having an amplitude level Vm.

  At this time, as shown in FIG. 3B, the current from the step-down converter 10 (specifically, the output-side capacitor C2) flows in the forward direction between the drain and source of the third switching element Qc. The output current Isw (negative) is output to the resonance circuit 22 via the connection point CP2 of

  Then, the current returned from the resonant circuit 22 via the first connection point CP1 flows in the forward direction between the drain and source of the second switching element Qb as shown in FIG. Reflux to 10 (specifically, the output side capacitor C2).

(5) Operation mode m5 (FIG. 4 (A))
Next, as shown in FIG. 5, when the second switching element Qb is turned off at timing t31 in the operation mode m4, the current flowing in the forward direction between the drain and source of the second switching element Qb is It flows to the body diode of the first switching element Qa.

  Then, as shown in FIG. 5, when the first switching element Qa is turned on again at timing t32 after a predetermined period (dead time period) has elapsed, the current has flowed to the body diode of the first switching element Qa. Current flows between the drain and source of the first switching element Qa, and the operation mode transitions to "m5". However, as shown in FIG. 5E, the output voltage pulse (Vsw1−Vsw2) maintains a negative output voltage pulse having an amplitude level Vm.

  At this time, as shown in FIG. 4A, the current flowing in the forward direction between the drain and source of the third switching element Qc resonates as the output current Isw (negative) through the second connection point CP2. It is output to the circuit 22.

  Then, the current returned from the resonant circuit 22 through the first connection point CP1 flows in the reverse direction between the drain and source of the first switching element Qa, as shown in FIG. Reflux to the element Qc.

(6) Operation mode m6 (FIG. 4 (B))
Next, as shown in FIG. 5, when the third switching element Qc is turned off at timing t33 in the operation mode m5, the current flowing in the forward direction between the drain and source of the third switching element Qc is The current flows to the body diode of the fourth switching element Qd, and the operation mode transitions to "m6". However, as shown in FIG. 5E, the output voltage pulse (Vsw1−Vsw2) maintains a negative output voltage pulse having an amplitude level Vm.

At this time, as shown in FIG. 4B, a current flows from the step-down converter 10 (specifically, the output-side capacitor C2) to the body diode of the fourth switching element Qd, and via the second connection point CP2. The output current Isw (negative) is output to the resonance circuit 22.

  Then, the current returned from the resonant circuit 22 through the first connection point CP1 flows in the reverse direction between the drain and source of the first switching element Qa in the reverse direction as shown in FIG. Specifically, it returns to the output side capacitor C2).

  After that, as shown in FIG. 5, when the timing t34 arrives, the operation mode m1 is entered and the direction of the output current Isw is reversed. The operation modes m1 to m6 are repeated by sequentially transitioning the above operation modes.

  Thus, the value of the output current Isw output to the resonant circuit 22 forms the sine waveform shown in FIG. 5F by repeatedly operating the transition of the operation mode from “m1” to “m6”. It is supposed to be. However, since the soft switching is performed at the switching timing to each operation mode, the switching is performed before the polarity is reversed.

[2.2] Operation outline of the inverter circuit of the present embodiment Next, an operation outline of the inverter circuit 21 of the present embodiment will be described while describing an abnormal state occurring during basic operation with reference to FIGS. 6 and 7. Do. 6 and 7 are circuit diagrams for describing an abnormal state during basic operation of the inverter circuit 21 of the present embodiment.

  In the basic operation, the inverter circuit 21 of the present embodiment operates by repeating the transition of the operation mode of “m1” to “m6” as described above. However, in the inverter circuit 21, when the occurrence of a short circuit state due to the occurrence of an arc discharge on the load side or the like and the rapid fluctuation of the load value occur, the direction of the output current Isw (that is, the positive or negative polarity) is included. The procedure may be different from the above-mentioned operation mode.

  In this case, the operation of inverter circuit 21 does not transition according to a series of operation procedures repeating the above operation modes m1 to m6, and the switching operation in each switching element Qa to Qd is not soft switching operation but hard In many cases, switching operation is performed.

  Then, when the hard switching operation occurs in this manner, in the series resonant inverter device 20, a switching loss occurs and a power loss occurs.

  In addition, when one switching element Q of the combination of the first switching element Qa and the second switching element Qb or the combination of the third switching element Qc and the fourth switching element Qd shifts to the off state, the circuit Due to the configuration, charging to a parasitic capacitance (not shown) will be performed.

  However, when the opposite off-state switching element Q shifts to the on-state after the dead time period, the load condition causes the charge to be insufficient. Therefore, the voltage between the drain and source of the switching element Q to be turned on in that state does not reach 0 V (volt), and zero volt switching can not be realized.

  Therefore, also in this case, a hard switching operation occurs, which causes an increase in switching loss, abnormal heat generation, high frequency noise, and the like.

Specifically, in the above-described operation mode m4, when arc discharge or the like occurs and the direction (that is, the positive / negative polarity) of the output current Isw is inverted, as shown in FIG. The current output from the step-down converter 10 flows in the reverse direction between the drain and source of the second switching element Qb, and is output to the resonant circuit 22 as the output current Isw (positive) through the first connection point CP1. Ru.

  Then, the current returned from the resonance circuit 22 through the second connection point CP2 flows in the reverse direction between the drain and source of the third switching element Qc, as shown in FIG. Reflux.

  In addition, when the timing t31 arrives in the abnormal state of the operation mode m4 and the second switching element Qb is turned off, the current flowing in the opposite direction between the drain and source of the second switching element Qb It flows to the body diode of the second switching element Qb. As a result, the path of the current does not transition from the second switching element Qb to the first switching element Qa.

  That is, at this time, the output current of the step-down converter 10 flows in the reverse direction between the drain and source of the second switching element Qb, and after flowing from the first connection point CP1 to the second connection point CP2, the third switching It flows between the drain and source of the element Qc. For this reason, the state of returning to the step-down converter 10 continues. As a result, as compared with the above operation mode m4 (normal state), the direction of the output current Isw is reversed, resulting in an abnormal state.

  Furthermore, at timing t32 in the abnormal state of the operation mode m4, when the first switching element Qa is turned on, the current flowing to the body diode of the second switching element Qb is the drain current of the first switching element Qa. Flowing forward between the sources, the operation mode transitions to "m5".

At this time, a voltage (Vm + Vb _bd ) which is the sum of the voltage having the amplitude level Vm and the forward voltage (Vb _bd ) of the body diode of the second switching element Qb is applied to the first switching element Qa. Become. As a result, at this timing, zero volt switching of the first switching element Qa can not be realized, and a hard switching operation occurs, so that an abnormal state also occurs in the operation mode m5.

  That is, in the operation mode m5 (abnormal state), in the inverter circuit 21, as shown in FIG. 6B, the current flowing in the forward direction between the drain and source of the first switching element Qa is the first The output current Isw (positive) is output to the resonance circuit 22 via the connection point CP1 of

  Then, the current returned from the resonant circuit 22 through the second connection point CP2 flows in the reverse direction between the drain and source of the third switching element Qc as shown in FIG. 6B, and the first switching element It will return to the drain of Qa. As a result, as compared with the above operation mode m5 (normal state), the direction of the output current Isw is reversed, which results in an abnormal state.

  In addition to the above, when the third switching element Qc is turned off at timing t33 in the abnormal state of the operation mode m5, the current flowing in the opposite direction between the drain and source of the third switching element Qc It flows to the body diode of the third switching element Qc. As a result, the path of the current does not transition from the third switching element Qc to the fourth switching element Qd.

That is, in this case, the current flowing in the forward direction between the drain and source of the first switching element Qa is the resonant circuit 2 as the output current Isw (positive) through the first connection point CP1.
It will be output to 2.

  Then, the current returned from the resonant circuit 22 via the second connection point CP2 flows through the body diode of the third switching element Qc and returns to the drain of the first switching element Qa, as in FIG. 6B. become.

  In particular, the current flowing in the forward direction between the drain and the source of the first switching element Qa flows from the first connection point CP1 to the second connection point CP2, and then flows through the body of the third switching element Qc. Therefore, the state of refluxing to the drain of the first switching element Qa continues. In this state, the direction of the output current Isw is reversed as compared with the above-described operation mode m5 (normal state), resulting in an abnormal state.

  Furthermore, when the fourth switching element Qd is turned on at timing t34 in the abnormal state of the operation mode m5, the current flowing in the body diode of the third switching element Qc is the source of the fourth switching element Qd. The current flows between the drains in the forward direction, and the operation mode transitions to "m6".

At this time, a voltage (Vm + _Vcbd ) which is a sum of a voltage having an amplitude level Vm and a forward voltage ( _Vcbd ) of a body diode of the third switching element Qc is applied to the fourth switching element Qd. Become. As a result, at this timing, zero volt switching of the fourth switching element Qd can not be realized, and a hard switching operation occurs, so that an abnormal state also occurs in the operation mode m6.

  That is, in the operation mode m6 (abnormal state), as shown in FIG. 7, the current flowing in the forward direction between the drain and the source of the first switching element Qa is output current through the first connection point CP1. It is output to the resonance circuit 22 as Isw (positive).

  Then, the current returned from the resonant circuit 22 via the second connection point CP2 flows in the forward direction between the drain and source of the fourth switching element Qd as shown in FIG. 7, and the step-down converter 10 (specifically, Will return to the output side capacitor C2). As a result, as compared with the above operation mode m6 (normal state), the direction of the output current Isw is reversed, resulting in an abnormal state.

  Thus, when an arc discharge or the like occurs on the load side, in the operation mode m4, the direction of the current to flow from the inverter circuit 21 to the resonance circuit 22 is reversed from the original direction, and the subsequent operation mode m5 and the operation mode Also in m6, the inverted state of the output current is maintained. As a result, even in the operation mode m5 and the operation mode m6, the abnormal state generated in the operation mode m4 is continued.

  Therefore, as shown in FIG. 5 (G), the waveform of the output current Isw collapses, a hard switching operation occurs, and the switching loss increases, which causes abnormal heat generation and noise increase.

  Once in the abnormal state, the inverted output current does not recover to the normal state unless an external factor or the like occurs, so that the external factor is generated and the direction (positive or negative polarity) of the output current is once When it is reversed, the state continues and it becomes difficult to return to the soft switching operation.

Therefore, the power supply device 1 of the present embodiment is provided with the control circuit 30,
(1) detects the output current output from the inverter circuit 21;
(2) detecting the potential difference between the drain and source of each of the switching elements Qa to Qd;
(3) controlling the turn-off operation of each of the switching elements Qa to Qd based on the detected positive and negative polarities of the output current,
(4) It has a configuration for controlling the turn-on operation of each switching element Qa to Qd based on the positive / negative polarity of the detected output current and the potential difference between the drain and source of each detected switching element There is.

Specifically, the control circuit 30
(A) During a period in which the output current output from the inverter circuit 21 indicates negative, the potential difference between the drain and the source in the switching elements (that is, Qa and Qd) belonging to the first semiconductor switching element group becomes zero. Control the switching elements (Qa or Qd) belonging to the first switching element group in which the potential difference has become zero during the first period indicating the second period,
(B) a second period during which the output current shows a positive value and a period during which the potential difference between the drain and source in the switching elements (that is, Qb and Qc) belonging to the second semiconductor switching element group becomes zero During the period, the semiconductor switching element (Qb or Qc) belonging to the second semiconductor switching element group in which the potential difference becomes zero is controlled to be on.
It has a configuration.

In particular, the control circuit 30
(A) A switching element belonging to the first semiconductor switching element group in which the potential difference becomes zero during the first period, and the switching element (Qb or Qc) belonging to the second semiconductor switching element group is in the OFF operation. Control (Qa or Qd) on,
(B) A switching element belonging to the second semiconductor switching element group in which the potential difference becomes zero during the second period, and the switching element (Qa or Qd) belonging to the first semiconductor switching element group is in the off operation Control (Qb or Qc) on
It has a configuration.

  Therefore, in the case where the power supply device 1 of the present embodiment has such a configuration, the positive and negative polarities of the output current output from the inverter circuit 21 may fluctuate due to an external factor such as a load fluctuation. Even if there is any, it is possible to correct the fluctuation of the positive and negative polarities and to realize zero volt switching accurately by controlling the operation of each switching element Qa to Qd based on the voltage between the source and drain of each switching element. It can be done.

  And since the power supply device 1 of the present embodiment can operate the soft switching normally by preventing the hard switching caused by the external factor, the switching loss occurring in the inverter circuit 21 etc., abnormal heat generation, Also, the generation of spike current and high frequency noise can be reliably reduced or prevented.

[2.3] Configuration and Operation of Control Circuit Next, the configuration and operation of the control circuit 30 according to the present embodiment will be described with reference to FIG. Note that FIG. 8 shows the operation of each of the switching elements Qa to Qd constituting the inverter circuit 21 of the present embodiment, the timing of the output voltage pulse and the output current output from the inverter circuit 21, and each of the switching elements Qa to Qd. 4 is a timing chart showing the relationship between the D-S voltage detection signal Vq and the on-operation permission signal Pq for permitting the turn-on operation of each switching element.

As shown in FIG. 8, the control circuit 30 according to the present embodiment corrects the positive / negative polarity of the output current Isw output from the inverter circuit 21 and ensures that the drain-source voltage of each of the switching elements Qa to Qd is correct. Each switching element Qa to Qd is turned on only under the condition of 0V.

  Specifically, the control circuit 30 includes a resonant capacitor voltage detection circuit unit 31 that detects the voltage of the capacitor C3 that constitutes the resonant circuit 22, a differentiation circuit unit 32 that calculates the current flowing through the capacitor C3, and a series resonant inverter And a voltage detection circuit unit 33 for detecting an output voltage Vo of the device 20.

  Further, the control circuit 30 detects the output current Io of the series resonant inverter device 20 (that is, the output current of the power supply device 1), and the voltage between the drain and source of each of the switching elements Qa to Qd. Drain-to-source voltage detection circuit unit (hereinafter referred to as “DS circuit voltage circuit unit”) 35 for detecting the voltage, an operation circuit unit 36 for performing a predetermined operation, and a drive for driving each of the switching elements Qa to Qd. And a circuit unit 37.

  For example, the resonance capacitor voltage detection circuit unit 31 and the differentiation circuit unit 32 of the present embodiment constitute the current detection means of the present invention, and the D-S voltage detection circuit unit 35 is the potential difference detection means of the present invention. Configure. Further, for example, the arithmetic circuit unit 36 and the drive circuit unit 37 of the present embodiment constitute, for example, the control means of the present invention.

  The resonance capacitor voltage detection circuit unit 31 is connected between both ends of the capacitor C3 constituting the resonance circuit 22, detects a potential difference between both ends of the capacitor C3 (that is, a voltage between both ends), and detects the detected voltage value The signal shown is output to the differentiation circuit unit 32.

  The differentiating circuit unit 32 calculates the current flowing through the capacitor C3 (that is, the output current Isw of the inverter circuit 21) based on the signal supplied from the resonant capacitor voltage detection circuit unit 31, and calculates the value of the calculated current (that is, the current). A signal (hereinafter referred to as a “detected current value signal”) indicating a value is output to the arithmetic circuit unit 36.

  In particular, the differential circuit unit 32 determines the value of the current (ie, the output current Isw) flowing through the capacitor C3 based on the voltage value indicated by the signal supplied from the resonant capacitor voltage detection circuit unit 31 and the following (Expression 1) Calculate

  In the present embodiment, the voltage V across the capacitor C3 having the capacitance C is measured in this manner, and the current value I flowing through the capacitor C3 is calculated using (Equation 1) above. There is. And in this embodiment, by adopting this method, the wiring can be simplified and the miniaturization of the device can be realized.

  Also, instead of the above calculation method, there is also a method of directly measuring the value of the current flowing through the capacitor C3 using a current transformer or a Hall element. However, whichever method is used, the wiring for the current detection device becomes complicated, the design becomes complicated, and the size of the device itself becomes large, so it is difficult to miniaturize the device. As a result, in the present embodiment, the above method is adopted.

The voltage detection circuit unit 33 is connected to the secondary side of the transformer T1, detects a voltage difference between both ends of the transformer T1, that is, the value of the output voltage Vo of the series resonant inverter device 20, and detects the detected output voltage A signal indicating the value of Vo is output to the arithmetic circuit unit 36.

  The current detection circuit unit 34 is connected to one end of the secondary side of the transformer T1, detects the value of the output current Io of the series resonant inverter device 20, and outputs a signal indicating the value of the detected output current Io to the arithmetic circuit unit Output to 36.

  The D-S voltage detection circuit unit 35 detects the voltage (that is, the potential difference) between the drain electrode and the source electrode of each of the switching elements Qa to Qd constituting the inverter circuit 21 and detects each of the detected D-S The inter-voltage detection signals Vqa, Vqb, Vqc and Vqd are output to the arithmetic circuit unit 36.

  The arithmetic circuit unit 36 is an inverter based on the detected current value signal output from the differentiating circuit unit 32 and the D-S voltage detection signals Vqa to Vqd output from the D-S voltage detection circuit unit 35. An operation OFF permission signal for controlling the turn-off operation of each switching element Qa to Qd of circuit 21 and an operation ON permission signal for controlling the turn-on operation of each switching element Qa to Qd are generated.

  Then, the arithmetic circuit unit 36 outputs the generated off operation permission signal and the generated on operation permission signal to the drive circuit unit 37.

  Specifically, the arithmetic circuit unit 36 generates the first switching element Qa and the fourth switching element Qd while the current value (that is, the value of the output current Io) indicated by the detected current value signal is positive. The arithmetic processing for turning off is performed, and the arithmetic processing for turning off the second switching element Qb and the third switching element Qc is performed while the current value is negative.

In particular, as shown in FIG. 8C, the arithmetic circuit unit 36 of this embodiment is
(A1) “H” in a period in which the current value (ie, the value of the output current Io) indicated by the detected current value signal is positive (ie, the period of ti2 to ti3 and ti6 to ti7 shown in FIG. 8) A signal which is at the L level and is at the "L" level in another period is driven as a first off operation permission signal "I +" which permits the first switching element Qa and the fourth switching element Qd to be turned off. Output to the circuit unit 37,
(A2) The current value indicated by the detected current value signal is at the “H” level in the negative period (that is, the periods ti4 to ti5 and ti8 to ti9 shown in FIG. 8), and The signal which is at the “L” level in the period is output to the drive circuit unit 37 as a second off operation permission signal “I−” that permits the second switching element Qb and the third switching element Qc to be turned off.

  Note that ti1 to ti9 shown in FIG. 8C are timings before the polarity of the output current Isw is reversed, and when the switching elements Qa to Qd are not yet implemented at this time, they are for forced implementation. It is timing (switching time limit).

On the other hand, as shown in FIGS. 8C and 8D, the arithmetic circuit unit 36 of the present embodiment performs arithmetic processing for turning on the first switching element Qa or the fourth switching element Qd,
(B1) The voltage detection signal between D and S of the switching element Qa or Qd to be turned on during the period when the current value (that is, the value of the output current Io) indicated by the detection current value signal is negative In the period (hereinafter also referred to as the “first period”),
(B2) D-S of the switching element Qb or Qc that turns on the arithmetic processing for turning on the second switching element Qb or the third switching element Qc during the period when the current value is positive It is executed during a period (hereinafter also referred to as a “second period”) in which the inter-voltage detection signal is “0 V”.

In particular, as shown in FIG. 8E, the arithmetic circuit unit 36 of the present embodiment has the “H” level in the first period and the period in which the second switching signal Vgb is at the “L” level. In the other period, the signal having “L” level is output to the drive circuit unit 37 as a first on-operation permission signal Pqa _on which permits the first switching element Qa to be turned _on .

In addition, as shown in FIG. 8E, arithmetic circuit unit 36 has “H” level in the second period, and in a period in which first switching signal Vga is at “L” level, and The signal which becomes “L” level in other periods is output to the drive circuit unit 37 as a second on-operation permission signal Pqb _on which permits the turn-on operation of the second switching element Qb.

Then, as shown in FIG. 8E, arithmetic circuit unit 36 has “H” level in the second period and the period in which fourth switching signal Vgd is “L” level, and a signal which becomes "L" level in the period, as a third oN operation permission signal PQC _on to allow turn-on operation of the third switching element Qc, and outputs to the drive circuit section 37.

Furthermore, as shown in FIG. 8E, arithmetic circuit unit 36 has “H” level during the first period and during the period when third switching signal Vgc is “L” level, and The signal which becomes “L” level in the period is output to the drive circuit unit 37 as a fourth on-operation permission signal Pqd _on for permitting the turn-on operation of the fourth switching element Qd.

  As shown in FIGS. 8A and 8B, the drive circuit unit 37 generates each of the switching signals Vga to Vgd based on the off operation permission signal and the on operation permission signal supplied from the arithmetic circuit unit 36. And supplies the generated switching signals Vga to Vgd to the gates of the switching elements Qa to Qd of the inverter circuit 21.

  In particular, the drive circuit unit 37 controls the turn-off of the first switching element Qa and the fourth switching element Qd only while the first off-operation permission signal "I +" is input.

  The drive circuit unit 37 controls the turn-off of the second switching element Qb and the third switching element Qc only while the second off-operation permission signal I- is at the "H" level.

That is, the drive circuit unit 37
(1) Control the turn-on of the first switching element Qa only while the first on-operation permission signal Pqa _on is input,
(2) Control the turn-on of the second switching element Qb only while the second on-operation permission signal Pqb _on is input,
(3) Control turning _on of the third switching element Qc only while the third on-operation permission signal Pqcon is being input,
(4) The turn- _on of the fourth switching element Qd is controlled only while the fourth on-operation permission signal Pqd _on is input.

[3] Verification Result of Influence of Duty Ratio on Output Current of Inverter Circuit Next, referring to FIG. 9, the influence of the duty ratio of the output voltage pulse of the inverter circuit 21 on the output current Isw is verified.

  9 shows the timings of the output voltage pulse and the output current output from the inverter circuit 21 and the switching elements Qa when the duty ratio of the output voltage pulse of the inverter circuit 21 of the present embodiment is 70%. It is a timing chart which shows the relation between the voltage detection signal Vq between D-S of -Qd and the on-operation permission signal Pq which permits the turn-on operation of the switching element Qa.

  Although the case where the duty of the output voltage pulse is 100% has been described as an example, the power supply device 1 of the above-described embodiment has been described as an example where the duty of the output voltage pulse is 70%. , It was examined whether the inverter circuit 21 operates properly.

  As shown in FIG. 8, even when the duty of the output voltage pulse is 70%, the waveform of the output current Isw maintains a sine wave as in the case where the duty is 100%. It has been proved that the inverter circuit 21 of the present invention operates properly.

  Therefore, in the present embodiment, the hard switching operation is prevented regardless of the duty of the output voltage pulse by controlling the turn-on timing and the turn-off timing of each switching element Qa to Qd as described above. The reduction can be achieved.

[4] Others In the above embodiment, the resonance type inverter device of the present invention is the power supply device 1 including the series resonance type inverter device 20 or the step-down converter 10, the series resonance type inverter device 20, and the control circuit 30. And although the case where a power supply device was applied was explained, the control device of this application may be applied as a control device which has the control circuit 30 which controls series resonance type inverter device 20.

  Also, in this case, the control device having the control circuit 30 is configured by a computer having a storage device (such as a hard disk), a CPU and a memory (ROM or RAM), and control for causing the computer to function as a control device. It is also possible to realize by a program.

DESCRIPTION OF SYMBOLS 1 ... Power supply device 10 ... Step-down converter 20 ... Series resonance type inverter device 21 ... Inverter circuit 22 ... Resonant circuit 30 ... Control circuit 31 ... Resonant capacitor voltage detection circuit part 32 ... Differentiation circuit part 33 ... Voltage detection circuit part 34 ... Current detection Circuit part 35: Voltage detection circuit part 36 between D and S: Operation circuit part 37: Drive circuit part

Claims (8)

A full bridge type inverter circuit having a plurality of semiconductor switching elements and outputting voltage pulses whose positive and negative polarities periodically change by controlling the semiconductor switching elements;
A resonant circuit comprising an inductor and a capacitor connected in series to an output end of the inverter circuit;
Current detection means for detecting an output current output from the inverter circuit;
Potential difference detection means for detecting the potential difference between the drain and the source of each of the plurality of semiconductor switching elements;
Control means for controlling the on operation and the off operation of each of the semiconductor switching elements based on the positive / negative polarity of the detected output current and the potential difference between the drain and source of each of the detected semiconductor switching elements;
What is claimed is: 1. A resonant inverter device comprising: In the resonance type inverter device according to claim 1,
The control means
The off operation of each semiconductor switching element is controlled based on the positive or negative polarity of the detected output current, and the positive / negative polarity of the detected output current and the drain-source of each of the detected semiconductor switching elements The resonant inverter device which controls the on operation of each said semiconductor switching element based on the electrical potential difference between them. In the resonance type inverter device according to claim 2,
The inverter circuit is
A first semiconductor switching device group including two semiconductor switching devices that output the positive voltage pulse when they are simultaneously turned on;
A second semiconductor switching element group including two semiconductor switching elements including the semiconductor switching elements different from the first semiconductor switching element group and outputting the negative voltage pulse when turned on simultaneously;
Equipped with
The control means
The potential difference is zero during a first period in which the potential difference between the drain and the source in the semiconductor switching element belonging to the first semiconductor switching element group is zero, in a period in which the output current shows a negative value. Controlling the semiconductor switching elements belonging to the first semiconductor switching element group
The potential difference is zero during a second period in which the potential difference between the drain and the source in the semiconductor switching element belonging to the second semiconductor switching element group is zero, in a period in which the output current is positive. Controlling the semiconductor switching elements belonging to the second semiconductor switching element group
Resonance type inverter device. In the resonance type inverter device according to claim 3,
The control means
The semiconductor switching elements belonging to the first semiconductor switching element group in which the potential difference becomes zero are turned on during the first period, and the semiconductor switching elements belonging to the second semiconductor switching element group are in the off operation. To control
The semiconductor switching elements belonging to the second semiconductor switching element group in which the potential difference becomes zero are turned on during the second period, and the semiconductor switching elements belonging to the first semiconductor switching element group are in the off operation. To control
Resonance type inverter device. The resonance type inverter device according to any one of claims 1 to 4.
The current detection means
Detecting a potential difference at both ends of a capacitor belonging to the resonant circuit;
A resonant inverter device, which differentiates the detected potential difference to detect the output current.   A power supply device, comprising: the resonant inverter device according to any one of claims 1 to 5; and a step-down converter connected to an input terminal of the inverter circuit. A full bridge type inverter circuit which has a plurality of semiconductor switching elements and outputs voltage pulses whose positive and negative polarities periodically change by controlling the semiconductor switching elements, and is connected in series to the output terminal of the inverter circuit A control circuit for controlling a resonant inverter device comprising:
A resonant circuit comprising an inductor and a capacitor connected in series to an output end of the inverter circuit;
Current detection means for detecting an output current output from the inverter circuit;
Potential difference detection means for detecting the potential difference between the drain and the source of each of the plurality of semiconductor switching elements;
Control means for controlling the on operation and the off operation of each of the semiconductor switching elements based on the positive / negative polarity of the detected output current and the potential difference between the drain and source of each of the detected semiconductor switching elements;
A control device comprising: A full bridge type inverter circuit which has a plurality of semiconductor switching elements and outputs voltage pulses whose positive and negative polarities periodically change by controlling the semiconductor switching elements, and is connected in series to the output terminal of the inverter circuit A control program for controlling a resonant inverter device comprising: a resonant circuit comprising the integrated inductor and capacitor
Computer,
A resonant circuit comprising an inductor and a capacitor connected in series to an output end of the inverter circuit;
Current detection means for detecting an output current output from the inverter circuit;
Potential difference detection means for detecting the potential difference between the drain and the source of each of the plurality of semiconductor switching elements;
Control means for controlling the on / off operation of each of the semiconductor switching elements based on the positive / negative polarity of the detected output current and the potential difference between the drain and source of each of the detected semiconductor switching elements;
A control program characterized in that it functions as:

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