JP2019102611A - Interface unit and semiconductor device - Google Patents

Abstract

To provide an interface unit which can easily mount a sensor thereon with less space.SOLUTION: An interface unit includes: a plate-like bus bar that forms a cross-sectional shape sandwiching an U-shaped portion specified by opposite first and second erected portions 37d1 and 37d2 in its center, of which each flat surface portion on both ends are used as bus bar connection parts connected to a semiconductor unit; a support part 30b that seals the inside of the first and second erected parts with a resin, has a rectangular parallelepiped portion of which two surfaces parallel to the first and second erected portions are used as side surfaces, and has a cavity part 40b for sensor provided in the resin along the first erected portion; a sensor 60 inserted into the cavity part 40b for sensor; a flexible printed board having the sensor provided on the end; a wire 60a for sensor which is provided on the flexible printed board and is connected to the sensor; and a circuit board 70 for sensor arranged on the bottom surface side of the support part 30b.SELECTED DRAWING: Figure 6

Description

  The present invention relates to a technique for connecting a semiconductor device in which a plurality of semiconductor modules are connected in parallel and an external device through an interface unit.

  Semiconductor devices, particularly power semiconductor devices (power semiconductor devices), are soldered or screwed to an external device such as a general-purpose inverter via a printed board or a bus bar provided on the external device side. Connected by As a technology for connecting a semiconductor device and an external device, Patent Document 1 discloses an interface unit.

  In addition, as a technique related to current measurement of a bus bar through which a main current of a semiconductor module flows, Patent Document 2 discloses a plurality of bus bars, a plurality of current sensors respectively provided for the plurality of bus bars, and an output of a current sensor A current detection device is disclosed that includes a processing unit that receives a current value flowing to a corresponding bus bar and a flexible substrate provided with a wire that electrically connects the processing unit and the current sensor. The current can be measured with high accuracy by using a coreless current sensor having no magnetic core as the current sensor.

  Furthermore, Patent Document 3 includes a plurality of current paths installed in parallel, and a magnetic detection element provided corresponding to each current path and detecting the strength of the magnetic field generated by the current flowing through each current path. A current detection device is disclosed in which a magnetic detection unit and a part of a plurality of current paths are housed in a mold package.

Japanese Patent Application No. 2017-075243 Unexamined-Japanese-Patent No. 2006-1929 Unexamined-Japanese-Patent No. 2016-99292

  However, in the technique disclosed in Patent Document 1, mounting of the current sensor has not been considered. On the other hand, although the current sensor which measures the current which flows through a bus bar is indicated by patent documents 2, arrangement of the current sensor to a semiconductor module, and the concrete structure were not considered. In addition, in the technology disclosed in Patent Document 3, it is necessary to connect a current detection device between the semiconductor module and the connecting device such as a motor, but in addition to the main current wiring, wiring of sensor wiring etc. It is difficult and requires space for the current detection device. This causes problems such as an increase in the number of installation steps.

  The present invention was made in view of the above problems, and an object of the present invention is to provide an interface unit capable of easily mounting a sensor with a small space and a semiconductor device using the interface unit.

  In order to solve the above problems, a first aspect of an interface unit according to the present invention is an interface unit connected to a semiconductor unit, wherein (a) defined by opposing first and second rising portions The U-shaped part is held in the center, and both ends connected to the U-shaped part have a cross-sectional shape extending in the same plane in the opposite direction, and each of the planar parts of the both ends is connected to the semiconductor unit A rectangular bus-bar having a plate-like bus bar as a part, and (b) the first and second rising portions are internally sealed with a resin, and two sides parallel to the first and second rising portions are side surfaces A support portion having a portion, and a sensor cavity portion provided in a resin along the first rising portion of the rectangular parallelepiped portion; (c) a sensor inserted into the sensor cavity portion; an end portion of the sensor Flexible printed circuit board provided in Has a wiring electrically connected to a sensor is patterned sensor fine the flexible printed circuit board, and summarized in that and a circuit board for sensor disposed on the bottom side of the support portion.

  According to a first aspect of a semiconductor device of the present invention, a semiconductor chip is mounted, and a plurality of parallel semiconductor units and an interface unit according to the first aspect connected to the plurality of semiconductor units are provided. It is a summary.

  According to the interface unit of the present invention and the semiconductor device using the interface unit, the sensor can be easily mounted in a space-saving manner.

FIG. 1 is a perspective view (bird's-eye view) schematically showing an outline of a configuration of a semiconductor device according to an embodiment of the present invention. FIG. 2 is an exploded perspective view schematically showing the outline of the configuration of the semiconductor device according to the embodiment of the present invention. FIG. 3 is a plan view schematically showing the top of the configuration of the interface unit according to the embodiment of the present invention. FIG. 4 is a plan view schematically showing the configuration of the flexible substrate disposed on the lower surface of the interface unit according to the embodiment of the present invention. FIG. 5 is a plan view showing a state in which the flexible substrate is disposed on the lower surface of the interface unit according to the embodiment of the present invention. 6 is a cross-sectional view as viewed from the direction of the line VI-VI in FIG.

  Hereinafter, embodiments of the present invention will be described. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimension, the ratio of the thickness of each device and each member, and the like are different from actual ones. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios among the drawings are included.

  Further, the directions of “left and right” and “upper and lower” in the following description are merely definitions for convenience of description, and do not limit the technical idea of the present invention. Thus, for example, if the paper is rotated 90 degrees, "left and right" and "up and down" are read interchangeably, and if the paper is rotated 180 degrees, "left" is "right" and "right" is "left". Of course it will be.

  The semiconductor device according to the embodiment of the present invention is, as shown in FIG. 1, a pair of two semiconductor units 10 and 20 arranged in parallel on a metal base plate 100, and semiconductor units 10 and 20. And an interface unit 30 provided across the upper side of the above.

  As can be seen from the exploded perspective view of FIG. 2, the interface unit 30 located on the upper side of FIG. 2 connects the corresponding terminals of the semiconductor unit 10 located on the lower side of FIG. 2 and the semiconductor unit 20 in parallel. The semiconductor device shown in FIG. 1 is capable of screw (bolt) connection with an apparatus-side bus bar provided on the external apparatus side such as a general-purpose inverter via the interface unit 30.

  Each of the pair of semiconductor units 10 and 20 has a rectangular parallelepiped shape, and the semiconductor modules on which the power semiconductor chips are mounted are sealed inside by the sealing resin 10 a. As shown in FIG. 2, the pair of semiconductor units 10 and 20 has the long sides of the rectangle adjacent in parallel, and are arranged in parallel along the short side direction of each. Since members of the same name have the same structure and function between the pair of semiconductor units 10 and 20, hereinafter, the semiconductor unit 10 shown on the left side in FIG. 2 will be mainly described as a representative example, and the overlapping description will be appropriately omitted.

Although illustration is omitted, inside the sealing resin 10a of the semiconductor unit 10, a power semiconductor chip forming an upper arm on the positive electrode side and a power semiconductor chip forming a lower arm on the negative electrode side are provided. The semiconductor unit 10 is a so-called "2 in 1 type". However, the semiconductor unit of the present embodiment is not limited to the 2 in 1 type semiconductor unit, and may be a 1 in 1 type, a 6 in 1 type, or the like.
The power semiconductor chip employs a transistor such as a field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The transistor may have a vertical structure or a horizontal structure. Furthermore, a diode such as a freewheeling diode (FWD) may be provided.
Hereinafter, the case of 2 in 1 type which employ | adopted MOSFET as the semiconductor unit 10 is demonstrated.

  As shown in FIG. 2, at the center of the upper surface of the sealing resin 10a of the semiconductor unit 10, rectangular flat plate-like positive electrode terminals 15c, negative electrode terminals 17c and output terminals 19c are equally spaced in a plane pattern. The respective longitudinal directions are provided to extend along the short side direction of the semiconductor unit 10.

  The positive electrode terminal 15c, the negative electrode terminal 17c, and the output terminal 19c are all made of copper (Cu), aluminum (Al) or the like and have conductivity. At the center of each of the positive electrode terminal 15c, the negative electrode terminal 17c, and the output terminal 19c, a through hole concentric with the hole of the nut, which is disposed above the lower sealing resin 10a, is provided. .

  The positive electrode terminal 15c, the negative electrode terminal 17c, and the output terminal 19c are joined to the drain connection terminal 15a, the source connection terminal 17a, and the output connection terminal 19a at both ends on the lower surface side. Each of the drain connection terminal 15a, the source connection terminal 17a, and the output side connection terminal 19a is a rod-like terminal extending from the semiconductor module sealed inside the sealing resin 10a of the semiconductor unit 10.

  The drain connection terminal 15a is joined to the positive electrode terminal 15c on the sealing resin 10a by welding or soldering. Similarly, the source connection terminal 17a is joined to the negative electrode terminal 17c on the sealing resin 10a, and the output side connection terminal 19a is joined to the output terminal 19c on the sealing resin 10a by welding or soldering. The drain connection terminal 15a supplies a current to the drain electrode of the power semiconductor chip of the upper arm mounted on the semiconductor module. The source connection terminal 17a allows current to flow from the source electrode of the power semiconductor chip of the lower arm to the outside. The output-side connection terminal 19a is electrically connected to the source electrode of the power semiconductor chip of the upper arm and the drain electrode of the power semiconductor chip of the lower arm to flow an output current.

  On the upper surface of the sealing resin 10a of the semiconductor unit 10, at both ends in the longitudinal direction, mounting holes into which screws or the like for mounting the semiconductor unit 10 to other members or devices are inserted are provided. Around the mounting hole, there is provided a side wall which rises upward from the upper surface of the sealing resin 10a. The side walls form U-shaped ridges 16 and 18 so that the wall surfaces surround the mounting holes in a planar pattern.

  The upper ends of the source signal terminal 11 for the upper arm and the source signal terminal 13 for the lower arm, which extend linearly from the semiconductor module, are shown on both sides of the flange portion 16 and at the center position. There is. The source signal terminal 11 for the upper arm and the terminal 13 for the source signal for the lower arm are provided symmetrically on the same straight line along the direction in which the pair of semiconductor units 10 and 20 are arranged centering on the ridge portion 16 ing. The upper arm source signal terminal 11 and the lower arm source signal terminal 13 detect respective source voltages.

  Further, the upper end of each of the gate signal terminal 12 on the left side and the terminal 14 for the gate signal on the right side extending linearly from the semiconductor module is shown at positions closer to the end portions on both sides of the flange portion 16. The left gate signal terminal 12 and the right gate signal terminal 14 are symmetrically provided on the same straight line along the direction in which the pair of semiconductor units 10 and 20 are arranged around the ridge portion 16. The left gate signal terminal 12 and the right gate signal terminal 14 control ON / OFF of the power semiconductor chip.

<Interface unit>
As shown in FIGS. 1 to 3, the interface unit 30 has a shape similar to an inverted T-shape in a plane pattern by a storage portion 30 a and a support portion 30 b having a rectangular parallelepiped portion. The “inverted T-shaped” is configured by attaching the lower end in the longitudinal direction of the support portion 30b in the direction orthogonal to the center in the longitudinal direction (horizontal direction) of the storage portion 30a in FIG. The storage portion 30a is shaped like a double bridge in which two semicircular arch-shaped notches 30a1 and 30a2 are joined below the rectangular parallelepiped portion in the top view of FIG. As can be seen from the perspective view, it has a box-like shape as a whole.

-Storage unit-
The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are concentrated at equal intervals at the center of the flat upper surface of the housing portion 30a. It is arranged close. The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are disposed so as to be positioned at four corners of a square in a plane pattern. The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are bar-shaped as shown in FIG. It extends vertically upward to the

  The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 are respectively inserted into the housing 30a. In the first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34, the lower end of the storage portion 30a is provided inside the storage portion 30a. Connected to the internal wiring. The first source signal terminal 31, the first gate signal terminal 32, the second source signal terminal 33, and the second gate signal terminal 34 constitute an external connection control terminal.

  The first source signal terminal 31 is simultaneously connected to the source signal terminal 11 for the upper arm of each of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the storage portion 30a. The first gate signal terminals 32 are simultaneously connected to the gate signal terminals 12 on the left side of each of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the storage portion 30a. The second source signal terminal 33 is simultaneously connected to the source signal terminal 13 for the lower arm of each of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the storage portion 30a. The second gate signal terminal 34 is simultaneously connected to the gate signal terminal 14 on the right side of each of the pair of semiconductor units 10 and 20 via the corresponding internal wiring inside the housing portion 30a.

  As shown in FIG. 3, a central region that can be regarded as substantially rectangular is provided between the two semicircular arch-shaped notches 30a1 and 30a2 of the storage portion 30a. A first source signal terminal 31, a first gate signal terminal 32, a second source signal terminal 33, and a second gate signal terminal 34 are provided on the upper surface of the central region. The semicircular arched shape of the notches 30a1 and 30a2 of the storage portion 30a is along the arc of the ridge portion 16 of the sealing resin 10a of the semiconductor unit 10. As shown in FIG. 3, the width measured in the vertical direction at the top of the semicircular arch is the narrowest. That is, when looking between the end portions along the horizontal direction in FIG. 3, by providing the notches 30a1 and 30a2, the region where the width along the short side direction of the storage portion 30a becomes the narrowest sandwiches the central region It is formed of

  As shown in FIG. 2, concave portions are provided symmetrically on both sides of each notch 30 a 1 of the storage portion 30 a. Similarly, concave portions are provided symmetrically on both sides of the notch 30a2. The respective end portions of the first source signal internal interconnection 91 and the first gate signal internal interconnection 92 are exposed inside the concave portion on the left side of the left notch 30a1.

  As can be seen from FIG. 3, another end of the first source signal interconnection 91 and another of the first gate signal interconnection 92 are also provided inside the recess on the right side of the left notch 30a1. The ends are exposed as well. Similarly, the respective end portions of the second source signal internal wiring 93 and the second gate signal internal wiring 94 are exposed inside the recess on the left side of the right notch 30a2. Further, the other end of the second internal wiring for source signal 93 and the other end of the second internal wiring for gate signal 94 are exposed inside the recess on the right side of the notch 30a2 on the right side. It is provided.

  As can be seen from FIG. 2, in the lower part of the recess provided with the first source signal internal interconnection 91 and the first gate signal internal interconnection 92, a step having a height difference is provided. The end portion of the first source signal internal wiring 91 is disposed below the step provided in the recess on the left side of the notch 30a1, and the end portion of the first gate signal internal wiring 92 is disposed above the step. It is arranged. A through hole (through hole) is provided at each end of the step. An upper arm source signal terminal 11 extending from the lower semiconductor unit 10 in FIG. 2 is inserted into the through hole of the first source signal internal wiring 91. Further, the upper end of the left gate signal terminal 12 is inserted into the through hole of the first gate signal internal wiring 92.

  Although not shown, the first source signal internal wiring 91, the first gate signal internal wiring 92, and the second source signal are connected to the inside of the housing portion 30a at each end. An internal wiring 93 and a second internal wiring for gate signal 94 are arranged.

  The first source signal internal wiring 91, the first gate signal internal wiring 92, the second source signal internal wiring 93, and the second gate signal internal wiring 94 are mutually connected inside the storage portion 30a. They are stacked vertically separated. The source signal terminal 11 for the upper arm of the semiconductor unit 10, the terminal 12 for the gate signal on the left side, the terminal 13 for the source signal for the lower arm, and the terminal 14 for the gate signal on the right all use metal such as Cu. It can be made of a conductive material.

  The first source signal internal interconnection 91, the first gate signal internal interconnection 92, the second gate signal internal interconnection 94, and the second source signal internal interconnection 93 are arranged in this order on the inner side of the housing portion 30a. Are arranged from the bottom to the top. An insulating resin or the like is provided between each of the first source signal internal interconnection 91, the first gate signal internal interconnection 92, the second source signal internal interconnection 93, and the second gate signal internal interconnection 94. Is filled.

  In the lower part of the housing portion 30a, the source signal terminal 11 for the upper arm, the terminal 12 for the gate signal on the left side, the terminal 13 for the source signal for the lower arm, and the terminal 14 for the gate signal on the right Through holes are provided corresponding to the positions. Through holes 91 h and 92 h shown in FIG. 5 are provided concentrically with the through holes respectively provided at the end portions of first source signal internal interconnection 91 and first gate signal internal interconnection 92. It is done. Through holes 93 h and 94 h shown in FIG. 5 are provided concentrically with the through holes respectively provided at the end portions of second source signal internal wiring 93 and second gate signal internal wiring 94, respectively. It is done.

  The source signal terminals 11 and 21 for the upper arms of the pair of left and right semiconductor units 10 and 20 are collectively connected by the left branch portion and the right branch portion of the first source signal internal wiring 91 of the storage portion 30a. Ru. In addition, the source signal terminals 11 and 21 for the upper arm are electrically connected to the first source signal terminal 31 extending upward outside the storage portion 30 a via the central branch portion of the first source signal internal wiring 91. Connected to

  The left side gate signal terminals 12 and 22 of the pair of left and right semiconductor units 10 and 20 are collectively connected by the left side branch portion and the right side branch portion of the first gate signal internal wiring 92 of the storage portion 30a. Ru. Further, the left gate signal terminals 12 and 22 are electrically connected to the first gate signal terminal 32 extending upward outside the housing portion 30a via the central branch portion of the first gate signal internal wiring 92. Be done.

  In addition, the source signal terminals 13 and 23 for the lower arms of the pair of left and right semiconductor units 10 and 20 are grouped together by the left branch portion and the right branch portion of the second source signal internal wiring 93 of the storage portion 30a. It is connected. In addition, the source signal terminals 13 and 23 for the lower arm are electrically connected to the second source signal terminal 33 extending upward outside the housing portion 30a via the central branch portion of the second source signal internal wiring 93. Connected to

  The right side gate signal terminals 14 and 24 of the pair of left and right semiconductor units 10 and 20 are collectively connected by the left side branch portion and the right side branch portion of the second gate signal internal wiring 94 of the storage portion 30a. Ru. The right side gate signal terminals 14 and 24 are electrically connected to the second gate signal terminal 34 extending upward outside the housing portion 30 a through the central branch portion of the second gate signal internal wiring 94. Be done.

-Support part-
As shown in FIGS. 1 to 3, in the support portion 30 b of the interface unit 30, the positive electrode bus bar 35, the negative electrode bus bar 37, and the output bus bar 39 each made of a conductive plate member such as Cu. Is provided. As shown in the cross-sectional view of FIG. 6, the plus pole bus bar 35, the minus pole bus bar 37, and the output bus bar 39 are laterally symmetrical bent through four bending portions 4a, 4b, 4c and 4d bent at right angles. Right angle ohm (Ω) type. The Ω type is bent between the horizontal first region and the vertical second region, between the second region and the horizontal third region, the bending portion 4b, and between the third region and the vertical fourth region. It is comprised via the bending part 4d between the part 4c 4th area | region and the horizontal 5th area | region. The first area and the fifth area located at both ends of the right angle Ω-shape extend in the same plane in opposite directions. As shown in FIG. 6, the second region serving as the first rising portion and the fourth region serving as the second rising portion opposite to the first rising portion are inverted U-shaped with the third region interposed therebetween. (U-shaped part) is composed. A U-shaped portion composed of the second to fourth regions is held at the center, and the first and fifth regions located at both ends extend in the same plane in the opposite direction, and the Ω defined by the four right angles It has a cross-sectional shape of the mold. Although FIG. 6 shows a cross-sectional view of negative pole bus bar 37 as an example, positive pole bus bar 35 and output bus bar 39 also have the same cross-sectional shape as negative pole bus bar 37. In addition, although the bending parts 4a, 4b, 4c, and 4d are demonstrated as a right-angled symmetrical right angle omega type which bent at four right angles, cross-sectional shape is not limited. For example, the second area and the fourth area may rise at an acute angle or an obtuse angle with respect to the horizontal first area and the fifth area, and may not be symmetrical. In addition, part or all of the second area and the fourth area may be formed of a curved surface. That is, the first area and the fifth area may be substantially on the same plane, and the third area may be substantially horizontal to the first area and the fifth area, and may be located on different upper surfaces.

  A first region in which the main surface extends horizontally from the support portion 30b at the left end of the Ω type is a negative electrode bus bar connection portion 37a fixed and electrically joined to the negative electrode terminal 17c provided in the semiconductor module 10. A fifth region in which the main surface extends horizontally from the support portion 30b at the right end of the Ω shape is a negative electrode bus bar connection portion 37b fixed and electrically joined to the negative electrode terminal 17c provided in the semiconductor module 20. Further, a third region which is an Ω-type ceiling portion of the negative pole bus bar 37 is a negative pole external connection portion 37 c electrically connected by being fixed to the device side bus bar of the external device by a screw or the like.

  The negative pole external connection portion 37c is exposed on the upper surface of the support portion 30b, and has a through hole for connection to an external device at the center of the main surface. The left and right negative pole bus bar connecting portions 37a and 37b extend horizontally outward from the outer surface of the support portion 30b, and a through hole for connection with the semiconductor unit 10 is provided at the center of the main surface.

  As shown in FIG. 6, between the negative pole bus bar connecting portion 37a (first region) and the negative pole external connecting portion 37c, the first rising portion is parallel to the side surface of the rectangular parallelepiped portion of the support portion 30b. A sidewall region 37d1 (second region) is provided. The sidewall region 37d1 is resin-sealed in the resin 30d of the main body of the support portion 30b and integrally fixed. The boundary between the negative pole bus bar connecting portion 37a and the side wall region 37d1 is bent about 90 degrees with respect to the main surface of the negative pole bus bar connecting portion 37a in the bending portion 4a. The boundary between the negative pole external connection portion 37c (third region) and the sidewall region 37d1 is bent at about 90 degrees with respect to the main surface of the sidewall region 37d1 in the bent portion 4b, on the opposite side to the bent portion 4a. The sidewall region 37d1 is resin-sealed in the resin 30d of the main body of the support portion 30b and integrally fixed.

  A side wall region 37d2 (fourth region) which is a second rising portion is provided between the negative pole bus bar connection portion 37b and the negative pole external connection portion 37c in parallel with the side surface of the rectangular parallelepiped portion of the support portion 30b. ing. The side wall region 37d2 is also resin-sealed in the resin 30d of the main body of the support portion 30b and integrally fixed. The boundary between the negative pole bus bar connection portion 37b (fifth region) and the side wall region 37d2 is bent about 90 degrees with respect to the main surface of the negative pole bus bar connection portion 37b in the bending portion 4d. The boundary between the negative pole external connection portion 37c and the side wall region 37d2 is bent to the opposite side of the bent portion 4d by about 90 degrees with respect to the main surface of the side wall region 37d2 in the bent portion 4c.

  Similarly, plus pole bus bar connecting parts 35a and 35b are provided at both ends of plus pole bus bar 35, plus pole external connecting part 35c is provided at the center, plus pole bus bar connecting part 35a and plus pole external connecting part 35c. Side wall regions are provided between and between the plus pole bus bar connecting portion 35b and the plus pole external connecting portion 35c in parallel with the side surface of the rectangular parallelepiped portion of the support portion 30b. Further, output busbar connection portions 39a and 39b are provided at both ends of the output busbar 39, an output external connection portion 39c is provided at the center, and the output busbar connection portion 39a and the output external connection portion 39c are provided. Between and between the output bus bar connection portion 39b and the output external connection portion 39c, side wall regions are provided in parallel with the side surfaces of the rectangular parallelepiped portion of the support portion 30b. The respective structures of the positive electrode bus bar 35 and the output bus bar 39 are equivalent to those of the negative electrode bus bar 37, and therefore redundant description will be omitted.

  As shown in FIG. 6, resin 30 d on the lower surface side of support portion 30 b along at least a part of sidewall region 37 d 1 (second region) which is a first rising portion in the vicinity of bent portion 4 a of negative pole bus bar 37. It has a sensor cavity 40b that exposes the open end inside. Similarly, as shown in FIG. 5, the hollow portion for sensor along at least a part of the side wall region which is a rising portion in the vicinity of the bent portion 4a of the output bus bar 39 when viewed from the lower surface side of the support portion 30b. It has an open end of 40a. Furthermore, when viewed from the lower surface side of the support portion 30b, the open end of the sensor hollow portion 40c is provided along at least a part of the side wall region in the vicinity of the bent portion 4a of the positive electrode bus bar 35. Although not shown, a space of a nut glove for accommodating a nut is provided in the main body of the support portion 30b between the left and right side wall regions of each bus bar.

  As shown in FIG. 5, the sensor circuit board 70 is disposed in the circuit board storage portion 50 provided on the lower surface of the support portion 30 b. As shown in FIG. 4, the sensor circuit board 70 is in the shape of a band, the current sensor 60 is mounted at one end thereof, and the external connection portion 71 having a plurality of connection terminals is mounted at the other end. In addition, a plurality of sensor wires 60 a that electrically connect the current sensor 60 and the external connection portion 71 are formed along the longitudinal direction of the sensor circuit board 70. The sensor wiring 60a mainly includes a pattern along the longitudinal direction of the rectangular parallelepiped portion of the support portion 30b. The sensor circuit board 70 has a structure in which the sensor wiring 60a is formed of metal foil such as copper on a flexible printed board made of flexible insulating material such as polyimide, and has a thickness of, for example, 50 μm to 60 μm. Have.

  The current sensor 60 of the sensor circuit board 70 can be accommodated in each of the sensor cavity portions 40a, 40b and 40c. For example, the current sensor 60 is inserted into the sensor cavity 40 b and bent at the bending portion 61. By the bending at the bending portion 61, the restoring force (elastic force) of the flexible printed circuit constituting the sensor circuit board 70 acts on the side wall region 37d1. As a result, as shown in FIG. 6, the current sensor 60 is pressed against and fixed to the side wall region 37d1. The current flowing in the negative pole bus bar 37 is measured by the current sensor 60 pressed and fixed to the sidewall region 37d1. An elastic body such as a spring or rubber may be provided in the vicinity of the bent portion 61 to reinforce the restoring force.

  5 and 6 show an example in which the current sensor 60 is disposed in the sensor cavity 40b corresponding to the negative pole bus bar 37, but it is preferable to dispose the current sensor in the sensor cavity 40a or 40c. Flexible printed circuit board may be adopted. Further, FIG. 6 exemplifies a state in which the current sensor 60 is fixed in contact with the sidewall region 37d1 of the negative pole bus bar 37, as long as desired measurement by the current sensor is possible for the bus bar to be measured. The arrangement state of the current sensor is not limited to this. For example, a slight gap may be opened between current sensor 60 and sidewall region 37d1, and current sensor 60 may be disposed close to sidewall region 37d1 via the gap. Alternatively, a sealing resin or the like may be provided on the surface of sidewall region 37d1, and current sensor 60 may be disposed in contact with the surface of the sealing resin.

  As the current sensor, a magnetoresistive sensor using a high sensitivity magnetoresistive element such as an anisotropic magnetoresistive (AMR) element, a giant magnetoresistive (GMR) element, or a tunnel magnetoresistive (TMR) element is employed.

  As shown in FIG. 6, the bottom cover 30c is fitted on the lower surface side of the support portion 30b, whereby the sensor cavity portions 40a, 40b and 40c, and the sensor circuit board 70 are covered. As a covering means, a noise removing film may be used, or a resin sealing means may be employed.

  Since sensor cavity portions 40a, 40b and 40c in which current sensor 60 can be arranged are provided in interface unit 30 of the present embodiment, whether or not current sensor 60 can be mounted can be selected according to the purpose of use. . By designing the pattern of the sensor circuit board 70 inserted into the lower surface of the support portion 30b according to the specification, the positions of the sensor cavity portions 40a, 40b and 40c on which the current sensor 60 is mounted are selected according to the purpose of use. be able to. When the current sensor 60 is not necessary, the lower surface of the support portion 30b may be covered with the bottom cover 30c without mounting the current sensor 60 on the interface unit 30.

  Further, by mounting the current sensor 60, a semiconductor device having a short circuit protection function and an overcurrent protection function can be realized. For example, the abnormal current detection of the semiconductor device can be stably performed, and the soft shutdown of the semiconductor device can be instantaneously at the time of a malfunction such as an overcurrent.

  Furthermore, since the sensor circuit board 70 on which the current sensor 60 and the sensor wiring 60a are mounted can be housed in the interface unit 30, there is no need to enlarge the interface unit 30, and a miniaturized semiconductor device is realized. can do.

  In addition, sensor hollow portions 40a, 40b and 40c are provided in the vicinity of the bent portions 4a of the output bus bar 39, the negative pole bus bar 37, and the positive pole bus bar 35 to make the current flowing through each bus sensitive. 60 can be detected.

  Furthermore, since the sensor circuit board 70 on which the sensor wire 60a of the current sensor 60 is mounted is disposed in the circuit board storage portion 50 on the lower surface of the support portion 30b, the sensor wire 60a is not enlarged. A space for disposing the sensor circuit board 70 mounted thereon can be secured. In addition, a constant distance can be secured between the main current wire on the upper surface of the support portion 30b and the sensor wire 60a formed on the lower surface, and the output bus bar 39, the negative electrode bus bar 37, and the positive electrode bus bar It is less likely to receive electromagnetic noise from 35. Furthermore, since it is possible to keep away from the main current wiring of the external device, the possibility of receiving electromagnetic noise from the external device is reduced. Further, since the current sensor 60 and the sensor wiring 60a are covered by the bottom cover 30c and the covering means such as the noise removing film, malfunction does not occur even in an environment where the electromagnetic noise is relatively large.

  Further, the sensor circuit board 70 is formed such that the external connection portion 71 is disposed on the side on which the external connection control terminals 31, 32, 33, 34 are provided along the longitudinal direction of the lower surface of the support portion 30b. Be done. Thus, the sensor wiring 60 a of the sensor circuit board 70 does not unnecessarily cross the main current wiring of the output bus bar 39. With such a configuration, since the noise due to the switching current flowing through the output bus bar 39 is not received, the possibility of causing the malfunction of the current sensor is reduced. Since direct current flows through the negative pole bus bar 37 and the positive pole bus bar 35, there is no problem even if the sensor wiring 60a crosses.

  Furthermore, by adopting a magnetoresistive sensor using a high sensitivity magnetoresistive element such as an AMR element, a GMR element, or a TMR element as a current sensor, a large magnetic core is provided to focus the magnetic flux and enhance the sensitivity. It can be stored in the interface unit 30 without.

  As described above, the present invention includes various embodiments and the like which are not described above, and the technical scope of the present invention is defined only by the invention specific matters according to the scope of claims appropriate from the above description. It is a thing.

4a, 4b, 4c, 4d bent portion 10 semiconductor unit 10a sealing resin 11 source signal terminal 12 for upper arm terminal for left gate signal 13 terminal for lower arm source signal terminal 14 right gate signal terminal 15a drain Connection terminal 15c Plus pole terminal 16 collar portion 18 Rod portion 17a Source connection terminal 17c Minus pole terminal 19a Output side connection terminal 19c Output terminal 20 Semiconductor unit 21 Source signal terminal for upper arm 22 Bottom gate signal terminal 23 Source signal terminal for arm 24 Gate signal terminal 30 on the right Interface unit 30a Housing 30b Support 30c Bottom cover 30d Resin 31 First source signal terminal 32 First gate signal terminal 33 Second source signal terminal 34 Second gate signal terminal 35 plus pole bus bar 35a, 35b Positive pole bus bar connecting portion 35c Positive pole external connecting portion 37 Negative pole bus bar 37a, 37b Negative pole bus bar connecting portion 37c Negative pole external connecting portion 37d1, 37d2 Side wall region 39 Output bus bar 39a, 39b Output bus bar connecting portion 39c Output external Connection part 40a, 40b, 40c Sensor cavity 50 Circuit board storage part 60 Current sensor 60a Sensor wiring 61 Bent part 70 Sensor circuit board 71 External connection part 91 1st source signal internal wiring 92 1st gate signal For internal wiring 93 second internal wiring for source signal 94 internal wiring for second gate signal 91 h, 92 h, 93 h, 94 h through hole 100 base plate

Claims (9)

An interface unit connected to the semiconductor unit,
A U-shaped portion defined by opposing first and second rising portions is held in the center, and both ends connected to the U-shaped portion have a cross-sectional shape extending in the same plane in the opposite direction, Plate-shaped bus bars each of which is a bus bar connecting portion connected to the semiconductor unit;
The first and second rising portions are internally sealed with a resin, and a rectangular parallelepiped portion having two sides parallel to the first and second rising portions as side surfaces is provided. A supporting portion provided with a sensor cavity in the resin along a first rising portion;
The sensor includes a sensor inserted into the sensor cavity, a flexible printed circuit board provided with the sensor at an end, and a sensor wiring patterned on the flexible printed circuit and electrically connected to the sensor, the support A sensor circuit board disposed on the bottom side of the housing;
An interface unit comprising:   The interface unit according to claim 1, wherein the sensor is a current sensor that measures a current flowing through the bus bar.   The interface unit according to claim 1 or 2, wherein the sensor wiring mainly includes a pattern along a longitudinal direction of the rectangular parallelepiped portion of the support portion. The flexible printed circuit board has a bent portion for inserting the sensor into the sensor cavity by bending.
In a state where the flexible printed circuit board is bent at the bent portion and the sensor is inserted into the sensor cavity, the sensor is pressed against the first rising portion by the restoring force of the flexible printed circuit board and fixed The interface unit according to any one of claims 1 to 3, characterized in that: A plurality of bus bars each having the same configuration as the bus bar;
The plurality of bus bars are arranged side by side in the longitudinal direction of the rectangular parallelepiped portion,
The interface unit according to any one of claims 1 to 4, wherein the longitudinal direction of each of the plurality of bus bars is arranged along the short direction of the rectangular parallelepiped portion.   The interface unit according to claim 5, wherein the sensor cavity is provided for each of the plurality of bus bars. One of the plurality of bus bars is a bus bar disposed at one end side in the longitudinal direction of the support portion and through which a switching current flows,
The sensor circuit board further includes an external connection portion disposed on the other end side opposite to the one end side, and the sensor wiring connects the sensor and the external connection portion. The interface unit according to claim 5 or 6.   The interface unit according to any one of claims 1 to 7, further comprising a covering portion covering the sensor hollow portion and the sensor circuit board. A plurality of semiconductor units mounted and paralleled with semiconductor chips;
An interface unit connected to the plurality of semiconductor units;
And the interface unit comprises
A U-shaped portion defined by opposing first and second rising portions is held in the center, and both ends connected to the U-shaped portion have a cross-sectional shape extending in the same plane in the opposite direction, Plate-shaped bus bars each of which is a bus bar connecting portion connected to the semiconductor unit;
The first and second rising portions are internally sealed with a resin, and a rectangular parallelepiped portion having two sides parallel to the first and second rising portions as side surfaces is provided. A supporting portion provided with a sensor cavity in the resin along a first rising portion;
The sensor includes a sensor inserted into the sensor cavity, a flexible printed circuit board provided with the sensor at an end, and a sensor wiring patterned on the flexible printed circuit and electrically connected to the sensor, the support A sensor circuit board disposed on the bottom side of the housing;
The semiconductor device characterized by having.

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