JP2019102550A - Semiconductor substrate manufacturing method - Google Patents

Abstract

To provide an art to control a height of a local semiconductor region in a manufacturing method of a semiconductor substrate in which the local semiconductor region is exposed in a local range on a surface of the semiconductor substrate and another semiconductor region is exposed in a surrounding range surrounding the local range.SOLUTION: A semiconductor substrate manufacturing method comprises the steps of: forming a first recess 41 in a local range R1 of a semiconductor substrate and forming a second recess 42 having overhanging lateral faces at a position away from the local range R1; laminating a semiconductor layer 6 to be a local semiconductor region 61 on a surface of the semiconductor substrate where the first recess 41 and the second recess 46 are formed; and performing surface polishing on the surface of the semiconductor substrate until a space remaining under the overhang lateral faces is exposed. The end of surface polishing is clarified.SELECTED DRAWING: Figure 4

Description

  In the present specification, a surrounding area in which a local semiconductor region is exposed on a part of the surface of a semiconductor substrate, and surrounding the area where the local semiconductor region is exposed (hereinafter referred to as “local area”) We disclose a method of manufacturing a semiconductor substrate in which other semiconductor regions are exposed. For example, a method is disclosed for manufacturing a semiconductor substrate in which an n-type region is exposed substantially over the entire surface and a p-type region is exposed in part of the area. In this specification, a semiconductor layer which becomes a local semiconductor region after processing is called an upper semiconductor layer, and a layer which becomes another semiconductor region is called a lower semiconductor layer.

  At the time of manufacturing a semiconductor device, a semiconductor substrate may be manufactured in which a local semiconductor region is exposed in a local area and another semiconductor region is exposed in a surrounding area surrounding the local area. The semiconductor device may be manufactured by further processing the semiconductor substrate. When manufacturing the semiconductor substrate, the following steps may be carried out. (1) Prepare a semiconductor substrate in which the lower semiconductor layer is exposed over a local area and a surrounding area, (2) form a recess in the local area, and (3) a lower semiconductor in which a recess is formed The upper semiconductor layer is stacked on the surface of the layer, and (4) planar polishing is performed to remove the upper semiconductor layer stacked outside the recess to expose the lower semiconductor layer. Patent Document 1 discloses a technique for planarly polishing the surface of a semiconductor substrate using CMP (abbreviation of Chemical Mechanical Polishing).

JP 2012-23144 A

  In the above technology, it is difficult to control the end timing of the planar polishing. If the end timing is too early, the semiconductor layer stacked outside the recess is not removed. If the end timing is too late, the thickness of the semiconductor layer stacked in the recess will be insufficient.

  In particular, in the case of a nitride semiconductor, it is transparent, and even if a mark is formed on the surface of the lower semiconductor layer, it is difficult to visually recognize the mark, and the end timing of planar polishing is managed using the mark. Is difficult. This is particularly difficult when both the upper and lower semiconductor layers are nitride semiconductors.

  The present specification provides a technique capable of managing the end timing of planar polishing.

  The semiconductor substrate manufacturing method disclosed herein utilizes a semiconductor substrate in which other semiconductor regions are exposed in both the local range and the surrounding range. The manufacturing method includes the steps of forming a first recess in a local area of the semiconductor substrate and forming a second recess having an overhanging side surface, a first recess and a second recess. Depositing a semiconductor layer to be a local semiconductor region on the surface of the semiconductor substrate having the recess formed therein, and planarly polishing the surface of the semiconductor substrate until the space remaining under the side surface forming the overhang is exposed It has a process. The second recess is formed at a position separated from the local area. Here, "overhang" means that a space exists below the side surface. The space is not seen by being blocked by the side wall, when viewed from the front side of the semiconductor substrate. For example, the side surface forming the overhang is inclined with respect to the surface orthogonal to the surface of the semiconductor substrate in a direction away from the surface opening serving as the entrance of the recess toward the deep part of the recess.

  According to the above configuration, when the semiconductor layer to be the local semiconductor region is stacked on the surface of the semiconductor substrate in which the first recess and the second recess are formed, the semiconductor layer is formed below the overhanging side surface. Space remains. Therefore, by detecting that the above-mentioned remaining space is exposed in the planar polishing step, it is possible to know the timing when the upper semiconductor layer laminated outside the recess is removed and the lower semiconductor layer is exposed. You will be able to manage the end timing.

  The details and further improvement of the technology disclosed in the present specification will be described in the following "Forms and Examples for Carrying Out the Invention".

It is sectional drawing of the diode manufactured by the manufacturing method of an Example. It is a figure explaining the process of forming a n-type semiconductor layer in the manufacturing method of an example. It is a figure explaining the process of forming a trench and a mark in the manufacturing method of an example. It is a figure explaining the process of forming a p-type semiconductor layer in the manufacturing method of an example. In the manufacturing method of an Example, it is a figure explaining the process of planarly polishing. In the manufacturing method of an Example, it is a figure explaining the process of processing the surface of a semiconductor layer after the process of plane | planar grinding | polishing. FIG. 7 is a diagram for describing a step of forming an insulating film in the manufacturing method of the embodiment. It is a figure explaining the mark of a comparative example. It is a figure explaining the mark of an example. It is a figure explaining the mark of modification 1. It is a figure explaining the mark of modification 2. It is a figure explaining the mark of modification 3.

The features of the embodiment described below are organized.
(Feature 1) The second recess is a triangle having an opening at the top and a bottom at the bottom when viewed in cross section from the direction parallel to the surface of the semiconductor substrate.
(Feature 2) The step of planarizing is performed until the space remaining below the overhanging side surface is exposed and the width of the exposed space becomes a predetermined length.
(Feature 3) After the surface polishing, a step of processing the surface of the semiconductor substrate based on the remaining space is provided. The space doubles as a mark indicating the end timing of planar polishing and an alignment mark for subsequent processing.

  The manufacturing method of the embodiment will be described with reference to the drawings. FIG. 1 is a cross-sectional view of a diode 100 manufactured by the manufacturing method of the embodiment. FIGS. 2-7 is a figure which shows each process of the manufacturing method of an Example. 2 to 7 are cross-sectional views seen from the same direction as FIG.

The diode 100 shown in FIG. 1 includes an n-type region 4 stacked on the upper surface of the n ⁺ -type Si substrate 2 and a p-type region 61 stacked in a local range R1 of the upper surface of the n-type region 4. Is equipped. The p-type region 61 is disposed at the upper end of the protrusion 63 protruding from the upper surface of the n-type region 4. The n-type region 4 is a semiconductor region containing n-type GaN (gallium nitride) as a main component. The p-type region 61 is a semiconductor region containing p-type GaN as a main component. The portion where the n-type region 4 and the p-type region 61 are in contact is the pn junction of the diode 100. The n-type region 4 and the p-type region 61 may be mainly composed of nitride semiconductors other than GaN (for example, AlN (aluminum nitride)) or other compound semiconductors.

  The exposed surface of the p-type region 61 (other than the holes 81 described later) and the exposed surface of the n-type region 4 are covered with the insulating film 8. An anode electrode 12 is disposed above the insulating film 8. The anode electrode 12 passes through a hole 81 provided in a part of the insulating film 8 and is connected to the p-type region 61. Further, a cathode electrode 14 is connected to the lower surface of the Si substrate 2.

  Further, a concave mark 42 having a space S1 is provided at a position apart from the local range R1 on the surface of the n-type region 4. The mark 42 is used in the method of manufacturing the diode 100 described later. In the manufacturing process of the diode 100, the mark 42 is processed to the state shown in FIG. 1, and a part of the p-type semiconductor layer 62 and the insulating film 8 remain inside the mark 42. The method of using the mark 42 will be described later.

(Method of manufacturing diode 100)
First, as shown in FIG. 2, the Si substrate 2 is prepared, and the semiconductor layer 40 to be the n-type region 4 is grown (deposited) on the entire upper surface of the Si substrate 2 by epitaxial growth. In the modification, a substrate in which the semiconductor layer 40 is formed in advance on the upper surface of the Si substrate 2 may be prepared.

  Next, as shown in FIG. 3, a trench 41 is formed in a local range R1 of the upper surface of the semiconductor layer 40. The trench 41 is a square when viewed in cross section from a direction parallel to the top surface of the semiconductor layer 40. The trench 41 is formed, for example, by etching. Furthermore, a concave mark 42 is formed at a position apart from the local range R1 of the upper surface of the semiconductor layer 40. The mark 42 is an isosceles triangle in which the opening is located at the vertex and the base is located deep when viewed in a cross section from a direction parallel to the upper surface of the semiconductor layer 40. The depth D2 of the mark 42 is deeper than the depth D1 of the trench 41. The width W1 of the opening of the mark 42 is smaller than the width W2 of the bottom of the mark 42. That is, the mark 42 has an overhanging side surface, and there is a space S0 below the side surface of the mark 42. In other words, when viewed from the upper surface side of the semiconductor layer 40, the space S0 of the mark 42 is not seen by being blocked by the wall which is the side surface of the mark 42. The mark 42 is formed, for example, using a known etching technique disclosed in Japanese Patent Laid-Open No. 2004-152960.

  Next, as shown in FIG. 4, the semiconductor layer 6 to be the p-type region 61 is grown by epitaxial growth on the surface of the semiconductor layer 40 in which the trench 41 and the mark 42 are formed. The semiconductor layer 6 is stacked until the top surface of the semiconductor layer 6 (that is, the top surface of the semiconductor layer 6 deposited in the trench 41) in the local range R1 is higher than the top surface of the semiconductor layer 40. That is, the trench 41 is filled with the material to be the p-type region 61.

  On the other hand, the material is also deposited on the inner surface of the mark 42 to form the semiconductor layer 62. However, because the sides of the mark 42 have overhangs, less material is deposited on the sides of the mark 42 than materials deposited on the outside of the mark 42. Furthermore, because the openings of the marks 42 are narrow, the openings are closed by the material before the marks 42 are filled with the material. Thus, the space S1 constituting the mark 42 remains below the semiconductor layer 6. As shown in FIG. 4, the space S <b> 1 is the same isosceles triangle as the mark 42 when viewed in cross section from a direction parallel to the upper surface of the semiconductor layer 40.

  Next, as shown in FIG. 5, the surface of the semiconductor layer 6 is polished using CMP (abbreviation of Chemical Mechanical Polishing). The polishing is continued until the space S1 remaining under the semiconductor layer 6 is exposed. The space S1 remains below the semiconductor layer 6 and further below the surface of the semiconductor layer 40. Therefore, by continuing the polishing until the space S1 is exposed, the p-type region 61 is exposed in the local range R1, and the semiconductor layer 40 is exposed in the surrounding range R2 surrounding the local range R1, and the local range R1 is And the surface of the surrounding area R2 are in the same plane. Then, by continuing the polishing until the space S1 is exposed, the height from the bottom surface to the surface of the p-type region 61 becomes a predetermined height H1.

  In particular, the above polishing is continued until the width of the opening of the space S1 becomes a predetermined width W3. As described above, the space S1 is an isosceles triangle whose apex is located on the surface side of the semiconductor layer 40. Therefore, as the width of the opening of the exposed space S1 increases, a linear relationship is established in which the height from the lower surface of the semiconductor layer 40 to the surface after polishing decreases. The thickness of the semiconductor layer 40 after polishing can be adjusted based on the width W3 of the opening of the exposed space S1 using this linear relationship. When the end timing of the planar polishing is managed based on the mark 42 and the space S1 remaining there, the surface of the semiconductor layer 40 before polishing (the surface in FIG. 4) and the surface of the semiconductor layer 40 after polishing (FIG. 5) The relationship with the surface of) can be adjusted to a predetermined relationship. As a result, the height (thickness) of the p-type region 61 in the same plane as the semiconductor layer 40 after polishing can be adjusted to the predetermined height H1.

  Next, as shown in FIG. 6, the p-type region 61 exposed to the local range R1 and the semiconductor layer 40 exposed to the surrounding range R2 are processed. Specifically, the position of the p-type region 61 is specified based on the space S1 located in the surrounding range R2, and the mask 70 is arranged at the specified position. Then, the surface of the local region R1 and the surface of the surrounding region R2 are etched to form a protrusion 63 which protrudes from the surface of the n-type region 4 and which has a p-type region 61 at the upper end. The n-type semiconductor layer 40 remaining after the etching becomes the n-type region 4. The mask 70 is removed after etching.

  Next, as shown in FIG. 7, the insulating film 8 is formed to cover the entire surface of the convex portion 63 and the surface of the n-type region 4. At this time, the material to be the insulating film 8 also enters the space S1 in which the mark 42 remains. Then, as shown in FIG. 1, a hole 81 is formed in a part of the insulating film 8, and an anode electrode 12 connected to the p-type region 61 is formed by passing through the hole 81. Further, the cathode electrode 14 is formed on the lower surface of the Si substrate 2. Thereby, the diode 100 is manufactured.

  Here, a comparative example in which the mark 42 is not formed is assumed. In this comparative example, the height of the p-type region 61 after polishing is managed by managing the depth of polishing by CMP. In this method, when the thickness of the laminated semiconductor layer 6 (that is, the height from the surface of the semiconductor layer 40 to the surface of the semiconductor layer 6 in the state of FIG. 4) varies, it is p-type region 61 after polishing Make the height of the The height of the p-type region 61 after polishing is likely to be too high or too low. Alternatively, a phenomenon occurs in which the p-type semiconductor layer 6 stacked outside the trench 41 remains.

  On the other hand, in the present embodiment, in order to detect that the space S1 remaining under the semiconductor layer 6 is exposed in the step of planar polishing (see FIG. 5), regardless of the thickness of the semiconductor layer 6, The height H1 of the p-type region 61 after polishing can be easily managed.

  The advantages of the example mark 42 will be further described with reference to the comparative example shown in FIG. In the comparative example shown in FIG. 8, as shown in (a), a mark 142 having a shape different from that of the mark 42 of the example is formed on the upper surface of the semiconductor layer 40. The mark 142 is a square when viewed in a cross section in a direction parallel to the surface of the semiconductor layer 40. The depth is the same as the depth D2 of the mark 42. In this comparative example, the semiconductor layer 6 is grown on the top surface of the semiconductor layer 40. In the initial stage (b) in which the height C1 of the semiconductor layer 6 deposited on the surface of the semiconductor layer 40 outside the mark 142 is smaller than half the width W2 of the mark 142, the mark 142 becomes the semiconductor layer 6 Not filled with materials. In the step (c) in which the growth of the semiconductor layer 6 proceeds and the height C2 of the semiconductor layer 6 deposited on the surface of the semiconductor layer 40 outside the mark 142 becomes approximately equal to one half of the width W2 of the mark 142. Is filled with the material to be the semiconductor layer 6. Then, in the step (d) in which the height C3 of the semiconductor layer 6 deposited on the surface of the semiconductor layer 40 outside the mark 142 is larger than one half of the width W2 of the mark 142, the mark 142 becomes the semiconductor layer 6 Completely filled with materials. That is, in the case of a square mark, no space remains below the semiconductor layer 6. When both the semiconductor layer 40 and the semiconductor layer 6 are transparent, or when the semiconductor layer 40 and the semiconductor layer 6 are the same semiconductor material, an event indicating the planar polishing end timing can not be observed in the mark of FIG.

  On the other hand, in the present embodiment, as shown in FIG. 9, in the initial stage (b), although the material to be the semiconductor layer 6 is deposited on the inner surface of the mark 42, the surface of the semiconductor layer 40 outside the mark 42. In the step (c) where the growth of the semiconductor layer 6 to be deposited further proceeds (c), the opening of the mark 42 is covered with the material without the space behind the mark 42 being filled with the material. Then, even if the step (d) in which the growth of the semiconductor layer 6 progresses further and the height of the semiconductor layer 6 becomes the same as the height C3 at which the mark 142 is completely buried in the comparative example, Space S1 remains. The optical device characteristics such as the refractive index are different between the semiconductor layer 40 and the semiconductor layer 6 and the space S1, and the exposed range of the space S1 can be optically observed. Thus, in the planar polishing step shown in FIG. 5, the polishing end timing can be managed using the remaining space S1, and the height H1 of the p-type region 61 can be easily managed.

  Further, in the comparative example, when the height of the semiconductor layer 6 deposited on the surface of the semiconductor layer 40 is high, the mark 142 is completely filled with the material to be the semiconductor layer 6. Therefore, after the formation of the semiconductor layer 6, the mark 142 can not be used, and it becomes difficult to specify the range to be processed. On the other hand, in the manufacturing method of the embodiment, the position of the range to be processed, that is, the local range R1 including the p-type region 61 can be identified based on the space S1 remaining after planar polishing (see FIG. Figure 6). The mark 42 is also an alignment mark which becomes a position reference at the time of subsequent processing.

(Correspondence relationship)
The trench 41 of FIG. 3 is an example of the “first recess” in the claims, the mark 42 is an example of the “second recess”, and the p-type region 61 of FIG. 5 is the “local semiconductor region”. The n-type region 4 is an example of the “other semiconductor region”, the semiconductor layer 40 is an example of the lower semiconductor layer, and the semiconductor layer 6 is an example of the upper semiconductor layer.

(Modification 1)
The shape of the mark formed on the upper surface of the semiconductor layer 40 is not limited to the isosceles triangle. For example, as shown in FIG. 10, a mark 43 having the shape of a right triangle may be formed. When the mark 43 is viewed in a cross section in a direction parallel to the surface of the semiconductor layer 40, the opening of the surface is located at the apex of the acute angle, and the edge facing the acute angle is a right triangle. In this modification, the side surface corresponding to the oblique side facing the right angle of the right triangle is the side surface that forms the overhang. As shown in FIG. 10, a space S2 exists below the overhanging side surface of the mark 43. Therefore, also in this modification, the height H1 of the p-type region 61 can be easily managed using the remaining space, as in the embodiment. In particular, in the present modification as well, since the space S2 is triangular as in the embodiment, the height of the p-type region 61 after polishing is increased by continuing the polishing until the width of the opening of the space S2 becomes a predetermined width. It can be adjusted to the planned height H1. In the example isosceles triangle, the width of the opening is measured between each layer deposited on a pair of sides with overhangs. The thickness of the layer deposited on the pair of side surfaces tends to have a large error, and as a result, the error in the width of the opening also increases. On the other hand, in the modified right triangle, the width of the opening is measured between the side with the overhang and each layer deposited on the vertical side that is not the overhang. The thickness of the layer deposited on the vertical side tends to have a smaller error in the vicinity of the opening compared to the side having the overhang. As a result, compared with the configuration of the embodiment, the error in the width of the opening is reduced. That is, compared to the configuration of the embodiment, the height of the p-type region 61 after polishing can be adjusted with high accuracy.

(Modification 2)
Also, for example, as shown in FIG. 11, a mark 44 having a predetermined width extending obliquely to a plane orthogonal to the surface of the semiconductor substrate may be formed. Also in this modification, the mark 44 has an overhanging side surface, and a space S3 exists below the overhanging side surface. Therefore, also in this modification, the height H1 of the p-type region 61 can be easily managed using the remaining space, as in the embodiment.

(Modification 3)
Also, for example, as shown in FIG. 12, a mark 47 including a narrow trench 45 extending in a direction orthogonal to the upper surface of the semiconductor layer 40 and a wide trench 46 communicating with the trench 45 below the trench 45. May be formed. Also in this modification, the space S4 exists below the step surface between the side surface of the narrow trench 45 and the wide trench 46. That is, the mark 47 has an overhanging side surface. Therefore, also in this modification, the height H1 of the p-type region 61 can be easily managed using the remaining space, as in the embodiment.

  Hereinafter, points to be noted regarding the techniques shown in the embodiments will be described. The techniques described in the embodiments can be employed not only for the manufacture of diodes but also for the manufacture of transistors, LEDs (abbreviation of light emitting diodes), and the like.

  In the present embodiment, in the state shown in FIG. 4, the surface of the semiconductor layer 6 in the trench 41 has a higher relationship than the surface of the semiconductor layer 40 outside the trench 41, but the surface of the semiconductor layer 6 in the trench 41 is It is also useful when it is lower than the surface of the semiconductor layer 40 outside the trench 41. Even in this case, the height H1 of the p-type region 61 after the planar polishing can be stabilized to a predetermined value by managing the end timing of the planar polishing using the phenomenon that the space S1 is exposed.

  As mentioned above, although the specific example of this invention was described in detail, these are only an illustration and do not limit a claim. The art set forth in the claims includes various variations and modifications of the specific examples illustrated above. The technical elements described in the present specification or the drawings exhibit technical usefulness singly or in various combinations, and are not limited to the combinations described in the claims at the time of application. In addition, the techniques exemplified in the present specification or the drawings can simultaneously achieve a plurality of purposes, and achieving one of the purposes itself has technical utility.

2: Si substrate 4: n-type region 6: semiconductor layer 8: insulating film 12: anode electrode 14: cathode electrode 40: semiconductor layer 41: trench 42, 43, 44, 47: mark 61: p-type region 62: semiconductor layer 63: convex portion 70: mask 81: hole 100: diode D1, D2: depth H1, C1 to C3: height R1: local range R2: surrounding range S0 to S4: space

Claims (1)

A method of manufacturing a semiconductor substrate in which a local semiconductor region is exposed in a local area on the surface of the semiconductor substrate and another semiconductor area is exposed in a surrounding area surrounding the local area,
A second recess having a side surface forming an overhang as well as forming a first recess in the local region of the semiconductor substrate in which the other semiconductor region is exposed in the local region and the surrounding region. Forming the portion at a position separated from the local area;
Laminating a semiconductor layer to be the local semiconductor region on the surface of the semiconductor substrate on which the first recess and the second recess are formed;
Planar polishing the surface of the semiconductor substrate until the space remaining below the side surface forming the overhang is exposed;
A method of manufacturing a semiconductor substrate comprising:

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