JP2019101249A - Manufacturing method of nitride semiconductor element - Google Patents

Abstract

To manufacture in an easier manner an element with good properties and having periodic polarization inversion structure using a highly crystalline group III nitride semiconductor.SOLUTION: A first semiconductor layer 102 including nitride semiconductor is epitaxially grown, on a first substrate 101, in a +c-axis direction, to form a growth surface as group III polar surface. A nitride semiconductor is then crystal-grown on a second substrate 103 in a +c-axis direction, to form a second semiconductor layer 104 with a growth surface as group III polar surface. The second substrate 103 is then removed (peeling) to expose a group V polar surface of the second semiconductor layer 104 (fourth step). A plurality of groove part 104a are formed which are arrayed in the second semiconductor layer 104 and penetrating the second semiconductor layer 104. The nitride semiconductor is epitaxially grown in the +c-axis direction from a bottom face of each of the plurality of groove parts 104a, and a third semiconductor layer 108 is formed in each of the plurality of groove parts 104a with the growth surface as group III polar surface.SELECTED DRAWING: Figure 1I

Description

  The present invention relates to a method of manufacturing a nitride semiconductor device made of a nitride semiconductor.

  In devices that utilize the fact that crystals of group III nitrides such as GaN, AlN, InGaN do not have inversion symmetry in the c-axis direction, crystals of group III polarity such as periodically poled gallium nitride, which is an optical element, are used. There are devices in which crystals of N and N polarity (group V polarity) are periodically arranged in the plane.

  Such a periodically poled (PP) element is an optical element produced by arranging a material having a nonlinear optical effect so as to invert the polarization at a specific period, for example, the second harmonic generation And optical parametric oscillation, difference frequency generation, etc. This periodic structure is formed for the purpose of quasi phase matching (QPM) to obtain the output intensity of the element output light, and the period differs depending on the wavelength of the light to be a target.

As materials, lithium niobate (LiNbO ₃ ), lithium tantalate (LiTaO ₃ ), etc. having large nonlinear optical effects are used, and periodically poled lithium niobate (periodically poled LiNbO ₃ ) is PPLN, periodically poled lithium tantalate (Periodically poled LiTaO ₃ ) is an abbreviation such as PPLT. When using gallium nitride (GaN) as a material, it is abbreviated as PPGaN.

There are three advantages to using GaN and III-nitride semiconductors. One is to have transparency in a wide wavelength range. For example, LiNbO ₃ whereas having only transmissive in the range of 350nm~5μm, GaN has a permeability in a wide range of 365Nm～13myuemu. Furthermore, if AlGaN or AlN is used, the transmission wavelength can be further extended to the short wave side. This means that devices corresponding to light of various wavelengths can be manufactured using only a group III nitride semiconductor.

The second is that it has no photorefractive effect. Therefore, unlike PPLN, PPGaN does not require temperature control during operation and can be operated at room temperature. The third is that the light damage threshold is high. For example, while the photodamage threshold of LiNbO ₃ is about 0.3 GW / cm ² , the photodamage threshold of GaN is 34 TW / cm ² . For this reason, it is possible to produce a high power device.

S. Pezzagna et al., "Submicron periodic poling and chemical patterning of GaN", Applied Physics Letters, vol. 87, no. 6, 062106, 2005. A. Chowdhury et al., "Second-harmonic generation in periodically poled GaN", Applied Physics Letters, vol. 83, no. 6, pp. 1077-1079, 2003. R. Das, "Ultra-broadband optical parametric amplification by tailoring the group-velocity dispersion of Bragg reflection waveguides", Journal of Physics D: Applied Physics, vol. 42, pp. 1-7, 2009. S. A. Smith et al., "High rate and selective etching of GaN, AlGaN, and AlN using an inductively coupled plasma", Applied Physics Letters, vol. 71, no. 25, pp. 3631-3633, 1997.

As described above, it is known that the periodically poled device using the group III nitride semiconductor has superior points to LiNbO _{3 and the} like conventionally used, but there are problems in the device fabrication.

Unlike materials such as LiNbO ₃ , group III nitride semiconductors can not change the polarization provided by themselves by an external electric field, heat treatment, or the like. For this reason, in order to produce a periodically poled structure, it is necessary to grow crystals of group III polarity and crystals of group V polarity, respectively. For example, in Non-Patent Document 1, when a large amount of Mg is doped into a group III polar crystal, the polarization is reversed, and the fact that the crystal grown thereon becomes a group V polarity is utilized.

  In this manufacturing method, the growth is stopped once when the surface becomes a crystal of group V polarity, and a part of the mask having a periodic structure is covered with photolithography, and the group V polar crystal in the portion without the mask is made reactive. It is removed by ion etching (RIE) to expose a group III polarity crystal. Thereafter, crystal growth is performed again to obtain a structure in which the group III polarity and the group V polarity are periodically aligned.

  In Non-Patent Document 2, in molecular beam epitaxy (MBE), the presence of a buffer layer of AlN makes it possible to grow a group III-polar crystal while a crystal of group V polarity can grow without the buffer layer of AlN. There is. In this manufacturing method, first, an AlN buffer layer is formed, then a part of the AlN buffer layer is masked, and the part without the mask is removed by inductively coupled plasma RIE (ICP-RIE). By growing a Group III nitride semiconductor by MBE on this substrate, a structure in which crystals of Group III polarity and Group V polarity are periodically arranged is grown.

  Starting from the above two manufacturing methods, in the conventional method for manufacturing a periodically poled structure of group III nitride, crystal growth with the growth surface set to group V polarity is included as an essential step. The crystal of group V polarity contains more defects during growth than the crystal whose growth surface is made group III polar, and the crystal surface is roughened by being covered with a large number of concavities and convexities of hexagonal column and hexagonal column. I have a problem. In particular, Group III nitrides grown on different substrates with the growth plane as Group V polarity have less crystal quality and have more defects than those grown with the growth plane Group III polarity, and only rough crystals on the surface are obtained. It is not done. These are limitations on the device performance, and cause, for example, a decrease in wavelength conversion efficiency in periodically poled gallium nitride.

  In the conventional manufacturing method, after a layer for periodically poled inversion growth is formed in the vicinity of the interface on the dissimilar substrate, a crystal of group III polarity and a crystal of group V polarity are simultaneously grown. At this time, there is a difference between crystal growth rates of the two types of polarity, and in general, the growth rate of group III polarity is fast. Therefore, as the layer is thickened, the group III polar crystal grows in a convex shape. It is known that the surface roughness and the internal defect of the periodically poled structure as described above lead to the characteristic deterioration of the optical element. For example, in the waveguide type PP, the shape is uniform in the longitudinal direction of the waveguide It is known that the wavelength conversion efficiency is lowered because the effective refractive index of light is changed when the surface has unevenness, that is, when the thickness of the waveguide varies in the longitudinal direction of the waveguide. ing. In addition, a large amount of defects inside the crystal narrows the operable wavelength range.

  These irregularities can be planarized by polishing such as CMP, but the group III polar crystal is chemically inactive compared to the group V polar crystal, and the convex portion composed of the group III polar crystal is group V In the case of polishing so as to have the same height as the polar crystal, the polishing of the V group polar crystal also largely progresses, and the controllability of the element thickness is not high.

  As described above, in the prior art, there is a problem that it is difficult to easily manufacture an element having a periodic polarization inversion structure made of a group III nitride semiconductor having high crystallinity and having a good characteristic.

  The present invention has been made to solve the above-mentioned problems, and it is possible to easily manufacture an element having a periodic polarization inversion structure made of a group III nitride semiconductor having good crystallinity and having a good characteristic. The purpose is to

  In the method of manufacturing a nitride semiconductor device according to the present invention, a first step of forming a first semiconductor layer whose main surface is a group III polar surface on a first substrate, and a second substrate are provided. A second step of crystal-growing a nitride semiconductor in the + c axis direction to form a second semiconductor layer with the growth surface as a group III polar surface, a group III polar surface of the first semiconductor layer and a group III polarity of the second semiconductor layer After the third step of bonding the first substrate and the second substrate with the surfaces facing each other, and after the third step, the second substrate is removed to expose the V-group polar surface of the second semiconductor layer After the fourth step and the fourth step, the fifth step of forming a plurality of grooves arranged in the second semiconductor layer and penetrating the second semiconductor layer, and a nitride semiconductor from the bottom of each of the plurality of grooves Epitaxially grow in the + c axis direction, with each of the plurality of grooves having a growth surface of group III polarity As and a sixth step of forming a third semiconductor layer.

  In the method of manufacturing a nitride semiconductor device, in the first step, a nitride semiconductor is crystal-grown on the first substrate in the + c axis direction to form a first semiconductor layer with the growth surface as a group III polar surface.

  In the method of manufacturing a nitride semiconductor device, the first substrate may be formed of any of silicon, sapphire, and silicon carbide, and in the first step, the first semiconductor layer may be formed to a thickness of 410 nm or more.

  In the method of manufacturing a nitride semiconductor device, the first substrate may be made of a Group III nitride whose main surface is a Group III polar surface, and a part of the first substrate may be a first semiconductor layer.

  In the method of manufacturing a nitride semiconductor device, after the sixth step, the second semiconductor layer and the third semiconductor layer are patterned, and the second semiconductor layer and the third semiconductor layer are alternately arranged in the arrangement direction of the plurality of grooves. The method may further include a seventh step of connecting side by side and forming a rib pattern of a predetermined width extending in the arrangement direction of the plurality of grooves.

  As described above, according to the present invention, the first semiconductor layer and the second semiconductor layer having the growth surface formed as the group III polarity are integrated with the group III polarity faces facing each other, The surface of the layer is a group V polar face, and the surface of the first semiconductor layer facing in the same direction as the individual group V polar faces is a group III polar face, so periodic polarization inversion by a group III nitride semiconductor with good crystallinity It is possible to obtain an excellent effect that a device having good structure and characteristics can be easily manufactured.

FIG. 1A is a cross-sectional view showing a state of an intermediate step for illustrating a manufacturing method in a first embodiment of the present invention. FIG. 1B is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 1C is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 1D is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 1E is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 1F is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 1G is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 1H is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 1I is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the first embodiment of the present invention. FIG. 2A is a cross-sectional view showing a state in the middle of the process for illustrating the manufacturing method according to Embodiment 2 of the present invention. FIG. 2B is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the second embodiment of the present invention. FIG. 2C is a cross-sectional view showing a state in the middle of the process for illustrating the manufacturing method according to Embodiment 2 of the present invention. FIG. 2D is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the second embodiment of the present invention. FIG. 2E is a cross-sectional view showing a state in the middle of the process for illustrating the manufacturing method in the second embodiment of the present invention. FIG. 3A is a cross-sectional view showing a state in the middle of the process for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3B is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3C is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3D is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3E is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3F is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3G is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3H is a cross-sectional view showing a state of an intermediate step for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 3I is a cross-sectional view showing a state in the middle of the process for illustrating the manufacturing method in the third embodiment of the present invention. FIG. 4A is a perspective view showing a state of an intermediate step for illustrating the manufacturing method in the fourth embodiment of the present invention. FIG. 4B is a perspective view showing a state of an intermediate step for illustrating the manufacturing method in the fourth embodiment of the present invention. FIG. 4C is a perspective view showing a state of an intermediate step for illustrating the manufacturing method in the fourth embodiment of the present invention.

  Hereinafter, embodiments of the present invention will be described.

First Embodiment
First, a method of manufacturing a nitride semiconductor device according to the first embodiment of the present invention will be described with reference to FIGS. 1A to 1I. Below, the case where a period polarization inversion element is produced is demonstrated to an example.

  First, as shown in FIG. 1A, a first semiconductor layer 102 made of a nitride semiconductor is formed on a first substrate 101 (first step). Here, the nitride semiconductor crystal-grows (epitaxially grows) in the + c-axis direction to form the first semiconductor layer 102 with the growth surface as a group III polar surface.

  The first substrate 101 may be a substrate generally used to grow a nitride semiconductor such as GaN, and may be, for example, Si, sapphire, SiC, GaN or the like. In the first embodiment, a sapphire substrate is used as the first substrate 101. For the growth of GaN on a sapphire substrate, a method is generally used in which a GaN nucleation layer or the like grown at a low temperature is formed on the substrate, and then the growth temperature is raised to grow GaN. As the epitaxial growth method, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE) or the like may be used. The first semiconductor layer 102 obtained by these deposition methods is grown under the condition that the growth surface has a group III polarity.

  Here, the thickness of the first semiconductor layer 102 needs to consider the following two points. First, the first semiconductor layer 102 is a layer to be a template for regrowth. Since the first semiconductor layer 102 serves as a template for growing a group III nitride with group III polarity in the final step of device fabrication, it is desirable that a high quality layer of about 100 nm or more be present at the time of regrowth. When the first substrate 101 is a dissimilar substrate like the sapphire substrate assumed in the first embodiment, a layer having many defects of about 200 nm from the interface with the first substrate 101. This also needs to be considered. The second factor that determines the layer thickness is the thickness of the portion to be scraped off during the element fabrication process. The surface of the first semiconductor layer 102 is scraped 110 nm or more in total in the element manufacturing process. From the above, the thickness of the first semiconductor layer 102 is desirably 410 nm or more.

  On the other hand, the presence of the GaN layer having the same refractive index in the lower part of the periodically poled structure weakens the light confinement effect inside the periodically poled structure and is not preferable in the second harmonic generation. It is not preferable to make the layer thickness of a few μm or more. When a thick layer is used, a layer of AlGaN or AlN is inserted on the layer of GaN to cause a difference in refractive index with the periodically poled structure material, or AlGaN or GaN as shown in Non-patent Document 3. It is desirable to fabricate a periodic multi-layer structure by using a plurality of materials of the above to create a structure that confines light inside the periodically poled structure.

  Alternatively, a group III nitride substrate whose main surface has a group III polarity may be used as the first substrate 101, and a layer formed by epitaxial growth may not be formed thereon, and a part of the first substrate 101 may be used as the first semiconductor layer 102. Also in this case, in order to prevent the substrate and the refractive index of the periodically poled structure from becoming equal, it is possible to fabricate a structure that confines light inside the periodically poled structure such as a layer having a different refractive index or a periodic multilayer structure. desirable.

  Further, although the first semiconductor layer 102 is made of GaN in the above description, it may be made of AlGaN, AlN, InGaN or the like, or may be a laminated structure combining these materials. The important point is that the first semiconductor layer 102 is grown with the growth surface as the group III polarity, and the main surface is the group III polar surface.

  Next, as shown in FIG. 1B, the second semiconductor layer 104 is formed on the second substrate 103 by crystal growth of a nitride semiconductor in the + c axis direction, with the growth surface as a group III polar surface (the second step) ).

  Similarly to the first substrate 101, the second substrate 103 may be a substrate generally used for growing GaN, and may be made of, for example, Si, sapphire, SiC, GaN or the like. In the first embodiment, a sapphire substrate is used as the second substrate 103. As described above, for the growth of GaN on a sapphire substrate, a method of forming a GaN nucleation layer or the like grown at a low temperature on the substrate and then raising the growth temperature to grow GaN is generally used. . As the epitaxial growth method, MOCVD or MBE may be used. The second semiconductor layer 104 obtained by these methods also grows so that the growth surface has a group III polarity.

  The thickness of the second semiconductor layer 104 is determined in consideration of the following two points. First is the thickness of the device. The element thickness in the case of using a periodically poled element is assumed to be as wide as several hundred nm to several tens μm depending on the wavelength of light to be input and the output power to be obtained. If multimode propagation is avoided when the input wavelength is small, the element should be thinner. On the other hand, in order to increase the output, it is necessary to thicken the element to increase the input power. These need to be designed according to the application.

  The second factor that determines the thickness is the thickness that is scraped off during the device fabrication process. The second semiconductor layer 104 is scraped a plurality of times in the element manufacturing process, and is scraped 300 nm or more in total. From the above, it is desirable that the second semiconductor layer 104 be grown to 300 nm or more in addition to the thickness of the device.

  Next, as shown in FIG. 1C, the first substrate 101 and the second substrate 103 are arranged in a state in which the group III polar surface of the first semiconductor layer 102 and the group III polar surface of the second semiconductor layer 104 face each other. Bonding (third step). In the first embodiment, the group III polar surface of the first semiconductor layer 102 and the group III polar surface of the second semiconductor layer 104 are joined. As a method of bonding, a known bonding method such as normal temperature bonding or surface activation bonding (SAB) may be used.

  By the way, when it forms by epitaxial growth on the surface of the 1st semiconductor layer 102, surface roughness whose arithmetic mean roughness Ra is about several nm may remain. In this case, the above-described bonding may be performed after the surface of the first semiconductor layer 102 is polished and planarized by a method such as chemical mechanical polishing (CMP). In order to obtain good bonding, it is desirable to planarize the surface of the first semiconductor layer 102 to a Ra of up to several hundred pm or less. In the case of planarization by CMP, in order to cut off a GaN crystal of about 100 nm, the first semiconductor layer 102 needs to have a film thickness in consideration of the amount to be cut at this time.

  Next, after the third step, the second substrate 103 is removed (peeled off), and as shown in FIG. 1D, the V-group polar surface of the second semiconductor layer 104 is exposed (fourth step). A known method may be used to remove the second substrate 103. For example, a method may be considered such that the substrate is scraped and thinned by back grinding, and the second semiconductor layer 104 is exposed and planarized by CMP.

  Here, at the interface between the second semiconductor layer 104 and the second substrate 103, a layer with low crystal quality such as the aforementioned GaN nucleation layer may be present. This layer generally has a thickness of about several tens of nm. Also, the crystals on top of the nucleation layer contain many defects and are not suitable for device applications. Therefore, it is desirable that the second semiconductor layer 104 be further cut by about 200 nm from the interface between the second substrate 103 and the second semiconductor layer 104, and a crystal with a sufficiently high crystal quality be used as the surface. Here, the main surface of the exposed second semiconductor layer 104 is a Group V polarity GaN crystal because it is an inverted Group III polarity grown GaN crystal, and is a Group V polarity plane.

  Next, after removing the second substrate 103 as described above, as shown in FIG. 1E, a resist pattern 106 is formed on the exposed V-group polar surface of the second semiconductor layer 104. The resist pattern 106 is provided with a plurality of openings 106 a periodically arranged. The plurality of openings 106 a are grooves extending in a predetermined direction. For example, a commonly used photoresist is applied on the second semiconductor layer 104 to form a coating film. By patterning this coating film by a known photolithography technique, a resist pattern 106 having a plurality of openings 106 a can be formed.

  The period of the plurality of openings 106 a in the resist pattern 106 manufactured here needs to be adjusted according to the wavelength of light serving as a target when operating as an optical element. Generally, the period is shorter when light of short wavelength is targeted. For example, considering an element that receives light in the communication wavelength band 1550 nm and obtains the second harmonic, it suffices to invert the polarization every 8 μm, and according to this, the plural openings 106 a are formed periodically. Just do it. This shape can be sufficiently processed with the accuracy of photolithography.

  Next, by selectively etching the second semiconductor layer 104 using the formed resist pattern 106 as a mask, as shown in FIG. 1F, a plurality of semiconductor devices arranged in the second semiconductor layer 104 and penetrating the second semiconductor layer 104 Groove portion 104a is formed (fifth step). In the first embodiment, the group III polar surface 107 of the first semiconductor layer 102 is exposed at the bottom of the plurality of grooves 104 a. At this time, it is preferable not to stop the etching described above on the surface of the first semiconductor layer 102, and to scrape the first semiconductor layer 102 by 10 nm or more in the thickness direction.

  The reason why the first semiconductor layer 102 is also etched to some extent is that the periphery of the bonding interface 105 is highly likely to be damaged during bonding. The damaged layer is assumed to be about 10 nm in thickness. In addition, when the first semiconductor layer 102 and the second semiconductor layer 104 are made of the same material, it is not easy to reliably stop the etching at the interface, and it is also assumed that the first semiconductor layer 102 is etched. Be done.

  As a method of etching, there is a method of using a KOH aqueous solution or a NaOH aqueous solution to dissolve the V group polar GaN crystal which is the second semiconductor layer 104 and using ICP-RIE to etch the first semiconductor layer 102. Further, a method of etching both the second semiconductor layer 104 and the first semiconductor layer 102 by ICP-RIE can be considered.

  Next, the resist pattern 106 is removed, and as shown in FIG. 1G, the second semiconductor layer 104 in which the plurality of grooves 104a are formed is exposed. For example, it is possible to remove by dissolving the resist pattern 106 with acetone and ethanol.

  Next, the nitride semiconductor is epitaxially grown from the bottom of each of the plurality of grooves 104a in the + c axis direction, and the third semiconductor layer 108 is formed in each of the plurality of grooves 104a with the growth surface as a group III polar surface (sixth Process). In the first embodiment, since the group III polar surface 107 of the first semiconductor layer 102 is exposed at the bottom of each of the plurality of grooves 104 a, the nitride semiconductor is epitaxially grown from the group III polar surface 107 in the + c axis direction. As shown in FIG. 1H, the third semiconductor layer 108 is formed in each of the plurality of grooves 104a.

  The third semiconductor layer 108 is grown with the growth surface as a group III polarity. For example, GaN may be epitaxially grown. Thus, the third semiconductor layer 108 whose upper surface (surface) is a group III polar surface and the portion of the second semiconductor layer 104 whose upper surface is a group V polarity are alternately arranged in the arrangement direction of the groove portions 104a. The periodic polarization inversion structure connected by is obtained.

  In the first embodiment, the same semiconductor GaN as the first semiconductor layer 102 is grown as the third semiconductor layer 108, but the third semiconductor layer 108 may be AlGaN, AlN, InGaN, or a combination of these materials. It may be a laminated structure. The important point is that the third semiconductor layer 108 is grown with the group III polarity by the epitaxial growth on the group III polarity first semiconductor layer 102 exposed by etching.

  In the first embodiment, the fourth semiconductor layer 109 is grown on the second semiconductor layer 104 in the region other than the groove portion 104 a in addition to the portion of the groove portion 104 a. The fourth semiconductor layer 109 is grown with the growth surface as the V group polarity.

  Next, the fourth semiconductor layer 109 of V group polarity grown on the second semiconductor layer 104 is removed by a method such as CMP, and the second semiconductor layer is combined with the surface of the third semiconductor layer 108 as shown in FIG. 1I. Flatten the surface of the substrate 104.

  As described above, during the growth of the third semiconductor layer 108, the V-group fourth semiconductor layer 109 is grown on the second semiconductor layer 104. As a result, the surface of the second semiconductor layer 104 is roughened, and it is assumed that a step is generated between the second semiconductor layer 104 and the third semiconductor layer 108. The convex portion of the second semiconductor layer 104 is planarized to the same height as the third semiconductor layer 108. It is important to make the surface of the periodically polarized structure free of large irregularities.

  According to the first embodiment described above, since there is no crystal growth in which the growth surface has a V-group polarity, an element having a periodic polarization inversion structure of a group III nitride semiconductor with good crystallinity can be manufactured. Moreover, according to the first embodiment, for example, there is no flattening or the like in a state in which the group III polar crystal is convex, and the element can be more easily manufactured without using a complicated process.

Second Embodiment
Next, a method for manufacturing a nitride semiconductor device according to the second embodiment of the present invention will be described with reference to FIGS. 2A to 2E. Also in the following, the case of producing a periodically poled device will be described as an example.

  First, as in the first embodiment, as a first step, the first semiconductor layer 102 made of a nitride semiconductor is formed on the first substrate 101 (FIG. 1A). Here, the nitride semiconductor crystal-grows (epitaxially grows) in the + c-axis direction to form the first semiconductor layer 102 with the growth surface as a group III polar surface. Next, as in the first embodiment described above, as a second step, the nitride semiconductor is crystal-grown in the + c-axis direction on the second substrate 103, and the growth surface is a III-group polar surface, so that the second semiconductor Layer 104 is formed (FIG. 1B).

  Next, in a third step, the first substrate 101 and the second substrate 103 are bonded to each other in a state in which the group III polar surface of the first semiconductor layer 102 and the group III polar surface of the second semiconductor layer 104 face each other. (Figure 1C).

  Next, as shown in FIG. 2A, the second substrate 103 is removed by laser lift-off by irradiating a laser from the direction of the second substrate 103 to expose the V group polarity surface of the second semiconductor layer 104. By the laser irradiation, the second semiconductor layer 104 in the vicinity of the interface with the second substrate 103 is broken. Therefore, in the second semiconductor layer 104, a layer of a nitride semiconductor (for example, GaN) of about several μm is grown as a peeling sacrificial layer before the growth of the portion to be an element.

  In addition, on the crystal surface after laser lift-off, surface roughness of Ra> several tens of nm or more remains. Therefore, it is necessary to planarize the exposed group V polarity surface of the second semiconductor layer 104 by a method such as CMP. It is desirable that planarization be performed until Ra is about several hundred pm. Usually, in order to planarize the above-mentioned level of surface roughness by CMP, it is necessary to remove a few hundreds nm of nitride semiconductor crystal. From the above, in the second embodiment, it is desirable that the thickness of the second semiconductor layer 104 be about 3 μm or more.

  Next, after removing the second substrate 103 as described above, as shown in FIG. 2B, an inorganic mask 116 made of, for example, silicon oxide on the exposed group V polarity surface of the second semiconductor layer 104. Form Similar to the resist pattern 106 described above, the inorganic mask 116 is provided with a plurality of openings 116 a periodically arranged. The plurality of openings 116a are grooves extending in a predetermined direction.

  For example, on the surface of the second semiconductor layer 104 which is a V-group polar surface, a pattern is disposed in the portion of the opening 116a, and a lift-off mask including the opening in a region other than the opening 116a is formed. The lift-off mask may be formed by patterning a well-known photoresist by photolithography. Next, silicon oxide is deposited to a thickness of several tens of nm by a well-known deposition method such as sputtering on the lift-off mask to form a silicon oxide layer. After that, the lift-off mask is removed (lifted off), whereby an inorganic mask 116 made of silicon oxide can be formed.

  Next, by selectively etching the second semiconductor layer 104 using the formed inorganic mask 116 as a mask, as shown in FIG. 2C, a plurality of semiconductor devices arranged in the second semiconductor layer 104 and penetrating the second semiconductor layer 104 Groove portion 104a is formed (fifth step). Also in the second embodiment, the group III polar surface 107 of the first semiconductor layer 102 is exposed at the bottom surfaces of the plurality of grooves 104 a. At this time, as in the first embodiment, it is desirable not to stop the etching described above on the surface of the first semiconductor layer 102 and to scrape the first semiconductor layer 102 by 10 nm or more in the thickness direction.

  Next, a nitride semiconductor is epitaxially grown in the + c axis direction from the group III polar surface 107 of the first semiconductor layer 102 at the bottom of each of the plurality of grooves 104a, and as shown in FIG. 2D, in each of the plurality of grooves 104a. The third semiconductor layer 108 is formed (sixth step). The third semiconductor layer 108 is grown with the growth surface as a group III polarity. For example, GaN may be epitaxially grown. Thus, the third semiconductor layer 108 whose upper surface (surface) is a group III polar surface and the portion of the second semiconductor layer 104 whose upper surface is a group V polarity are alternately arranged in the arrangement direction of the groove portions 104a. The periodic polarization inversion structure connected by is obtained.

  Here, in the second embodiment, the third semiconductor layer 108 is grown in the state where the inorganic mask 116 is formed. Therefore, as is well known, the inorganic mask 116 serves as a selective growth mask. The growth of the nitride semiconductor is prevented on the inorganic mask 116 other than the opening 116a, and the third semiconductor layer 108 is regrown only on the group III polar surface 107 at the bottom of the plurality of grooves 104a. Therefore, according to the second embodiment, by controlling the layer thickness of the second semiconductor layer 104, it is possible to control the thickness of the element. Since the second semiconductor layer 104 is manufactured by epitaxial growth of III group polarity, it is possible to obtain thickness controllability on the order of several nm.

  Next, the inorganic mask 116 is removed, and the surface of the second semiconductor layer 104 is planarized together with the surface of the third semiconductor layer 108 as shown in FIG. 2E. For example, the inorganic mask 116 made of silicon oxide can be selectively removed with respect to other nitride semiconductor layers by etching using hydrofluoric acid as an etching solution.

  Also in the second embodiment described above, since there is no crystal growth in which the growth surface has a V-group polarity, it is possible to manufacture an element having a periodic polarization inversion structure of a group III nitride semiconductor with good crystallinity. Further, according to the second embodiment, for example, there is no flattening or the like in a state in which the group III polar crystal is convex, and the element can be more easily manufactured without using a complicated process.

Third Embodiment
Next, a method of manufacturing a nitride semiconductor device according to the third embodiment of the present invention will be described with reference to FIGS. 3A to 3I. Also in the following, the case of producing a periodically poled device will be described as an example.

  First, as shown in FIG. 3A, the first semiconductor layer 102 made of a nitride semiconductor is formed on the first substrate 101 (first step). Here, the nitride semiconductor crystal-grows (epitaxially grows) in the + c-axis direction to form the first semiconductor layer 102 with the growth surface as a group III polar surface. This is similar to the first and second embodiments.

  Subsequently, the etch stop layer 201 and the bonding layer 202 are epitaxially grown on the first semiconductor layer 102. The bonding layer 202 is a layer that receives damage to crystals when bonding is performed. Furthermore, since the above-described planarization CMP may be performed before bonding, the bonding layer 202 is desirably 110 nm or more.

  The etching stop layer 201 is a layer that stops etching when etching the second semiconductor layer 104 and the bonding layer 202 described later. In addition, it also serves as a base when the third semiconductor layer 118 described later is regrown by epitaxial growth. Therefore, it is desirable that the etching stop layer 201 be a group III nitride and a material different from the bonding layer 202 and have a etching rate that is largely different.

  For example, there is a report that AlN has an etching rate ratio of about 38: 1 in ICP-RIE using a Cl-based gas relative to GaN (see Non-Patent Document 4). Therefore, when the bonding layer 202 is made of GaN and the etching stop layer 201 is made of AlN, etching can be stopped at the surface of the etching stop layer 201. In the third embodiment, the bonding layer 202 is made of GaN, and the etching stopper layer 201 is made of AlN. According to the third embodiment, since the first semiconductor layer 102 does not have to consider polishing before the bonding and bonding damage, it may be about 300 nm or more. It is important that all of these layers be grown with the growth plane as group III polarity.

  Next, as in the first and second embodiments described above, as shown in FIG. 3B, the nitride semiconductor is crystal-grown in the + c-axis direction on the second substrate 103, and the growth surface is made III-polar plane. The second semiconductor layer 104 is formed (second step).

  Next, as shown in FIG. 3C, the first substrate 101 and the second substrate 103 are formed in a state in which the group III polar surface of the first semiconductor layer 102 and the group III polar surface of the second semiconductor layer 104 face each other. Bonding (third step). In the third embodiment, the group III polar surface of bonding layer 202 and the group III polar surface of second semiconductor layer 104 are bonded.

  Next, after the third step, as in the first embodiment described above, the second substrate 103 is removed (peeled off), and as shown in FIG. 3D, the V group polarity surface of the second semiconductor layer 104 is exposed. (4th step). The main surface of the exposed second semiconductor layer 104 is a Group V polarity GaN crystal because it is an inverted Group III polarity grown GaN crystal, and is a Group V polarity plane.

  Next, after removing the second substrate 103 as described above, as shown in FIG. 3E, on the exposed group V polar surface of the second semiconductor layer 104 as in the first embodiment described above. , Resist pattern 106 is formed. The resist pattern 106 is provided with a plurality of openings 106 a periodically arranged.

  Next, the second semiconductor layer 104 and the bonding layer 202 are selectively etched using the formed resist pattern 106 as a mask, whereby the second semiconductor layer 104 is arranged in the second semiconductor layer 104 as shown in FIG. 3F. Forming a plurality of grooves 104a that penetrate through (step 5). In the third embodiment, the bonding layer 202 is also penetrated to form a plurality of grooves 104a, and the group III polar surface of the etching stopper layer 201 is exposed at the bottom of the plurality of grooves 104a. In the third embodiment, since the etching stop layer 201 is provided, the etching described above is automatically stopped at the etching stop layer 201.

  For example, an etching method in which the etching rate is largely different between the etching stopper layer 201 and the bonding layer 202 may be used. For example, when the etching stopper layer 201 is made of AlN, first, the second semiconductor layer 104 having V group polarity is etched by wet etching using KOH or the like to expose the group III polarity surface of the bonding layer 202. Next, the bonding layer 202 is selectively etched away by ICP-RIE using a chlorine-based gas having a large difference in etching rate between the bonding layer 202 made of GaN and the etching stop layer 201 made of AlN. In addition, the second semiconductor layer 104 to the bonding layer 202 may be etched by ICP-RIE using a Cl-based gas.

  Next, the resist pattern 106 is removed, and as shown in FIG. 3G, the second semiconductor layer 104 in which the plurality of grooves 104 a are formed is exposed. Note that, as described in Embodiment 2, when using an inorganic mask, the inorganic mask is not removed.

  Next, the nitride semiconductor is epitaxially grown from the bottom of each of the plurality of grooves 104a in the + c axis direction, and as shown in FIG. 3H, the growth surface in each of the plurality of grooves 104a is a III semiconductor polar surface Form 118 (sixth step). In the third embodiment, the third semiconductor layer 118 is regrown on the group III polarity surface of the etching stopper layer 201 exposed to the bottom surfaces of the plurality of grooves 104 a. For example, GaN may be epitaxially grown. Thus, the third semiconductor layer 118 whose upper surface (surface) is a group III polar surface and the portions of the second semiconductor layer 104 whose upper surface is a group V polarity are alternately arranged in the arrangement direction of the groove portions 104a. The periodic polarization inversion structure connected by is obtained.

  In the third embodiment, in order to stop the etching at the etching stop layer 201, the thickness of the element in which the second semiconductor layer 104 and the third semiconductor layer 118 are periodically arrayed before the growth of the third semiconductor layer 118; The relationship of the growth film thickness of the three semiconductor layers 118 can be known. From this, it is possible to control the device thickness by controlling the thickness of the layer to be grown. In the first and second embodiments, in order to control the device thickness in the growth stage of the second semiconductor layer 104 which is the beginning of the device manufacturing process, the device manufactured from the planned device thickness by the polishing process or the like in the device manufacturing process. It is assumed that the thickness is shifted. On the other hand, in the third embodiment, since the device thickness is controlled by the layer thickness of the third semiconductor layer 118 which is the final stage of the device manufacturing process, improvement in controllability is expected.

  When the resist pattern 106 is used as described above, the resist pattern 106 is removed and then regrowth is performed. Therefore, in addition to the groove portion 104 a, the second semiconductor layer 104 in the region other than the groove portion 104 a The fourth semiconductor layer 109 is grown. The fourth semiconductor layer 109 is grown with the growth surface as the V group polarity.

  Next, the fourth semiconductor layer 109 of V group polarity grown on the second semiconductor layer 104 is removed by a method such as CMP, and the second semiconductor layer is combined with the surface of the third semiconductor layer 118 as shown in FIG. 3I. Flatten the surface of the substrate 104. Since the third semiconductor layer 118 is scraped in this step, it is desirable to grow the third semiconductor layer 118 by a film thickness in consideration of this step. In the case of using the inorganic mask described in Embodiment 2, since the thickness to be removed by polishing such as CMP can be minimized, it is expected that the controllability of the element thickness by the third semiconductor layer 118 can be improved. it can.

  Also in the third embodiment described above, since there is no crystal growth in which the growth plane is made the V group polarity, it is possible to manufacture an element having a periodic polarization inversion structure of a group III nitride semiconductor with good crystallinity. Moreover, according to the first embodiment, for example, there is no flattening or the like in a state in which the group III polar crystal is convex, and the element can be more easily manufactured without using a complicated process.

Fourth Embodiment
Next, a method of manufacturing a nitride semiconductor device according to the fourth embodiment of the present invention will be described with reference to FIGS. 4A to 4C. In the following, the case of fabricating a waveguide type periodic polarization inverting element will be described as an example.

  First, as described in the first embodiment, as shown in FIG. 4A in the first to sixth steps, the second semiconductor layer 104 whose surface is a group III polar surface, and the surface is a group III polar surface. The third semiconductor layer 108 formed as a surface forms a periodically poled element alternately arranged on the first semiconductor layer 102.

  Next, on the second semiconductor layer 104 and the third semiconductor layer 108 alternately arranged, a mask pattern 301 extending in the arrangement direction and having a predetermined width is formed. For example, the mask pattern 301 may be formed by applying a photoresist to form a resist film, and patterning the formed resist film by a known photolithography technique.

  Next, the second semiconductor layer 104 and the third semiconductor layer 108 are patterned by etching the second semiconductor layer 104 and the third semiconductor layer 108 using the mask pattern 301 as a mask, as shown in FIG. 4B, the second semiconductor The layers 104 and the third semiconductor layers 108 are alternately arranged and connected, and a rib pattern 302 having a predetermined width extending in the arranging direction is formed (seventh step). After that, if the mask pattern 301 is removed, as shown in FIG. 4C, a waveguide type periodic polarization reversal element having the rib pattern 302 as a core can be obtained. For example, it is possible to dissolve and remove the mask pattern 301 with acetone and ethanol.

  Here, the period of the polarization inversion by the second semiconductor layer 104 and the third semiconductor layer 108 generally varies depending on the waveguide core size and the wavelength of the input light. For this reason, it is necessary to make the period different from that of the periodically poled device in the case where the waveguide structure as described in the above-described embodiment is not employed.

  The longer the waveguide having the rib pattern 302 as the core, the longer the interaction length, and the output of the second harmonic increases. However, if it is not possible to realize a uniform polarization inversion period in the waveguide direction of the waveguide, a uniform waveguide core size, etc., the second harmonic generation efficiency is lowered. In addition, increasing the waveguide length narrows the corresponding band, and it is required to design the length depending on the application.

  The width of the waveguide is a factor that determines the core size of the waveguide (the width of the rib pattern 302), and therefore, the width needs to be set in consideration of the wavelength and power of the input light. If the core size is reduced, only a single mode can be propagated, and improvement in conversion efficiency can be expected. However, in this case, the input power can not be increased in order to prevent the element breakdown because the power density is increased, and the output power can not be increased. From the above relationship, when manufacturing a waveguide-type periodic structure inversion element, it is important to determine the polarization inversion period after designing the waveguide structure.

  As described above, according to the present invention, the first semiconductor layer and the second semiconductor layer in which the growth surface is formed as the group III polarity are integrated with their group III polarity faces facing each other. The surface of the semiconductor layer is a group V polar face, and the surface of the first semiconductor layer facing the same direction as the individual group V polar faces is a group III polar face, so periodic polarization by a group III nitride semiconductor with good crystallinity An element with good characteristics having an inverted structure can be more easily manufactured.

  According to the present invention, first, it is possible to reduce the amount of defects in the second semiconductor layer 104 whose surface side is the V group polarity to the same level as a crystal grown with the group III polarity surface as the growth surface. To lead to In particular, when a group III nitride substrate whose main surface is a group III polar surface is used as the second substrate 103, group III nitride crystals can be produced by homoepitaxial growth, so that the group V polar crystal quality is higher than that of the prior art. Can be expected to improve significantly.

  In addition, the impurity concentration can be reduced and made uniform by forming only the growth with the group III polar plane as the growth plane. In the case where the group III polar plane is the growth plane (group III polar growth) and the case where the group V polar plane is the growth plane (group V polar growth) in the growth of the group III nitride crystal, There is a difference, and in general, the crystal of group V polarity takes in more impurities. In the first embodiment, since the group V polarity growth is not performed, the impurity concentration which is a light scattering source can be reduced.

  Furthermore, in the present invention, the crystals of the group III polarity and the group V polarity are not grown simultaneously as in the prior art, and the surface side of the second semiconductor layer is made the group V polarity plane. To grow a periodic structure. For this reason, it is not necessary to consider the thickness non-uniformity resulting from the growth rate being different between the group III polar growth and the group V polar growth. Even when irregularities are generated in the periodically poled structure, the convex portions are made of V group polar crystals, and therefore, it is possible to obtain a flat surface having the same height as that of group III polar crystals with little fluctuation in element thickness in the polishing process. Can. For this reason, it is possible to produce a periodically poled inverted structure having a uniform thickness by the thickness of the group III polar crystal regrown with good controllability by epitaxial growth.

  The present invention is not limited to the embodiments described above, and many modifications and combinations can be made by those skilled in the art within the technical concept of the present invention. It is clear.

  DESCRIPTION OF SYMBOLS 101 ... 1st board | substrate, 102 ... 1st semiconductor layer, 103 ... 2nd board | substrate, 104 ... 2nd semiconductor layer, 104a ... groove part, 105 ... junction interface, 106 ... resist pattern, 106a ... opening part, 107 ... III group polarity Surface 108 third semiconductor layer 109 fourth semiconductor layer.

Claims (5)

A first step of forming a first semiconductor layer whose main surface is a group III polar surface on a first substrate;
A second step of crystal-growing a nitride semiconductor in the + c axis direction on the second substrate to form a second semiconductor layer with the growth surface as a group III polar surface;
A third step of bonding the first substrate and the second substrate in a state in which the group III polar surface of the first semiconductor layer and the group III polar surface of the second semiconductor layer face each other;
After the third step, a fourth step of removing the second substrate to expose a V-group polar surface of the second semiconductor layer;
A fifth step of forming a plurality of grooves arranged in the second semiconductor layer and penetrating the second semiconductor layer after the fourth step;
And N. forming an epitaxial semiconductor in the + c axis direction from the bottom of each of the plurality of grooves and forming a third semiconductor layer in each of the plurality of grooves with the growth surface as a group III polar surface. A method of manufacturing a nitride semiconductor device characterized by In the method of manufacturing a nitride semiconductor device according to claim 1,
In the first step, a nitride semiconductor is crystal-grown in the + c axis direction on the first substrate to form the first semiconductor layer with a growth surface as a group III polar surface. How to make In the method of manufacturing a nitride semiconductor device according to claim 1 or 2,
The first substrate is made of any of silicon, sapphire and silicon carbide,
In the first process, the first semiconductor layer is formed to have a thickness of 410 nm or more. In the method of manufacturing a nitride semiconductor device according to claim 1,
The first substrate is made of a Group III nitride, the main surface of which is a Group III polar surface, and a portion of the first substrate is made of the first semiconductor layer. Method. In the manufacturing method of the nitride semiconductor device according to any one of claims 1 to 4,
After the sixth step, the second semiconductor layer and the third semiconductor layer are patterned, and the second semiconductor layer and the third semiconductor layer are alternately connected in the arrangement direction of the plurality of grooves. A method of manufacturing a nitride semiconductor device, further comprising: a seventh step of forming a rib pattern having a predetermined width extending in the arrangement direction of the plurality of grooves.

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