JP2019097101A - Solid state image pickup device and imaging system - Google Patents

Abstract

To provide a solid state image pickup device capable of reducing deterioration of an image quality due to a reset operation of a photoelectric conversion part during a non-accumulation period of an imaging scanning and a focus detection scanning.SOLUTION: The solid state image pickup device comprises: a plurality of pixels which is arranged so as to structure a plurality of pixel rows, and includes a plurality of photoelectric conversion parts, a holding part, an amplification part outputting a pixel signal based on an amount of an electric charge held by the holding part, and a reset part resetting each photoelectric conversion part; and a scanning circuit performing a reset operation of each photoelectric conversion part and a reading operation of the pixel signal based on the electric charge occurred in the photoelectric conversion part in each pixel row. Each of the plurality of pixel rows includes at least one pixel row, and structures a plurality of unit pixel rows setting the holding part as a unit. The scanning circuit executes the reset operation so that a timing of a start of the reset operation in each of the plurality of pixel rows is not overlapped with the period when performing the reading operation in the pixel row belonging to the adjacent unit pixel row of the unit pixel row to which the pixel row in which the reset operation is performed belongs.SELECTED DRAWING: Figure 10

Description

  The present invention relates to a solid-state imaging device and an imaging system.

  2. Description of the Related Art In an imaging system such as a video camera or an electronic still camera, an auto focus (AF) function of automatically performing focus (focus, focus) adjustment at the time of shooting is widely used. As an apparatus having an AF function, an imaging apparatus capable of acquiring both an imaging signal and a signal for focus detection is known.

  In Patent Document 1, an imaging signal is obtained by performing imaging scanning that thins and scans rows for imaging, and focus detection scanning that scans at least a part of a row that is not scanned by imaging scanning for focus detection. An imaging device is described which acquires both a focus detection signal. Further, Patent Document 1 describes that the image quality can be improved by resetting the photoelectric conversion unit in the non-accumulation period of the imaging scanning line and the focus detection scanning line.

JP, 2016-116214, A

  However, when the reset operation of the photoelectric conversion unit is performed in the non-accumulation period of the imaging scanning line and the focus detection scanning line as described in Patent Document 1, the image quality may be deteriorated depending on the mode.

  An object of the present invention is to provide a solid-state imaging device capable of reducing deterioration in image quality due to a reset operation of a photoelectric conversion unit in a non-accumulation period of an imaging scanning line and a focus detection scanning line.

  According to one aspect of the present invention, a plurality of pixel rows are arranged, each of the plurality of photoelectric conversion units generating charges by photoelectric conversion, and one of the plurality of photoelectric conversion units A plurality of pixels including a holding unit that holds a charge, an amplification unit that outputs a pixel signal based on an amount of the charge held by the holding unit, and a reset unit that resets the photoelectric conversion unit; And the charge transfer for transferring the charge generated in the photoelectric conversion unit to the holding unit, and the charge generated in the photoelectric conversion unit for each of the pixel rows. And a plurality of pixel rows each including at least one pixel row, and forming a plurality of unit pixel rows in units of the holding unit. , The scanning circuit The timing of the start of the reset operation in each of the pixel rows does not overlap with the period in which the read operation is performed in the pixel row belonging to the unit pixel row next to the unit pixel row to which the pixel row subject to the reset operation belongs. According to another aspect of the present invention, there is provided a solid state imaging device for performing the reset operation.

  According to the present invention, it is possible to reduce the deterioration of the image quality due to the reset operation of the photoelectric conversion unit in the non-accumulation period of the imaging scanning line and the focus detection scanning line.

It is a block diagram showing a schematic structure of a solid-state imaging device by a 1st embodiment. It is a circuit diagram showing an example of composition of a unit pixel of a solid imaging device by a 1st embodiment. It is a conceptual diagram of the imaging optical system in the solid-state imaging device by 1st Embodiment. It is a figure which shows the structural example of the vertical scanning circuit of the solid-state imaging device by 1st Embodiment. It is a schematic diagram which shows operation | movement of each pixel line in the drive method of the solid-state imaging device by 1st Embodiment. It is a schematic diagram which shows the timing of the imaging scan in the drive method of the solid-state imaging device by 1st Embodiment, and AF scan. 5 is a timing chart showing a reset operation, an imaging row reading operation, and an AF row reading operation. It is a schematic diagram which shows operation | movement of each pixel line in the drive method of the solid-state imaging device by 1st Embodiment. It is a timing chart which shows the drive method of the solid-state imaging device by a reference example. It is a timing chart which shows the drive method of the solid-state imaging device by a 1st embodiment. It is a circuit diagram which shows the structural example of the unit pixel of the solid-state imaging device by 2nd Embodiment. It is a schematic diagram which shows operation | movement of each pixel row in the drive method of the solid-state imaging device by 2nd Embodiment. It is a schematic diagram which shows the timing of the imaging scan in the drive method of the solid-state imaging device by 2nd Embodiment, and AF scan. It is a schematic diagram which shows operation | movement of each pixel row in the drive method of the solid-state imaging device by 2nd Embodiment. It is a timing chart which shows the drive method of the solid-state imaging device by a 2nd embodiment. It is a schematic diagram which shows the timing of the imaging scan in the drive method of the solid-state imaging device by 3rd Embodiment, and AF scan. It is a schematic diagram which shows the timing of the imaging scan in the drive method of the solid-state imaging device by 3rd Embodiment, and AF scan. It is a timing chart which shows the drive method of the solid-state imaging device by a reference example. It is a timing chart which shows the drive method of the solid-state imaging device by a 2nd embodiment. It is a block diagram which shows schematic structure of the imaging system by 4th Embodiment. It is a figure showing an example of composition of an imaging system by a 5th embodiment, and a mobile.

First Embodiment
A solid-state imaging device and a method of driving the same according to a first embodiment of the present invention will be described with reference to FIGS.

  First, the structure of the solid-state imaging device according to the present embodiment will be described using FIGS. 1 to 4. FIG. 1 is a block diagram showing a schematic configuration of a solid-state imaging device according to the present embodiment. FIG. 2 is a circuit diagram showing a configuration example of a unit pixel of the solid-state imaging device according to the present embodiment. FIG. 3 is a conceptual view of an imaging optical system in the solid-state imaging device according to the present embodiment. FIG. 4 is a view showing a configuration example of the vertical scanning circuit of the solid-state imaging device according to the present embodiment.

  As shown in FIG. 1, the solid-state imaging device 100 according to the present embodiment includes a pixel area 10, a vertical scanning circuit 20, a column readout circuit 30, a horizontal scanning circuit 40, an output circuit 50, and a control circuit 60. Have.

  The pixel area 10 is provided with a plurality of unit pixels 12 arranged in a matrix over a plurality of rows and a plurality of columns. FIG. 1 shows a pixel area 10 including n unit pixel rows from unit pixel row V1 to unit pixel row Vn. Each unit pixel row includes a plurality of unit pixels 12 arranged in one column in the row direction. The number of rows and the number of columns of the pixel array arranged in the pixel area 10 are not particularly limited. In addition to the unit pixels 12 for detecting imaging signals and focus detection signals, other pixels (not shown) such as light-shielded optical black pixels and dummy pixels that do not output signals are disposed in the pixel area 10. It may be done.

  A control line 14 is disposed on each unit pixel row of the pixel array of the pixel area 10 so as to extend in a first direction (horizontal direction in FIG. 1, in one example, horizontal direction). The control lines 14 are respectively connected to the unit pixels 12 arranged in the first direction, and a signal line common to the unit pixels 12 is formed. In the present specification, the first direction in which the control line 14 extends may be referred to as a row direction. Further, in each column of the pixel array of the pixel area 10, the output line 16 is disposed so as to extend in a second direction (vertical direction in FIG. 1, an example vertical direction in FIG. 1) intersecting the first direction. There is. The output lines 16 are respectively connected to the unit pixels 12 arranged in the second direction, and a signal line common to the unit pixels 12 is formed. In the present specification, the second direction in which the output line 16 extends may be referred to as the column direction.

  The control line 14 of each unit pixel row is connected to the vertical scanning circuit 20. The vertical scanning circuit 20 is a circuit unit that supplies a control signal for driving a readout circuit in the unit pixel 12 to the unit pixel 12 via the control line 14 when reading out a pixel signal from the unit pixel 12. One end of the output line 16 of each column is connected to the column readout circuit 30. The pixel signal read out from the unit pixel 12 is input to the column readout circuit 30 via the output line 16. The column readout circuit 30 is a circuit unit that performs predetermined signal processing, such as amplification processing and AD conversion processing, on pixel signals read out from the unit pixels 12. The column readout circuit 30 may include a differential amplifier circuit, a sample hold circuit, an AD converter circuit, and the like.

  The horizontal scanning circuit 40 is a circuit unit that supplies control signals for transferring the pixel signals processed by the column readout circuit 30 sequentially to the output circuit 50 for each column to the column readout circuit 30. The output circuit 50 includes a buffer amplifier, a differential amplifier, and the like, and is a circuit unit for outputting the pixel signal read from the column readout circuit 30 to a signal processing unit outside the solid-state imaging device 100. The control circuit 60 is a circuit unit for supplying control signals for controlling the operation of the vertical scanning circuit 20, the column readout circuit 30, the horizontal scanning circuit 40, and the output circuit 50 and the timing thereof. The control circuit 60 supplies at least a part of control signals for controlling the operation of the vertical scanning circuit 20, the column reading circuit 30, the horizontal scanning circuit 40, and the output circuit 50 and the timing thereof from outside the solid-state imaging device 100. Good.

  Each unit pixel 12 can be configured by, for example, the circuit shown in FIG. The unit pixel 12 shown in FIG. 2 includes photoelectric conversion units DA and DB, transfer transistors M1A and M1B, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

  The photoelectric conversion units DA, DB are, for example, photodiodes. The photoelectric conversion unit DA has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1A. The photoelectric conversion unit DB has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1B.

  The drains of the transfer transistors M1A and M1B are connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A connection node of the drains of the transfer transistors M1A and M1B, the source of the reset transistor M2, and the gate of the amplification transistor M3 is a so-called floating diffusion (FD) node. The capacitance component of the FD node functions as a holding unit of charges transferred from the photoelectric conversion units DA and DB, and also functions as a charge voltage conversion unit.

  The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply node that supplies the voltage VDD. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line 16. A current source 18 is connected to the output line 16.

  In the case of the unit pixel 12 shown in FIG. 2, the control line 14 includes transfer gate signal lines TXA and TXB, a reset signal line RES, and a selection signal line SEL. The transfer gate signal line TXA is connected to the gate of the transfer transistor M1A. The transfer gate signal line TXB is connected to the gate of the transfer transistor M1B. The reset signal line RES is connected to the gate of the reset transistor M2. The selection signal line SEL is connected to the gate of the selection transistor M4.

  The photoelectric conversion units DA and DB convert incident light into charges of an amount according to the light amount (photoelectric conversion), and accumulate the generated charges. The transfer transistor M1A transfers the charge of the photoelectric conversion unit DA to the FD node by being turned on. The transfer transistor M1B transfers the charge of the photoelectric conversion unit DB to the FD node by being turned on. The transfer transistors M1A and M1B constitute a charge transfer unit that transfers the charge of the photoelectric conversion units DA and DB to the FD node.

  The FD node has a voltage corresponding to the amount of charge transferred from the photoelectric conversion units DA and DB by charge-voltage conversion by the capacitance. The amplification transistor M3 has a configuration in which the voltage VDD is supplied to the drain and the bias current is supplied from the current source 18 to the source via the selection transistor M4, and an amplification unit (source follower circuit) having a gate as an input node Configure Thus, the amplification transistor M3 outputs a signal based on the voltage of the FD node to the output line 16 via the selection transistor M4. The reset transistor M2 is turned on to reset the FD node to a voltage corresponding to the voltage VDD. At this time, by turning on the transfer transistors M1A and M1B, reset of the photoelectric conversion units DA and DB is also possible. The reset transistor M2, together with the transfer transistors M1A and M1B, constitutes a reset unit that resets the photoelectric conversion units DA and DB.

  One common micro lens ML is disposed in the light incident direction of the photoelectric conversion units DA and DB, and light divided by the pupil is made to be incident on the photoelectric conversion unit DA and the photoelectric conversion unit DB, respectively. . For example, as shown in FIG. 3, color filters CF and microlenses ML are disposed on the photoelectric conversion units DA and DB. The light having passed through the pupil 70 of the imaging lens passes through the microlens ML and the color filter CF, and enters the photoelectric conversion units DA and DB. At this time, the light flux that has passed through a partial pupil region 72a of the pupil 70 of the imaging lens is incident on the photoelectric conversion unit DA. Further, the light flux that has passed through the other part of the pupil region 72b of the pupil 70 of the imaging lens is incident on the photoelectric conversion unit DB. In one example, the photoelectric conversion units DA and the photoelectric conversion units DB are arranged in the row direction. In another example, the photoelectric conversion units DA and the photoelectric conversion units DB are arranged in the column direction.

  Assuming that the subject image acquired by the photoelectric conversion unit DA is the A image and the subject image acquired by the photoelectric conversion unit DB is the B image, the relative position of the A and B images is detected to thereby shift the focus of the object image. The amount (defocus amount) can be detected. That is, it is possible to perform phase difference focus detection. A signal obtained by adding the signal based on the charge generated by the photoelectric conversion unit DA and the signal based on the charge generated by the photoelectric conversion unit DB can be used as an imaging signal.

  FIG. 4 is a circuit diagram showing a configuration of a portion related to driving of an arbitrary m-th row of vertical scanning circuit 20. Referring to FIG. The unit of one row in the description of FIG. 4 is not a unit pixel row but a pixel row.

  As shown in FIG. 4, the vertical scanning circuit 20 has a decoder unit 22 and a scanning circuit unit 24 provided for each pixel row of the pixel area 10. The scanning circuit unit 24 includes a logic generation unit 26 and a logic circuit that generates a control signal of the unit pixel 12 according to an output signal of the logic generation unit 26 or an external signal.

  The control circuit 60 supplies a predetermined control signal to the decoder unit 22 and the scanning circuit unit 24. The decoder unit 22 selects a row address based on the control signal supplied from the control circuit 60. For example, the decoder signal DEC [m] is supplied from the decoder unit 22 to the scanning circuit unit 24 in the m-th row. Among the plurality of control signals supplied from the control circuit 60 to the scan circuits 24 of all the rows, the row selection latch pulse for selecting the rows at regular intervals is transmitted from the common wiring to the scan circuit 24 of each row. Supplied to

  The logic generation unit 26 outputs a row selection signal to the wiring 111 in accordance with the decoder signal DEC [m] supplied from the decoder unit 22 and the row selection latch pulse supplied from the control circuit 60. The scanning circuit unit 24 takes the logical product of the row selection signal and the external PSEL signal to generate the control signal pSEL [m] supplied to the selection signal line SEL. Further, the scanning circuit unit 24 takes the NAND of the row selection signal and the external PRESB signal, and generates the control signal pRES [m] supplied to the reset signal line RES.

  Further, the logic generation unit 26 outputs a shutter operation signal to the wirings 113 and 114 in accordance with the decoder signal DEC [m] and the row selection latch pulse. The scanning circuit unit 24 takes a logical product of the shutter operation signal output to the wiring 113 and the external PTXA signal to generate a control signal pTXA [m]. Further, the scanning circuit unit 24 takes the logical product of the shutter operation signal output to the wiring 114 and the external PTXB signal to generate a control signal pTXB [m].

  The external PSEL signal, the external PRESB signal, the external PTXA signal, and the external PTXB signal may be supplied from the control circuit 60.

  Next, a method of driving the solid-state imaging device according to the present embodiment will be described with reference to FIGS. 5 and 8 are schematic views showing the operation of each pixel row in the method of driving the solid-state imaging device according to the present embodiment. FIG. 6 is a schematic view showing timings of imaging scanning and AF scanning. FIG. 7 is a timing chart showing a reset operation, an imaging row reading operation, and an AF row reading operation. FIG. 9 is a timing chart showing a driving method of the solid-state imaging device according to the reference example. FIG. 10 is a timing chart showing a driving method of the solid-state imaging device according to the present embodiment.

  FIG. 5 schematically shows the operation from the unit pixel row V1 to the unit pixel row V12 among the unit pixel row V1 to the unit pixel row Vn configuring the pixel area 10.

  In the method of driving the solid-state imaging device according to the present embodiment, the predetermined operation is performed in a cycle of four rows in units of unit pixel rows. That is, unit pixel rows V1, V2, V3, V5, V6, V7, V9, V10, and V11 are rows for acquiring imaging signals (hereinafter, referred to as "imaging rows"). The unit pixel rows V4, V8, and V12 are focus detection rows (hereinafter referred to as "AF rows") for acquiring a signal for focus detection.

  FIG. 6 is a schematic view showing timings of imaging scanning and AF scanning. In FIG. 6, the horizontal axis represents time, and the vertical axis represents the row scanning direction.

  The operation in each pixel row includes a reset operation (also referred to as “shutter operation”) and a read operation. The reset operation is an operation of resetting the charge of the photoelectric conversion units DA and DB. The charge accumulation period is started by releasing the reset state of the photoelectric conversion units DA and DB, and after a predetermined accumulation time has elapsed, the charge accumulation period is transferred by transferring the charges of the photoelectric conversion units DA and DB to the FD node. Ends. Transfer of charge from the photoelectric conversion units DA and DB to the FD node corresponds to the read operation. This series of operations is performed commonly for the imaging row and the AF row.

  The reset operation and the read operation in the imaging row, and the reset operation and the read operation in the AF row are performed row-sequentially, respectively. The accumulation time is determined by the timing of the reset operation and the read operation of each row. Such driving is so-called rolling shutter driving.

  In this specification, a series of operations in which the reset operation of the imaging row is performed in a row-sequential manner is referred to as “imaging reset scan”. Further, a series of operations for performing the reading operation of the imaging row in a row-sequential manner shall be referred to as “imaging lead scanning”. Further, the imaging reset scanning and the imaging lead scanning are collectively referred to as “imaging scanning”. Similarly, a series of operations for performing the reset operation of the AF row in a row-sequential manner shall be called "AF reset scan". In addition, a series of operations for performing the reading operation of the AF row in a row-sequential manner shall be referred to as "AF read scan". Further, the AF reset scan and the AF lead scan are collectively referred to as "focus detection scan (AF scan)".

  In the driving method of the present embodiment, the imaging scan and the AF scan are performed independently. In FIG. 6, a period from the timing of the reset operation of the imaging row to the timing of the reading operation is the charge accumulation time in the imaging row. Similarly, the period from the timing of the reset operation of the AF row to the timing of the read operation is the charge accumulation time in the AF row. Although FIG. 6 shows an example in which the AF row is read after reading the imaging row, the reading of the imaging row may be performed after reading the AF row.

  FIG. 7 is a timing chart showing a basic operation in one pixel row. 7A shows the reset operation in the imaging row and the AF row, FIG. 7B shows the reading operation in the imaging row, and FIG. 7C shows the reading operation in the AF row.

  In the reset operation, as shown in FIG. 7A, when the control signal pSEL is low and the control signal pRES is high, the control signals pTXA and pTXB are high at a predetermined timing according to the vertical scanning signal pV. Make it As a result, the transfer transistors M1A and M1B are turned on, and the photoelectric conversion units DA and DB are reset to a predetermined potential corresponding to the voltage VDD.

  In the read operation of the imaging row, as shown in FIG. 7B, the control signal pSEL is set to the high level at a predetermined timing according to the vertical scanning signal pV, and the selection transistor M4 is turned on. At this time, the control signal pRES is at high level, and the FD node is reset. After setting the control signal pRES to low level, by setting the control signal pSHn to high level, the reset signal output to the output line 16 through the selection transistor M4 is held in the sample and hold capacitor for N signal. The control signal pSHn is a control signal of a switch that controls connection and disconnection of the sample and hold capacitor for the N signal. Then, the control signals pTXA and pTXB are simultaneously set to the high level, and the signal charges accumulated in the photoelectric conversion units DA and DB are transferred to the FD node. At this time, by setting the control signal pSHs to a high level, the optical signal output to the output line 16 through the selection transistor M4 is held in the sample and hold capacitor for the S signal. The control signal pSHs is a control signal of a switch that controls connection and disconnection of the sample and hold capacitor for the S signal. Then, the horizontal transfer signal pH is sequentially turned on for each column to transfer the S signal and the N signal held in the sample and hold capacitor to the output circuit 50. By calculating and outputting the difference between the S signal and the N signal in the output circuit 50, it is possible to obtain a pixel signal with a good S / N ratio.

  In the reading operation of the AF row, as shown in FIG. 7C, an operation of setting only the control signal pTXA to high level and an operation of setting only the control signal pTXB to high level in the same procedure as the reading operation of the imaging row. And separately. Thereby, as focus detection signals, an A image signal based on only the signal charge stored in the photoelectric conversion unit DA and a B image signal based on only the signal charge stored in the photoelectric conversion unit DB are separately acquired. be able to.

  As described above, in the reset operation, the control signal pSEL is at the low level, and the pixel signal is not output to the output line 16. Therefore, the reset operation and the read operation of different rows can be performed at the same timing.

  FIG. 8 is a schematic view showing the operation of each pixel row in the method of driving a solid-state imaging device according to the present embodiment. The vertical direction in FIG. 8 indicates unit pixel rows V1 to V12 similar to those in FIG. The repetition period of the imaging row and the AF row is also the same as in the case of FIG. In FIG. 8, the horizontal direction is a time axis, and a control signal for selecting a row to be scanned, that is, a period H 1, a period H 2,... It is defined.

  For example, in the pixel of the unit pixel row V1 which is an imaging row, a period H1 is a period for accumulating signal charges (accumulation state), a period H2 is a period for performing an imaging signal readout operation, and a period H3 to a period H10 are It is a period (non-accumulation state) in which the charge to be the signal charge is not accumulated. The pixel in the unit pixel row V4 that is an AF row is a period in which the period H1 performs a reset operation for resetting the photoelectric conversion units DA and DB, and the period H2 to the period H10 are accumulation states. In this specification, a horizontal period in which a reset operation is performed may be referred to as a “reset period”, and a horizontal period in which a read operation is performed may be referred to as a “read period”.

  Next, problems to be solved by the driving method of the solid-state imaging device according to the present embodiment will be described with reference to FIG. FIG. 9 is an example of a timing chart showing operations in period H5, period H6 and period H7 of unit pixel rows V4, V5, V6 and V7.

  In FIG. 9, control signals for driving the selection transistors M4 of the unit pixel rows V4, V5, V6, and V7 are represented by pSEL4, pSEL5, pSEL6, and pSEL7, respectively. Further, control signals for driving the reset transistors M2 of the unit pixel rows V4, V5, V6 and V7 are represented by pRES4, pRES5, pRES6 and pRES7, respectively. Further, control signals for driving the transfer transistors M1A and M1B of the unit pixel rows V4, V5, V6 and V7 are represented by pTX4, pTX5, pTX6 and pTX7, respectively. The transfer transistors M1A and M1B of each pixel row are operated at different timings as shown in FIG. 7C in the readout operation of the AF row, but are operated at the same timing in the operation shown in FIG. Therefore, FIG. 9 shows one signal.

  The row selection latch pulse is supplied from the control circuit 60 to the vertical scanning circuit 20 as described with reference to FIG. Then, in the vertical scanning circuit 20, the row selection latch pulse and the external PSEL signal supplied from the outside of the sensor are logically selected to select each row. Therefore, the period between the row selection latch pulses is defined as a period H5, a period H6, and a period H7, respectively, based on the rising of the row selection latch pulse. That is, in FIG. 9, the period from time t0 to time t6 is period H5, the period from time t6 to time t12 is period H6, and the period from time t12 to time t18 is period H7.

  In period H5, unit pixel row V4 which is an AF row and unit pixel rows V6 and V7 which are imaging rows are in an accumulation state as shown in FIG. 8, and control signals pSEL, pRES and pTX of each row have predetermined levels. Will be held by On the other hand, in the period H5, the unit pixel row V5 which is an imaging row is a period in which the reading operation is performed as shown in FIG. 8, and the operation described below is performed.

  At time t0, the control signal pRES5 is at high level, and the FD node of the unit pixel row V5 is in the reset state.

  At time t1, the control signal pSEL5 is controlled to the high level by the vertical scanning circuit 20, so that the selection transistor M4 of the unit pixel row V5 is turned on, and the signal from the unit pixel 12 to the output line 16 of the unit pixel row V5. It becomes possible to read out. That is, the unit pixel row V5 is selected.

  At time t2, the vertical scanning circuit 20 controls the control signal pRES5 to a low level, whereby the reset of the FD node of the unit pixel row V5 is released. The pixel signal based on the voltage of the FD node after reset release is output as a reset signal (N signal) through the output line 16.

  At time t3, the control signal pTX5 is controlled to the high level by the vertical scanning circuit 20, and the signal charges accumulated in the photoelectric conversion units DA and DB of the unit pixel row V5 are transferred to the FD node. The pixel signal based on the voltage of the FD node after transfer of the signal charge is output as an optical signal (S signal) through the output line 16.

  At time t4, the control signal pRES5 is controlled to the high level by the vertical scanning circuit 20, whereby the potential of the FD node of the unit pixel row V5 is reset.

  At time t5, the control signal pSEL5 is controlled to a low level by the vertical scanning circuit 20, so that the selection transistor M4 of the unit pixel row V5 is turned off, and the unit pixel 12 of the unit pixel row V5 is disconnected from the output line 16. That is, the selection of the unit pixel row V5 is cancelled.

  In a period H6 started from time t6, the unit pixel row V4 as the AF row and the unit pixel row V7 as the imaging row are in the accumulation state as shown in FIG. 8, and the control signals pSEL, pRES, pTX of each row are , Is held at a predetermined level. On the other hand, in period H6, unit pixel row V5 which is an imaging row is a period of a non-accumulation state as shown in FIG. 8, and unit pixel row V6 which is an imaging row is a reading operation as shown in FIG. Period, and the operation described below is performed.

  At time t6, the vertical scanning circuit 20 controls the control signal pTX5 to the high level in response to the rising of the row selection pulse. As a result, the transfer transistors M1A and M1B of the unit pixel row V5 are turned on, and the photoelectric conversion units DA and DB are reset. The photoelectric conversion units DA and DB of the unit pixel row V5 maintain the reset state until the transfer transistors M1A and M1B are turned off. That is, the unit pixel row V5 is in the non-accumulated state.

  At time t7, the control signal pSEL6 is controlled to the high level by the vertical scanning circuit 20, so that the selection transistor M4 of the unit pixel row V6 is turned on, and the signal from the unit pixel 12 to the output line 16 of the unit pixel row V6 is It becomes possible to read out. That is, the unit pixel row V6 is selected.

  At time t8, the vertical scanning circuit 20 controls the control signal pRES6 to a low level, whereby the reset of the FD node of the unit pixel row V6 is released. The pixel signal based on the voltage of the FD node after reset release is output as a reset signal (N signal) through the output line 16.

  At time t9, the control signal pTX6 is controlled to the high level by the vertical scanning circuit 20, and the signal charges accumulated in the photoelectric conversion units DA and DB of the unit pixel row V6 are transferred to the FD node. The pixel signal based on the voltage of the FD node after transfer of the signal charge is output as an optical signal (S signal) through the output line 16.

  At time t10, the control signal pRES6 is controlled to the high level by the vertical scanning circuit 20, whereby the potential of the FD node of the unit pixel row V6 is reset.

  At time t11, the control signal pSEL6 is controlled to low level by the vertical scanning circuit 20, so that the selection transistor M4 of the unit pixel row V6 is turned off, and the unit pixel 12 of the unit pixel row V6 is disconnected from the output line 16. That is, the selection of the unit pixel row V6 is cancelled.

  In a period H7 started from time t12, the unit pixel row V4 which is the AF row is in the storage state as shown in FIG. 8, and the control signals pSEL4, pRES4 and pTX4 are held at predetermined levels. On the other hand, in period H7, unit pixel rows V5 and V6 which are imaging rows are in a non-accumulation state as shown in FIG. 8, and unit pixel rows V7 which are imaging rows are as shown in FIG. During a read operation, the operation described below is performed.

  At time t12, the control signal pTX6 is controlled to the high level by the vertical scanning circuit 20 according to the rise of the row selection pulse. As a result, the transfer transistors M1A and M1B of the unit pixel row V6 are turned on, and the photoelectric conversion units DA and DB are reset. The photoelectric conversion units DA and DB of the unit pixel row V6 maintain the reset state until the transfer transistors M1A and M1B are turned off. That is, the unit pixel row V6 is in the non-accumulated state.

  At time t13, the vertical scanning circuit 20 controls the control signal pSEL7 to the high level, so that the selection transistor M4 of the unit pixel row V7 is turned on, and the signal from the unit pixel 12 to the output line 16 of the unit pixel row V7 is output. It becomes possible to read out. That is, unit pixel row V7 is selected.

  At time t14, the vertical scanning circuit 20 controls the control signal pRES7 to a low level, whereby the reset of the FD node of the unit pixel row V7 is released. The pixel signal based on the voltage of the FD node after reset release is output as a reset signal (N signal) through the output line 16.

  At time t15, the control signal pTX7 is controlled to the high level by the vertical scanning circuit 20, and the signal charges accumulated in the photoelectric conversion units DA and DB of the unit pixel row V7 are transferred to the FD node. The pixel signal based on the voltage of the FD node after transfer of the signal charge is output as an optical signal (S signal) through the output line 16.

  At time t16, the control signal pRES7 is controlled to the high level by the vertical scanning circuit 20, whereby the potential of the FD node of the unit pixel row V7 is reset.

  At time t17, the control signal pSEL7 is controlled to the low level by the vertical scanning circuit 20, so that the selection transistor M4 of the unit pixel row V7 is turned off, and the unit pixel 12 of the unit pixel row V7 is disconnected from the output line 16. That is, the selection of the unit pixel row V7 is cancelled.

  However, in the driving method shown in FIG. 9, a difference is generated between the reading state of the unit pixel row V5 and the reading state of the unit pixel rows V6 and V7. That is, in the period H5 in which the reading operation of the unit pixel row V5 is performed, the unit pixel rows V4 and V6 adjacent to the unit pixel row V5 are in the storage state, and the pixel circuit is not operating. On the other hand, in the period H6 in which the reading operation of the unit pixel row V6 is performed, the reset operation of the photoelectric conversion units DA and DB is started in the unit pixel row V5 adjacent to the unit pixel row V6. In addition, in a period H7 in which the reading operation of the unit pixel row V7 is performed, in the unit pixel row V6 adjacent to the unit pixel row V7, the reset operation of the photoelectric conversion units DA and DB is started.

  In such a case, when capacitive coupling (coupling) occurs between unit pixels 12 of adjacent unit pixel rows, when the reset operation is started in the unit pixel rows adjacent to the period in which the read operation is performed. The influence is transmitted to the read signal and may be noise. Coupling between unit pixels 12 in adjacent unit pixel rows is not particularly limited, but may occur due to, for example, capacitive coupling between floating diffusion portions (FD nodes) of these unit pixels 12 or the like.

  For example, in the period H6 in which the reading of the unit pixel row V6 is performed, the reset operation of the photoelectric conversion units DA and DB of the unit pixels 12 of the unit pixel row V5 whose reading is completed in the period H5 is started. At this time, an influence of reset start of the photoelectric conversion units DA and DB of the unit pixel 12 of the unit pixel row V5 is transmitted to the readout signal from the unit pixel 12 of the unit pixel row V6, and may be superimposed on the output signal as noise. is there.

  Similarly, in the period H7 in which the reading of the unit pixel row V7 is performed, the reset operation of the photoelectric conversion units DA and DB of the unit pixels 12 of the unit pixel row V6 whose reading is completed in the period H6 is started. At this time, the influence of the start of resetting of the photoelectric conversion units DA and DB of the unit pixel 12 of the unit pixel row V6 is transmitted to the readout signal from the unit pixel 12 of the unit pixel row V7 and superimposed as noise on the output signal. is there.

  As a result, an output difference occurs due to the difference in noise component to be superimposed between the signal read out from the unit pixel row V5 and the signal read out from the unit pixel rows V6 and V7, which causes the image quality to deteriorate.

  From this point of view, in the present embodiment, the solid-state imaging device is driven according to, for example, the timing chart shown in FIG.

  The timing chart shown in FIG. 10 is different from the timing chart shown in FIG. 9 in the timing for starting the reset operation of the photoelectric conversion units DA and DB of the unit pixel 12 in the unit pixel row in the non-accumulation state.

  Specifically, in the unit pixel row V5, the time to start the reset operation of the photoelectric conversion units DA and DB of the unit pixel 12 in the non-accumulation state is shifted from time t6 to time t12. Similarly, in the unit pixel row V6, the time to start the reset operation of the photoelectric conversion units DA and DB of the unit pixel 12 in the non-accumulation state is shifted from time t12 to time t18. By doing this, for the unit pixel rows V5, V6, and V7, the operation states of the adjacent pixels in the horizontal period in which the read operation is performed can be made uniform.

  As a result, while performing the reset operation of the photoelectric conversion units DA and DB in the non-accumulated state, it is possible to reduce the image quality deterioration due to the occurrence of the unit pixel 12 affected and the unit pixel 12 not affected.

  As described above, according to this embodiment, it is possible to reduce the deterioration of the image quality due to the reset operation of the photoelectric conversion unit in the non-accumulation period of the imaging row and the focus detection row.

Second Embodiment
A solid-state imaging device and a method of driving the same according to a second embodiment of the present invention will be described with reference to FIGS. The same members of the present embodiment as those of the solid-state imaging device according to the first embodiment are represented by the same reference numbers not to repeat or to simplify their explanation.

  The solid-state imaging device according to the present embodiment is the same as the solid-state imaging device according to the first embodiment except that the configuration of the unit pixel 12 is different.

  FIG. 11 is a circuit diagram showing a configuration example of a unit pixel of the solid-state imaging device according to the present embodiment. The unit pixel 12 of the solid-state imaging device according to the present embodiment includes photoelectric conversion units DA1, DB1, DA2, DB2, transfer transistors M1A1, M1B1, M1A2, M1B2, a reset transistor M2, an amplification transistor M3, and a selection transistor M4. including.

  The photoelectric conversion units DA1, DB1, DA2, and DB2 are, for example, photodiodes. The photoelectric conversion unit DA1 has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1A1. The photoelectric conversion unit DB1 has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1B1. The photoelectric conversion unit DA2 has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1A2. The photoelectric conversion unit DB2 has an anode connected to the ground node and a cathode connected to the source of the transfer transistor M1B2.

  The drains of the transfer transistors M1A1, M1B1, M1A2 and M1B2 are connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. A connection node of the drains of the transfer transistors M1A1, M1B1, M1A2, and M1B2, the source of the reset transistor M2, and the gate of the amplification transistor M3 is an FD node. The capacitance component of the FD node functions as a holding unit of charges transferred from the photoelectric conversion units DA1, DB1, DA2, and DB2, and also functions as a charge-voltage conversion unit.

  The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply node that supplies the voltage VDD. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line 16. A current source 18 is connected to the output line 16.

  In the case of the unit pixel 12 shown in FIG. 11, the control line 14 includes transfer gate signal lines TXA1, TXB1, TXA2, TXB2, a reset signal line RES, and a selection signal line SEL. The transfer gate signal line TXA1 is connected to the gate of the transfer transistor M1A1. The transfer gate signal line TXB1 is connected to the gate of the transfer transistor M1B1. The transfer gate signal line TXA2 is connected to the gate of the transfer transistor M1A2. The transfer gate signal line TXB2 is connected to the gate of the transfer transistor M1B2. The reset signal line RES is connected to the gate of the reset transistor M2. The selection signal line SEL is connected to the gate of the selection transistor M4.

  The photoelectric conversion units DA1, DB1, DA2, DB2 convert (photoelectrically convert) incident light into an amount of charge corresponding to the light amount, and accumulate the generated charge. The transfer transistor M1A1 is turned on to transfer the charge of the photoelectric conversion unit DA1 to the FD node. The transfer transistor M1B1 is turned on to transfer the charge of the photoelectric conversion unit DB1 to the FD node. The transfer transistor M1A2 is turned on to transfer the charge of the photoelectric conversion unit DA2 to the FD node. The transfer transistor M1B2 is turned on to transfer the charge of the photoelectric conversion unit DB2 to the FD node. The transfer transistors M1A1, M1B1, M1A2, and M1B2 form a charge transfer unit that transfers the charges of the photoelectric conversion units DA1, DB1, DA2, and DB2 to the FD node.

  The FD node has a voltage corresponding to the amount of charge transferred from the photoelectric conversion units DA1, DB1, DA2, and DB2 by charge-voltage conversion by the capacitance. The amplification transistor M3 has a configuration in which the voltage VDD is supplied to the drain and the bias current is supplied from the current source 18 to the source via the selection transistor M4, and an amplification unit (source follower circuit) having a gate as an input node Configure Thus, the amplification transistor M3 outputs a signal based on the voltage of the FD node to the output line 16 via the selection transistor M4. The reset transistor M2 is turned on to reset the FD node to a voltage corresponding to the voltage VDD. At this time, when the transfer transistors M1A1, M1B1, M1A2, and M1B2 are turned on, the photoelectric conversion units DA1, DB1, DA2, and DB2 can be reset. The reset transistor M2, together with the transfer transistors M1A1, M1B1, M1A2, and M1B2, form a reset unit that resets the photoelectric conversion units DA1, DB1, DA2, and DB2.

  A common micro lens ML1 is disposed in the light incident direction of the photoelectric conversion units DA1 and DB1, and light divided into pupils is respectively incident on the photoelectric conversion units DA1 and DB1. Similarly, the common micro lens ML2 is disposed in the light incident direction of the photoelectric conversion units DA2 and DB2, and the light divided by the pupil is respectively incident on the photoelectric conversion units DA2 and DB2. There is.

  In one example, the photoelectric conversion units DA1 and the photoelectric conversion units DB1 are arranged in the row direction. The photoelectric conversion units DA2 and the photoelectric conversion units DB2 are arranged in the row direction. The photoelectric conversion unit DA1 and the photoelectric conversion unit DB1 (microlens ML1), and the photoelectric conversion unit DA2 and the photoelectric conversion unit DB2 (microlens ML2) are arranged in the column direction.

  The photoelectric conversion unit DA1 and the photoelectric conversion unit DB1, and the photoelectric conversion unit DA2 and the photoelectric conversion unit DB2 may be arranged in the column direction. The photoelectric conversion unit DA1 and the photoelectric conversion unit DB1 (microlens ML1), and the photoelectric conversion unit DA2 and the photoelectric conversion unit DB2 (microlens ML2) may be arranged in the row direction.

  The photoelectric conversion units DA1 and DB1 and the photoelectric conversion units DA2 and DB2 output signals based on light having passed through different microlenses ML1 and ML2, and are also elements of different pixels. In other words, each unit pixel 12 has pupil division pixels including the photoelectric conversion units DA1 and DB1 and pupil division pixels including the photoelectric conversion units DA2 and DB2. The pixel including the photoelectric conversion units DA1 and DB1 and the pixel including the photoelectric conversion units DA2 and DB2 share the FD node, the reset transistor M2, the amplification transistor M3, and the selection transistor M4. Each unit pixel row includes two pixel rows of a pixel row in which a plurality of pixels including photoelectric conversion units DA1 and DB1 are arranged and a pixel row in which a plurality of pixels including photoelectric conversion units DA2 and DB2 are arranged. It can be said that it has. In this case, the number of pixel rows included in the pixel array of the pixel area 10 is 2n. Among the pixels belonging to one unit pixel row, the pixels including the photoelectric conversion units DA1 and DB1 arranged in the same column and the pixels including the photoelectric conversion units DA2 and DB2 share the holding unit (FD node) . In other words, the plurality of pixel rows constitute a plurality of unit pixel rows in units of holding units.

  In the following description, when it is not necessary to distinguish two pixels of the unit pixel 12, the photoelectric conversion units DA1 and DB1 or the photoelectric conversion units DA2 and DB2 may be referred to as the photoelectric conversion units DA and DB. The transfer transistors M1A1 and M1B1 or the transfer transistors M1A2 and M1B2 may be referred to as transfer transistors M1A and M1B.

  Next, a method of driving the solid-state imaging device according to the present embodiment will be described with reference to FIG. 12 to FIG. 12 and 14 are schematic views showing the operation of each pixel row in the method of driving the solid-state imaging device according to the present embodiment. FIG. 13 is a schematic view showing timings of imaging scanning and AF scanning. FIG. 15 is a timing chart showing a method of driving the solid-state imaging device according to the present embodiment.

  FIG. 12 schematically shows the operation from the unit pixel row V1 to the unit pixel row V10 among the unit pixel row V1 to the unit pixel row Vn constituting the pixel area 10. Each unit pixel row includes two pixel rows as described above. Here, it is assumed that the code of each unit pixel row is assigned a branch number to distinguish two pixel rows belonging to these. For example, two pixel rows included in the unit pixel row V1 are described as "V1-1" and "V1-2". The same applies to the unit pixel row V2 and thereafter.

  Here, it is assumed that color filters of predetermined colors are arranged in a so-called Bayer arrangement in the pixels of each pixel row. For example, R or Gr is applied to the pixels in the pixel row V1-1, V2-1, V3-1, V4-1, V5-1, V 6-1, V7-1, V8-1, V9-1, and V10-1. Color filters are arranged. In addition, in the pixel rows V1-2, V2-2, V3-2, V4-2, V5-2, V6-2, V7-2, V8-2, V9-2, V10-2, Gb or A color filter of B is arranged.

  In the method of driving the solid-state imaging device according to the present embodiment, the predetermined operation is performed in a cycle of three rows in units of pixel rows. That is, the pixel rows V1-1, V2-2, V4-1, V5-2, V7-1, V8-2, and V10-1 are first imaging rows. The pixel rows V1-2, V3-1, V4-2, V6-1, V7-2, V9-1, and V10-2 are AF rows or non-readout rows. The pixel rows V2-1, V3-2, V5-1, V6-2, V8-1, and V9-2 are second imaging rows. Pixel row V1-1 and pixel row V2-1, pixel row V2-2 and pixel row V3-2, pixel row V4-1 and pixel row V5-1, pixel row V5-2 and pixel row V6-2, pixel row V7-1 and the pixel row V8-1, and the pixel row V8-2 and the pixel row V9-2 respectively have the same color filter array. Here, it is assumed that the pixel rows V1-2, V3-1, and V4-2 are non-readout rows, and the pixel rows V6-1, V7-2, V9-1, and V10-2 are AF rows.

  FIG. 13 is a schematic view showing timings of imaging scanning and AF scanning. In FIG. 13, the horizontal axis represents time, and the vertical axis represents the row scanning direction.

  As described in the first embodiment using FIG. 6, the operation in each pixel row includes the reset operation and the read operation. The reset operation and the read operation in the imaging row, and the reset operation and the read operation in the AF row are performed row by row, respectively. A series of operations for performing the reset operation of the imaging row in a row-sequential manner is imaging reset scanning, and a series of operations for performing the reading operation of the imaging row in a row-sequential manner is imaging lead scanning. Similarly, a series of operations for performing the reset operation of the AF row in a row-sequential manner is an AF reset scan, and a series of operations for performing a readout operation of the AF row in a row-sequential manner is an AF read scan. The AF area start position in FIG. 13 corresponds to the pixel row V6-1 in FIG. The accumulation time is determined by the timing of the reset operation and the read operation of each row.

  In the solid-state imaging device according to the present embodiment, as described above, among the pixels belonging to one unit pixel row, the pixels including the photoelectric conversion units DA1 and DB1 disposed in the same column and the pixels including the photoelectric conversion units DA2 and DB2 And share the holding unit (FD node).

  For example, when matching with a required angle of view, when reading out while thinning out some rows without reading out all the pixel rows, the photoelectric conversion units DA and DB of the pixels in the non-readout row are in the non-accumulation state Reset to However, when one of two pixel rows belonging to the same unit pixel row is a readout row and the other is a non-readout row, the holding unit (FD node) shared by the pixels of these two pixel rows is read out Needs to be used when reading out one of the pixel rows. Therefore, in the period in which the one pixel row is read, it is necessary to temporarily cancel the reset of the non-accumulation state in the other pixel row which is the non-readout row. On the other hand, it is also known that when the release timing of reset in the non-accumulated state is close to the read timing, it affects the output signal.

  From this point of view, in the present embodiment, in the case where one of the two pixel rows including the pixels sharing the storage unit (FD node) is in the accumulation state (including the readout period), the other pixel row is included. For the row, reset of the photoelectric conversion units DA and DB is released only during that time. That is, the reset in the non-accumulation state is performed when neither of the pixel rows sharing the holding unit (FD node) is in the accumulation state (shaded period indicated as “non-accumulation” in FIG. 13). With this configuration, it is possible to perform reading from the one pixel row and to suppress the influence on the output signal due to the release of the reset of the non-accumulation state.

  FIG. 14 is a schematic diagram more specifically showing the operation of each pixel row shown in FIG. The vertical direction in FIG. 14 indicates the pixel rows V1-1 to V10-2 similar to those in FIG. The repetition period of the first imaging row, the AF row (non-readout row), and the second imaging row is also the same as in the case of FIG. In FIG. 14, the horizontal direction is a time axis, and a period H1, a period H2,..., A period H10 are defined with the interval (one horizontal period) of row selection latch pulses as a reference unit. In this embodiment, signals of pixels (for example, pixels in pixel row V1-1 and pixels in pixel row V2-1) having color filters of the same color are output to the same output line 16 at the same timing. .

  As shown in the schematic view of FIG. 14, when one of the two pixel rows belonging to the same unit pixel row is in the accumulation state or at the time of the reading operation, the other pixel row is in the non-accumulation state An operation of canceling reset (PD reset) of the photoelectric conversion units DA and DB is performed.

  FIG. 15 is a timing chart showing an operation from period H5 to period H7 of pixel rows V4-1, V4-2, V5-1, V5-2, V6-1, V6-2, V7-1, V7-2. An example of

  In FIG. 15, control signals for driving the selection transistors M4 of the unit pixel rows V4, V5, V6, and V7 are represented by pSEL4, pSEL5, pSEL6, and pSEL7, respectively. Further, control signals for driving the reset transistors M2 of the unit pixel rows V4, V5, V6 and V7 are represented by pRES4, pRES5, pRES6 and pRES7, respectively. Further, control signals for driving the transfer transistors M1A1 and M1B1 of the pixel rows V4-1, V5-1, V6-1, and V7-1 are represented by pTX4-1, pTX5-1, pTX6-1, and pTX7-1, respectively. ing. Further, control signals for driving the transfer transistors M1A2 and M1B2 of the pixel rows V4-2, V5-2, V6-2, and V7-2 are represented by pTX4-2, pTX5-2, pTX6-2, and pTX7-2, respectively. ing. The transfer transistors M1A and M1B in each pixel row are operated at different timings as shown in FIG. 8C in the readout operation of the AF row, but are operated at the same timing in the operation shown in FIG. In FIG. 15, they are represented as one signal.

  In FIG. 15, the period from time t0 to time t6 is period H5, the period from time t6 to time t12 is period H6, and the period from time t12 to time t18 is period H7.

  In the period H5, the read operation is performed at the same time on the pixel row V4-1 and the pixel row V5-1 which are imaging rows including pixels provided with color filters of the same color set. The signals read from the two pixels in each column of the pixel rows are added and output from the same output line 16.

  Specifically, at time t1, the control signals pSEL4 and pSEL5 become high level, and the unit pixel rows V4 and V5 are selected. At time 2, the control signals pRES4 and pRES5 become low level, and the reset of the FD node of the unit pixel 12 of the unit pixel row V4 and V5 is released. At time t3, the control signals pTX4-1 and pTX5-1 become high level, and the charges of the photoelectric conversion units DA1 and DB1 of the pixels in the pixel row V4-1 and the charges of the photoelectric conversion units DA1 and DB1 of the pixels in the pixel row V5-1 Are transferred to the FD node. Thus, a signal obtained by adding the signal read from the pixel in the pixel row V4-1 and the signal read from the pixels in the pixel row V5-1 is output to the output line 16 of each column.

  In the period H6, the read operation is performed at the same time on the pixel row V4-2 and the pixel row V6-2, which are imaging rows including pixels provided with color filters of the same color set. The signals read from the two pixels in each column of the pixel rows are added and output from the same output line 16.

  Specifically, at time t7, the control signals pSEL5 and pSEL6 become high level, and the unit pixel rows V5 and V6 are selected. At time 8, the control signals pRES5 and pRES6 become low level, and the reset of the FD node of the unit pixel 12 of the unit pixel rows V5 and V6 is released. At time t9, the control signals pTX5-2 and pTX6-2 become high level, and the charges of the photoelectric conversion units DA2 and DB2 of the pixels of the pixel row V5-2 and the charges of the photoelectric conversion units DA2 and DB2 of the pixels of the pixel row V6-2 Are transferred to the FD node. Thus, a signal obtained by adding the signal read from the pixel of the pixel row V5-2 and the signal read from the pixels of the pixel row V6-2 is output to the output line 16 of each column.

  The pixels in the pixel rows V4-1 and V5-1 for which the read operation is completed in the period H5 shift to the non-accumulation state. At this time, since neither the pixel row V4-1 and the pixel row V4-2 sharing the holding portion (FD node) are in the storage state, the control signal pRES4 is held at the high level, and the photoelectric conversion portion DA in the non-storage state , DB is reset. On the other hand, of the pixel rows V5-1 and V5-2 sharing the holding portion (FD node), the pixel row V5-2 is in the storage state (read operation period), and thus the pixel row V5-1 is in the non-storage state. The photoelectric conversion units DA and DB are not reset.

  In the period H7, the read operation is performed at the same time on the pixel row V7-1 and the pixel row V8-1, which are imaging rows including pixels provided with color filters of the same color set. The signals read from the two pixels in each column of the pixel rows are added and output from the same output line 16.

  Specifically, at time t13, the control signal pSEL7 and the control signal pSEL8 (not shown) become high level, and the unit pixel rows V7 and V8 are selected. At time 14, the control signal pRES7 and the unshown pRES8 become low level, and the reset of the FD node of the unit pixel 12 of the unit pixel rows V7 and V8 is released. At time t15, the control signal pTX7-1 and the control signal pTX8-1 (not shown) become high level, and the charge of the photoelectric conversion units DA1 and DB1 of the pixel of the pixel row V7-1 and the photoelectric conversion unit DA1 of the pixel of the pixel row V8-1 , DB1's charge is transferred to the FD node. Thus, a signal obtained by adding the signal read from the pixel of the pixel row V7-1 and the signal read from the pixels of the pixel row V8-1 is output to the output line 16 of each column.

  The pixels in the pixel rows V5-2 and V6-2 for which the read operation has been completed in the period H6 shift to the non-accumulation state. At this time, since the pixel row V5-1 and the pixel row V5-2 sharing the holding portion (FD node) are not in the storage state, the control signal pRES5 is held at the high level, and the photoelectric conversion portion DA in the non-storage state. , DB is reset. On the other hand, of the pixel rows V6-1 and V6-2 sharing the holding portion (FD node), the pixel row V6-1 is in the accumulation state as the AF row, and the pixel row V6-2 is in the non-accumulation state. The photoelectric conversion units DA and DB are not reset.

  When the states at the time of readout of the pixel row in each period are compared, in the pixel row V4-1 and the pixel row V5-1 in which the readout operation is performed in the period H5, the photoelectric conversion units DA in the non-accumulation state in the adjacent unit pixel row V3. , DB is reset. Similarly, in the pixel row V5-2 and the pixel row V6-2 in which the read operation is performed in the period H6, the photoelectric conversion units DA and DB in the non-accumulation state are reset in the adjacent unit pixel row V4. On the other hand, in the pixel row V7-1 and the pixel row V8-1 in which the readout operation is performed in the period H7, the photoelectric conversion units DA and DB in the non-accumulation state are not reset in the adjacent unit pixel row V6. Therefore, as described in the first embodiment, an output difference occurs due to a difference in noise components to be superimposed between the signals read out in the periods H5 and H6 and the signal read out in the period H7, thereby degrading the image quality. It becomes a cause.

  From this point of view, also in the present embodiment, the reset of the photoelectric conversion units DA and DB in the non-accumulated state in the unit pixel row V4 is started from time t6. Similarly, the reset of the photoelectric conversion units DA and DB in the non-accumulated state in the unit pixel row V5 is started from time t12. As a result, while performing the reset operation of the photoelectric conversion units DA and DB in the non-accumulated state, it is possible to reduce the image quality deterioration due to the occurrence of the unit pixel 12 affected and the unit pixel 12 not affected. Further, in the present embodiment, since the lines to be thinned out are reduced and the signals of a plurality of pixel lines are added and read out at the same time, it is possible to reduce moiré.

  As described above, according to this embodiment, it is possible to reduce the deterioration of the image quality due to the reset operation of the photoelectric conversion unit in the non-accumulation period of the imaging scanning line and the focus detection scanning line.

Third Embodiment
A solid-state imaging device and a method of driving the same according to a third embodiment of the present invention will be described using FIGS. 16 to 19. The same members of the present embodiment as those of the solid-state imaging device according to the first and the second embodiments are represented by the same reference numerals, and the description will be omitted or simplified.

  In the present embodiment, a driving example will be described in which a phase difference detection signal and an imaging signal are acquired from a pixel row including pixels that output a phase difference detection signal in the solid-state imaging device according to the first embodiment.

  FIG. 16 schematically shows the operation from the unit pixel row V1 to the unit pixel row V5 among the unit pixel row V1 to the unit pixel row Vn constituting the pixel area 10.

  In the driving method of the solid-state imaging device according to the present embodiment, it is assumed that the predetermined operation is performed in a cycle of three rows in units of unit pixel rows. That is, the unit pixel rows V1, V3, and V4 are rows for acquiring imaging signals (hereinafter, referred to as "imaging rows"). The unit pixel rows V2 and V5 are imaging / focus detection rows (hereinafter referred to as “imaging / AF rows”) that acquire signals for imaging and acquire signals for focus detection.

  FIG. 17 is a schematic diagram more specifically showing the operation of each pixel row shown in FIG. The vertical direction in FIG. 17 indicates unit pixel rows V1 to V5 similar to those in FIG. The repetition period of the imaging row and the imaging / AF row is also the same as in the case of FIG. In FIG. 17, the horizontal direction is a time axis, and a period H1, a period H2,..., A period H10 are defined with the interval (one horizontal period) of row selection latch pulses as a reference unit.

  For example, in the unit pixel row V1, the reset operation is performed in the period H1, the accumulation is performed in the period H2 to the period H3, and the image signal readout operation is performed in the period H4. After the period H5, the photoelectric conversion units DA and DB in the non-accumulation state are reset.

  In the unit pixel row V2, the reset operation is performed in the period H3, the storage is performed in the period H4, and the read operation is performed in the periods H5 and H6. After the period H7, the photoelectric conversion units DA and DB in the non-accumulation state are reset. The operation of the unit pixel row V2 is different from the operation of the unit pixel row V1 in that the signal for focus detection is read out in the H5 period one horizontal period before the period H6 in which the signal for image pickup is read out. .

  FIG. 18 is an example of a timing chart showing an operation from period H1 to period H10 of unit pixel row V1 to unit pixel row V5. In FIG. 18, control signals for driving the transfer transistors M1A of unit pixel rows V1, V2, V3, V4 and V5 are represented by pTX1-A, pTX2-A, pTX3-A, pTX4-A, and pTX5-A, respectively. ing. Control signals for driving the transfer transistors M1B of the unit pixel rows V1, V2, V3, V4, and V5 are represented by pTX1-B, pTX2-B, pTX3-B, pTX4-B, and pTX5-B, respectively.

  In the unit pixel row V1, in the period H1, the control signals pTX1_A and pTX1_B are controlled to the high level to simultaneously perform the reset operation of the photoelectric conversion units DA and DB, and start accumulation of signal charges. After the accumulation periods H2 and H3 have elapsed, the control signals pTX1_A and pTX1_B are simultaneously controlled to the high level in the period H4, and the signal charges accumulated in the photoelectric conversion units DA and DB are transferred to the FD node and added. Read out as imaging information.

  In the unit pixel row V2, in period H3, the control signals pTX2_A and pTX2_B are controlled to the high level to perform reset operations of the photoelectric conversion units DA and DB simultaneously, and start accumulation of signal charges. After the accumulation period of the period H4, the control signal pTX2_A is controlled to the high level in the period H5, the signal charge accumulated in the photoelectric conversion unit DA is transferred to the FD node, and read out as focus detection information (A signal). Thereafter, while holding the charge transferred from the photoelectric conversion unit DA to the FD node, the control signals pTX2_A and pTX2_B are simultaneously controlled to the high level in the period H6, and stored in the photoelectric conversion units DA and DB. Transfer the signal charge to the FD node. As a result, the signal charges generated by the photoelectric conversion units DA and DB during the two horizontal periods of the periods H4 and H5 are added at the FD node and read as imaging information (A + B signal). By obtaining the B signal from the A signal and the A + B signal thus acquired, it becomes possible to perform phase difference detection based on the A signal and the B signal.

  At this time, in the period H6 in which the reading of the unit pixel row V2 is performed, the unit pixel row V1 adjacent to the unit pixel row V2 is in the non-accumulation state, and the photoelectric conversion units DA and DB are reset. On the other hand, in the period H7 in which the reading of the unit pixel row V3 is performed, the unit pixel row V2 adjacent to the unit pixel row V3 is in the non-accumulation state, and the reset of the photoelectric conversion units DA and DB is started. Therefore, as described in the first embodiment, there is a concern that noise caused by the start of resetting of the photoelectric conversion units DA and DB in the non-accumulated state of the unit pixel row V2 is superimposed on the signal read from the unit pixel row V3. is there.

  From such a viewpoint, in the present embodiment, the solid-state imaging device is driven in accordance with, for example, the timing chart shown in FIG. In the timing chart shown in FIG. 19, the start of the reset of the photoelectric conversion units DA and DB in the non-accumulation state is delayed by two horizontal periods (2H period) than in the case of FIG. With this configuration, reset of the photoelectric conversion units DA and DB in the non-accumulation state is not performed in adjacent unit pixel rows at the time of reading of any unit pixel row, and deterioration in image quality due to noise mixing can be reduced.

  As a result, while performing the reset operation of the photoelectric conversion units DA and DB in the non-accumulated state, it is possible to reduce the image quality deterioration due to the occurrence of the unit pixel 12 affected and the unit pixel 12 not affected.

  As described above, according to this embodiment, it is possible to reduce the deterioration of the image quality due to the reset operation of the photoelectric conversion unit in the non-accumulation period of the imaging scanning line and the focus detection scanning line.

Fourth Embodiment
An imaging system according to a fourth embodiment of the present invention will be described with reference to FIG. The same members of the present embodiment as those of the solid-state imaging device according to the first to third embodiments are represented by the same reference numbers not to repeat or to simplify their explanation. FIG. 20 is a block diagram showing a schematic configuration of an imaging system according to the present embodiment.

  The solid-state imaging device 100 described in the first to third embodiments is applicable to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, in-vehicle cameras, observation satellites and the like. In addition, a camera module including an optical system such as a lens and a solid-state imaging device is also included in the imaging system. FIG. 20 illustrates a block diagram of a digital still camera as an example of these.

  The imaging system 200 illustrated in FIG. 20 includes an imaging device 201, a lens 202 for forming an optical image of a subject on the imaging device 201, a diaphragm 204 for changing the amount of light passing through the lens 202, and protection of the lens 202. Barrier 206. The lens 202 and the diaphragm 204 are optical systems that condense light on the imaging device 201. The imaging device 201 is the solid-state imaging device 100 described in the first to third embodiments, and converts an optical image formed by the lens 202 into image data.

  The imaging system 200 also includes a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 performs AD conversion for converting an analog signal output from the imaging device 201 into a digital signal. In addition, the signal processing unit 208 performs an operation of outputting image data by performing various corrections and compressions as necessary. The AD conversion unit which is a part of the signal processing unit 208 may be formed on the semiconductor substrate provided with the imaging device 201, or may be formed on a semiconductor substrate different from the imaging device 201. In addition, the imaging device 201 and the signal processing unit 208 may be formed on the same semiconductor substrate.

  The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 further includes a recording medium 214 such as a semiconductor memory for recording or reading imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading the recording medium 214. Have. The recording medium 214 may be built in the imaging system 200 or may be removable.

  The imaging system 200 further includes an overall control / calculation unit 218 that controls various operations and the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from the outside, and the imaging system 200 may have at least the imaging device 201 and a signal processing unit 208 that processes an output signal output from the imaging device 201.

  The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

  By applying the solid-state imaging device 100 according to the first to third embodiments, an imaging system capable of acquiring a high quality image with little noise can be realized.

Fifth Embodiment
An imaging system and a mobile unit according to a fifth embodiment of the present invention will be described with reference to FIG. FIG. 21 is a diagram showing the configuration of an imaging system and a mobile according to the present embodiment.

  FIG. 21 (a) shows an example of an imaging system related to a vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the solid-state imaging device 100 according to any one of the first to third embodiments. The imaging system 300 performs image processing on a plurality of image data acquired by the imaging device 310, and the parallax (phase difference of parallax image) from the plurality of image data acquired by the imaging system 300. It has the parallax acquisition part 314 which performs calculation. In addition, the imaging system 300 calculates the distance to the object based on the calculated parallax, and the collision determination unit 318 determines whether there is a possibility of collision based on the calculated distance. And. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are an example of a distance information acquisition unit that acquires distance information to an object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 318 may use any of the distance information to determine the collision possibility. The distance information acquisition means may be realized by hardware designed specifically, or may be realized by a software module. Also, it may be realized by an FPGA (Field Programmable Gate Array), an ASIC (Application Specific Integrated Circuit) or the like, or may be realized by a combination of these.

  The imaging system 300 is connected to the vehicle information acquisition device 320, and can acquire vehicle information such as a vehicle speed, a yaw rate, and a steering angle. Further, the imaging system 300 is connected to a control ECU 330, which is a control device that outputs a control signal for generating a braking force to the vehicle based on the determination result of the collision determination unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, when the possibility of collision is high as the determination result of the collision determination unit 318, the control ECU 330 performs vehicle control to avoid a collision and reduce damage by applying a brake, returning an accelerator, suppressing an engine output or the like. The alarm device 340 sounds an alarm such as a sound, displays alarm information on a screen of a car navigation system or the like, gives a vibration to a seat belt or a steering wheel, or the like to warn the user.

  In the present embodiment, the imaging system 300 captures an image of the surroundings of the vehicle, for example, the front or the rear. The imaging system in the case of imaging a vehicle front (imaging range 350) was shown in FIG.21 (b). The vehicle information acquisition device 320 sends an instruction to the imaging system 300 or the imaging device 310. Such a configuration can further improve the accuracy of distance measurement.

  Although an example in which control is performed so as not to collide with another vehicle has been described above, the present invention is also applicable to control for automatically driving following other vehicles, and control for automatically driving so as not to get out of a lane. . Furthermore, the imaging system is not limited to a vehicle such as a host vehicle, but can be applied to, for example, a mobile object (mobile device) such as a ship, an aircraft, or an industrial robot. In addition, the present invention can be applied not only to mobiles but also to devices that widely use object recognition, such as Intelligent Transport System (ITS).

[Modified embodiment]
The present invention is not limited to the above embodiment, and various modifications are possible.

  For example, a configuration in which part of the configuration of any of the embodiments is added to another embodiment or a configuration in which a part of the configuration of the other embodiment is replaced is also an embodiment of the present invention.

  In the above embodiment, although the case where the influence of the fluctuation of the potential of the FD node occurs between adjacent unit pixel rows is described as an example, the influence of the fluctuation of the potential of the FD node is the same as that of the adjacent unit pixel rows. It may occur out of range. Therefore, it is preferable to apply the driving method described in the above embodiment to at least a unit pixel row in which the influence of the fluctuation of the potential of the FD node accompanying the reset operation is affected.

  Further, in the above embodiment, the pupil division is performed by sharing one microlens ML with two photoelectric conversion units DA and DB of one pixel. However, a part of the pupil is formed by the light shielding film and the wiring layer The pupil division may be performed by two pixels having a photoelectric conversion unit that shields the area.

  Further, in the above embodiment, all pixels arranged in the pixel area 10 are pupil divided pixels, but it is not necessary to set all pixels as pupil divided pixels. For example, at least a part of the pixels belonging to at least the AF row may be pupil divided pixels.

  Further, although one output line 16 is disposed in each column in the above embodiment, a plurality of output lines 16 may be disposed in each column. In this case, the reading operation for one imaging row and the reading operation for another imaging row are simultaneously executed, and the pixel signal read from the pixels belonging to the one imaging row and the pixel signal read from the pixels belonging to the other imaging row Can be output to separate output lines arranged in the same column.

  Further, the imaging system shown in the above embodiment is an example of an imaging system to which the solid-state imaging device of the present invention can be applied, and an imaging system to which the solid-state imaging device of the present invention can be applied is shown in FIGS. It is not limited to the configuration shown in FIG.

  In addition, the said embodiment only shows the example of embodiment in the case of implementing this invention, and the technical scope of this invention should not be limitedly interpreted by these. That is, the present invention can be implemented in various forms without departing from the technical concept or the main features thereof.

DA, DB, DA1, DB1, DA2, DB2 ... photoelectric conversion units M1A, M1B, M1A1, M1B1, M1A2, M1B2 ... transfer transistor M2 ... reset transistor M3 ... amplification transistor M4 ... selection transistor 10 ... pixel area 12 ... unit pixel 14 ... Control line 16 ... Output line 20 ... Vertical scanning circuit 60 ... Control circuit 100 ... Solid-state imaging device

Claims (9)

A plurality of photoelectric conversion units arranged to form a plurality of pixel rows, each of which generates an electric charge by photoelectric conversion; a holding unit which holds the electric charge generated in any of the plurality of photoelectric conversion units; A plurality of pixels including an amplification unit that outputs a pixel signal based on the amount of charge held by the holding unit, and a reset unit that resets the photoelectric conversion unit;
The photoelectric conversion unit includes, for each of the plurality of pixels, a reset operation of the photoelectric conversion unit of the pixel and charge transfer for transferring the charge generated in the photoelectric conversion unit to the holding unit for each pixel row. And a scanning circuit for reading out a pixel signal based on the charge generated in
Each of the plurality of pixel rows includes at least one pixel row, and configures a plurality of unit pixel rows having the holding unit as a unit,
The scanning circuit performs the read operation in a pixel row belonging to a unit pixel row next to a unit pixel row to which the pixel row to which the reset operation is performed belongs in a timing of starting the reset operation in each of the plurality of pixel rows. A solid-state imaging device characterized in that the reset operation is performed so as not to overlap with a period to be performed. The holding portion of the pixel of the unit pixel row to which the pixel row to which the reset operation is performed belongs and the holding portion of the pixel of the unit pixel row next to the unit pixel row to which the pixel row to which the reset operation is performed are adjacent. The solid-state imaging device according to claim 1, which matches. The plurality of pixel rows constitute the unit pixel row by two adjacent pixel rows, and the pixels belong to one of the two pixel rows constituting the unit pixel row and the other pixel row. The pixel shares the holding unit and the amplification unit,
The scanning circuit executes the reset operation when neither a pixel belonging to the one of the two pixel rows constituting the unit pixel row nor a pixel belonging to the other is an accumulation period. The solid-state imaging device according to claim 1 or 2. The plurality of pixel rows include a plurality of imaging rows acquiring imaging signals and a plurality of focus detection rows acquiring focus detection signals.
The scanning circuit performing the reset operation and the reading operation on the plurality of imaging rows such that the signals of the plurality of focus detection rows are output after the signals from the plurality of imaging rows; The solid-state imaging device according to any one of claims 1 to 3, wherein a focus detection scan for performing the reset operation and the readout operation is independently performed on the plurality of focus detection rows. . The plurality of photoelectric conversion units included in each of the plurality of pixels include a first photoelectric conversion unit and a second photoelectric conversion unit sharing a microlens.
The plurality of pixel rows include a plurality of imaging rows acquiring imaging signals, and a plurality of imaging / focus detection rows acquiring imaging signals and focus detection signals.
The scanning circuit performs a read operation of a pixel signal based on the charge generated in the first photoelectric conversion unit in the first horizontal period in each of the plurality of imaging and focus detection rows, and performs the first operation. The pixel signal readout operation based on the charge generated in the first photoelectric conversion unit and the second photoelectric conversion unit is performed in a second horizontal period following the horizontal period. The solid-state imaging device according to 2. The scanning circuit simultaneously executes the reading operation for one pixel row and the reading operation for another pixel row, and a pixel signal read from pixels belonging to the one pixel row and the other pixel row The solid-state imaging device according to any one of claims 1 to 5, wherein a pixel signal read out from a pixel to which the pixel belongs is output to the same output line. The scanning circuit simultaneously executes the reading operation for one pixel row and the reading operation for another pixel row, and a pixel signal read from pixels belonging to the one pixel row and the other pixel row The solid-state imaging device according to any one of claims 1 to 5, wherein a pixel signal read out from a pixel to which the pixel belongs is output to separate output lines arranged in the same column. A solid-state imaging device according to any one of claims 1 to 7,
And a signal processing unit configured to process a signal output from the pixel of the solid-state imaging device. It is a mobile and
A solid-state imaging device according to any one of claims 1 to 7,
Distance information acquisition means for acquiring distance information to an object from a parallax image based on a signal from the solid-state imaging device;
A control unit configured to control the movable body based on the distance information.

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