JP7490708B2 - Photoelectric conversion device - Google Patents

Description

The present invention relates to a photoelectric conversion device.

Patent Document 1 discloses a solid-state imaging device having an analog-to-digital (AD) conversion circuit that converts pixel signals output from pixels into digital signals. The solid-state imaging device disclosed in Patent Document 1 reduces image quality degradation caused by streaking that can occur during operation of the AD converter by shorting vertical signal lines between columns.

JP 2015-56840 A

However, the method described in the above-mentioned Patent Document 1 may not be effective enough depending on the circuit configuration of the photoelectric conversion device to which it is applied.

Therefore, the present invention aims to provide a photoelectric conversion device that can output a higher quality signal.

According to one aspect of the present invention, there is provided an image display device comprising: a plurality of pixels; a plurality of output lines to which signals are respectively output from corresponding pixels; an amplifier section arranged corresponding to each of the plurality of output lines and configured to amplify the signal output to the corresponding output line; a comparator section arranged corresponding to each of the plurality of output lines and configured to have a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the amplifier section and the second input terminal receiving a reference signal; and a switch having a first terminal and a second terminal, the plurality of output lines including a first output line and a second output line, the first terminal being connected to a node between the amplifier section corresponding to the first output line and the comparator section corresponding to the first output line, a comparison unit that compares the signal corresponding to an output of the amplifier unit with the reference signal; and a switch that is connected to a node between an amplifier unit that corresponds to a line of force and a comparison unit that corresponds to the second output line , the comparison unit being capable of performing an offset clamp operation that sets an offset based on potentials input to the first input terminal and the second input terminal, the comparison unit being capable of comparing the signal corresponding to the output of the amplifier unit with the reference signal, the switch being turned on during a period before the offset clamp operation is completed, and the switch being turned off during a period after the offset clamp operation is completed and before a first comparison operation after the completion of the offset clamp operation is started .

According to another aspect of the present invention, there is provided a photoelectric conversion device having a plurality of pixels, a plurality of output lines to which signals are output from the corresponding pixels, an amplifier unit arranged corresponding to each of the plurality of output lines and amplifying the signal output to the corresponding output line, a comparison unit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, a signal corresponding to the output of the amplifier unit is input to the first input terminal and a reference signal is input to the second input terminal, a second input capacitance arranged corresponding to each of the plurality of output lines, and a switch having a first terminal and a second terminal, the reference signal is input to the second input terminal through the second input capacitance, the plurality of output lines include a first output line and a second output line, the first terminal is connected to a second input capacitance corresponding to the first output line, the second terminal is connected to a second input capacitance corresponding to the second output line, the comparison unit is capable of performing an offset clamp operation to set an offset based on the potential input to the first input terminal and the second input terminal, and the switch is turned on during a period before the offset clamp operation is completed.

According to another aspect of the present invention, there is provided a comparison circuit having a plurality of pixels, a plurality of output lines to which signals are respectively output from corresponding pixels, a comparison circuit arranged corresponding to each of the plurality of output lines and having a first input terminal and a second input terminal, a signal corresponding to an output of the output line is input to the first input terminal and a reference signal is input to the second input terminal, a switch having a first terminal and a second terminal, and a first input capacitance arranged corresponding to each of the plurality of output lines, wherein a signal corresponding to an output of the output line is input to the first input terminal via the first input capacitance, the plurality of output lines include a first output line and a second output line, and the first terminal is connected to a first input capacitance corresponding to the first output line, The second terminal is connected to a first input capacitance corresponding to the second output line, the comparison unit is capable of performing an offset clamp operation to set an offset based on potentials input to the first input terminal and the second input terminal , the comparison unit is capable of performing a comparison operation between the signal corresponding to the output of the output line and the reference signal, and the switch is turned on during a period before the offset clamp operation is completed, and the switch is turned off during a period after the offset clamp operation is completed and before a first comparison operation after the offset clamp operation is completed starts .

According to another aspect of the present invention, there is provided a photoelectric conversion device comprising: a plurality of pixels; a plurality of output lines to which signals are output from the corresponding pixels; a comparison unit arranged corresponding to each of the plurality of output lines, having a first input terminal and a second input terminal, to which a signal corresponding to the output of the output line is input to the first input terminal and a reference signal is input to the second input terminal; a second input capacitance arranged corresponding to each of the plurality of output lines; and a switch having a first terminal and a second terminal, wherein the reference signal is input to the second input terminal via the second input capacitance; the plurality of output lines include a first output line and a second output line; the first terminal is connected to a second input capacitance corresponding to the first output line; and the comparison unit is capable of performing an offset clamp operation to set an offset based on the potential input to the first input terminal and the second input terminal; and the switch is turned on during a period before the offset clamp operation is completed, and the switch is turned off after the offset clamp operation is completed.

The present invention provides a photoelectric conversion device that can output a higher quality signal.

1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a first embodiment. FIG. 2 is a circuit diagram showing a configuration of a pixel and a column circuit according to the first embodiment. 5 is a timing chart showing a method for driving the photoelectric conversion device according to the first embodiment. FIG. 5 is a timing chart showing a method for driving the photoelectric conversion device according to the first embodiment. FIG. FIG. 11 is a circuit diagram showing a configuration of a pixel and a column circuit according to a second embodiment. FIG. 13 is a circuit diagram showing a configuration of a pixel and a column circuit according to a third embodiment. FIG. 13 is a circuit diagram showing a configuration of a pixel and a column circuit according to a fourth embodiment. FIG. 13 is a circuit diagram showing a configuration of a pixel and a column circuit according to a fourth embodiment. FIG. 13 is a circuit diagram showing a configuration of a pixel and a column circuit according to a fifth embodiment. FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a fifth embodiment. FIG. 13 is a circuit diagram showing a configuration of a pixel and a column circuit according to a fifth embodiment. FIG. 13 is a timing chart showing a method for driving a photoelectric conversion device according to a fifth embodiment. FIG. 13 is a block diagram of an apparatus according to a sixth embodiment. FIG. 23 is a block diagram of an apparatus according to a seventh embodiment.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings. Identical or corresponding elements in multiple drawings are given the same reference numerals, and their description may be omitted or simplified.

In the first to fifth embodiments described below, an image pickup device will be mainly described as an example of a photoelectric conversion device. However, the photoelectric conversion device in each embodiment is not limited to an image pickup device, and can be applied to other devices. Examples of other devices include a distance measurement device and a photometry device. The distance measurement device can be, for example, a focus detection device or a distance measurement device using TOF (Time-Of-Flight). The photometry device can be a device that measures the amount of light incident on the device.

[First embodiment]
1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to the first embodiment. The photoelectric conversion device includes a pixel array 10, a current source 13, a vertical scanning circuit 14, a timing generator 15, a reference signal generating circuit 16, a counter 17, a digital signal processing circuit 18, and a readout circuit 19.

The pixel array 10 has a plurality of pixels 100 arranged in a matrix across a plurality of rows and a plurality of columns. Each of the plurality of pixels 100 includes a photoelectric conversion unit consisting of a photoelectric conversion element such as a photodiode. The pixel 100 outputs a photoelectric conversion signal, which is an analog signal corresponding to the amount of light incident on the photoelectric conversion element. The pixel 100 also outputs a noise signal, which is an analog signal of a noise level. The pixel array 10 may also have optical black pixels (not shown) in which the photoelectric conversion element is shielded from light, and the output signal of the pixel is used as a reference for the black level.

In each row of the pixel array 10, a plurality of control lines 11 are arranged, extending in a first direction (horizontal direction in FIG. 1). Each of the plurality of control lines 11 is connected to the pixels 100 arranged in the first direction, and serves as a signal line common to these pixels 100. The first direction in which the control lines 11 extend is sometimes called the row direction or horizontal direction. The control lines 11 are connected to a vertical scanning circuit 14.

In each column of the pixel array 10, an output line 12 is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. Each of the output lines 12 is connected to the pixels 100 arranged in the second direction, and serves as a signal line common to these pixels 100. The second direction in which the output lines 12 extend is sometimes called the column direction or vertical direction. Each of the output lines 12 is connected to a readout circuit 19 and a current source 13 arranged corresponding to each column.

The vertical scanning circuit 14 is a control circuit that receives a control signal output from the timing generator 15, generates a control signal for driving the pixels 100, and supplies the control signal to the pixels 100 via the control line 11. The vertical scanning circuit 14 may include logic circuits such as a shift register and an address decoder. The vertical scanning circuit 14 drives the pixels 100 of the pixel array 10 on a row-by-row basis. The signals read out from the pixels 100 on a row-by-row basis are input to the readout circuit 19 via the output line 12 provided for each column of the pixel array 10.

In FIG. 1, only three rows and three columns of pixels 100, control lines 11, and output lines 12 are shown, but in reality, the pixels 100, control lines 11, and output lines 12 may be arranged over thousands of rows and thousands of columns.

The readout circuit 19 has a column circuit 20 and a horizontal scanning circuit 25 provided corresponding to the output line 12 of each column. The column circuit 20 has a function of reading out the noise signal and photoelectric conversion signal output from the pixel 100 and converting them into a digital signal, and a function of holding the digital signal after AD conversion. The column circuit 20 has an amplifier unit 21, an analog signal holding unit 22, an AD conversion unit 23, and a digital signal holding unit 24.

The amplifier 21 amplifies the noise signal and the photoelectric conversion signal output from the pixel 100 and outputs an analog signal. The analog signal holding unit 22 temporarily holds the analog signal output from the amplifier 21. The analog signal holding unit 22 also outputs the held signal.

The reference signal generating circuit 16 is a circuit that receives a control signal output from the timing generator 15 and generates a reference signal to be supplied to the AD conversion unit 23. The reference signal is a signal having a predetermined amplitude, and may include, for example, a signal whose signal level (signal magnitude) changes over time. The reference signal typically includes a ramp signal. A ramp signal is a signal whose signal level changes monotonically over time, for example, a signal whose output voltage monotonically decreases or increases over time. The ramp signal also includes a signal whose potential changes in a step-like manner. Note that the reference signal is not particularly limited as long as it has an amplitude applicable to AD conversion.

The AD conversion unit 23 compares the signal output from the analog signal holding unit 22 with the reference signal output from the reference signal generation circuit 16, and outputs a latch signal based on the comparison result to the digital signal holding unit 24.

The counter 17 counts the pulses of the clock signal to generate a count signal whose value changes over time and outputs it to the digital signal holding unit 24.

The digital signal holding unit 24 holds the count signal output from the counter 17 as a digital signal at the timing when the latch signal output from the AD conversion unit 23 changes. The digital signal holding unit 24 can hold the digital values of the noise signal and the photoelectric conversion signal.

The horizontal scanning circuit 25 performs scanning to sequentially supply control signals to the digital signal holding units 24 of each column. As a result, the digital signals held in the digital signal holding units 24 of each column are sequentially transferred to the digital signal processing circuit 18. The horizontal scanning circuit 25 can be configured using a shift register, an address decoder, etc.

The digital signal processing circuit 18 processes the digital signals output from the digital signal holding unit 24 of each column and outputs the processed signals to the outside of the photoelectric conversion device. Examples of signal processing performed by the digital signal processing circuit 18 include correction processing using digital correlated double sampling and amplification processing.

The timing generator 15 is a control circuit for supplying control signals to the vertical scanning circuit 14, the readout circuit 19, the reference signal generating circuit 16, and the counter 17 to control their operation and timing. At least some of the control signals supplied to the vertical scanning circuit 14, the readout circuit 19, the reference signal generating circuit 16, and the counter 17 may be supplied from outside the photoelectric conversion device.

2 is a circuit diagram showing the configuration of the pixel 100 and the column circuit 20 according to this embodiment. In FIG. 2, the circuit configuration of two pixels 100 and a part of the circuit configuration of two columns of the column circuit 20 of the photoelectric conversion device of FIG. 1 are extracted and shown in more detail. The two columns shown in FIG. 2 are the nth column and the n+1th column (n is a natural number). The nth column and the n+1th column are sometimes simply called the first column and the second column. When it is necessary to distinguish between the elements of the two columns, the symbols of some elements in FIG. 2 may be given the suffix "a" indicating that they are elements of the nth column or the suffix "b" indicating that they are elements of the n+1th column. In addition, the output line 12 (12a) through which a signal is output from the pixel 100a of the nth column may be called the first output line, and the output line 12 (12b) through which a signal is output from the pixel 100b of the n+1th column may be called the second output line. The elements in the nth column and the n+1th column have roughly the same configuration, so a description of the elements in the n+1th column may be omitted.

FIG. 2 illustrates pixels 100a and 100b, a current source 13, amplifiers 21a and 21b, analog signal holding units 22a and 22b, AD converters 23a and 23b, and a switch 191. The other elements in FIG. 1 are omitted in FIG. 2.

Pixel 100a has a photoelectric conversion element PD, a transfer transistor M1, a reset transistor M2, an amplification transistor M3, and a selection transistor M4.

The photoelectric conversion element PD is, for example, a photodiode. The anode of the photoelectric conversion element PD is connected to the ground node, and the cathode of the photoelectric conversion element PD is connected to the source of the transfer transistor M1. The drain of the transfer transistor M1 is connected to the source of the reset transistor M2 and the gate of the amplification transistor M3. The node FD to which the drain of the transfer transistor M1, the source of the reset transistor M2, and the gate of the amplification transistor M3 are connected is a so-called floating diffusion portion. The floating diffusion portion includes a capacitance component (floating diffusion capacitance) and functions as a charge storage portion. The floating diffusion capacitance includes PN junction capacitance, wiring capacitance, etc.

The drain of the reset transistor M2 and the drain of the amplification transistor M3 are connected to a power supply voltage node to which a voltage VDD is supplied. The source of the amplification transistor M3 is connected to the drain of the selection transistor M4. The source of the selection transistor M4 is connected to the output line 12.

In the case of the pixel configuration of FIG. 2, the control line 11 of each row includes a signal line connected to the gate of the transfer transistor M1, a signal line connected to the gate of the reset transistor M2, and a signal line connected to the gate of the selection transistor M4. A control signal PTX is supplied to the gate of the transfer transistor M1 from the vertical scanning circuit 14. A control signal PRES is supplied to the gate of the reset transistor M2 from the vertical scanning circuit 14. A control signal PSEL is supplied to the gate of the selection transistor M4 from the vertical scanning circuit 14. Multiple pixels 100a, 100b in the same row are connected to a common signal line and are simultaneously controlled by a common control signal.

In this embodiment, the description will be made on the assumption that, of the electron-hole pairs generated in the photoelectric conversion element PD by the incidence of light, the electrons are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 100a may be composed of an N-type MOS transistor. When each transistor is composed of an N-type MOS transistor, the corresponding transistor is turned on when a high-level control signal is supplied from the vertical scanning circuit 14. Also, the corresponding transistor is turned off when a low-level control signal is supplied from the vertical scanning circuit 14. However, the signal charge is not limited to electrons, and holes may be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is the opposite conductivity type to that described in this embodiment. Also, the names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor or the function of interest. Some or all of the names of the source and drain used in this embodiment may be called by the opposite names.

The photoelectric conversion element PD converts incident light into an amount of charge corresponding to the amount of light (photoelectric conversion). When the transfer transistor M1 is turned on, it transfers the charge held by the photoelectric conversion element PD to the node FD. The charge transferred from the photoelectric conversion element PD is held in the capacitance (floating diffusion capacitance) of the node FD. As a result, the node FD has a potential corresponding to the amount of charge transferred from the photoelectric conversion element PD through charge-voltage conversion by the floating diffusion capacitance.

When the selection transistor M4 is turned on, it connects the amplification transistor M3 to the output line 12. The amplification transistor M3 has a configuration in which a voltage VDD is supplied to its drain and a bias current is supplied to its source from a current source 13 via the selection transistor M4, forming an amplification circuit (source follower circuit) with the gate as an input node. As a result, the amplification transistor M3 outputs a signal based on the voltage of the node FD to the output line 12 via the selection transistor M4. In this sense, the amplification transistor M3 and the selection transistor M4 are an output section that outputs a pixel signal according to the amount of charge held in the node FD.

The reset transistor M2 has a function of controlling the supply of a voltage (voltage VDD) to the node FD to reset the node FD as a charge storage unit. When the reset transistor M2 is turned on, it resets the node FD to a voltage corresponding to the voltage VDD.

The amplifier 21a has an input capacitance 211, a differential amplifier 212, a feedback capacitance 213, and a switch 214. The first terminal of the input capacitance 211 is an input node of the amplifier 21a. The first terminal of the input capacitance 211 is connected to the output line 12. The second terminal of the input capacitance 211 is connected to the inverting input terminal of the differential amplifier 212, the first terminal of the feedback capacitance 213, and the first terminal of the switch 214. A power supply line having a reference voltage Vc0r is connected to the non-inverting input terminal of the differential amplifier 212. The output terminal of the differential amplifier 212 is an output node of the amplifier 21a. The output terminal of the differential amplifier 212 is connected to the second terminal of the feedback capacitance 213 and the second terminal of the switch 214.

With the above circuit configuration, the amplifier 21a functions as an inverting amplifier circuit that amplifies the voltage of the analog signal output to the output line 12. The switch 214 is controlled by a control signal from the timing generator 15 and is controlled to be on or off. When the switch 214 transitions from on to off, the potential input to the input capacitance 211 at that time is clamped. The amplification factor of the amplifier 21a when the switch 214 is off is determined by the ratio of the capacitance value of the input capacitance 211 to the capacitance value of the feedback capacitance 213.

The analog signal holding unit 22a has a switch 221, a holding capacitance 222, and an amplifier 223. The output node of the amplifier 21a is connected to a first terminal of the switch 221. The first terminal of the switch 221 is the input node of the analog signal holding unit 22a. The second terminal of the switch 221 is connected to the holding capacitance 222 and the input terminal of the amplifier 223. The output terminal of the amplifier 223 is the output node of the analog signal holding unit 22a.

The switch 221 is controlled by a control signal from the timing generator 15 and is controlled to be on or off. When the switch 221 transitions from on to off, the analog signal output from the amplifier 21a at that time is held in the holding capacitance 222. The amplifier 223 (first buffer) is a buffer circuit such as a source follower, and outputs an analog signal according to the potential held in the holding capacitance 222. In this way, the analog signal holding unit 22a forms a sample-and-hold circuit that holds the analog signal output from the amplifier 21a.

The first terminal of the switch 191 is connected to the node to which the storage capacitor 222 of the nth column is connected, and the second terminal of the switch 191 is connected to the node to which the storage capacitor 222 of the n+1th column is connected. The switch 191 is controlled by a control signal sw from the timing generator 15 and is controlled to be on or off. When the control signal sw is at a high level, the switch 191 is turned on, and when the control signal sw is at a low level, the switch 191 is turned off. When the switch 191 is on, the analog signal held in the storage capacitor 222 of the nth column and the analog signal held in the storage capacitor 222 of the n+1th column are averaged. The potential of the analog signal output from the analog signal holding unit 22a of the nth column is defined as comp_in[n], and the potential of the analog signal output from the analog signal holding unit 22b of the n+1th column is defined as comp_in[n+1].

The AD conversion unit 23a has input capacitors 231 and 236, a comparator 232, switches 233 and 234, and an amplifier 235. The comparator 232 is a fully differential comparator having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, and functions as a comparison unit for AD conversion. The comparator 232 compares the potentials of the first input terminal and the second input terminal, and outputs a signal based on the comparison result as an output signal OUT from the first output terminal and the second output terminal. This output signal is input to a latch circuit (not shown). The latch circuit outputs the latch signal to the digital signal holding unit 24.

The output node of the analog signal holding unit 22a is connected to a first terminal of an input capacitance 231 (first input capacitance). The first terminal of the input capacitance 231 is an input node of the AD conversion unit 23a. The second terminal of the input capacitance 231 is connected to a first input terminal of the comparator 232 and a first terminal of the switch 233. The second terminal of the switch 233 is connected to a first output terminal of the comparator 232.

The reference signal Vramp is input to the input terminal of the amplifier 235 from the reference signal generating circuit 16. The amplifier 235 (second buffer) is a buffer circuit such as a source follower. The output terminal of the amplifier 235 is connected to a first terminal of the input capacitance 236 (second input capacitance). The second terminal of the input capacitance 236 is connected to the second input terminal of the comparator 232 and the first terminal of the switch 234. The second terminal of the switch 234 is connected to the second output terminal of the comparator 232. The switches 233 and 234 are controlled by a control signal comp_res from the timing generator 15 and are controlled to be on or off. When the control signal comp_res is at a high level, the switches 233 and 234 are turned on, and when the control signal comp_res is at a low level, the switches 233 and 234 are turned off.

3(a) is a timing diagram showing a driving method of the photoelectric conversion device according to this embodiment. FIG. 3(a) shows the levels of the control signals comp_res and sw, the potential of the reference signal Vramp, and the potential of the input signals comp_in[n] and comp_in[n+1]. Also, "Var" in FIG. 3(a) shows the variation in the timing at which the level of the output signal of the comparator 232 of each column changes. The period from time t10 to time t17 in FIG. 3(a) is the period during which the AD conversion of the noise signal is performed by comparing the noise signal from the pixel 100 with the reference signal Vramp in the AD conversion unit 23. The driving timing of the AD conversion of the noise signal will be described with reference to FIG. 3(a).

At time t10, the control signal comp_res is at a high level, and the switches 233 and 234 are on. This resets the potentials of the first input terminal, the second input terminal, the first output terminal, and the second output terminal of the comparator 232. In addition, the control signal sw is at a low level, and the switch 191 is off.

The input signals comp_in[n] and comp_in[n+1] are signals in which noise generated in the amplifier 21 and analog signal holding unit 22 is superimposed on the noise signal output from the pixel 100. The noise signal clamped in the amplifier 21 contains a component of charge reinjection when the switch 214 transitions from on to off. Charge reinjection is a phenomenon in which the charge under the gate of the transistor constituting the switch 214 moves to each of the inverting input terminal and output terminal of the differential amplifier 212 when the switch 214 transitions from on to off. The charge reinjection component contained in the noise signal differs for each amplifier 21 of each column. Therefore, at time t10, the input signal comp_in[n] and the input signal comp_in[n+1] are at different potentials.

At time t11, the control signal sw becomes high level. This turns on the switch 191, and the analog signal held in the holding capacitance 222 of the nth column and the analog signal held in the holding capacitance 222 of the n+1th column are averaged. Therefore, the averaged signals held in the holding capacitances 222 of the nth column and the n+1th column are input to the AD conversion unit 23 as the input signals comp_in[n] and comp_in[n+1] via the amplifier 223. As a result, after time t11, the input signals comp_in[n] and comp_in[n+1] have the same potential. Also, at time t11, the reference signal Vramp is set to the offset level.

At time t12, the control signal comp_res goes to low level. This turns off the switches 233 and 234. The potential of the second input terminal of the comparator 232 at time t12 is a reset potential based on the reference signal Vramp, which is an offset level. A charge based on the potential of the offset level of the reference signal Vramp at time t12 is clamped in the input capacitance 236. Hereinafter, this operation may be referred to as an offset clamp operation. This completes the offset clamp operation of the input capacitance 236.

In addition, the charge based on the output potential of the comparator 232 at time t12 is clamped in the input capacitance 231. That is, the offset clamp operation of the input capacitance 231 is completed. Since the input signal comp_in[n] and the input signal comp_in[n+1] have the same potential, the same potential is clamped in the input capacitance 231. That is, the potential clamped in the input capacitance 231 of the nth column and the n+1th column by the offset clamp operation is a potential that differs by ΔV compared to the potential of the input signal before time t11. The noise signal held in the input capacitance 231 includes a noise component of the AD conversion unit 23. This noise component includes a component of charge reinjection when the switch 233 transitions from on to off. In addition, the signal held in the input capacitance 236 includes a component of charge reinjection when the switch 234 transitions from on to off.

At time t13, the offset level setting of the reference signal Vramp is released. This causes the potential of the reference signal Vramp to return to the potential at time t10.

At time t14, the control signal sw goes to low level. The switch 191 turns off, and the averaging of the analog signal held in the holding capacitor 222 of the nth column and the analog signal held in the holding capacitor 222 of the n+1th column is canceled. As a result, the input signal comp_in[n] and the input signal comp_in[n+1] have different potentials.

At time t15, the reference signal generating circuit 16 changes the potential of the reference signal Vramp depending on time. Also at time t15, the counter 17 starts counting the clock signal.

Time t16 is the time when the potential of the reference signal Vramp exceeds the offset level. Around time t16, the magnitude relationship between the input signals comp_in[n], comp_in[n+1] and the reference signal Vramp is reversed, and the level of the output signal of the comparator 232 changes. This causes a latch signal to be output from the latch circuit to the digital signal holding unit 24. In response to the change in the latch signal, the digital signal holding unit 24 holds the count signal at that time. The count signal held in the digital signal holding unit 24 is a digital signal that corresponds to the noise signal.

At time t17, the reference signal generation circuit 16 stops the change in the potential of the reference signal Vramp. The potential of the reference signal Vramp then returns to the potential at time t10. Also, at time t17, the counter 17 stops counting the clock signal and resets the count value.

After time t17, the photoelectric conversion signal is AD converted in the same manner as the noise signal, and a digital signal corresponding to the photoelectric conversion signal is held in the digital signal holding unit 24. After that, the horizontal scanning circuit 25 sequentially scans the digital signal holding unit 24 of each column, and outputs the digital signal held in the digital signal holding unit 24 of each column to the digital signal processing circuit 18.

As described above, a digital signal based on the noise signal and a digital signal based on the photoelectric conversion signal are output from the column circuit 20 of each column to the digital signal processing circuit 18. The digital signal based on the photoelectric conversion signal contains a noise signal component. Therefore, the digital signal processing circuit 18 can generate a signal with less noise signal by subtracting the digital signal based on the noise signal from the digital signal based on the photoelectric conversion signal.

Figure 4 is a timing diagram showing a driving method when the switch 191 is not turned on in the photoelectric conversion device of this embodiment. The effect of this embodiment will be explained with mutual reference to Figures 3(a) and 4.

In the driving method of FIG. 3(a), the control signal sw is at a high level and the switch 191 is on during the period from time t11 to time t14. In contrast, in the driving method of FIG. 4, the control signal sw is maintained at a low level during the period from time t21 to time t24, which corresponds to the period from time t11 to time t14. As a result, the difference between FIG. 4 and FIG. 3(a) is that the switch 191 is not turned on. In other words, FIG. 4 shows a case in which the switch 191 in this embodiment is not provided.

As shown in FIG. 4, at time t22, the input signal comp_in[n] and the input signal comp_in[n+1] are at different potentials. Therefore, different potentials are clamped to the input capacitance 231 of the nth column and the input capacitance 231 of the n+1th column. In the example of FIG. 4, the input signal comp_in[n] at time t22 and the input signal comp_in[n] at time t16 are almost the same. In this case, at time t16 when the potential of the reference signal Vramp exceeds the offset level, the level of the output signal of the nth column comparator 232 changes. In addition, the input signal comp_in[n+1] at time t22 and the input signal comp_in[n+1] at time t16 are also almost the same. In this case, at time t16 when the potential of the reference signal Vramp exceeds the offset level, the level of the output signal of the n+1th column comparator 232 also changes. Therefore, as shown in FIG. 4, when the switch 191 is not turned on during the offset clamp operation, the level of the output signal of the comparator 232 in the nth column and the level of the output signal of the comparator 232 in the (n+1)th column change almost simultaneously. Therefore, as shown by "Var" in FIG. 4, there is little variation in the timing at which the level of the output signal of the comparator 232 in each column changes.

If there is little variation in the timing at which the output signal level of the comparator 232 of each column changes, the output signal levels of multiple comparators 232 may change simultaneously within a short period of time. This may cause noise due to factors such as IR drop and current fluctuations. In particular, when there are many columns of pixels 100, many comparators 232 are arranged in the photoelectric conversion device, and the effect of this noise is significant. This noise may propagate to other comparators 232 through the power supply wiring or signal wiring commonly arranged between columns, and may cause deterioration in the quality of the output signal. Furthermore, in circuits subsequent to the comparator 232, this noise may also cause deterioration in the quality of the output signal by causing AD conversion errors and reduced accuracy in the counting operation of the clock signal in the counter 17.

On the other hand, in the driving method shown in FIG. 3(a), switch 191 is on during offset clamp operation at time t12. As a result, the input potential of comparator 232 during offset clamp operation at time t12 and the input potential of comparator 232 during AD conversion at time t16 are different potentials. That is, the potential of input signal comp_in[n] during AD conversion is ΔV higher than during offset clamp. Also, the potential of input signal comp_in[n+1] during AD conversion is ΔV lower than during offset clamp.

In the driving method shown in FIG. 3(a), as shown by "Var" in FIG. 3(a), there is a large variation in the timing at which the level of the output signal of the comparator 232 of each column changes. Therefore, the levels of the output signals of the multiple comparators 232 are unlikely to change simultaneously within a short period of time, and the noise that occurs when the level of the output signal of the comparator 232 of each column changes can be reduced.

As described above, this embodiment provides a photoelectric conversion device that can output a higher quality signal.

In this embodiment, the switch 191 is arranged between the signal line of the nth column and the signal line of the n+1th column, and is turned on during offset clamp operation to average the signals of the two columns. However, for example, a similar switch 191 may be arranged between the signal line of the n+1th column and the signal line of the n+2th column. In this case, the signals of three columns may be averaged. The switch 191 may also be arranged between the signal lines of each column. In this case, it is possible to average some or all of the signals of all the columns of the pixel array 10. In addition, the combination of columns to be averaged or the number of columns to be averaged may be changed each time each row of the pixel array 10 is read out. In this case, the variation in the timing at which the level of the output signal of the comparator 232 changes becomes two-dimensionally irregular, so that the effect on image quality caused by this variation can be made less noticeable.

In addition, in this embodiment, the switch 191 is controlled to be on during offset clamping at time t12. However, if the potential of the input signal comp_in[n] is different between the offset clamping and the AD conversion, the switch 191 may be changed from on to off at a time before time t12.

A modified example in which switch 191 is turned from on to off before time t12 will be described in more detail with reference to the timing diagram in FIG. 3(b). Descriptions of parts common to FIG. 3(a) may be omitted or simplified as appropriate.

At time t11, the control signal sw goes to high level. This turns on the switch 191, and the analog signal held in the holding capacitor 222 of the nth column and the analog signal held in the holding capacitor 222 of the n+1th column are averaged.

At time t31, the control signal sw goes to low level. The switch 191 turns off, and the averaging of the analog signal held in the holding capacitor 222 of the nth column and the analog signal held in the holding capacitor 222 of the n+1th column is canceled. As a result, the input signals comp_in[n] and comp_in[n+1] gradually return to the potential at time t10.

At time t32, the control signal comp_res goes low and the offset clamp operation is completed. Time t32 is the time before the input signals comp_in[n] and comp_in[n+1] return to the potentials at time t10.

At time t33, the offset level setting of the reference signal Vramp is released. This causes the potential of the reference signal Vramp to return to the potential at time t10.

In this way, after switch 191 is turned off and averaging is released, the offset clamp operation is completed before the input signal returns to its original potential, making it possible to set the potential of the input signal comp_in[n] to different potentials between offset clamping and AD conversion. Note that "ΔV" shown in FIG. 3(b) indicates the difference in potential of the input signal comp_in[n] between offset clamping and AD conversion. In the modified example of FIG. 3(b), for the same reason as described in the explanation of FIG. 3(a), noise that occurs when the level of the output signal of comparator 232 of each column changes can also be reduced.

The photoelectric conversion device of this embodiment may also be configured to change the gain by changing the setting of the amplifier 21 or the amount of change (slope) per unit time of the potential of the reference signal Vramp. In this case, the operation of the switch 191 during offset clamping may be made different depending on the gain. The variation in the timing at which the level of the output signal of the comparator 232 changes may change depending on the gain. Alternatively, the level of noise caused by the change in the level of the output signal may change depending on the gain of the photoelectric conversion device. In this way, since the optimal control method may change depending on the gain, it may be desirable to change the operation of the switch 191.

Furthermore, the variation in the timing at which the level of the output signal of the comparator 232 changes may also vary depending on the temperature of the photoelectric conversion device. Therefore, the temperature of the photoelectric conversion device may be measured by a temperature sensor, and the operation of the switch 191 during offset clamping may be varied depending on the temperature.

[Second embodiment]
A photoelectric conversion device according to this embodiment will be described. The same components as those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

FIG. 5 is a circuit diagram showing the configuration of the pixel 100 and column circuit 20 according to this embodiment. In the photoelectric conversion device of this embodiment, a switch 192 is provided instead of the switch 191 in FIG. 2.

The first terminal of the switch 192 is connected to a node between the analog signal holding unit 22a of the nth column and the AD conversion unit 23a, and the second terminal of the switch 192 is connected to a node between the analog signal holding unit 22b of the n+1th column and the AD conversion unit 23b. In other words, the first terminal of the switch 192 is connected to a node between the amplifier 223 of the nth column and the input capacitance 231, and the second terminal of the switch 192 is connected to a node between the amplifier 223 of the n+1th column and the input capacitance 231. The switch 192 is controlled by a control signal sw from the timing generator 15 and is controlled to be on or off. When the control signal sw is at a high level, the switch 192 is turned on, and when the control signal sw is at a low level, the switch 192 is turned off. When the switch 192 is on, the analog signal input to the input capacitance 231 of the nth column and the analog signal input to the input capacitance 231 of the n+1th column are averaged. The other circuit configurations are the same as those in FIG. 2, so their explanations are omitted.

The driving method of the photoelectric conversion device of this embodiment is the same as that shown in FIG. 3(a). That is, the switch 192 is on during the offset clamp operation at time t12. As a result, the input potential of the comparator 232 during the offset clamp operation at time t12 and the input potential of the comparator 232 during the AD conversion at time t16 are different from each other. That is, the potential during the AD conversion of the input signal comp_in[n] is ΔV larger than that during the offset clamp. Also, the potential during the AD conversion of the input signal comp_in[n+1] is ΔV smaller than that during the offset clamp. Therefore, as in the first embodiment, the levels of the output signals of the multiple comparators 232 are less likely to change simultaneously within a short period of time, and noise generated when the levels of the output signals of the comparators 232 of each column change can be reduced.

As described above, this embodiment provides a photoelectric conversion device that can output a higher quality signal.

[Third embodiment]
A photoelectric conversion device according to this embodiment will be described. The same components as those in the first embodiment are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

Figure 6 is a circuit diagram showing the configuration of the pixel 100 and column circuit 20 according to this embodiment. In the photoelectric conversion device of this embodiment, a switch 193 is provided instead of the switch 191 in Figure 2.

The first terminal of the switch 193 is connected to a node between the amplifier 235 of the nth column and the input capacitance 236, and the second terminal of the switch 193 is connected to a node between the amplifier 235 of the n+1th column and the input capacitance 236. The switch 193 is controlled by a control signal sw from the timing generator 15 and is controlled to be on or off. When the control signal sw is at a high level, the switch 193 is turned on, and when the control signal sw is at a low level, the switch 193 is turned off. When the switch 193 is on, the analog signal input to the input capacitance 236 of the nth column and the analog signal input to the input capacitance 236 of the n+1th column are averaged. The other circuit configurations are the same as in FIG. 2, so their explanations are omitted. In addition, the driving method of the photoelectric conversion device is also the same as in FIG. 3(a), so their explanations are omitted.

The effect of this embodiment will be described. The reference signal Vramp is input to the amplifier 235 via a reference signal line common to each column. However, due to performance variations, wiring resistance variations, etc. of the amplifiers 235 of each column, the output node of the amplifier 235 of the nth column and the output node of the amplifier 235 of the n+1th column may have different potentials. During the offset clamp operation at time t12 in FIG. 3(a), the input capacitance 236 of the nth column and the input capacitance 236 of the n+1th column are shorted via the switch 193, so that the same potential is clamped to the input capacitance 236 of the nth column and the input capacitance 236 of the n+1th column. In contrast, during the period after time t13, the switch 193 is off, and the output node of the amplifier 235 of the nth column and the output node of the amplifier 235 of the n+1th column have different potentials due to variations. As a result, the potentials of the reference signals input to the comparators 232 of the nth column and the n+1th column are different from each other during the AD conversion at time t16. Therefore, the levels of the output signals of multiple comparators 232 are less likely to change simultaneously, and noise that occurs when the levels of the output signals of the comparators 232 in each column change can be reduced.

As described above, this embodiment provides a photoelectric conversion device that can output a higher quality signal.

In the above description, it is assumed that the amount of change per unit time of the potential of the reference signal of the nth column and the n+1th column is the same during the period in which the AD conversion is performed, but this is not limited to the above. The amount of change per unit time of the potential of the reference signal of the nth column and the amount of change per unit time of the potential of the reference signal of the nth column may be different from each other.

[Fourth embodiment]
The photoelectric conversion device according to this embodiment will be described. The same components as those in the first to third embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

Figure 7 is a circuit diagram showing the configuration of a pixel 100 and a column circuit 20 according to this embodiment. The photoelectric conversion device of this embodiment differs from Figure 2 in that the amplifier 21 and analog signal holding unit 22 are not provided. Also, in Figure 7, a switch 194 is provided instead of the switch 191 in Figure 2.

The switch 194 is disposed between the output line 12a of the nth column and the output line 12b of the n+1th column. That is, the first terminal of the switch 194 is connected to the output line 12a of the nth column, and the second terminal of the switch 194 is connected to the output line 12b of the n+1th column. The switch 194 is controlled by a control signal sw from the timing generator 15 and is controlled to be on or off. When the control signal sw is at a high level, the switch 194 is turned on, and when the control signal sw is at a low level, the switch 194 is turned off. When the switch 194 is on, the analog signal input to the input capacitance 231 of the nth column and the analog signal input to the input capacitance 231 of the n+1th column are averaged. The other circuit configurations are the same as those in FIG. 2 except that the amplifier 21 and the analog signal holding unit 22 are not disposed, and therefore will not be described.

The driving method of the photoelectric conversion device of this embodiment is the same as that shown in FIG. 3(a). That is, the switch 194 is on during the offset clamp operation at time t12. As a result, the input potential of the comparator 232 during the offset clamp operation at time t12 and the input potential of the comparator 232 during the AD conversion at time t16 are different from each other. The potential of the input signal comp_in[n] during the AD conversion is ΔV larger than that during the offset clamp. Also, the potential of the input signal comp_in[n+1] during the AD conversion is ΔV smaller than that during the offset clamp. Therefore, as in the first embodiment, the levels of the output signals of the multiple comparators 232 are less likely to change simultaneously within a short period of time, and noise generated when the levels of the output signals of the comparators 232 of each column change can be reduced.

Even when the switch 194 is disposed between the two output lines 12 as in the configuration of FIG. 7, the driving method shown in FIG. 3(b) may be applied. That is, after the switch 194 is turned off and the averaging is canceled, a driving method may be applied in which the offset clamp operation is completed in the middle of returning from the potential at the time of averaging to the original potential.

However, as shown in FIG. 3A, there may be cases where it is desirable to complete the offset clamp operation during averaging. An example of such a case will be described. Generally, the output line 12 has a large parasitic capacitance and a large load resistance. For example, in a two-dimensionally arranged pixel array 10, the resistance value between the output node of the pixel 100 and the input node of the AD conversion unit 23 differs depending on the row of the pixel 100. Therefore, the potential at the time of AD conversion and the potential ΔV at the time of completion of the offset clamp may vary depending on the row of the pixel 100 being read out. In addition, the potential ΔV may vary depending on the temperature of the photoelectric conversion device and the manufacturing variation of the parasitic capacitance of the output line 12. For the above reasons, when a switch 194 is arranged between two output lines 12, it may be desirable to complete the offset clamp operation during averaging.

In addition, FIG. 7 shows a configuration in which a switch 194 is arranged between two output lines 12, but this switch may be connected to the output node of the amplifier 235 like the switch 193 in FIG. 6 of the third embodiment. FIG. 8 is a circuit diagram showing a modified example of the pixel 100 and column circuit 20 according to this embodiment.

As shown in FIG. 8, in this modification, a switch 196 is provided instead of the switch 194 in FIG. 7. A first terminal of the switch 196 is connected to a node between the amplifier 235 of the nth column and the input capacitance 236, and a second terminal of the switch 196 is connected to a node between the amplifier 235 of the (n+1)th column and the input capacitance 236. The operation and effect of the switch 196 are similar to those of the switch 193 in the third embodiment, and therefore a description thereof will be omitted. For the same reason, in this modification, noise that occurs when the level of the output signal of the comparator 232 in each column changes can be reduced.

Furthermore, FIG. 7 and FIG. 8 may be combined. In other words, a configuration may be provided in which both switch 194 in FIG. 7 and switch 196 in FIG. 8 are provided. Note that switch 194 and switch 196 may be controlled in synchronization with each other, or may be controlled by different control signals.

The photoelectric conversion device of this embodiment may be configured to change the gain by changing the setting of the amplifier 21 or the amount of change (slope) per unit time of the potential of the reference signal Vramp. In this case, for example, the time t32 at which the offset clamp operation is completed may be made to differ depending on the gain between time t31 and time t33. The variation in the timing at which the level of the output signal of the comparator 232 changes may change depending on the gain. Alternatively, the degree of noise caused by the change in the level of the output signal may change depending on the gain of the photoelectric conversion device. In this way, since the optimal control method may change depending on the gain, it may be desirable to change the operation of the switches 194 and 196.

[Fifth embodiment]
The photoelectric conversion device according to this embodiment will be described. The same components as those in the first to fourth embodiments are denoted by the same reference numerals, and the description of these components may be omitted or simplified.

FIG. 9 is a circuit diagram showing the configuration of the pixel 100 and column circuit 20 according to this embodiment. In addition to the switch 192 in FIG. 5, the photoelectric conversion device of this embodiment is provided with a switch 195 (output line connection switch).

The switch 195 is disposed between the nth column output line 12a and the n+1th column output line 12b. That is, one terminal (third terminal) of the switch 195 is connected to the nth column output line 12a, and the other terminal (fourth terminal) of the switch 195 is connected to the nth column output line 12b. The switch 195 is controlled by a control signal vl_sw from the timing generator 15 and is controlled to be on or off. When the control signal vl_sw is at a high level, the switch 195 is turned on, and when the control signal vl_sw is at a low level, the switch 195 is turned off. When the switch 195 is on, the analog signal of the nth column output line 12a and the analog signal of the n+1th column output line 12b are averaged.

The switch 214 is controlled by a control signal camp_res from the timing generator 15 and is controlled to be on or off. When the switch 214 transitions from on to off, the amplifier 21 is released from reset and the potential input to the input capacitance 211 at that time is clamped. The rest of the circuit configuration is the same as in FIG. 5, so a description thereof will be omitted.

Figure 10 is a timing diagram showing a method of driving a photoelectric conversion device according to this embodiment. In addition to the same signals as in Figure 3(a), Figure 10 also shows the levels of the control signals camp_res and vl_sw, the potential vline[n] of the output line 12a of the nth column, and the potential vline[n+1] of the output line 12b of the n+1th column. The operation from time t11 to time t17 in Figure 10 is the same as the operation shown in Figure 3(a), so a description thereof will be omitted.

At time t40, the control signal vl_sw goes to high level. This turns on the switch 195, and the analog signal on the output line 12a of the nth column and the analog signal on the output line 12b of the (n+1)th column are averaged. Also, at time t40, the control signal camp_res goes to high level. This turns on the switch 214, and the amplifier unit 21 goes to a reset state.

At time t41, the control signal vl_sw goes to low level. This turns off the switch 195, and the averaging of the analog signal on the nth column output line 12a and the analog signal on the (n+1)th column output line 12b is canceled.

At time t42, the control signal camp_res goes to low level, and the switch 214 turns off. When the switch 214 transitions from on to off, the amplifier unit 21 is released from the reset state, and the potential input to the input capacitance 211 at that time is clamped. Time t42 is the time before the averaging of the analog signal of the nth column output line 12a and the analog signal of the n+1th column output line 12b is released at time t41, and the analog signals of the output lines of each column return to their original potential. In this operation, the potential input to the input capacitance 211 at time t42 is clamped.

After time t42, the potentials of the output lines 12a and 12b return to the potentials before averaging. Therefore, a difference of ΔV' occurs between the potential clamped to the input capacitance 211 and the potentials of the output lines 12a and 12b during AD conversion. Therefore, as in the first embodiment, the levels of the output signals of the multiple comparators 232 are less likely to be inverted simultaneously within a short period of time, and noise generated when the level of the output signal of the comparator 232 in each column changes can be reduced. The potential clamped to the input capacitance 211 is determined based on the characteristic variation of the pixel 100. Therefore, the variation in the timing at which the level of the output signal changes is irregular with respect to the coordinates of the pixel 100 in the pixel array 10. Therefore, the effect on image quality caused by this variation can be made less noticeable.

The photoelectric conversion device of this embodiment may be configured to change the gain by changing the setting of the amplifier 21 or the amount of change (slope) per unit time of the potential of the reference signal Vramp. In this case, for example, the time from time t41 to time t42 may be made different depending on the gain. Also, the variation in the timing at which the level of the output signal of the comparator 232 changes may change depending on the gain. Alternatively, the level of noise caused by the change in the level of the output signal may change depending on the gain of the photoelectric conversion device. In this way, since the optimal control method may change depending on the gain, it may be desirable to change the operation of the switch 195.

In addition, in the configuration of FIG. 9, the potential of the reference signal Vramp when the offset clamp operation is completed may differ depending on the column, and this configuration can increase the variability in the timing at which the level of the output signal of the comparator 232 changes. This modified example will be described with reference to the circuit diagrams of FIG. 9 and FIG. 11 and the timing diagram of FIG. 12.

As described above, FIG. 9 shows two circuits, the nth column and the n+1th column. FIG. 11 shows two circuits, the n+2th column and the n+3th column. Thus, the circuit diagrams in FIG. 9 and FIG. 11 show the configuration of the pixels 100 and the column circuits 20 for four consecutive columns. The n+2th column and the n+3th column are sometimes simply called the third column and the fourth column. When it is necessary to distinguish between the elements of the two columns, the symbols of some elements in FIG. 11 may be given the subscript "c" indicating that they are elements of the n+2th column or the subscript "d" indicating that they are elements of the n+3th column. In addition, the output line 12c through which a signal is output from the pixel 100c in the n+2th column may be called the third output line, and the output line 12d through which a signal is output from the pixel 100d in the n+3th column may be called the fourth output line. The elements in the n+2th column and the n+3th column have roughly the same configuration as the elements in the nth and n+1st columns, except for the potential of the reference signal, so a description of the circuit configuration may be omitted.

As shown in FIG. 9, a reference signal Vramp is input from the reference signal generating circuit 16 to the input terminals of the amplifiers 235 in the nth and n+1th columns. Also, as shown in FIG. 11, a reference signal Vramp' different from the reference signal Vramp is input from the reference signal generating circuit 16 to the input terminals of the amplifiers 235 in the n+2th and n+3th columns. The other elements shown in FIG. 11 are similar to the elements shown in FIG. 9, so a description thereof will be omitted.

Figure 12 is a timing diagram showing a modified example of the driving method of the photoelectric conversion device according to the present embodiment. In addition to the same signals as in Figure 10, Figure 12 shows the potential of the reference signal Vramp' and the potentials of the input signals comp_in[n+2] and comp_in[n+3]. Also, in Figure 12, the potentials vline[n] and vline[n+1] are omitted. Note that in the period from time t40 to t42, the reference signal Vramp and the reference signal Vramp' are at the same potential. Note that the operation in the periods other than times t51, t52, t53, and t54 is generally similar to that in Figure 10, and therefore the description may be omitted or simplified.

At time t51, the reference signal Vramp of the nth and n+1th columns is set to a first offset level. The reference signal Vramp' of the n+2th and n+3th columns is set to a second offset level. The second offset level of the reference signal Vramp' is set to a potential higher than the first offset level of the reference signal Vramp.

At time t52, the control signal comp_res goes to low level. This turns off the switches 233 and 234. The potentials of the second input terminals of the comparators 232 in the nth and n+1th columns at time t52 are reset potentials based on the reference signal Vramp, which is the first offset level. The potentials of the second input terminals of the comparators 232 in the n+2th and n+3rd columns at time t52 are reset potentials based on the reference signal Vramp', which is the second offset level.

At time t53, the settings of the reference signal Vramp and the reference signal Vramp' to the first and second offset levels are released. This causes the potentials of the reference signal Vramp and the reference signal Vramp' to return to the potentials prior to time t51.

Time t16 is the time when the potential of the reference signal Vramp exceeds the first offset level. Around time t16, the magnitude relationship between the input signals comp_in[n], comp_in[n+1] and the reference signal Vramp is reversed, and the levels of the output signals of the comparators 232 in the nth and n+1th columns change.

Time t54 is the time when the potential of the reference signal Vramp' exceeds the second offset level. Around time t54, the magnitude relationship between the input signals comp_in[n+2], comp_in[n+3] and the reference signal Vramp' is reversed, and the levels of the output signals of the comparators 232 in the n+2th and n+3th columns change.

As described above, the timing at which the level of the output signal of the comparator 232 in the nth and n+1th columns changes is different from the timing at which the level of the output signal of the comparator 232 in the nth and n+1th columns changes. Therefore, according to this modified example, as shown by "Var" in FIG. 12, it is possible to increase the variance in the timing at which the level of the output signal of the comparator 232 in each column changes.

Sixth Embodiment
The photoelectric conversion device in the above-described embodiment can be applied to various devices, such as digital still cameras, digital camcorders, camera heads, copiers, fax machines, mobile phones, vehicle-mounted cameras, observation satellites, surveillance cameras, etc. Fig. 13 shows a block diagram of a digital still camera as an example of the device.

The device 70 shown in FIG. 13 includes a barrier 706, a lens 702, an aperture 704, and an imaging device 700 (an example of a photoelectric conversion device). The device 70 further includes a signal processing unit (processing device) 708, a timing generating unit 720, an overall control/calculation unit 718 (control device), a memory unit 710 (storage device), a recording medium control I/F unit 716, a recording medium 714, and an external I/F unit 712. At least one of the barrier 706, the lens 702, and the aperture 704 is an optical device corresponding to the device. The barrier 706 protects the lens 702, and the lens 702 forms an optical image of a subject on the imaging device 700. The aperture 704 makes the amount of light passing through the lens 702 variable. The imaging device 700 is configured as in the above-mentioned embodiment, and converts the optical image formed by the lens 702 into image data (image signal). The signal processing unit 708 performs various corrections, data compression, etc. on the imaging data output from the imaging device 700. The timing generating unit 720 outputs various timing signals to the imaging device 700 and the signal processing unit 708. The overall control/calculation unit 718 controls the entire digital still camera, and the memory unit 710 temporarily stores image data. The recording medium control I/F unit 716 is an interface for recording or reading image data to the recording medium 714, which is a removable recording medium such as a semiconductor memory for recording or reading imaging data. The external I/F unit 712 is an interface for communicating with an external computer or the like. Timing signals and the like may be input from outside the device. The device 70 may further include a display device (monitor, electronic viewfinder, etc.) that displays information obtained by the photoelectric conversion device. The device includes at least a photoelectric conversion device. The device 70 further includes at least one of an optical device, a control device, a processing device, a display device, a storage device, and a mechanical device that operates based on information obtained by the photoelectric conversion device. The mechanical device is a movable part (for example, a robot arm) that operates in response to a signal from the photoelectric conversion device.

Each pixel may include multiple photoelectric conversion units (a first photoelectric conversion unit and a second photoelectric conversion unit). The signal processing unit 708 may be configured to process a pixel signal based on the charge generated in the first photoelectric conversion unit and a pixel signal based on the charge generated in the second photoelectric conversion unit, and to obtain distance information from the imaging device 700 to the subject.

[Seventh embodiment]
14(a) and 14(b) are block diagrams of devices related to the vehicle-mounted camera in this embodiment. The device 80 has the imaging device 800 (an example of a photoelectric conversion device) of the above-mentioned embodiment and a signal processing device (processing device) that processes a signal from the imaging device 800. The device 80 has an image processing unit 801 that performs image processing on a plurality of image data acquired by the imaging device 800, and a parallax calculation unit 802 that calculates parallax (phase difference of parallax images) from a plurality of image data acquired by the device 80. The device 80 also has a distance measurement unit 803 that calculates a distance to an object based on the calculated parallax, and a collision determination unit 804 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax calculation unit 802 and the distance measurement unit 803 are examples of distance information acquisition means that acquire distance information to the object. That is, the distance information is information related to the parallax, the defocus amount, the distance to the object, and the like. The collision determination unit 804 may use any of these distance information to determine the possibility of a collision. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination of these.

The device 80 is connected to a vehicle information acquisition device 810 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The device 80 is also connected to a control ECU 820, which is a control device that outputs a control signal to generate a braking force for the vehicle based on the judgment result of the collision judgment unit 804. The device 80 is also connected to an alarm device 830 that issues an alarm to the driver based on the judgment result of the collision judgment unit 804. For example, if the judgment result of the collision judgment unit 804 indicates that there is a high possibility of a collision, the control ECU 820 performs vehicle control to avoid a collision and reduce damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 830 warns the user by sounding an alarm, displaying alarm information on the screen of a car navigation system, etc., or vibrating the seat belt or steering wheel. The device 80 functions as a control means that controls the operation of controlling the vehicle as described above.

In this embodiment, the surroundings of the vehicle, for example the front or rear, are captured by the device 80. FIG. 14(b) shows the device when capturing an image of the area in front of the vehicle (imaging range 850). A vehicle information acquisition device 810, which serves as an imaging control means, sends an instruction to the device 80 or the imaging device 800 to perform an imaging operation. This configuration can further improve the accuracy of distance measurement.

Although the above describes an example of control to avoid collision with other vehicles, the invention can also be applied to control of automatic driving by following other vehicles, control of automatic driving to avoid going out of lanes, etc. Furthermore, the device is not limited to vehicles such as automobiles, but can be applied to moving bodies (moving devices) such as ships, aircraft, artificial satellites, industrial robots, and consumer robots. In addition, the invention can be applied to a wide range of devices that use object recognition or biometric recognition, such as intelligent transport systems (ITS) and surveillance systems, and is not limited to moving bodies.

[Modified embodiment]
The present invention is not limited to the above-mentioned embodiment, and various modifications are possible. For example, an example in which a part of the configuration of any of the embodiments is added to another embodiment, or an example in which a part of the configuration of another embodiment is replaced with another embodiment is also an embodiment of the present invention. In this specification, an example in which one column circuit is provided for one column of pixels has been described, but multiple output lines may be provided for one column of pixels. In this case, pixels in some rows are connected to some of the multiple output lines, and pixels in other rows are connected to another part of the output lines. A column circuit may be provided for each of the multiple output lines. Also, a form in which one column circuit is provided for multiple columns of pixels may be used.

The disclosure of this specification includes the complement of the concepts described in this specification. In other words, if this specification states, for example, that "A is B" (A = B), this specification is deemed to disclose or suggest that "A is not B" even if the statement that "A is not B" (A ≠ B) is omitted. This is because when it states that "A is B", it is assumed that the case where "A is not B" is taken into consideration.

The disclosure of this specification includes the following configurations.
(Configuration 1)
A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
an amplifier section arranged corresponding to each of the plurality of output lines and amplifying a signal output to the corresponding output line;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the amplification unit, and the second input terminal receiving a reference signal;
a switch having a first terminal and a second terminal;
having
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a node between an amplifier section corresponding to the first output line and a comparator section corresponding to the first output line;
the second terminal is connected to a node between an amplifier section corresponding to the second output line and a comparator section corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
The photoelectric conversion device, wherein the switch is turned on during a period before the offset clamp operation is completed.
(Configuration 2)
a storage capacitor arranged corresponding to each of the plurality of output lines and configured to store a signal output from the amplifier unit;
the first terminal is connected to a storage capacitor of the first output line;
The photoelectric conversion device according to configuration 1, wherein the second terminal is connected to a holding capacitance of the second output line.
(Configuration 3)
a first input capacitance arranged corresponding to each of the plurality of output lines;
a signal corresponding to an output of the amplifier unit is input to the first input terminal via the first input capacitance;
the first terminal is connected to a first input capacitance of the first output line;
The photoelectric conversion device according to configuration 1, wherein the second terminal is connected to a first input capacitance of the second output line.
(Configuration 4)
a storage capacitor arranged corresponding to each of the plurality of output lines and configured to store a signal output from the amplifier;
a first buffer disposed between the storage capacitor and the first input capacitor in correspondence with each of the plurality of output lines;
and
the first terminal is connected to a node between a first buffer corresponding to the first output line and a first input capacitance corresponding to the first output line;
The photoelectric conversion device according to configuration 3, wherein the second terminal is connected to a node between a first buffer corresponding to the second output line and a first input capacitance corresponding to the second output line.
(Configuration 5)
A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
an amplifier section arranged corresponding to each of the plurality of output lines and amplifying a signal output to the corresponding output line;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the amplification unit, and the second input terminal receiving a reference signal;
a second input capacitance arranged corresponding to each of the plurality of output lines;
a switch having a first terminal and a second terminal;
having
the reference signal is input to the second input terminal via the second input capacitance;
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a second input capacitance corresponding to the first output line;
the second terminal is connected to a second input capacitance corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
The photoelectric conversion device, wherein the switch is turned on during a period before the offset clamp operation is completed.
(Configuration 6)
a second buffer disposed between a signal line to which the reference signal is supplied and the second input capacitance, the second buffer corresponding to each of the plurality of output lines;
the first terminal is connected to a node between a second buffer corresponding to the first output line and a second input capacitance corresponding to the first output line;
The photoelectric conversion device according to configuration 5, wherein the second terminal is connected to a node between a second buffer corresponding to the second output line and a second input capacitance corresponding to the second output line.
(Configuration 7)
7. The photoelectric conversion device according to any one of the preceding claims, wherein an operation of the switch differs depending on a gain setting of the amplifier unit.
(Configuration 8)
8. The photoelectric conversion device according to any one of configurations 1 to 7, wherein an operation of the switch differs depending on a gain setting of the comparison unit.
(Configuration 9)
9. The photoelectric conversion device according to any one of configurations 1 to 8, wherein an operation of the switch differs depending on an amount of change per unit time of a potential of the reference signal.
(Configuration 10)
10. The photoelectric conversion device according to any one of the preceding claims, wherein the operation of the switch differs depending on a temperature of the photoelectric conversion device.
(Configuration 11)
11. The photoelectric conversion device according to any one of configurations 1 to 10, wherein the switch is turned off after the offset clamp operation is completed.
(Configuration 12)
11. The photoelectric conversion device according to any one of configurations 1 to 10, wherein the switch is turned on and then turned off, after which the offset clamp operation is completed.
(Configuration 13)
13. The photoelectric conversion device according to configuration 12, wherein after the switch is turned off, the potential of the reference signal starts to change depending on time.
(Configuration 14)
an output line connection switch having a third terminal and a fourth terminal;
the third terminal is connected to a node between a pixel corresponding to the first output line and an amplifier corresponding to the first output line;
The photoelectric conversion device according to any one of configurations 1 to 13, wherein the fourth terminal is connected to a node between a pixel corresponding to the second output line and an amplifier unit corresponding to the second output line.
(Configuration 15)
15. The photoelectric conversion device according to configuration 14, wherein the output line connection switch is turned on during a period before the offset clamp operation is completed.
(Configuration 16)
the plurality of output lines further includes a third output line;
The photoelectric conversion device described in any one of configurations 1 to 15, characterized in that at the time when the offset clamp operation is completed, the potential of the reference signal input to the comparison unit corresponding to the first output line and the potential of the reference signal input to the comparison unit corresponding to the third output line are different from each other.
(Configuration 17)
A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the output line, and the second input terminal receiving a reference signal;
a switch having a first terminal and a second terminal;
a first input capacitance arranged corresponding to each of the plurality of output lines;
having
a signal corresponding to an output of the output line is input to the first input terminal via the first input capacitance;
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a first input capacitance corresponding to the first output line;
the second terminal is connected to a first input capacitance corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
During a period before the offset clamp operation is completed, the switch is turned on,
the switch is turned off after the offset clamp operation is completed.
(Configuration 18)
A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the output line, and the second input terminal receiving a reference signal;
a second input capacitance arranged corresponding to each of the plurality of output lines;
a switch having a first terminal and a second terminal;
having
the reference signal is input to the second input terminal via the second input capacitance;
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a second input capacitance corresponding to the first output line;
the second terminal is connected to a second input capacitance corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
During a period before the offset clamp operation is completed, the switch is turned on,
the switch is turned off after the offset clamp operation is completed.
(Configuration 19)
The photoelectric conversion device according to any one of structures 1 to 18,
an optical device corresponding to the photoelectric conversion device;
A control device for controlling the photoelectric conversion device;
a processing device that processes a signal output from the photoelectric conversion device;
a display device that displays information obtained by the photoelectric conversion device;
An apparatus comprising at least one of a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on the information obtained by the photoelectric conversion device.
(Configuration 20)
20. The device according to configuration 19, wherein the processing device processes the image signals generated by the plurality of photoelectric conversion units, respectively, and obtains distance information from the photoelectric conversion units to a subject.

The present invention can also be realized by supplying a program that realizes one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that realizes one or more of the functions.

The above-mentioned embodiments are merely examples of the implementation of the present invention, and the technical scope of the present invention should not be interpreted in a limiting manner. In other words, the present invention can be implemented in various forms without departing from its technical concept or main features.

100, 100a, 100b Pixel 12 Output line 21, 21a, 21b Amplification unit 23, 23a, 23b AD conversion unit 191 Switch

Claims (24)

A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
an amplifier section arranged corresponding to each of the plurality of output lines and amplifying a signal output to the corresponding output line;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the amplification unit, and the second input terminal receiving a reference signal;
a switch having a first terminal and a second terminal;
having
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a node between an amplifier section corresponding to the first output line and a comparator section corresponding to the first output line;
the second terminal is connected to a node between an amplifier section corresponding to the second output line and a comparator section corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
the comparison unit is capable of performing a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal,
During a period before the offset clamp operation is completed, the switch is turned on,
The switch is turned off during a period after the offset clamp operation is completed and before the first comparison operation after the offset clamp operation is completed starts.
A photoelectric conversion device comprising: a storage capacitor arranged corresponding to each of the plurality of output lines and configured to store a signal output from the amplifier unit;
the first terminal is connected to a storage capacitor of the first output line;
The photoelectric conversion device according to claim 1 , wherein the second terminal is connected to a storage capacitor of the second output line. a first input capacitance arranged corresponding to each of the plurality of output lines;
a signal corresponding to an output of the amplifier unit is input to the first input terminal via the first input capacitance;
the first terminal is connected to a first input capacitance of the first output line;
The photoelectric conversion device according to claim 1 , wherein the second terminal is connected to a first input capacitance of the second output line. a storage capacitor arranged corresponding to each of the plurality of output lines and configured to store a signal output from the amplifier;
a first buffer disposed between the storage capacitor and the first input capacitor in correspondence with each of the plurality of output lines;
and
the first terminal is connected to a node between a first buffer corresponding to the first output line and a first input capacitance corresponding to the first output line;
The photoelectric conversion device according to claim 3 , wherein the second terminal is connected to a node between a first buffer corresponding to the second output line and a first input capacitance corresponding to the second output line. The signal includes a noise signal and a photoelectric conversion signal, and the comparison operation uses the noise signal and the photoelectric conversion signal.
2. The photoelectric conversion device according to claim 1 . The pixel includes a transfer transistor, and when the transfer transistor is turned on, the pixel outputs the photoelectric conversion signal, and the switch is turned off during a period before the transfer transistor is turned on.
6. The photoelectric conversion device according to claim 5 . A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
an amplifier section arranged corresponding to each of the plurality of output lines and amplifying a signal output to the corresponding output line;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the amplification unit, and the second input terminal receiving a reference signal;
a second input capacitance arranged corresponding to each of the plurality of output lines;
a switch having a first terminal and a second terminal;
having
the reference signal is input to the second input terminal via the second input capacitance;
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a second input capacitance corresponding to the first output line;
the second terminal is connected to a second input capacitance corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
The photoelectric conversion device, wherein the switch is turned on during a period before the offset clamp operation is completed. a second buffer disposed between a signal line to which the reference signal is supplied and the second input capacitance, the second buffer corresponding to each of the plurality of output lines;
the first terminal is connected to a node between a second buffer corresponding to the first output line and a second input capacitance corresponding to the first output line;
The photoelectric conversion device according to claim 7 , wherein the second terminal is connected to a node between a second buffer corresponding to the second output line and a second input capacitance corresponding to the second output line. the comparison unit is capable of performing a comparison operation between the signal corresponding to the output of the amplification unit and the reference signal,
The switch is turned off during a period after the offset clamp operation is completed and before the first comparison operation after the offset clamp operation is completed starts.
8. The photoelectric conversion device according to claim 7 . The photoelectric conversion device according to claim 1 , wherein the operation of the switch differs depending on a gain setting of the amplifier section. The photoelectric conversion device according to claim 1 , wherein the operation of the switch differs depending on a gain setting of the comparator. 2 . The photoelectric conversion device according to claim 1 , wherein the operation of the switch differs depending on a change amount per unit time of the potential of the reference signal. The photoelectric conversion device according to claim 1 , wherein the operation of the switch differs depending on the temperature of the photoelectric conversion device. 2. The photoelectric conversion device according to claim 1 , wherein after the switch is turned off, the potential of the reference signal starts to change depending on time. an output line connection switch having a third terminal and a fourth terminal;
the third terminal is connected to a node between a pixel corresponding to the first output line and an amplifier corresponding to the first output line;
The photoelectric conversion device according to claim 1 , wherein the fourth terminal is connected to a node between a pixel corresponding to the second output line and an amplifier section corresponding to the second output line. 16. The photoelectric conversion device according to claim 15 , wherein the output line connection switch is turned on during a period before the offset clamp operation is completed. the plurality of output lines further includes a third output line;
2. The photoelectric conversion device according to claim 1, wherein at the time when the offset clamp operation is completed, a potential of a reference signal input to a comparison unit corresponding to the first output line and a potential of a reference signal input to a comparison unit corresponding to the third output line are different from each other. A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the output line, and the second input terminal receiving a reference signal;
a switch having a first terminal and a second terminal;
a first input capacitance arranged corresponding to each of the plurality of output lines;
having
a signal corresponding to an output of the output line is input to the first input terminal via the first input capacitance;
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a first input capacitance corresponding to the first output line;
the second terminal is connected to a first input capacitance corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
the comparison unit is capable of performing a comparison operation between the signal corresponding to the output of the output line and the reference signal,
During a period before the offset clamp operation is completed, the switch is turned on,
the switch is turned off during a period after the offset clamp operation is completed and before a first comparison operation after the offset clamp operation is completed starts . The signal includes a noise signal and a photoelectric conversion signal, and the comparison operation uses the noise signal and the photoelectric conversion signal.
20. The photoelectric conversion device according to claim 18 , The pixel includes a transfer transistor, and when the transfer transistor is turned on, the pixel outputs the photoelectric conversion signal, and the switch is turned off during a period before the transfer transistor is turned on.
20. The photoelectric conversion device according to claim 19 . A plurality of pixels;
a plurality of output lines to which signals are output from corresponding pixels;
a comparison unit arranged corresponding to each of the plurality of output lines, the comparison unit having a first input terminal and a second input terminal, the first input terminal receiving a signal corresponding to an output of the output line, and the second input terminal receiving a reference signal;
a second input capacitance arranged corresponding to each of the plurality of output lines;
a switch having a first terminal and a second terminal;
having
the reference signal is input to the second input terminal via the second input capacitance;
the plurality of output lines includes a first output line and a second output line;
the first terminal is connected to a second input capacitance corresponding to the first output line;
the second terminal is connected to a second input capacitance corresponding to the second output line;
the comparison unit is capable of performing an offset clamp operation for setting an offset based on potentials input to the first input terminal and the second input terminal,
During a period before the offset clamp operation is completed, the switch is turned on,
the switch is turned off after the offset clamp operation is completed. The comparator is capable of performing a comparison operation between the signal corresponding to the output of the output line and the reference signal, and the switch is turned off during a period before the first comparison operation starts after the offset clamp operation is completed.
22. The photoelectric conversion device according to claim 21 . The photoelectric conversion device according to any one of claims 1 to 22 ,
an optical device corresponding to the photoelectric conversion device;
A control device for controlling the photoelectric conversion device;
a processing device that processes a signal output from the photoelectric conversion device;
a display device that displays information obtained by the photoelectric conversion device;
An apparatus comprising at least one of a memory device that stores information obtained by the photoelectric conversion device, and a mechanical device that operates based on the information obtained by the photoelectric conversion device. 24. The device according to claim 23 , wherein the processing device processes image signals generated by a plurality of photoelectric conversion units, respectively, and obtains distance information from the photoelectric conversion units to a subject.

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