JP2019087209A - Image processing apparatus and image processing method - Google Patents

Abstract

To provide an image processing apparatus and an image processing method that can accurately perform pursuing control over a memory.SOLUTION: An image processing apparatus has: a coordinate acquisition part which acquires write coordinates corresponding to the position of a pixel having been written in response to the writing of the pixel at the predetermined position in a plurality of first blocks included in image data being written; a read coordinate acquisition part which acquires read coordinates corresponding to the position of a second block to be read among a plurality of second blocks of a frame being written to a memory, the read coordinates being updated according to a data transfer length in the reading; and a control part which controls whether to permit a request to read a read part based upon position relation between the write coordinates and read coordinate.SELECTED DRAWING: Figure 2

Description

  The present invention relates to an image processing apparatus and an image processing method.

  In recent years, the number of pixels of an imaging device used for a digital camera or the like has reached tens of millions of pixels. As the number of pixels of the imaging device increases, the time required for writing and reading image data acquired by the imaging device to the memory also increases. In order to reduce the time required for writing to and reading from the memory, for example, it is proposed to read the image data from the memory immediately after writing the image data from the imaging device to the memory to perform image processing or the like. . Specifically, the memory transfer control unit manages the read address and the address being written, and executes the write process and the read process in parallel, thereby reducing the time from the start of the image data write to the completion of the read A method has been proposed. Such control is called chase control.

  Patent Document 1 discloses a technology for performing memory access so that read processing does not pass write processing. In Patent Document 1, a read counter that counts the number of reads and a write counter that counts the number of writes are used. In Patent Document 1, when the difference between the number of times of reading and the number of times of writing exceeds the upper limit setting value, the writing process is stopped. On the other hand, in Patent Document 1, when the difference between the number of times of reading and the number of times of writing becomes less than the lower limit setting, the reading process is stopped.

Unexamined-Japanese-Patent No. 2003-323333

  However, in the prior art, when the size and the like differ between the block when performing the writing process and the block when performing the reading process, the chase control to the memory can not necessarily be performed properly. .

  An object of the present invention is to provide an image processing apparatus and an image processing method capable of properly performing chase control on a memory.

  According to one aspect of the embodiment, the writing unit writes the image data to the memory in units of the first block, and the reading unit reads the image data from the memory in units of the second block. While the image data is being written to the memory by the writing unit, the writing unit outputs a request to read the image data of the frame being written to the memory, and the read request is permitted. The reading unit reads the image data from the memory, and the writing unit writes a line for writing a pixel at a predetermined position among the plurality of first blocks included in the image data of the frame being written to the memory Corresponding to the position of the pixel where the writing is completed. A read coordinate acquisition unit for acquiring the read coordinates corresponding to the position of the second block to be read out of the plurality of second blocks in the frame being written to the memory; A read coordinate acquisition unit that updates the read coordinates according to a data transfer length at the time of reading, the write coordinates acquired by the write coordinate acquisition unit, and the read coordinates acquired by the read coordinate acquisition unit And a control unit that controls whether or not to permit the read request from the read unit based on the positional relationship with the case where the positional relationship between the writing coordinates and the reading coordinates does not satisfy a predetermined condition. And a control unit that controls not to permit the read request from the read unit. The image processing apparatus is provided to symptoms.

  According to another aspect of the embodiment, the plurality of writing units each writing the image data into the memory in units of the first block, the plurality of writings including the first writing unit and the second writing unit And a reading unit for reading image data from the memory in units of the second block, the plurality of writing being performed while the one frame of the image data is being written to the memory by the plurality of writing units. A reading unit for outputting a read request for the image data of the frame being written to the memory by the unit, and for reading the image data from the memory in response to the read request being permitted; The writing of the pixel at a predetermined position among the plurality of first blocks included in the image data is performed by the first In response to what has been done by the penetration unit, the first writing unit acquires writing coordinates corresponding to the position of the pixel for which writing has been completed, and is included in the image data of the frame being written to the memory Corresponds to the position of the pixel for which writing has been completed by the second writing unit in response to the writing of the pixel at a predetermined position of the plurality of first blocks being performed by the second writing unit Acquiring a writing coordinate, and acquiring a reading coordinate corresponding to a position of the second block to be read out of the plurality of second blocks in the frame being written to the memory Reading coordinate acquiring unit, the writing coordinates acquired by the writing coordinate acquiring unit, and the reading coordinate acquiring unit Therefore, the control unit controls whether to permit the read request from the read unit based on the positional relationship with the read coordinates acquired, and the positional relationship between the write coordinates and the read coordinates is An image processing apparatus is provided, including: a control unit that controls not to permit the read request from the read unit when a predetermined condition is not satisfied.

  According to the present invention, it is possible to provide an image processing apparatus and an image processing method capable of appropriately performing chase control on a memory.

FIG. 1 is a block diagram showing an image processing apparatus according to a first embodiment. It is a block diagram showing a memory control part. It is a figure which shows notionally the order of write access and read access. It is a figure which shows the example of the aspect of the block division of write-in process and read-out process. It is a timing chart which shows operation of a memory control part of a 1st embodiment. It is a flowchart which shows operation | movement of the image processing apparatus of 1st Embodiment. It is a block diagram which shows the structure of a write-in address production | generation part and a read-out address production | generation part. It is a figure which shows the example of the aspect of block division of the modification (the 1) of 1st Embodiment. It is a figure which shows the example of the aspect of block division of the modification (the 2) of 1st Embodiment. It is a figure which shows notionally the jump of an access coordinate when an access reaches the end of a division block. It is a block diagram showing the image processing device by a 2nd embodiment. It is a block diagram showing a memory control part. It is a figure which shows notionally the order of write-in access. It is a figure which shows the example of the aspect of the block division of write-in process and read-out process. It is a timing chart which shows operation of a memory control part of a 2nd embodiment. It is a flowchart which shows operation | movement of the image processing apparatus of 2nd Embodiment. It is a figure which shows the example of the aspect of block division of the modification (the 1) of 2nd Embodiment. It is a figure which shows the example of the aspect of block division of the modification (the 2) of 2nd Embodiment.

  Hereinafter, with reference to the accompanying drawings, modes for carrying out the present invention will be described. In addition, this invention is not limited to the following embodiment, In the range which does not deviate from the summary, it can change suitably. Further, in the drawings described below, components having the same function are denoted by the same reference numerals, and the description thereof may be omitted or simplified.

First Embodiment
An image processing apparatus and an image processing method according to the first embodiment will be described with reference to the drawings. FIG. 1 is a block diagram showing an image processing apparatus 100 according to the present embodiment. In the present embodiment, when the image processing apparatus 100 is an imaging apparatus including an imaging element, more specifically, the case where the image processing apparatus 100 is a digital camera will be described as an example, but the present invention is not limited Absent.

  As shown in FIG. 1, the image processing apparatus 100 includes an image sensor 102, an A / D converter 103, a correction processor 104, a non-volatile memory 105, a non-volatile memory control unit 106, and an operation unit 107. have. The image processing apparatus 100 further includes a central processing unit (CPU) 108, a development processing unit 109, a display control unit 110, a display unit 111, a memory 112, and a memory control unit 120. The image processing apparatus 100 includes an imaging optical system 101. The imaging optical system 101 may be detachable from the body of the image processing apparatus 100 or may not be detachable.

  An imaging optical system (imaging optical unit) 101 is disposed in front of the imaging element 102. The imaging optical system 101 includes a lens, a stop, and the like. At the time of photographing, the imaging optical system 101 performs focus adjustment, exposure adjustment, and the like, and forms an optical image on the imaging element 102. The imaging device (imaging unit, imaging unit) 102 has a photoelectric conversion function of converting an optical image formed by the imaging optical system 101 into an electrical signal (analog image signal). That is, photoelectric conversion parts (photoelectric conversion elements) are arranged in a matrix on the light receiving surface (not shown) of the imaging device 102. As the imaging element 102, for example, a CCD image sensor, a CMOS image sensor, or the like is used. For example, the image sensor 102 outputs moving image data in which one frame is horizontal 1920 pixels × vertical 1080 pixels, 60 frames per second (fps). The A / D conversion unit 103 converts an analog image signal from the imaging element 102 into a digital image signal.

  The CPU 108 controls the entire image processing apparatus 100, instructs operation to each functional block (each processing unit), and executes various control and processing. The memory 112 stores data such as still images, moving images, and sounds. The memory 112 can also store constants used when operating the CPU (control unit, processing unit) 108, programs executed by the image processing apparatus 100, and the like. The memory 112 has sufficient storage capacity to store them. The memory 112 is also used when temporarily storing image data and the like being processed. For example, a dynamic random access memory (DRAM) is used as the memory 112.

  The memory control unit 120 writes and reads data to and from the memory 112 in accordance with an instruction from the CPU 108. The non-volatile memory control unit 106 writes and reads data to and from the non-volatile memory 105 in accordance with an instruction from the CPU 108. The nonvolatile memory 105 is electrically erasable and recordable, and for example, an EEPROM (Electrically Erasable Programmable Read Only Memory) or the like is used. The non-volatile memory 105 stores constants used when operating the CPU 108, programs, and the like. The CPU 108 controls the correction processing unit 104, the development processing unit 109, the memory control unit 120, the non-volatile memory control unit 106, the display control unit 110, the operation unit 107, and the imaging device 102 through a bus line not shown. Do as appropriate. The CPU 108 executes a program stored in the non-volatile memory 105 or the like to implement various processes performed by the image processing apparatus 100.

  The correction processing unit 104 performs pixel correction, black level correction, shading correction, flaw correction, lateral chromatic aberration correction, and the like on the image data output from the A / D conversion unit 103. The memory control unit 120 writes the image data subjected to the correction processing by the correction processing unit 104 in the memory 112. Further, the memory control unit 120 reads the image data written in the memory 112 from the memory 112, and transfers the read image data to, for example, the development processing unit 109. The development processing unit 109 performs resizing processing such as enlargement / reduction, compression / decompression processing, format conversion processing, development processing, distortion correction, and the like on the image data. The memory control unit 120 writes the image data processed by the development processing unit 109 in the memory 112. Further, the image data written in the memory 112 is read by the memory control unit 120 and appropriately transferred to each functional block.

  The correction processing unit 104 and the development processing unit 109 have a memory (not shown) for storing image data in order to perform the above-described processing. In order to reduce the capacity of the memory, the correction processing unit 104 and the development processing unit 109 divide blocks 300a to 300i set by dividing image data of one frame in both the horizontal direction and the vertical direction (see FIG. 3). The above processing is performed in units of. Therefore, in the present embodiment, writing and reading of image data to the memory are performed in units of divided blocks. The blocks 300a to 300i will be described in detail later.

  Furthermore, in the present embodiment, in order to reduce the delay in processing, follow-up control is performed in which the image data is sequentially read from the address at which the writing of the image data is completed. When follow-up control is performed in units of divided blocks, read processing from the block can not be performed unless writing of the image data of the block to be read is completely completed. Therefore, in the present embodiment, in order to further reduce the delay in processing, follow-up control is performed in units of lines (blocks) 320 (see FIG. 3) which are smaller units respectively included in a plurality of divided blocks. Therefore, in the present embodiment, the image data is sequentially read out from the line for which the writing process has been completed among the lines included in the block. Such chase control is executed by the memory control unit 120 or the like. Note that each line included in the divided block is divided into the same size as the size in the horizontal direction of the divided block, so it can also be called a divided line.

  The display unit 111 is controlled by the display control unit 110 and displays various image data and the like. For example, a liquid crystal monitor or the like is used as the display unit 111. The operation unit 107 includes a switch, a button, and the like operated by the user, and is used for the power ON / OFF operation, the shutter ON / OFF operation, and the like.

  FIG. 2 is a block diagram showing the memory control unit 120. As shown in FIG. The memory control unit 120 includes a direct memory access controller (DMAC) 210 and a chase control unit 200. The DMAC 210 has a WRDMAC (Write DMAC) 211 which is a write DMAC. The DMAC 210 also has an RDDMAC (Read DMAC) 213 which is a read DMAC. A memory interface (I / F) 205 controls the memory 112 in accordance with control signals from the WRDMAC 211 and RDDMAC 213.

The chase control unit 200 includes a writing coordinate calculation unit (writing coordinate acquisition unit) 201, a reading coordinate calculation unit (reading coordinate acquisition unit) 202, a coordinate comparison unit 203, and a reading request mask unit 204. The chase control unit 200 calculates write coordinates (H _W1 , V _W1 ) to (H _W3 , V _W3 ) described later based on the write offset signals WR_OFFSET1 to WR_OFFSET3 from the WRDMAC 211. Further, the chase control unit 200 calculates read coordinates (H _R , V _R ) based on the data transfer length signal RD_TRANS and the read offset signals RD_OFFSET1 to RD_OFFSET3 supplied from the RDDMAC 213. The readout coordinates include horizontal coordinates H _R and vertical coordinates V _R. The chase control unit 200 appropriately masks the read request signal RD_REQ from the RDDMAC 213 based on the comparison result between the write coordinates and the read coordinates. The chasing control is performed in which the RDDMAC 213 sequentially reads out the image data of the address for which the writing has been completed by the WRDMAC 211. Such chase control is performed by the chase control unit 200.

  The WRDMAC 211 includes a write address generation unit 212 that generates an address (access address) for writing data in the memory 112, that is, a write address (write address value) WADRS. The write address generation unit 212 can manage and control data transfer length and the like.

  The RDDMAC 213 includes a read address generation unit 214 that generates an address for reading data from the memory 112, that is, a read address (read address value) RADRS. The read address generation unit 214 can manage and control data transfer length and the like.

  The WRDMAC 211 has a function of incrementing the write address WADRS. Therefore, the WRDMAC 211 can store image data in order in a predetermined address space (address area) on the memory 112. Further, the RDDMAC 213 has a function of incrementing the read address RADRS. Therefore, the RDDMAC 213 can sequentially read out the image data stored in a predetermined address space on the memory 112. Further, the WRDMAC 211 and RDDMAC 213 can jump the access address appropriately (offset jump function), and can sequentially perform writing processing and reading processing of the image data of the divided block to the memory 112.

  Thus, the WRDMAC 211 can function as a writing unit that writes image data to the memory 112. Further, the RDDMAC 213 can function as a reading unit that reads the image data written in the memory 112 by the WRDMAC 211 from the memory 112.

  FIG. 7 is a block diagram showing the configuration of the write address generator 212 and the read address generator 214. Since the configuration of the write address generation unit 212 and the configuration of the read address generation unit 214 are the same, here, the write address generation unit 212 and the read address generation unit 214 will be described using the same drawing, that is, FIG. I decided to.

  The WRDMAC 211 and the RDDMAC 213 have an offset jump function of jumping the access address each time a certain amount of image data is transferred. For example, the access address is jumped each time transfer of image data of one line 320 (see FIG. 3) is completed. In addition, the access address is jumped each time transfer of image data of one divided block 300a to 300i (see FIG. 3) is completed. In addition, the access address is jumped each time transfer of image data of one block line 321a to 321c (see FIG. 3) is completed. In order to realize such an offset jump function, the CPU 108 performs the following settings on the WRDMAC 211 and RDDMAC 213. That is, the CPU 108 sets the start address by inputting the start address value to the address counter provided in the WRDMAC 211 and the RDDMAC 213. Further, the CPU 108 inputs the number of image divisions in the horizontal direction and the number of divisions of the image in the vertical direction to the calculation unit 701 of the WRDMAC 211 or RDDMAC 213. Here, although the case of inputting the number of horizontal and vertical divisions has been described as an example, the information to be input is not limited to this. Information indicating the aspect of division in the horizontal direction and the aspect of division in the vertical direction may be input as appropriate. As a result, it is possible to have a configuration in which division is not uniformly performed, or a configuration in which each divided block is overlapped. The CPU 108 also inputs the horizontal image size, that is, the number of pixels of the image in the horizontal direction, and the number of vertical lines, that is, the number of pixels of the image in the vertical direction, to the calculation unit 701. In addition, the CPU 108 inputs a burst length, that is, a data length that can be continuously accessed by addressing in one request signal, to the calculation unit 701. The CPU 108 also inputs an offset value (offset jump value) to the address addition value calculation unit 702 of the WRDMAC 211 or RDDMAC 213. The offset value indicates the amount of offset applied in the offset jump. There are a plurality of such offset values, and an appropriate offset value is selected according to the location where the offset jump is performed. The offset value is set by, for example, the CPU 108.

  The calculation unit 701 calculates the data transfer length based on the horizontal image size, the number of horizontal and vertical divisions, the number of vertical lines, the burst length and the like, and outputs the calculated data transfer length to the address addition value calculation unit 702. The data transfer length is the length (data amount) of data transferred in one access to the memory 112. Calculation unit 701 generates an offset signal based on the amount of data transferred in access to memory 112, and outputs the generated offset signal to address addition value calculation unit 702. Specifically, when the writing process reaches the pixels 301 to 309 located at the end (end) of the line 320, the first write offset signal WR_OFFSET1 is generated. When the read processing reaches the pixels 301 to 309 located at the end of the line 320, the first read offset signal RD_OFFSET1 is generated. When the write processing reaches the pixels 311, 312, 314, 315, 317, and 318 located at the end of the divided blocks 300a, 300b, 300d, 300e, and 300h, the second write offset signal WR_OFFSET2 is generated. Be done. When the read processing reaches the pixels 311, 312, 314, 315, 317, and 318 located at the end of the divided blocks 300a, 300b, 300d, 300e, and 300h, the second read offset signal RD_OFFSET2 is generated. Be done. When the writing process reaches the pixels 313 and 316 located at the tail end of the block lines 321a and 321b, the third write offset signal WR_OFFSET3 is generated.

  The address addition value calculation unit 702 calculates an address addition value based on the data transfer length output from the calculation unit 701, and outputs the calculated address addition value to the address calculation unit 703. When the address addition value calculation unit 702 receives the offset signal from the calculation unit 701, the address addition value calculation unit 702 adds an appropriate offset value to the data transfer length received from the calculation unit 701. The address addition value calculation unit 702 can grasp which divided block is being subjected to the writing process and the reading process based on the offset signal, and therefore can select an appropriate offset value. Then, the address addition value calculation unit 702 outputs the value obtained by the addition to the address calculation unit 703 as an address addition value.

  When the access to the memory 112 is started, the address calculation unit 703 outputs an address value based on the start address set by the CPU 108. After the access to the memory 112 is started, the address calculation unit 703 adds the address addition value output from the address addition value calculation unit 702 to the current address value, and outputs the calculated address value. When the offset signal is issued from the calculation unit 701, the address addition value output from the address addition value calculation unit 702 is offset by the offset value corresponding to the offset signal. Therefore, when the offset signal is issued from the calculation unit 701, an address jump corresponding to the offset value corresponding to the offset signal is performed.

  FIG. 3 conceptually shows the order of write access and read access. FIG. 3 conceptually shows a virtual address space in the memory 112 so as to correspond to an image. As shown in FIG. 3, rectangular divided blocks 300a to 300i are set by dividing image data of one frame into three in the horizontal direction and the vertical direction. The divided blocks 300a to 300i are accessed two-dimensionally and continuously. In the following description, reference numerals 300a to 300i will be used when describing each divided block, and reference numeral 300 will be used when describing divided blocks in general.

  Each divided block 300 includes a plurality of lines 320. Further, a block line 321a is constituted by the plurality of divided blocks 300a to 300c, and a block line 321b is constituted by the plurality of divided blocks 300d to 300f. Further, a block line 321c is configured by the plurality of divided blocks 300g to 300i. Here, reference numerals 321a to 321c are used when describing individual block lines, and reference numeral 321 is used when describing general block lines.

  The number of pixels (size) in the horizontal direction of divided blocks 300a, 300d and 300g is XA, the number of pixels in the horizontal direction of divided blocks 300b, 300e and 300h is XB, and the number of pixels in the horizontal direction of divided blocks 300c, 300f and 300i is XC I assume. The number of lines (number of pixels) in the vertical direction of divided blocks 300a to 300c is YA, the number of lines in the vertical direction of divided blocks 300d to 300f is YB, and the number of lines in the vertical direction of divided blocks 300g to 300i is YC. Here, YA = 4, YB = 4, and YC = 6 are set in order to simplify the description, but the number of lines in the vertical direction is actually much larger than these values. Further, the number of pixels in the horizontal direction of one frame is XH (= XA + XB + XC). The number of pixels XA to XC, the number of lines YA to YC, the offset value, and the like are previously input from the CPU 108 to the calculation unit 701 of the DMAC 210 and the address addition value calculation unit 702 as described above. Then, these values are stored in advance in a register (not shown) provided in the calculation unit 701 and the address addition value calculation unit 702. Arrows in FIG. 3 conceptually indicate a jump of coordinates, that is, an address jump. The address to which the data of the pixel at the upper left end of the image of one frame is written is the address at the top of the address area to which the image data of the frame is written.

  As described above, in the present embodiment, the writing process and the reading process are performed in units of the divided block 300. For example, first, the image data of the divided block 300 a located at the upper left of FIG. 3 in one frame is written to the memory 112. After the writing of the image data of the divided block 300a is completed, the writing of the image data of the divided block 300b on the right side of the divided block 300a is performed. After the writing of the image data of the divided block 300b is completed, the writing of the image data of the divided block 300c on the right side of the divided block 300b is performed. As described above, the writing of the image data of the divided blocks 300a to 300c located in the first block line 321a into the memory 112 is sequentially performed from the left to the right. After the writing of the image data of the divided blocks 300a to 300c of the first block line 321a is completed, the writing of the image data of the divided blocks 300d to 300f of the second block line 321b is sequentially performed. After the writing of the image data of the divided blocks 300 d to 300 f of the second block line 321 b is completed, the writing of the image data of the divided blocks 300 g to 300 i of the third block line 321 c is sequentially performed. Thus, writing of the image data of all the divided blocks 300a to 300i to the memory 112 is sequentially performed. Here, although the access at the time of writing is described as an example, the access at the time of reading is similarly performed.

  The order in write access is described more specifically below. First, the image data of the divided block 300a is written to the memory 112 as follows. That is, according to the address value issued by the write address generation unit 212, writing of the image data of the first line 320 of the divided block 300a into the memory 112 is performed. The first coordinate of the first line 320 of the divided block 300a is (1, 1), and the last coordinate of the first line 320 of the divided block 300a is (XA, 1). When the data transfer length in one write access is equal to the data length corresponding to one line 320, the writing in line 320 is completed by one write access. On the other hand, when the data transfer length in one write access is shorter than the data length corresponding to one line 320, the write in line 320 is completed by a plurality of write accesses.

  After the writing of the image data of the first line 320 of the divided block 300a is completed, the writing of the image data of the second line 320 of the divided block 300a is performed. The top coordinates of the second line 320 of the divided block 300a are (1, 2). The memory address corresponding to coordinate (1, 2) is not the memory address next to the memory address corresponding to coordinate (XA, 1). Therefore, when transitioning from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. Specifically, when the writing process reaches the last coordinate of the first line 320 of the divided block 300a, the address added value calculating unit 702 of the write address generating unit 212 adds the offset value to the address value. Ru. That is, the jump of the access address is performed by adding the value corresponding to the data transfer length and the offset value to the current address value. The offset value to be added here is (XH-XA).

  Thereafter, writing of the image data of the divided block 300a is sequentially performed. The offset value is added to the address value each time the writing process reaches the pixel 301 at the last coordinate of each line 320 except the last line 320 of the divided block 300a. As a result, the image data of the divided block 300a is sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 300a to the memory 112 is completed, the writing of the image data of the divided block 300b on the right side of the divided block 300a is performed. The coordinates of the last pixel 311 of the YAth line 320 which is the last line 320 of the divided block 300a, that is, the coordinates of the last pixel 311 of the divided block 300a are (XA, YA). On the other hand, the coordinates of the beginning of the first line 320 of the divided block 300b, that is, the coordinates of the beginning of the divided block 300b are (XA + 1, 1). The memory address corresponding to coordinate (XA + 1, 1) is not the memory address next to the memory address corresponding to coordinate (XA, YA). Therefore, when shifting from the writing of the image data of the first divided block 300a to the writing of the image data of the second divided block 300b, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 300a. That is, the value according to the data transfer length and the offset value are added to the address value, and the jump of the access address is performed. The offset value to be added here is (−XH × (YA−1)), and the memory address corresponding to (XA, YA) jumps to the memory address corresponding to the coordinate (XA + 1, 1). Since the offset value is negative, the vertical coordinate returns from YA to the memory address corresponding to one. Thus, the access address jumps and writing of the image data of the first line 320 of the divided block 300b is performed. After the writing of the image data of the first line 320 of the divided block 300b is completed, the writing of the image data of the second line 320 of the divided block 300b is performed. The last coordinate of the first line 320 of the divided block 300b is (XA + XB, 1), and the first coordinate of the second line 320 of the divided block 300b is (XA + 1, 2). Therefore, when transitioning from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. That is, when the writing process reaches the end coordinates of the first line 320 of the divided block 300b, the offset value is added to the address value. The offset value added here is (XH−XB). Thereafter, the image data of the divided block 300b is sequentially written. The offset value is added to the address value each time the writing process reaches the pixel 302 at the last coordinate of each line 320 except the last line 320 of the divided block 300b. Thereby, the image data of the divided block 300b is sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 300b to the memory 112 is completed, the writing of the image data of the divided block 300c on the right side of the divided block 300b is performed. Coordinates of the tail end of the divided block 300b are (XA + XB, YA). On the other hand, the top coordinates of the first line 320 of the divided block 300c are (XA + XB + 1, 1). The memory address corresponding to the coordinate (XA + XB + 1, 1) is not the memory address next to the memory address corresponding to the coordinate (XA + XB, YA). Therefore, when shifting from the writing of the image data of the divided block 300b to the writing of the image data of the divided block 300c, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 300b. That is, the value according to the data transfer length and the offset value are added to the address value, and the jump of the access address is performed. The offset value added here is (−XH × (YA−1)). Jump from the memory address corresponding to the coordinates (XA + XB, YA) to the memory address corresponding to the coordinates (XA + XB + 1, 1). Since the offset value is negative, the vertical address returns from YA to 1. Thus, the access address jumps and writing of the image data of the first line 320 of the divided block 300c is performed.

  After the writing of the image data of the first line 320 of the divided block 300c is completed, the writing of the image data of the second line 320 of the divided block 300c is performed. The last coordinate of the first line 320 of the divided block 300c is (XA + XB + XC, 1), and the first coordinate of the second line 320 of the divided block 300c is (XA + XB + 1, 2). Therefore, when transitioning from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. That is, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 300c. The offset value to be added here is (XH-XC). Thereafter, writing of the image data of the divided block 300c is sequentially performed. The offset value is added to the address value each time the writing process reaches the last pixel 303 of each line 320 except the last line 320 of the divided block 300c. Thus, the image data of the divided block 300c is sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 300c to the memory 112 is completed, the writing of the image data of the lower divided block 300d of the divided block 300a is performed. Coordinates of the tail end of the divided block 300c are (XA + XB + XC, YA). On the other hand, the top coordinates of the first line 320 of the divided block 300d are (1, YA + 1). The memory address corresponding to the coordinate (1, YA + 1) is the memory address next to the memory address corresponding to the coordinate (XA + XB + XC, YA). Therefore, the offset value is not added to the address value when shifting from the writing of the image data of the divided block 300c to the writing of the image data of the divided block 300d. In other words, the offset value = 0 is added. Thereafter, writing of the image data of the divided block 300d is sequentially performed. Every time the writing process reaches the pixel 304 at the last coordinate of each line 320 except the last line 320 of the divided block 300d, an offset value, that is, (XH-XA) is added to the address value. Thereby, the image data of the divided block 300d is sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 300d into the memory 112 is completed, the writing of the image data of the divided block 300e on the right side of the divided block 300d is performed. When shifting from the writing of the image data of the divided block 300d to the writing of the image data of the divided block 300e, the offset value is added to the address value. The offset value to be added here is (−XH × (YB−1)). Thus, the process shifts from the writing of the image data of the divided block 300d to the writing of the image data of the divided block 300e. Then, the writing of the image data of the divided block 300e is sequentially performed. Every time the writing process reaches the pixel 305 at the last coordinate of each line 320 except the last line 320 of the divided block 300e, the offset value (XH−XB) is added to the address value. Thereby, the image data of the divided block 300e is sequentially written while the access address is sequentially jumped.

  After the writing of the image data of the divided block 300e to the memory 112 is completed, the writing of the image data of the divided block 300f on the right side of the divided block 300e is performed. When shifting from the writing of the image data of the divided block 300e to the writing of the image data of the divided block 300f, the offset value is added to the address value. The offset value to be added here is (−XH × (YB−1)). Thus, the process shifts from the writing of the image data of the divided block 300e to the writing of the image data of the divided block 300f. Thereafter, writing of the image data of the divided block 300 f is sequentially performed. Every time the writing process reaches the last pixel 306 of each line 320 except for the last line 320 of the divided block 300f, an offset value (XH−XC) is added to the address value. Thereby, the image data of the divided block 300f is sequentially written while the access address is sequentially jumped.

  After the writing of the image data of the divided block 300 f to the memory 112 is completed, the writing of the image data of the lower divided block 300 g of the divided block 300 d is performed. When shifting from the writing of the image data of the divided block 300 f to the writing of the image data of the divided block 300 g, the offset value is not added to the address value. That is, the address addition value corresponding to the data transfer length is added to the address value, and the process shifts from the writing of the image data of the divided block 300 f to the writing of the image data of the divided block 300 g. Thereafter, the image data of the divided block 300g is sequentially written. Each time the writing process reaches the last pixel 307 of each line 320 except the last line 320 of the divided block 300g, an offset value, that is, (XH−XA) is added to the address value. As a result, the image data of the divided block 300g is sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 300g to the memory 112 is completed, the writing of the image data of the divided block 300h on the right side of the divided block 300g is performed. When shifting from the writing of the image data of the divided block 300g to the writing of the image data of the divided block 300h, the offset value is added to the address value. The offset value to be added here is (−XH × (YC−1)). Thus, the process shifts from the writing of the image data of the divided block 300g to the writing of the image data of the divided block 300h. Thereafter, the image data of the divided block 300h is sequentially written. Every time the writing process reaches the last pixel 308 of each line 320 except for the last line 320 of the divided block 300h, an offset value, that is, (XH-XB) is added to the address value. As a result, the image data of the divided block 300h is sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 300h to the memory 112 is completed, the writing of the image data of the divided block 300i on the right side of the divided block 300h is performed. When shifting from the writing of the image data of the divided block 300h to the writing of the image data of the divided block 300i, the offset value is added to the address value. The offset value to be added here is (−XH × (YC−1)). Thus, the process shifts from the writing of the image data of the divided block 300h to the writing of the image data of the divided block 300i. Thereafter, the writing of the image data of the divided block 300i is sequentially performed. Every time the writing process reaches the last pixel 309 of each line 320 except the last line 320 of the divided block 300i, an offset value, that is, (XH−XC) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 300i is sequentially performed.

  The image divided into nine divided blocks 300 is sequentially written to the memory 112 by the above processing.

  Although the write process has been described as an example here, the read process can be performed similarly. The operation of the read address generation unit 214 when reading the image data of the plurality of divided blocks 300 from the memory 112 is substantially the same as the operation described above of the write address generation unit 212 when writing the image data of the plurality of divided blocks 300 into the memory 112 It is similar. Therefore, the details of the read process are omitted here.

  As described above, the image processing apparatus according to the present embodiment performs chase control in units of blocks (lines) 320 included in the divided block 300. Therefore, when it becomes possible to read out the image data of a certain line 320, even if the writing of all the image data of the divided block 300 to be written is not completed, the reading of the image data of that line 320 is possible. As appropriate. The WRDMAC 211 writes a plurality of lines (blocks) 320 included in an image of one frame in the memory 122 in a predetermined order as described above. Further, the RDDMAC 213 reads a plurality of lines (blocks) 320 included in an image of one frame from the memory 112 in a predetermined order as described above.

  Next, signals input and output between the DMAC 210, the memory I / F 205, and the chase control unit 200 will be described. As shown in FIG. 2, the write request signal WR_REQ from the WRDMAC 211 is input to the memory I / F 205. The write request signal WR_REQ is a signal for requesting the memory I / F 205 to write image data to the memory 112. For example, when the WRDMAC 211 receives image data of one line 320 or a part thereof from the correction processing unit 104 and writes the image data of the one line 320 or a part thereof to the memory I / F 205 A request signal WR_REQ is issued.

  An acknowledge signal WR_ACK output in a pulse form from the memory I / F 205 is input to the WRDMAC 211. For example, when the memory I / F 205 receives the write request signal WR_REQ from the WRDMAC 211 and the memory I / F 205 can receive the write data WR_DATA, the memory I / F 205 outputs an acknowledge signal WR_ACK. After receiving the acknowledge signal WR_ACK, the WRDMAC 211 writes, for example, write data WR_DATA, which is image data of one line 320 or a part thereof, to the memory 112 via the memory I / F 205. After receiving the acknowledge signal WR_ACK, the write address generation unit 212 increments the address value in preparation for the next write, and adds various offset values to the address value as necessary.

  The read request signal RD_REQ output from the RDDMAC 213 is input to the read coordinate calculation unit 202 and the read request mask unit 204. The read request signal RD_REQ is a signal for requesting the memory I / F 205 to read image data from the memory 112. The read request signal RD_REQ is input to the memory I / F 205 as a read request signal RD_REQ_MASK_OUT through the read request mask unit 204. For example, when the RDDMAC 213 can receive image data of one line 320 or a part of it, a read request signal RD_REQ is issued. The acknowledge signal RD_ACK output in a pulse form from the memory I / F 205 is input to the RDDMAC 213. For example, when the memory I / F 205 receives the read request signal RD_REQ_MASK_OUT and the memory I / F 205 can transmit the read data RD_DATA, an acknowledge signal RD_ACK is output. After receiving the acknowledge signal RD_ACK, the RDDMAC 213 reads read data RD_DATA, which is image data of one line 320 or a part thereof, for example, from the memory 112 via the memory I / F 205. The RDDMAC 213 transmits the read data RD_DATA read from the memory 112 to the development processing unit 109. After receiving the acknowledge signal RD_ACK, the read address generation unit 214 increments the address value in preparation for the next read, and adds various offset values to the address value as necessary.

When the write address generation unit 212 adds the offset value to the address value, the write offset signals WR_OFFSET1 to WR_OFFSET3 are issued by the WRDMAC 211. The write offset signals WR_OFFSET1 to WR_OFFSET3 issued by the WRDMAC 211 are input to the write coordinate calculation unit 201. The writing coordinate calculation unit 201 calculates first to third writing coordinates indicating where the writing process has reached, based on the writing offset signals WR_OFFSET1 to WR_OFFSET3. The first writing coordinates include horizontal coordinates H _w1 and vertical coordinates V _w1 . The second writing coordinates include horizontal coordinates H _w2 and vertical coordinates V _w2 . The third writing coordinates include horizontal coordinates H _w3 and vertical coordinates V _w3 . The first writing coordinates are updated when the writing process reaches the last pixels 301 to 309 of the line 320 excluding the last line 320 of the divided block 300. The first writing coordinates indicate the coordinates of the last pixels 301 to 309 of the line 320 excluding the last line 320 of the lines 320 for which the writing process has been completed. The second writing coordinates are when writing processing reaches the last pixels 311, 312, 314, 315, 317, and 318 of the divided block 300 excluding the last divided block among the divided blocks 300 of the block line 321. It will be updated. The second writing coordinates indicate the coordinates of the last pixels 311, 312, 314, 315, 317, and 318 of the last divided block 300 of the divided blocks 300 for which the writing process has been completed. The third writing coordinates are updated when writing processing reaches the last pixel 313, 316 of the block line 321 excluding the last block line 321 among the plurality of block lines 321. The third writing coordinates indicate the coordinates of the last pixels 313 and 316 of the block line 321 for which the writing process has been completed. The write offset signals WR_OFFSET1 to WR_OFFSET3 issued from the WRDMAC 211 are output at High level in synchronization with the write request signal WR_REQ.

  The writing coordinate calculation unit 201 can function as writing coordinate calculation means for calculating, based on the writing offset signal, writing coordinates indicating the position of the block 320 in which writing has been completed among the plurality of blocks (lines) 320. The writing coordinate calculation unit 201 updates the writing coordinates each time the writing of the plurality of blocks 320 included in one frame is completed. The read coordinate calculation unit 202 can function as read coordinate calculation means that calculates read coordinates indicating the end of the target part of the read based on the read offset signal and the data transfer length signal.

  The writing coordinate calculation unit 201 acquires a first writing coordinate corresponding to the position of the latest line 320 that has been written in the division block 300 to be written. In addition, the writing coordinate calculation unit 201 acquires a second writing coordinate corresponding to the last position of the latest divided block 300 in the block 300 in which all the pixels have been written. In addition, the writing coordinate calculation unit 201 acquires a third writing coordinate corresponding to the last position of the latest divided block 300 among the written divided blocks 300 at the right end (end portion) of the frame.

When the read address generation unit 214 adds the offset value to the address value, the read offset signals RD_OFFSET1 to RD_OFFSET3 are issued by the RDDMAC 213. The read offset signals RD_OFFSET1 to RD_OFFSET3 from the RDDMAC 213 are input to the read coordinate calculation unit 202. Reading coordinate calculation unit 202, then read request signal RD_REQ_MASK_OUT calculates the read coordinates indicating coordinates of the last pixel in the interesting portions of the reading process when it becomes High level _{(H R, V} R). The read coordinate calculation unit 202 calculates read coordinates (H _R , V _R ) based on the read offset signals RD_OFFSET1 to RD_OFFSET3 and the data transfer length signal RD_TRANS.

Reading coordinate calculation unit 202 increases the value of the amount corresponding _{H R} of the data transfer length indicated by the data transfer length signal RD_TRANS. When the read offset signal RD_OFFSET1 issued in the reading process of the line 320 excluding the last line 320 included in the divided block 300 is received, the read coordinate calculation unit 202 operates as follows. That is, the read coordinate calculation unit 202, an amount corresponding with decreasing the value of H _R horizontal size of the divided blocks 300 (number of pixels) increases the value of V _R by one. Further, when the read offset signal RD_OFFSET2 which is issued each time the read processing reaches the last pixel of the divided block 300 excluding the last divided block 300 of the block line 321 is received, the read coordinate calculation unit 202 To work. That is, the read coordinate calculation unit 202 reduces the value of the amount corresponding V _R of a value obtained by subtracting 1 from the number of lines 320 included in the divided blocks 300. Further, when the read offset signal RD_OFFSET3 which is generated each time the read processing reaches the last pixel of the block line 321 is received, the read coordinate calculation unit 202 operates as follows. That is, the read coordinate calculation unit 202, a slight proportion value of an amount corresponding H _R of the horizontal size of the block lines 321 (the number of pixels) increases the value of V _R by one. When the read request signal RD_REQ is issued from the RDDMAC 213 to the read request mask unit 204, the read coordinate calculation unit 202 updates the read coordinates (H _R , V _R ).

  The chase control unit 200 is provided with a coordinate comparison unit 203. The first to third writing coordinates calculated by the writing coordinate calculation unit 201 are input to the coordinate comparison unit 203. Further, the read coordinate calculated by the read coordinate calculation unit 202 is input to the coordinate comparison unit 203. The coordinate comparison unit 203 reads out the first to third writing coordinates for grasping the position of the line 320 for which the writing process has been completed and the reading for grasping the last position of the portion to be read next. Compare with coordinates. As a result of comparing the first to third writing coordinates and the reading coordinates, it is preferable that the reading process is performed when any one of the following conditional expressions (1) to (3) is satisfied. Therefore, when any one of the conditional expressions (1) to (3) is satisfied, the coordinate comparison unit 203 sets the request mask signal REQ_MASK output to the read request mask unit 204 to the low level. As described later, when the request mask signal REQ_MASK is set to the low level, the read request signal RD_REQ from the RDDMAC 213 is not masked in the read request mask unit 204, and the read processing is performed. On the other hand, when none of the conditional expressions (1) to (3) is satisfied, the reading process is not performed.

Therefore, when none of the following conditional expressions (1) to (3) is satisfied, the coordinate comparison unit 203 sets the request mask signal REQ_MASK output to the read request mask unit 204 to the high level.
H _W1 HH _R and V _W1 VV _R (1)
H _W2 HH _R and V _W2 VV _R (2)
H _W3 HH _R and V _W3 VV _R (3)
The determination as to whether or not any one of the conditions (1) to (3) is satisfied is performed at the rise timing of the clock signal CLK. Thus, the coordinate comparison unit 203 controls the request mask signal REQ_MASK.

When the first condition is not satisfied, the second condition is not satisfied, and the third condition is not satisfied, the coordinate comparison unit 203 controls not to permit the read unit. The first condition is that H _w1 is _equal to or greater than H _R and V _w1 is _equal to or greater than V _R. The second condition is that H _w2 is _equal to or greater than H _R and V _w2 is _equal to or greater than V _R. The third condition is that H _w3 is _equal to or greater than H _R and V _w3 is _equal to or greater than V _R.

  When the request mask signal REQ_MASK is at the low level, the read request mask unit 204 sets the read request signal RD_REQ_MASK_OUT output to the memory I / F 205 to the high level. On the other hand, when the request mask signal REQ_MASK is at the high level, the read request mask unit 204 sets the read request signal RD_REQ_MASK_OUT output to the memory I / F 205 to the low level. As described above, the coordinate comparison unit 203 and the read request mask unit 204 can function as a control unit that controls whether the read request from the RDDMAC 213 is permitted based on the positional relationship between the write coordinates and the read coordinates. .

  The WRDMAC 211 outputs a write completion signal WR_END to the coordinate comparison unit 203 when the write process for the last pixel of the image data of one frame is completed. When receiving the write completion signal WR_END, the coordinate comparison unit 203 sets the request mask signal REQ_MASK to Low level in order to release the mask of the read request signal RD_REQ. After the writing of the image data of one frame is completed, the read request signal RD_REQ output from the RDDMAC 213 is not masked by the read request mask unit 204. The read request signal RD_REQ is output to the memory I / F 205 as a read request signal RD_REQ_MASK_OUT signal. Note that mask control of chase control is started based on the read start signal RD_START supplied from the RDDMAC 213 to the coordinate comparison unit 203.

  The details of the operation performed by the chase control unit 200 will be described with reference to FIGS. 4 and 5. FIG. 4 is a diagram showing an example of the aspect of block division in the write processing and the read processing. FIG. 4 shows an example in which the aspect of block division for write processing is different from the aspect of block division for read processing. More specifically, the size of the write divided blocks WR0_0 to WR2_2 is different from the size of the read divided blocks RD0_0 to RD3_3. FIG. 4 corresponds to the case where the aspect of block division in the processing unit that writes the image is different from the aspect of block division in the processing unit that reads the image. Blocks for write processing are shown by solid lines, and blocks for read processing are shown by dashed lines. The number of divisions of the write processing block is set to 3 in both the horizontal and vertical directions. That is, nine divided blocks for write processing are set. On the other hand, the number of divisions of the read processing block is set to 4 in both the horizontal and vertical directions. That is, sixteen read divided blocks are set.

The numbers of pixels in the horizontal direction of the write divided blocks (write divided blocks) WR0_ *, WR1_ *, and WR2_ * (* is an integer from 0 to 2) are WXA, WXB, and WXC, respectively. In addition, the number of lines of divided blocks WR * _0, WR * _1, and WR * _2 (* is an integer of 0 to 2) for writing, that is, the number of pixels in the vertical direction are WYA = 4, WYB = 4, WYC, respectively. It is assumed that = 6. Here, in order to simplify the description, WYA = 4, WYB = 4, and WYC = 6, but the number of lines in the vertical direction is actually much larger than these values. The numbers of pixels in the horizontal direction of the divided blocks for reading (read divided blocks) RD0_ *, RD1_ *, RD2_ *, RD3_ * (* is an integer from 0 to 3) are respectively RXA, RXB, RXC, and RXD. The number of lines of the divided blocks RD * _0, RD * _1, RD * _2, RD * _3 (* is an integer from 0 to 3) for reading, that is, the number of pixels in the vertical direction are RYA = 3 and RYB = 3, respectively. , RYC = 3, RYD = 5. Here, in order to simplify the description, RYA = 3, RYB = 3, RYC = 3, and RYD = 5, but the number of lines in the vertical direction is actually much larger than these values. However, the number of pixels in the horizontal direction of each block satisfies the following conditions (4) to (6).
RXA <WXA (4)
(RXA + RXB) <(WXA + WXB) (5)
(RXA + RXB + RXC) <(WXA + WXB + WXC) (6)

  FIG. 5 is a timing chart showing the operation of the memory control unit 120. FIG. 5 shows a period (write period) in which write processing for divided blocks WR0_0 to WR2_0 for write is performed and a period (read period) in which read processing for divided blocks RD0_0 to RD3_0 for read is performed. It is done. Here, the case where the size in the horizontal direction of each of the divided blocks WR0_0 to WR2_0 and RD0_0 to RD3_0 is equal to or less than the data length transferable by one access will be described as an example. In order to simplify the description, the case where one line of data is transferred in one request will be described as an example.

  First, before the writing process and the reading process for an image of one frame are started, initialization is performed in the writing coordinate calculation unit 201 and the reading coordinate calculation unit 202. That is, in the writing coordinate calculation unit 201, the first to third writing coordinates are initialized to (0, 1). Further, in the read coordinate calculation unit 202, the read coordinate is initialized to (0, 1). Then, writing of the leading writing divided block WR0_0 and reading of the leading reading divided block RD0_0 are started.

  First, at an early stage, the image data of any line 320 of the divided blocks for writing WR0_0 to WR2_2 is not written to the memory 112. Therefore, at this stage, as shown below, the image data of the first line 320 of the divided block RD0_0 for reading is not read out. That is, first, the read request signal RD_REQ output from the RDDMAC 213 is set to the high level. In addition, the first read offset signal RD_OFFSET1 output from the RDDMAC 213 becomes High level in synchronization with the read request signal RD_REQ. The read-out coordinates are updated by the read-out coordinate calculation unit 202 at time tr0 of the fall of the read-out coordinate update signal output in a pulse shape in synchronization with the rise of the read-out request signal RD_REQ. The coordinates at the end of the first line 320 of the divided block RD0_0 for reading are (RXA, 1), so the reading coordinates are updated to (RXA, 1). At this stage, the first to third writing coordinates are all (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK output from the coordinate comparison unit 203 is at the high level. Since the request mask signal REQ_MASK is at the high level, the read request signal RD_REQ_MASK_OUT output from the read request mask unit 204 to the memory I / F 205 is at the low level. Therefore, the image data of the first line 320 of the divided block WR0_0 for writing is not read from the memory 112.

  Next, the image data of the first line 320 of the divided block WR0_0 for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ from the WRDMAC 211 is set to the high level. The first write offset signal WR_OFFSET1 from the WRDMAC 211 goes high in synchronization with the write request signal WR_REQ. An acknowledge signal WR_ACK is returned from the memory I / F 205 to the WRDMAC 211, and writing of image data of the first line 320 of the divided block WR0_0 for writing into the memory 112 is performed. The write request signal WR_REQ goes low in synchronization with the falling of the acknowledge signal WR_ACK. Further, the first write offset signal WR_OFFSET1 becomes low level in synchronization with the fall of the write request signal WR_REQ. The first writing coordinates are updated by the writing coordinate calculation unit 201 at time tw0 of the fall of the first writing coordinate update signal synchronized with the acknowledge signal WR_ACK. Since the last coordinate of the first line 320 of the write divided block WR0_0 is (WXA, 1), the first write coordinate is updated to (WXA, 1). At this stage, since the conditional expression (1) is satisfied, the request mask signal REQ_MASK from the coordinate comparison unit 203 is at the low level. Since the request mask signal REQ_MASK is at the low level, the read request signal RD_REQ_MASK_OUT output from the read request mask unit 204 to the memory I / F 205 is at the high level. Thereafter, the acknowledge signal RD_ACK is sent in a pulse form from the memory I / F 205 to the RDDMAC 213, and the image data of the first line 320 of the read divided block RD0_0 is read from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

  Next, the read request signal RD_REQ is set to the high level. The first read offset signal RD_OFFSET1 becomes high level in synchronization with the read request signal RD_REQ. The read-out coordinate is updated by the read-out coordinate calculation unit 202 at time tr1 of falling of the read-out coordinate update signal which is emitted in a pulse shape in synchronization with the rising of the read request signal RD_REQ. Since the reading of the image data of the first line 320 of the divided block RD0_0 for reading from the memory 112 is completed, the read target in the next reading process is the second of the read divided block RD0_0. The third line 320. The last coordinate of the second line 320 of the read divided block RD0_0 is (RXA, 2). For this reason, the readout coordinates are updated to (RXA, 2). At this stage, the first writing coordinates are (WXA, 1), and the second writing coordinates and the third writing coordinates are both (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK from the coordinate comparison unit 203 is at the high level. Since the request mask signal REQ_MASK is at the high level, the read request signal RD_REQ_MASK_OUT output from the read request mask unit 204 to the memory I / F 205 is at the low level. Therefore, at this stage, the image data of the second line 320 of the divided block WR0_0 for writing is not read from the memory 112.

  Next, the image data of the second line 320 of the divided block WR0_0 for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ is set to the high level. The first write offset signal WR_OFFSET1 becomes high level in synchronization with the write request signal WR_REQ. Thereafter, an acknowledge signal WR_ACK is returned, and the image data of the second line 320 of the divided block WR0_0 for writing is written to the memory 112. The write request signal WR_REQ goes low in synchronization with the falling of the acknowledge signal WR_ACK. The first write offset signal WR_OFFSET1 becomes low level in synchronization with the fall of the write request signal WR_REQ. The first write coordinates are updated at time tw1 of the fall of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK. Since the last coordinate of the second line 320 of the divided block WR0_0 for writing is (WXA, 2), the first writing coordinate is updated to (WXA, 2). At this stage, since the conditional expression (1) is satisfied, the request mask signal REQ_MASK from the coordinate comparison unit 203 becomes low level, and the read request signal RD_REQ_MASK_OUT becomes high level. Thereafter, the acknowledge signal RD_ACK is sent back to the RDDMAC 213, and the image data of the second line 320 of the read divided block RD0_0 is read out from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

  Next, the read request signal RD_REQ is set to the high level. The second read offset signal RD_OFFSET2 becomes High level in synchronization with the read request signal RD_REQ. The readout coordinates are updated at time tr2 of the fall of the readout coordinate update signal which is emitted in a pulse shape in synchronization with the rise of the readout request signal RD_REQ. Since reading of the image data of the second line 320 of the divided block RD0_0 for reading is completed, the line 320 to be read in the next reading process is the third of the third divided block RD0_0 for reading. Line 320. The last coordinate of the third line 320 of the read divided block RD0_0 is (RXA, 3). For this reason, the readout coordinates are updated to (RXA, 3). At this stage, the first writing coordinates are (WXA, 2), and the second writing coordinates and the third writing coordinates are both (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK is at the high level, and the read request signal RD_REQ_MASK_OUT is at the low level. Therefore, at this stage, the image data of the third line 320 of the divided block WR0_0 for writing is not read from the memory 112.

  The image data of the third line 320 of the divided block WR0_0 for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ is set to the high level. The first write offset signal WR_OFFSET1 becomes high level in synchronization with the write request signal WR_REQ. Thereafter, the acknowledge signal WR_ACK is returned, and the image data of the third line 320 of the divided block WR0_0 is written to the memory 112. The write request signal WR_REQ goes low in synchronization with the falling of the acknowledge signal WR_ACK. The first write offset signal WR_OFFSET1 becomes low level in synchronization with the fall of the write request signal WR_REQ. The first write coordinates are updated at time tw2 of the fall of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK. Since the last coordinate of the third line 320 of the divided block WR0_0 for writing is (WXA, 3), the first writing coordinate is updated to (WXA, 3). At this stage, since the conditional expression (1) is satisfied, the request mask signal REQ_MASK from the coordinate comparison unit 203 becomes low level, and the read request signal RD_REQ_MASK_OUT becomes high level. Thereafter, the acknowledge signal RD_ACK is sent back to the RDDMAC 213, and the image data of the third line 320 of the divided block RD0_0 for reading is read out from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. The second read offset signal RD_OFFSET2 becomes low level in synchronization with the fall of the read request signal RD_REQ. In this way, the reading of the image data of all the lines 320 of the leading read divided block RD0_0 from the memory 112 is completed.

  Next, the read request signal RD_REQ is set to the high level. The first read offset signal RD_OFFSET1 becomes high level in synchronization with the read request signal RD_REQ. The readout coordinates are updated at time tr3 of the fall of the readout coordinate update signal which is emitted in a pulse shape in synchronization with the rise of the readout request signal RD_REQ. Since reading of the image data of all the lines 320 of the divided block RD0_0 for reading has been completed from the memory 112, the first read process of the next reading process is the first of the divided blocks RD1_0 for reading. Line 320. The last coordinate of the first line 320 of the divided block RD1_0 for reading is (RXA + RXB, 1). For this reason, the readout coordinates are updated to (RXA + RXB, 1). At this stage, the first writing coordinate is (WXA, 3), the second writing coordinate is (0, 1), and the third writing coordinate is (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK is at the high level, and the read request signal RD_REQ_MASK_OUT is at the low level. Therefore, at this stage, the image data of the first line 320 of the divided block WR1_0 for writing is not read from the memory 112.

  The image data of the fourth line 320 of the divided block WR0_0 for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ is set to the high level. The second write offset signal WR_OFFSET2 becomes high level in synchronization with the write request signal WR_REQ. An acknowledge signal WR_ACK is returned from the memory I / F 205 to the WRDMAC 211, and the image data of the fourth line 320 of the divided block WR0_0 for writing is written to the memory 112. The write request signal WR_REQ goes low in synchronization with the falling of the acknowledge signal WR_ACK. The second write offset signal WR_OFFSET2 becomes low level in synchronization with the fall of the write request signal WR_REQ. The second write coordinates are updated at time tw3 of the fall of the second write coordinate update signal synchronized with the acknowledge signal WR_ACK. Since the last coordinate of the fourth line 320 of the divided block WR0_0 for writing is (WXA, 4), the second writing coordinate is updated to (WXA, 4). At this stage, the readout coordinates are (RXA + RXB, 1), and none of the conditional expressions (1) to (3) is satisfied. Therefore, the request mask signal REQ_MASK from the coordinate comparison unit 203 is at the high level, and the read request signal RD_REQ_MASK_OUT is at the low level. Therefore, at this stage, the image data written to the fourth line 320 of the divided block WR0_0 for writing is not read from the memory 112.

  Next, the image data of the first line 320 of the divided block WR1_0 for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ is set to the high level. The first write offset signal WR_OFFSET1 becomes high level in synchronization with the write request signal WR_REQ. An acknowledge signal WR_ACK is returned from the memory I / F 205 to the WRDMAC 211, and the image data of the first line 320 of the divided block WR1_0 for writing is written to the memory 112. The write request signal WR_REQ goes low in synchronization with the falling of the acknowledge signal WR_ACK. The first write offset signal WR_OFFSET1 becomes low level in synchronization with the fall of the write request signal WR_REQ. The first write coordinates are updated at time tw4 of the fall of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK. Since the last coordinate of the first line 320 of the divided block WR1_0 for writing is (WXA + WXB, 1), the first writing coordinate is updated to (WXA + WXB, 1). At this stage, the readout coordinates are (RXA + RXB, 1), which satisfies the conditional expression (1). Therefore, the request mask signal REQ_MASK from the coordinate comparison unit 203 is at the low level, and the read request signal RD_REQ_MASK_OUT is at the high level. After that, the acknowledge signal RD_ACK is returned to the RDDMAC 213, and the image data of the first line 320 of the divided block RD1_0 for reading is read out from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

  Next, the read request signal RD_REQ is set to the high level. The first read offset signal RD_OFFSET1 becomes high level in synchronization with the read request signal RD_REQ. The read coordinates are updated at time tr4 of the falling edge of the read coordinate update signal which is emitted in a pulse shape in synchronization with the rising of the read request signal RD_REQ. Since the reading of the image data of the first line 320 of the divided block RD1_0 for reading is completed, the line 320 to be read in the next reading process is the second of the divided blocks RD1_0 for reading. Line 320. The last coordinate of the second line 320 of the divided block RD1_0 for reading is (RXA + RXB, 2). For this reason, the readout coordinates are updated to (RXA + RXB, 2). At this stage, the first writing coordinate is (WXA + WXB, 1), the second writing coordinate is (WXA, 4), and the third writing coordinate is (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK is at the high level, and the read request signal RD_REQ_MASK_OUT is at the low level. Therefore, at this stage, the image data of the second line 320 of the divided block WR1_0 for writing is not read from the memory 112.

  Next, the image data of the second line 320 of the divided block WR1_0 for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ is set to the high level. The first write offset signal WR_OFFSET1 becomes high level in synchronization with the write request signal WR_REQ. An acknowledge signal WR_ACK is returned from the memory I / F 205 to the WRDMAC 211, and the image data of the second line 320 of the divided block WR1_0 for writing is written to the memory 112. The write request signal WR_REQ goes low in synchronization with the falling of the acknowledge signal WR_ACK. The first write offset signal WR_OFFSET1 becomes low level in synchronization with the fall of the write request signal WR_REQ. The first writing coordinate is updated by the writing coordinate calculation unit 201 at time tw5 at which the first writing coordinate update signal synchronized with the acknowledge signal WR_ACK falls. Since the last coordinate of the second line 320 of the divided block WR1_0 for writing is (WXA + WXB, 2), the first writing coordinate is updated to (WXA + WXB, 2). At this stage, the read coordinates are (RXA + RXB, 2), and the conditional expression (1) is satisfied. Therefore, the request mask signal REQ_MASK is at the low level, and the read request signal RD_REQ_MASK_OUT is at the high level. Thereafter, the acknowledge signal RD_ACK is sent in a pulse form from the memory I / F 205 to the RDDMAC 213, and the image data of the second line 320 of the read divided block RD1_0 is read from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. The first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

  The subsequent write processing of the write divided block WR1_0 is the same as the above-described write processing for the write divided block WR0_0, and thus the description thereof is omitted. At time tw6, the first writing coordinate is updated to (WXA + WXB, 3), and at time tw7, the second writing coordinate is updated to (WXA + WXB, 4).

  Further, the subsequent read process of the read divided blocks RD1_0 and RD2_0 is the same as the above-described read process for the read divided block RD0_0, and thus the description thereof is omitted. At times tr5, tr6, tr7 and tr8, the read coordinates are updated to (RXA + RXB, 3), (RXA + RXB + RXC, 1), (RXA + RXB + RXC, 2), and (RXA + RXB + RXC, 3).

  The writing process of the divided block WR2_0 for writing is also similar to the above-described writing process for the divided block WR0_0 for writing, and thus the description thereof will be omitted. At times tw8, tw9, and tw10, the first writing coordinates are updated to (WXA + WXB + WXC, 1), (WXA + WXB + WXC, 2), and (WXA + WXB + WXC, 3), respectively. When writing the image data of the fourth line 320 of the divided block WR2_0 for writing into the memory 112, the third write offset signal WR_OFFSET3 becomes High level in synchronization with the write request signal WR_REQ. Further, the third write offset signal WR_OFFSET3 becomes low level in synchronization with the fall of the write request signal WR_REQ. The third write coordinate is updated to (WXA + WXB + WXC, 4) at time tw11 of the fall of the third write coordinate update signal synchronized with the acknowledge signal WR_ACK.

  In the reading process of the read divided block RD3_0, the read coordinates are updated to (RXA + RXB + RXC + RXD, 1) at time tr9. The third write coordinate is (WXA + WXB + WXC, 4), and since the conditional expression (3) is satisfied, the request mask signal REQ_MASK is Low level, and the read request signal RD_REQ_MASK_OUT is High level. Therefore, the image data is read from the first line 320 of the divided block RD3_0 for reading. At time tr10, the readout coordinates are updated to (RXA + RXB + RXC + RXD, 2). The third write coordinate is (WXA + WXB + WXC, 4), and since the conditional expression (3) is satisfied, the request mask signal REQ_MASK is Low level, and the read request signal RD_REQ_MASK_OUT is High level. Therefore, the image data is read from the second line 320 of the divided block RD3_0 for reading. At time tr11, the readout coordinates are updated to (RXA + RXB + RXC + RXD, 3). The third write coordinate is (WXA + WXB + WXC, 4), and since the conditional expression (3) is satisfied, the request mask signal REQ_MASK is Low level, and the read request signal RD_REQ_MASK_OUT is High level. Therefore, the image data is read from the third line 320 of the divided block RD3_0 for reading.

  The writing process and the reading process are performed on the divided blocks WR0_1 to WR2_2 for writing and the divided blocks RD0_1 to RD3_3 for reading in the same manner as described above.

  The dots shown in FIG. 4 indicate the state where the writing process has been completed up to the third line 320 of the divided block WR1_2 for writing. In this state, the first writing coordinate is (WXA + WXB, 11), the second writing coordinate is (WXA, 14), and the third writing coordinate is (WXA + WXB + WXC, 8). Also, the readout coordinates are (RXA + RXB + RXC, 8). In this state, the reading of the image data of the second line 320 of the read divided block RD2_2 from the memory 112 is completed. Thereafter, when the writing process proceeds and the image data of the first line 320 of the divided block WR2_2 for writing is written, the first writing coordinates become (WXA + WXB + WXC, 9), and the conditional expression (1) Is satisfied. Then, the image data of the third line 320 of the divided block RD2_2 for reading is read from the memory 112, and the reading coordinates are updated to (RXA + RXB + RXC, 9).

  When the write processing of the write divided block WR2_2 is completed, the WRDMAC 211 sets the write completion signal WR_END to the high level. When the write completion signal WR_END goes to the high level, the coordinate comparison unit 203 stops comparison of the coordinates based on the conditional expressions (1) to (3), and sets the request mask signal REQ_MASK to the low level. As a result, after the write process of the write divided block WR2_2 is completed, the read request signal RD_REQ output from the RDDMAC 213 is not masked by the read request mask unit 204. Therefore, after the writing process of the write divided block WR2_2 is completed, the image data of the read divided block is continuously read from the memory 112.

  Here, although the case where the size in the horizontal direction of each of the divided blocks WR0_0 to WR2_2 and RD0_0 to RD3_2 is equal to or less than the data length that can be transferred by one access is described as an example, Absent. For example, when the size in the horizontal direction of each of the divided blocks WR0_0 to WR2_0 and RD0_0 to RD3_0 is larger than the data length that can be transferred in one access, the following processing is performed. That is, when data is written to one line 320, issuance of a write request and data writing are performed a plurality of times. Further, in reading data from one line 320, issuance of a read request and reading of data are performed a plurality of times.

  When the data of the last pixel of the line 320 is not written, the WRDMAC 211 maintains the write offset signals WR_OFFSET1 to WR_OFFSET3 at Low level. On the other hand, when writing the data of the last pixel of the line 320, the WRDMAC 211 sets one of the write offset signals WR_OFFSET1 to WR_OFFSET3 to the high level. The first to third writing coordinates are updated by the writing coordinate calculation unit 201 only when the data of the last pixel of the line 320 is written.

  Further, when the data of the last pixel of the line 320 is not read, the RDDMAC 213 maintains the read offset signals RD_OFFSET1 to RD_OFFSET3 at Low level. On the other hand, when reading the data of the last pixel of the line 320 in the read, the RDDMAC 213 sets one of the read offset signals RD_OFFSET1 to RD_OFFSET3 to the high level. The readout coordinates are updated regardless of whether or not the data of the last pixel of the line 320 is read out. When the data of the last pixel of the line 320 is not read out, the readout coordinate calculation unit 202 performs the following operation. That is, every time the read request signal RD_REQ is supplied from the RDDMAC 213, the read coordinate calculation unit 202 updates the read coordinates from the RDDMAC 213 based on the data transfer length signal RD_TRANS. On the other hand, when the data of the last pixel of the line 320 is read out, the reading coordinate calculation unit 202 performs the following operation. The read coordinate calculation unit 202 updates the read coordinates based on the read offset signals RD_OFFSET1 to RD_OFFSET3 from the RDDMAC 213 and the data transfer length signal RD_TRANS from the RDDMAC 213.

  FIG. 6 is a flowchart showing the operation of the image processing apparatus according to the present embodiment. The processing illustrated in FIG. 6 is mainly executed by the CPU 108 and the memory control unit 120.

  First, in response to an instruction from the CPU 108, the WRDMAC 211 and RDDMAC 213 start processing (step S600).

  Next, the writing coordinate calculation unit 201 initializes the first to third writing coordinates to, for example, (0, 1). Further, the readout coordinate calculation unit 202 initializes the readout coordinates to, for example, (0, 1). The initialization of these coordinate values is performed according to an instruction from the CPU 108 (step S601).

  In step S602, the coordinate comparison unit 203 determines whether any one of the conditional expressions (1) to (3) is satisfied. If one of the conditional expressions (1) to (3) is satisfied (YES in step S602), the process proceeds to step S603. In step S603, the read request mask unit 204 cancels the mask process for the read request signal RD_REQ from the RDDMAC 213. Thereafter, the process proceeds to step S605. If none of the conditional expressions (1) to (3) is satisfied (NO in step S602), the process proceeds to step S604. In step S604, the read request mask unit 204 masks the read request signal RD_REQ from the RDDMAC 213. As a result, reading of image data from the memory 112 by the RDDMAC 213 is stopped. Thereafter, the process proceeds to step S605.

  In step S605, it is determined whether the first write offset signal WR_OFFSET1 from the WRDMAC 211 is at the high level. If the first writing offset signal WR_OFFSET1 is at the high level (YES in step S605), the first writing coordinates are updated to the coordinates of the last pixel of the line 320 for which the writing process has been completed (step S608). If the first write offset signal WR_OFFSET1 is not at the high level (NO in step S605), the process proceeds to step S606.

  In step S606, it is determined whether the second write offset signal WR_OFFSET2 output from the WRDMAC 211 is at the high level. If the second writing offset signal WR_OFFSET2 is at the high level (YES in step S606), the second writing coordinates are updated to the coordinates of the last pixel of the line 320 for which the writing process has been completed (step S609). If the second write offset signal WR_OFFSET2 is not at the high level, the process proceeds to step S607.

  In step S607, it is determined whether the third write offset signal WR_OFFSET3 output from the WRDMAC 211 is at the high level. If the third write offset signal WR_OFFSET3 is at the high level, the third write coordinates are updated to the coordinates of the last pixel of the line 320 for which the writing process has been completed (step S610). If the third write offset signal WR_OFFSET3 is not at the high level, the process proceeds to step S611.

  In step S611, it is determined whether the read request signal RD_REQ output from the RDDMAC 213 is at the high level. If the read request signal RD_REQ is at the high level, the process proceeds to step S612. On the other hand, if the read request signal RD_REQ is not at the high level, the process proceeds to step S615.

In step S612, it is determined whether any one of the first to third read offset signals RD_OFFSET1 to RD_OFFSET3 is at the high level. If one of the first to third read offset signals RD_OFFSET1 to RD_OFFSET3 is at the high level (YES in step S612), the process proceeds to step S613. In step S613, the readout coordinate H _R in the horizontal direction and the readout coordinate V _{R in the} vertical direction are updated. Thereafter, the process proceeds to step S615. If all the first to third read offset signals RD_OFFSET1 to RD_OFFSET3 are not at the high level (NO in step S612), the process proceeds to step S614. In step S614, the readout coordinate H _R in the horizontal direction is updated. Thereafter, the process proceeds to step S615.

  In step S615, it is determined whether the writing process has been completed. When the writing process is completed (YES in step S615), the process proceeds to step S616.

  In step S616, after the mask for the read request signal RD_REQ is released, the process proceeds to step S617. On the other hand, when the writing process is not completed (NO in step S615), the process returns to step S602, and the same process as described above is performed.

  In step S617, the reading process of the line (block) 320 whose reading is not completed is performed, and it is determined whether the reading process is completed. If the reading process is not completed (NO in step S617), the reading process of the line 320 which is not completed is continuously performed. On the other hand, when the reading process is completed (YES in step S617), the chase control ends.

  As described above, the writing coordinates corresponding to the block (line) 320 for which the writing processing has been completed are compared with the reading coordinates corresponding to the block 320 in which the reading processing is performed. Then, reading is performed based on the result of comparison between the writing coordinates and the reading coordinates. In this embodiment, since the readability is determined by comparing the coordinates, even if the size of the write block 320 is different from the size of the read block 320, the block is not completely written. There is no possibility to read out 320. Therefore, according to the present embodiment, it is possible to provide an image processing apparatus and an image processing method capable of appropriately performing chase control.

(Modification (Part 1))
An image processing apparatus and an image processing method according to a modification (part 1) of the embodiment will be described with reference to FIG. FIG. 8 is a diagram showing an aspect of block division in the present modification. A thick solid line in FIG. 8 conceptually shows a divided block for writing, and a thick broken line in FIG. 8 conceptually shows a divided block for reading.

  In this modification, the access start coordinates in the writing process are different from the access start coordinates in the reading process. That is, in this modification, the coordinates of the beginning of the first line 320 of the first division block WR0_0 for writing are different from the coordinates of the beginning of the first line 320 of the division block RD0_0 for reading first. ing. Here, an example will be described in which, in one frame, an area where read processing is performed is smaller than an area where write processing is performed.

  The difference in the horizontal direction between the access start coordinates in the write process and the access start coordinates in the read process is DIFX. The difference in the vertical direction between the access start coordinates in the write process and the access start coordinates in the read process is DIFY.

In such a case, for example, the first to third writing coordinates described above may be shifted by the difference amounts DIFX and DIFY of the access start coordinates. The first to third writing coordinates (H _W1 , V _W1 ) ', (H _W2 , V _W2 )', and (H _W3 , V _W3 ) 'shifted by the difference amount DIFX of access start coordinates and DIFY are And the following formulas (7) to (9). The access start coordinate in the read process is (1, 1). The write coordinates (H _W1 , V _W1 ) ′, (H _W2 , V _W2 ) ′, and (H _W3 , V _W3 ) ′ shifted by the difference amount DIFX of access start coordinates by DIFY are the write coordinate calculation unit 201. Calculated by
(H _W1 , V _W1 ) ′ = (H _W1 −DIFX, V _W1 −DIFY) (7)
(H _W2 , V _W2 ) ′ = (H _W2 −DIFX, V _W2 −DIFY) (8)
(H _W3 , V _W3 ) ′ = (H _W3 −DIFX, V _W3 −DIFY) (9)

Although the case where the first to third writing coordinates are shifted by the difference amounts DIFX and DIFY of access start coordinates has been described here as an example, the present invention is not limited to this. For example, the readout coordinates may be shifted by the difference amount DIFX, DIFY of the access start coordinates. The read coordinates (H _R , V _R ) ′ shifted by the difference amount DIFX of the access start coordinates and DIFY by the following equation (10) when the access start coordinates in the writing process are (1, 1) expressed. The read coordinate (H _R , V _R ) ′ shifted by the difference amount DIFX of the access start coordinate and DIFY is calculated by the read coordinate calculation unit 202.
(H _R , V _R ) ′ = (H _R + DIFX, V _R + DIFY) (10)
Thus, the access start coordinates in the write process may be different from the access start coordinates in the read process.

(Modification (Part 2))
An image processing apparatus and an image processing method according to a modification (part 2) of the present embodiment will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagram showing an aspect of block division in the present modification. A thick solid line in FIG. 9 conceptually shows a divided block for writing, and a thick broken line in FIG. 9 conceptually shows a divided block for reading.

  This modification shows the case where a part of adjacent divided blocks overlap. Here, even when adjacent blocks overlap, they are referred to as divided blocks. The overlap amount in the horizontal direction of the read divided blocks RD * _ * is OLX. The overlapping amount in the vertical direction of the read divided blocks RD * _ * is OLY.

In such a case, for example, when the divided block RD * _ * to be read is switched, the above-mentioned read coordinates may be shifted by the amount of overlap OLX, OLY. The readout coordinates (H _R , V _R ) ′ shifted by the amount of overlap OLX, OLY are expressed by the following equation (11). The read coordinate (H _R , V _R ) ′ shifted by the overlap amount OLX, OLY is calculated by the read coordinate calculation unit 202.
(H _R , V _R ) ′ = (H _R −OLX, V _R −OLY) (11)

  Thus, adjacent divided blocks may overlap. Here, although the case where adjacent divided blocks for reading RD * _ * overlap is described as an example, adjacent divided blocks for writing WR * _ * may be overlapped.

FIG. 10 conceptually shows a jump of access coordinates when the end of the divided block is reached. FIG. 10A shows a case where adjacent divided blocks 300 a to 300 c overlap in the horizontal direction. When access reaches the pixels 311 and 312 at the last coordinates (H ₂ , V ₂ ) of the divided blocks 300 a and 300 _b , as in the image processing apparatus according to the first embodiment described above with reference to FIG. The offset value is added to the address value. The offset value added here is (−XH × (YA−1) −OLX).

FIG. 10B shows a case where adjacent divided blocks 300 d to 300 i overlap in both the horizontal direction and the vertical direction. When access reaches the pixel 316 at the last coordinate (H ₃ , V ₃ ) of the block line 321 b, as in the image processing apparatus according to the first embodiment described above with reference to FIG. It is added to the value. The offset value to be added here is (−XH × OLY).

  In this way, parts of adjacent divided blocks may overlap. Also in this modification, it is possible to provide an image processing apparatus capable of appropriately performing chase control on the memory 112.

Second Embodiment
An image processing apparatus and an image processing method according to the second embodiment will be described with reference to FIGS. 11 to 16. The same members of the present embodiment as those of the image processing apparatus and the image processing method according to the first embodiment shown in FIGS. 1 to 10 are represented by the same reference numbers not to repeat or to simplify their explanation.

  The image processing apparatus 1100 according to the present embodiment includes a plurality of development processing units 109a and 109b, a plurality of WRDMACs 211a and 211b, and a plurality of writing coordinate calculation units 201a and 201b.

  FIG. 11 is a block diagram showing an image processing apparatus according to the present embodiment. As shown in FIG. 11, the image processing apparatus 1100 includes an image sensor 102, an A / D converter 103, a correction processor 104, a non-volatile memory 105, a non-volatile memory control unit 106, and an operation unit 107. have. The image processing apparatus 100 further includes a CPU 108, a display control unit 110, a display unit 111, a memory 112, a plurality of development processing units 109a and 109b, and a memory control unit 120a. The image processing apparatus 100 includes an imaging optical system 101. The imaging optical system 101 may be detachable from the body of the image processing apparatus 100 or may not be detachable.

  The development processing units 109a and 109b respectively perform resizing processing such as enlargement / reduction, compression / expansion processing, format conversion processing, development processing, distortion correction, and the like on the image data. The development processing unit 109a takes charge of processing for a predetermined area of the image data. The development processing unit 109 b takes charge of processing for an area of the image data that is different from the area handled by the development processing unit 109 a. The memory control unit 120 a writes the image data processed by the correction processing unit 104 or the development processing units 109 a and 109 b in the memory 112. Further, the memory control unit 120 a reads the image data written in the memory 112 and transmits the image data to the development processing units 1109 a and 1109 b and the like.

  The memory control unit 120a has a DMAC 210a and a chase control unit 200a. The DMAC 210a has a plurality of WRDMACs 211a and 211b. The configuration of the WRDMACs 211a and 211b is the same as the configuration of the WRDMAC 211 described above with reference to FIG. Also, the DMAC 210 a has an RDDMAC 213. The memory I / F 205 controls the memory 112 according to the control signal from the WRDMAC 211 a or 211 b or the control signal from the RDDMAC 213.

  When the write processing reaches the last pixels 301 to 309 (see FIG. 3) of the line 320, the first write offset signals WR_OFFSET1_a and WR_OFFSET1_b are generated by the WRDMACs 211a and 211b, respectively. When the read processing reaches the last pixels 301 to 309 of the line 320, the first read offset signal RD_OFFSET1 is generated by the RDDMAC 213, respectively. When the writing process reaches the end pixels 311, 312, 314, 315, 317, and 318 of the divided blocks 300a, 300b, 300d, 300e, 300g, and 300h, the following process is performed. That is, the second write offset signals WR_OFFSET2_a and WR_OFFSET2_b are generated by the WRDMACs 211a and 211b, respectively. When the read processing reaches the last pixels 311, 312, 314, 315, 317, and 318 of the divided blocks 300a, 300b, 300d, 300e, and 300h, a second read offset signal RD_OFFSET2 is generated. When the write processing reaches the last pixels 313 and 316 of the block lines 321a and 321b, third write offset signals WR_OFFSET3_a and WR_OFFSET3_b are generated by the WRDMACs 211a and 211b, respectively. When the read processing reaches the last pixels 313 and 316 of the block lines 321 a and 321 b, the third read offset signal RD_OFFSET 3 is generated by the RDDMAC 213.

The chase control unit 200a includes write coordinate calculation units 201a and 201b, a write coordinate integration unit (write coordinate specification unit) 1201, a read coordinate calculation unit 202, a coordinate comparison unit 203, and a read request mask unit 204. ing. The follow-up control unit 200a calculates write coordinates (H _{W1 _a} , V _{W1 _a} ) to (H _{W3 _a} , V _{W3 _a} ) described later based on the write offset signals WR_OFFSET1 _a to WR_OFFSET3 _a from the WRDMAC 211a. Further, the follow-up control unit 200a calculates write coordinates (H _{W1 _b} , V _{W1 _b} ) to (H _{W3 _b} , V _{W3 _b} ) described later based on the write offset signals WR_OFFSET1 _b to WR_OFFSET3 _b from the WRDMAC 211b. Further, the chase control unit 200a calculates the read coordinates based on the data transfer length signal RD_TRANS and the read offset signals RD_OFFSET1 to RD_OFFSET3 supplied from the RDDMAC 213. The chase control unit 200 appropriately masks the read request signal RD_REQ from the RDDMAC 213 based on the comparison result between the write coordinates and the read coordinates. The follow-up control is performed in which the RDDMAC 213 sequentially reads out the image data of the portion where the writing of the image data is completed by the WRDMAC 211a and 211b. Such chase control is performed by the chase control unit 200a.

  The WRDMACs 211a and 211b respectively include write address generation units 212a and 212b that generate memory addresses for writing data in the memory 112, that is, write addresses WADRS_a and WADRS_b. The configuration of the WRDMACs 211a and 211b is the same as the configuration of the WRDMAC 211 described above with reference to FIG. The write address generation units 212a and 212b can manage and control data transfer lengths and the like. The WRDMACs 211a and 211b each have a function of incrementing the write address WADRS. Therefore, the WRDMACs 211a and 211b can sequentially store image data in a predetermined address space on the memory 112. Also, the WRDMACs 211a and 211b can jump the access address as appropriate. Also, the WRDMACs 211a and 211b can sequentially write the image data of the divided blocks 1300a_a to 1300i_a and 1300a_b to 1300i_b (see FIG. 13) to the memory 112.

  FIG. 13 conceptually shows write access and read access performed in the present embodiment. FIG. 13 conceptually shows a virtual address space in the memory 112 so as to correspond to an image. As shown in FIG. 13, by dividing image data of one frame into six in the horizontal direction and into three in the vertical direction, 18 divided blocks 1300a_a to 1300i_a and 1300a_b to 1300i_b of rectangular shape are set.

  A divided block 1300a is configured by the divided block 1300a_a and the divided block 1300a_b on the right side of the divided block 1300a_a. A divided block 1300b is configured by the divided block 1300b_a on the right side of the divided block 1300a_b and the divided block 1300b_b on the right side of the divided block 1300b_a. A divided block 1300c is configured by the divided block 1300c_a on the right side of the divided block 1300b_b and the divided block 1300c_b on the right side of the divided block 1300c_a. A divided block 1300d is configured by the lower divided block 1300d_a of the divided block 1300a_a and the divided block 1300d_b on the right side of the divided block 1300d_a. A divided block 1300e is configured by the divided block 1300e_a on the right side of the divided block 1300d_b and the divided block 1300e_b on the right side of the divided block 1300e_a. A divided block 1300f is configured by the divided block 1300f_a on the right side of the divided block 1300e_b and the divided block 1300f_b on the right side of the divided block 1300f_a. A divided block 1300g is configured by the lower divided block 1300g_a of the divided block 1300d_a and the divided block 1300g_b on the right side of the divided block 1300g_a. A divided block 1300h is configured by the divided block 1300h_a on the right side of the divided block 1300g_b and the divided block 1300h_b on the right side of the divided block 1300h_a. A divided block 1300i is configured by the divided block 1300i_a on the right side of the divided block 1300h_b and the divided block 1300i_b on the right side of the divided block 1300i_a.

  The number of pixels (size) in the horizontal direction of the divided blocks 1300a_a, 1300d_a, and 1300g_a is XA. The number of pixels in the horizontal direction of the divided blocks 1300a_b, 1300d_b, and 1300g_b is XA. The number of pixels in the horizontal direction of the divided blocks 1300a, 1300d, and 1300g is XA '. The number of pixels in the horizontal direction of the divided blocks 1300b_a, 1300e_a, and 1300h_a is XB. The number of pixels in the horizontal direction of the divided blocks 1300b_b, 1300e_b, and 1300h_b is XB. The number of pixels in the horizontal direction of the divided blocks 1300b, 1300e, and 1300h is XB '. The number of pixels in the horizontal direction of the divided blocks 1300c_a, 1300f_a, and 1300i_a is XC. The number of pixels in the horizontal direction of the divided blocks 1300 c_b, 1300 f_b, and 1300 i_b is XC. The number of pixels in the horizontal direction of the divided blocks 1300c, 1300f, and 1300i is XC '.

  The number of lines (number of pixels) in the vertical direction of the divided blocks 1300a to 1300c is YA, the number of lines in the vertical direction of the divided blocks 1300d to 1300f is YB, and the number of lines in the vertical direction of the divided blocks 1300g to 1300i is YC.

  Here, YA = 4, YB = 4, and YC = 6 are set in order to simplify the description, but the number of lines in the vertical direction is actually much larger than these values. Further, the number of pixels in the horizontal direction of one frame is assumed to be XH (= XA '+ XB' + XC '). The number of pixels XA to XC, the number of lines YA to YC, the offset value, and the like are input in advance from the CPU 108 to the calculation unit 701 of the DMAC 210a and the address addition value calculation unit 702. Then, these values are stored in advance in a register (not shown) provided in the calculation unit 701 and the address addition value calculation unit 702.

  The image data of the divided blocks 1300a_a, 1300b_a, 1300c_a, 1300d_a, 1300e_a, 1300f_a, 1300g_a, 1300h_a, and 1300i_a are written to the memory 112 by the WRDMAC 211a. Here, when describing each of these divided blocks, reference numerals 1300a_a to 1300i_a will be used, and when describing these divided blocks in general, reference numeral 1300 * _a will be used. Writing of the image data of the divided blocks 1300a_b, 1300b_b, 1300c_b, 1300d_b, 1300e_b, 1300f_b, 1300g_b, 1300h_b and 1300i_b into the memory 112 is performed by the WRDMAC 211b. Here, when describing each of these divided blocks, reference numerals 1300a_b to 1300i_b will be used, and when describing these divided blocks in general, reference numeral 1300 * _b will be used. Further, when describing each of the divided blocks 1300a to 1300i, reference numerals 1300a to 1300i will be used, and when describing these divided blocks in general, reference numeral 1300 will be used. The solid arrows in FIG. 13 conceptually indicate a jump of coordinates in the process performed by the WRDMAC 211a, that is, an address jump. The broken arrow in FIG. 13 conceptually shows a jump of coordinates in the process performed by the WRDMAC 211b, that is, an address jump. By appropriately setting the offset value, processing can be shared by the plurality of WRDMACs 211a and 211b.

  Each divided block 1300 * _a, 1300 * _b includes a plurality of lines 320, respectively. Further, a block line 1321a is configured by the plurality of divided blocks 1300a to 1300c, and a block line 1321b is configured by the plurality of divided blocks 1300d to 1300f. Further, a block line 1321 c is configured by the plurality of divided blocks 1300 g to 1300 i. When describing individual block lines, reference numerals 1321a to 1321c will be used, and when describing block lines in general, reference numeral 1321 will be used.

  The image data of the divided block 1300a_a is written to the memory 112 by the WRDMAC 211a. Further, the image data of the divided block 1300a_b is written to the memory 112 by the WRDMAC 211b. After the writing of the image data of the divided block 1300a_a is completed, the image data of the divided block 1300b_a is written to the memory 112 by the WRDMAC 211a. After the writing of the image data of the divided block 1300a_b is completed, the image data of the divided block 1300b_b is written to the memory 112 by the WRDMAC 211b. After the writing of the image data of the divided block 1300b_a is completed, the image data of the divided block 1300c_a is written to the memory 112 by the WRDMAC 211a. After the writing of the image data of the divided block 1300b_b is completed, the image data of the divided block 1300c_b is written to the memory 112 by the WRDMAC 211b. As described above, the WRDMAC 211a sequentially writes the image data of the divided blocks 1300a_a, 1300b_a, and 1300c_a located in the first block line 1321a into the memory 112. The WRDMAC 211b sequentially writes the image data of the divided blocks 1300a_b, 1300b_b, and 1300c_b located in the first block line 1321a into the memory 112.

  After the writing of the image data of the divided blocks 1300a_a, 1300b_a, 1300c_a of the first block line 1321a is completed, the following processing is performed. That is, the writing of the image data of the divided blocks 1300 d — a, 1300 e — a and 1300 f — a of the second block line 1321 b is sequentially performed by the WRDMAC 211 a. Further, after the writing of the image data of the divided blocks 1300a_b, 1300b_b, and 1300c_b of the first block line 1321a is completed, the following processing is performed. That is, the writing of the image data of the divided blocks 1300 d_b, 1300 e_b, and 1300 f_b of the second block line 1321 b is sequentially performed by the WRDMAC 211 b.

  After the writing of the image data of the divided blocks 1300 d — a, 1300 e — a, and 1300 f — a of the second block line 1321 b is completed, the following processing is performed. That is, the writing of the image data of the divided blocks 1300 g — a, 1300 h — a, and 1300 i — a of the third block line 1321 c is sequentially performed by the WRDMAC 211 a. Further, after the writing of the image data of the divided blocks 1300 d_b, 1300 e_b, and 1300 f_b of the second block line 1321 b is completed, the following processing is performed. That is, the WRDMAC 211b sequentially writes the image data of the divided blocks 1300g_b, 1300h_b, and 1300i_b of the third block line 1321c.

  Thus, writing of the image data of all the divided blocks 1300a to 1300i to the memory 112 is sequentially performed. Here, the write access is described as an example, but the read access is similarly performed.

  The order of the write access is more specifically described below. Images of nine divided blocks 1300a_a to 1300i_a are sequentially written to the memory 112 by the WRDMAC 211a as follows. First, writing of the image data of the divided block 1300a_a to the memory 112 is performed by the WRDMAC 211a as follows. That is, the image data of the first line 320 of the divided block 1300a_a is written to the memory 112 according to the address value issued by the write address generation unit 212a. When the data transfer length in one write access is equal to the data length corresponding to one line 320, the writing on line 320 is completed by one write access. On the other hand, when the data transfer length in one write access is shorter than the data length corresponding to one line 320, the write on line 320 is completed by a plurality of write accesses.

  After the writing of the image data of the first line 320 of the divided block 1300a_a is completed, the writing of the image data of the second line 320 of the divided block 1300a_a is performed by the WRDMAC 211a. The last coordinate of the first line 320 of the divided block 1300a_a is (XA, 1), and the first coordinate of the second line 320 of the divided block 1300a_a is (1, 2). The memory address corresponding to coordinate (1, 2) is not the memory address next to the memory address corresponding to coordinate (XA, 1). Therefore, when shifting from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. Specifically, when the writing process reaches the last coordinate (XA, 1) of the first line 320 of the divided block 1300a_a, the offset value is added to the address value by the address addition value calculation unit 702. That is, the jump of the access address is performed by adding the value corresponding to the data transfer length and the offset value to the current address value. The offset value to be added here is (XH-XA).

  After this, the writing of the image data of the divided block 1300a_a is sequentially performed by the WRDMAC 211a. The offset value is added to the address value each time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300 a — a. Thereby, the image data of the divided block 1300a_a is sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 1300a_a to the memory 112 is completed, the writing of the image data of the divided block 1300b_a is performed by the WRDMAC 211a. The coordinates of the last pixel of the YAth line 320, which is the last line 320 of the divided block 1300a_a, that is, the coordinates of the last pixel of the divided block 1300a_a, is (XA, YA). On the other hand, the coordinates of the beginning of the first line 320 of the divided block 1300b_a, that is, the coordinates of the beginning of the divided block 1300b_a, are (XA '+ 1, 1). The memory address corresponding to the coordinate (XA '+ 1, 1) is not the memory address next to the memory address corresponding to the coordinate (XA, YA). Therefore, when shifting from the writing of the image data of the divided block 1300a_a to the writing of the image data of the divided block 1300b_a, a jump of the access address is performed. Specifically, when the writing process reaches the end coordinates of the divided block 1300a_a, the offset value is added to the address value. That is, the jump of the access address is performed by adding the address value and the offset value to the address value according to the data transfer length. The offset value to be added here is (−XH × (YA−1) + XA). A jump is made from the memory address corresponding to the coordinates (XA, YA) to the memory address corresponding to the coordinates (XA '+ 1, 1). Since the offset value is negative, the vertical address returns from YA to 1. Writing of the image data of the first line 320 of the divided block 1300b_a is performed by the WRDMAC 211a. After the writing of the image data of the first line 320 of the divided block 1300b_a is completed, the writing of the image data of the second line 320 of the divided block 1300b_a is performed by the WRDMAC 211a. The last coordinate of the first line 320 of the divided block 1300b_a is (XA '+ XB, 1), and the first coordinate of the second line 320 of the divided block 1300b_a is (XA' + 1, 2) . Therefore, when shifting from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. That is, when the writing process reaches the last coordinate of the first line 320 of the divided block 1300b_a, the offset value is added to the address value. The offset value added here is (XH−XB). After that, the writing of the image data of the divided block 1300b_a is sequentially performed by the WRDMAC 211a. The offset value is added to the address value each time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300 b — a. As a result, while the access address is sequentially jumped, the writing of the image data of the divided block 1300b_a is sequentially performed by the WRDMAC 211a.

  After the writing of the image data of the divided block 1300b_a to the memory 112 is completed, the writing of the image data of the divided block 1300c_a is performed by the WRDMAC 211a. The coordinate of the end of divided block 1300b_a is (XA '+ XB, YA), and the coordinate of the head of the first line 320 of divided block 1300c_a is (XA' + XB '+ 1, 1). The memory address corresponding to the coordinate (XA '+ XB' + 1, 1) is not the next memory address of the memory address corresponding to the coordinate (XA '+ XB, YA). Therefore, when transitioning from the writing of the image data of the divided block 1300b_a to the writing of the image data of the divided block 1300c_a, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the end coordinates of the divided block 1300b_a. That is, the jump of the access address is performed by adding the value according to the data transfer length and the offset value to the address value. The offset value to be added here is (−XH × (YA−1) + XB). The memory address corresponding to the coordinates (XA '+ XB, YA) jumps to the memory address corresponding to the coordinates (XA' + XB '+ 1, 1). Since the offset value is negative, the vertical address returns from YA to 1. Writing of the image data of the first line 320 of the divided block 1300c_a is performed by the WRDMAC 211a.

  After the writing of the image data of the first line 1320 of the divided block 1300c_a is completed, the writing of the image data of the second line 320 of the divided block 1300c_a is performed by the WRDMAC 211a. The coordinate of the end of the first line 320 of the divided block 1300c_a is (XA '+ XB' + XC, 1), and the coordinate of the beginning of the second line 320 of the divided block 1300c_a is (XA '+ XB' + 1, 2). Therefore, when shifting from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. That is, when the writing process reaches the last coordinate of the divided block 1300c_a, the offset value is added to the address value. The offset value to be added here is (XH-XC). Thereafter, the writing of the image data of the divided block 1300c_a is sequentially performed by the WRDMAC 211a. The offset value is added to the address value each time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300c_a. As a result, while the access address is sequentially jumped, the writing of the image data of the divided block 1300 c_a is sequentially performed by the WRDMAC 211 a.

  After the writing of the image data of the divided block 1300c_a into the memory 112 is completed, the writing of the image data of the divided block 1300d_a is performed by the WRDMAC 211a. The coordinates of the tail end of the divided block 1300c_a is (XA '+ XB' + XC, YA), and the coordinates of the head of the first line 320 of the divided block 1300d_a is (1, YA + 1). The memory address corresponding to the coordinate (1, YA + 1) is not the next memory address of the memory address corresponding to the coordinate (XA '+ XB' + XC, YA). Therefore, when shifting from the writing of the image data of the divided block 1300c_a to the writing of the image data of the divided block 1300d_a, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the end coordinates of the divided block 1300c_a. That is, the jump of the access address is performed by adding the value according to the data transfer length and the offset value to the address value. The offset value added here is XC. After that, the writing of the image data of the divided block 1300d_a is sequentially performed by the WRDMAC 211a. Every time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300d_a, the offset value, that is, (XH−XA) is added to the address value. Thereby, while the access address is sequentially jumped, the writing of the image data of the divided block 1300 d — a is sequentially performed by the WRDMAC 211 a.

  After the writing of the image data of the divided block 1300d_a into the memory 112 is completed, the writing of the image data of the divided block 1300e_a is performed by the WRDMAC 211a. At the transition from the writing of the image data of the divided block 1300d_a to the writing of the image data of the divided block 1300e_a, the offset value is added to the address value. The offset value to be added here is (−XH × (YB−1) + XA). Thus, the process shifts from the writing of the image data of the divided block 1300d_a to the writing of the image data of the divided block 1300e_a. Then, the writing of the image data of the divided block 1300e_a is sequentially performed by the WRDMAC 211a. Every time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300e_a, the offset value, that is, (XH−XB) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300 e_a is sequentially performed by the WRDMAC 211 a.

  After the writing of the image data of the divided block 1300e_a to the memory 112 is completed, the writing of the image data of the divided block 1300f_a is performed by the WRDMAC 211a. At the transition from the writing of the image data of the divided block 1300e_a to the writing of the image data of the divided block 1300f_a, the offset value is added to the address value. The offset value to be added here is (−XH × (YB−1) + XB). Thus, the process shifts from the writing of the image data of the divided block 1300e_a to the writing of the image data of the divided block 1300f_a. Thereafter, writing of the image data of the divided block 1300 f — a is sequentially performed by the WRDMAC 211 a. Every time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300 f — a, the offset value, that is, (XH−XC) is added to the address value. As a result, while the access address is sequentially jumped, the writing of the image data of the divided block 1300f_a is sequentially performed by the WRDMAC 211a.

  After the writing of the image data of the divided block 1300 f — a into the memory 112 is completed, the writing of the image data of the divided block 1300 g — a is performed by the WRDMAC 211 a. The coordinates of the tail end of the divided block 1300f_a are (XA '+ XB' + XC, YA + YB), and the coordinates of the head of the first line 320 of the divided block 1300g_a is (1, YA + YB + 1). The memory address corresponding to the coordinate (1, YA + YB + 1) is not the memory address next to the memory address corresponding to the coordinate (XA '+ XB' + XC, YA + YB). Therefore, when shifting from the writing of the image data of the divided block 1300 f — a to the writing of the image data of the divided block 1300 g — a, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 1300 f — a. That is, the jump of the access address is performed by adding the value according to the data transfer length and the offset value to the address value. The offset value added here is XC. After that, the writing of the image data of the divided block 1300g_a is sequentially performed by the WRDMAC 211a. Every time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300g_a, the offset value, that is, (XH-XA) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300g_a is sequentially performed by the WRDMAC 211a.

  After the writing of the image data of the divided block 1300g_a to the memory 112 is completed, the writing of the image data of the divided block 1300h_a is performed by the WRDMAC 211a. When shifting from the writing of the image data of the divided block 1300g_a to the writing of the image data of the divided block 1300h_a, the offset value is added to the address value. The offset value to be added here is (−XH × (YC−1) + XA). Thus, the process shifts from the writing of the image data of the divided block 1300g_a to the writing of the image data of the divided block 1300h_a. Thereafter, writing of the image data of the divided block 1300h_a is sequentially performed by the WRDMAC 211a. Every time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300h_a, the offset value, that is, (XH−XB) is added to the address value. Thus, the WRDMAC 211a sequentially writes the image data of the plurality of lines 320 of the divided block 1300h_a while sequentially jumping the access address.

  After the writing of the image data of the divided block 1300h_a to the memory 112 is completed, the writing of the image data of the divided block 1300i_a is performed by the WRDMAC 211a. At the transition from the writing of the image data of the divided block 1300h_a to the writing of the image data of the divided block 1300i_a, the offset value is added to the address value. The offset value added here is (−XH × (YC−1) + XB). Thus, the process shifts from the writing of the image data of the divided block 1300h_a to the writing of the image data of the divided block 1300i_a. Thereafter, writing of the image data of the divided block 1300i_a is sequentially performed by the WRDMAC 211a. Every time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300i_a, the offset value (XH−XC) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300i_a is sequentially performed by the WRDMAC 211a.

  By the process as described above, images of nine divided blocks 1300 a — a to 1300 i — a are sequentially written to the memory 112 by the WRDMAC 211 a.

  On the other hand, images of nine divided blocks 1300a_b to 1300i_b are sequentially written to the memory 112 by the WRDMAC 211b as follows. First, writing of the image data of the divided block 1300a_b to the memory 112 is performed by the WRDMAC 211b as follows. That is, the image data of the first line 320 of the divided block 1300a_b is written to the memory 112 according to the address value issued by the write address generation unit 212b. The first coordinate of the first line 320 of the divided block 1300a_b is (XA + 1, 1), and the last coordinate of the first line 320 of the divided block 1300a_b is (XA ′, 1). When the data transfer length in one write access is equal to the data length corresponding to one line 320, the writing on line 320 is completed by one write access. On the other hand, when the data transfer length in one write access is shorter than the data length corresponding to one line 320, the write on line 320 is completed by a plurality of write accesses.

  After the writing of the image data of the first line 320 of the divided block 1300a_b is completed, the writing of the image data of the second line 320 of the divided block 1300a_b is performed by the WRDMAC 211b. The last coordinate of the first line 320 of the divided block 1300a_b is (XA ', 1), and the first coordinate of the second line 320 of the divided block 1300a_b is (XA + 1, 2). The memory address corresponding to the coordinate (XA + 1, 2) is not the memory address next to the memory address corresponding to the coordinate (XA ′, 1). Therefore, when shifting from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. Specifically, when the writing process reaches the last coordinate of the first line 320 of the divided block 1300a_b, the offset value is added to the address value by the address addition value calculation unit 702. That is, the jump of the access address is performed by adding the value corresponding to the data transfer length and the offset value to the current address value. The offset value to be added here is (XH-XA).

  After this, the writing of the image data of the divided block 1300a_b is sequentially performed by the WRDMAC 211b. The offset value is added to the address value each time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300a_b. As a result, the image data of the divided blocks 1300a_b are sequentially written while sequentially jumping the access address.

  After the writing of the image data of the divided block 1300a_b to the memory 112 is completed, the writing of the image data of the divided block 1300b_b is performed by the WRDMAC 211b. The coordinates of the last pixel of the YAth line 320, which is the last line 320 of the divided block 1300a_b, that is, the coordinates of the last pixel of the divided block 1300a_b, is (XA ', YA). On the other hand, the coordinates of the beginning of the first line 320 of the divided block 1300b_b, that is, the coordinates of the beginning of the divided block 1300b_b, are (XA '+ XB + 1, 1). The memory address corresponding to the coordinate (XA '+ XB + 1, 1) is not the memory address next to the memory address corresponding to the coordinate (XA', YA). Therefore, when shifting from the writing of the image data of the divided block 1300a_b to the writing of the image data of the divided block 1300b_b, a jump of the access address is performed. Specifically, when the writing process reaches the last coordinate of divided block 1300a_b, the offset value is added to the address value. That is, the jump of the access address is performed by adding the value according to the data transfer length and the offset value to the address value. The offset value to be added here is (−XH × (YA−1) + XB). The memory address corresponding to the coordinates (XA ', YA) jumps to the memory address corresponding to the coordinates (XA' + XB + 1, 1). Since the offset value is negative, the vertical address returns from YA to 1. Thus, the access address jumps, and the writing of the image data of the first line 320 of the divided block 1300b_b is performed by the WRDMAC 211b. After the writing of the image data of the first line 320 of the divided block 1300b_b is completed, the writing of the image data of the second line 320 of the divided block 1300b_b is performed by the WRDMAC 211b. The last coordinate of the first line 320 of the divided block 1300b_b is (XA '+ XB', 1), and the coordinate of the top of the second line 320 of the divided block 1300b_b is (XA '+ XB + 1, 2) is there. Therefore, when transitioning from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. That is, when the writing process reaches the last coordinate of the first line 320 of the divided block 1300b_b, the offset value is added to the address value. The offset value added here is (XH−XB). After this, the writing of the image data of the divided block 1300b_b is sequentially performed by the WRDMAC 211b. The offset value is added to the address value each time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300 b — b. As a result, while the access address is sequentially jumped, the writing of the image data of the divided block 1300b_b is sequentially performed by the WRDMAC 211b.

  After the writing of the image data of the divided block 1300b_b to the memory 112 is completed, the writing of the image data of the divided block 1300c_b is performed by the WRDMAC 211b. The coordinate of the end of divided block 1300b_b is (XA '+ XB', YA), and the coordinate of the beginning of the first line 320 of divided block 1300c_b is (XA '+ XB' + XC + 1, 1). The memory address corresponding to the coordinate (XA '+ XB' + XC + 1,1) is not the next memory address of the memory address corresponding to the coordinate (XA '+ XB', YA). Therefore, when shifting from the writing of the image data of the divided block 1300b_b to the writing of the image data of the divided block 1300c_b, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 1300b_b. That is, the memory address corresponding to the coordinates (XA ′ + XB ′, YA) corresponds to the coordinates (XA ′ + XB ′ + XC + 1, 1) by adding the value corresponding to the data transfer length and the offset value to the address value. The access address jumps to the memory address. The offset value added here is (−XH × (YA−1) + XC). Because the offset value is negative, the vertical address is returned. Thus, the access address jumps and writing of the image data of the first line 320 of the divided block 1300c_b is performed by the WRDMAC 211b.

  After the writing of the image data of the first line 320 of the divided block 1300c_b is completed, the writing of the image data of the second line 320 of the divided block 1300c_b is performed by the WRDMAC 211b. The last coordinate of the first line 320 of the divided block 1300 c_b is (XA ′ + XB ′ + XC ′, 1), and the coordinate of the beginning of the second line 320 of the divided block 1300 c_b is (XA ′ + XB ′ + XC + 1 , 2). Therefore, when transitioning from the writing of the image data of the first line 320 to the writing of the image data of the second line 320, a jump of the access address is performed. That is, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 1300 c_b. The offset value to be added here is (XH-XC). Thereafter, the image data of the divided block 1300 c_b is sequentially written by the WRDMAC 211 b. The offset value is added to the address value each time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300c_b. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300 c_b is sequentially performed by the WRDMAC 211 b.

  After the writing of the image data of the divided block 1300c_b into the memory 112 is completed, the writing of the image data of the divided block 1300d_b is performed by the WRDMAC 211b. The coordinates of the tail end of divided block 1300 c_b are (XA ′ + XB ′ + XC ′, YA). On the other hand, the top coordinates of the first line 320 of the divided block 1300d_b are (XA + 1, YA + 1). The memory address corresponding to the coordinates (XA + 1, YA + 1) is not the memory address next to the memory address corresponding to the coordinates (XA '+ XB' + XC ', YA). Therefore, when shifting from the writing of the image data of the divided block 1300 c_b to the writing of the image data of the divided block 1300 d_b, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 1300 c_b. That is, the jump of the access address is performed by adding the value according to the data transfer length and the offset value to the address value. The offset value added here is XA. Thereafter, writing of the image data of the divided block 1300d_b is sequentially performed by the WRDMAC 211b. Every time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of the divided block 1300d_b, the offset value, that is, (XH-XA) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300d_b is sequentially performed by the WRDMAC 211b.

  After the writing of the image data of the divided block 1300d_b into the memory 112 is completed, the writing of the image data of the divided block 1300e_b is performed by the WRDMAC 211b. At the transition from the writing of the image data of the divided block 1300 d_b to the writing of the image data of the divided block 1300 e_b, the offset value is added to the address value. The offset value to be added here is (−XH × (YB−1) + XB). Thus, the process shifts from the writing of the image data of the divided block 1300d_b to the writing of the image data of the divided block 1300e_b. Then, writing of the image data of the divided block 1300e_b is sequentially performed by the WRDMAC 211b. Every time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of divided block 1300e_b, the offset value, that is, (XH-XB) is added to the address value. As a result, while the access address is sequentially jumped, the writing of the image data of the divided block 1300e_b is sequentially performed by the WRDMAC 211b.

  After the writing of the image data of the divided block 1300e_b into the memory 112 is completed, the writing of the image data of the divided block 1300f_b is performed by the WRDMAC 211b. When shifting from the writing of image data of divided block 1300e_b to the writing of image data of divided block 1300f_b, the offset value is added to the address value. The offset value to be added here is (−XH × (YB−1) + XC). Thus, the process shifts from the writing of the image data of the divided block 1300e_b to the writing of the image data of the divided block 1300f_b. After this, the writing of the image data of the divided block 1300 f — b is sequentially performed by the WRDMAC 211 b. Every time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300 f — b, the offset value, that is, (XH−XC) is added to the address value. As a result, while the access address is sequentially jumped, the writing of the image data of the divided block 1300f_b is sequentially performed by the WRDMAC 211b.

  After the writing of the image data of the divided block 1300 f — b into the memory 112 is completed, the writing of the image data of the divided block 1300 g — b is performed by the WRDMAC 211 b. The coordinates of the tail end of the divided block 1300f_b are (XA '+ XB' + XC ', YA + YB), and the coordinates of the head of the first line 320 of the divided block 1300g_b are (XA + 1, YA + YB + 1). The memory address corresponding to the coordinates (XA + 1, YA + YB + 1) is not the memory address next to the memory address corresponding to the coordinates (XA ′ + XB ′ + XC ′, YA + YB). Therefore, when shifting from the writing of the image data of the divided block 1300 f — b to the writing of the image data of the divided block 1300 g — b, a jump of the access address is performed. Specifically, the offset value is added to the address value when the writing process reaches the last coordinate of the divided block 1300 f — b. That is, the jump of the access address is performed by adding the value according to the data transfer length and the offset value to the address value. The offset value added here is XA. Thereafter, the writing of the image data of the divided block 1300g_b is sequentially performed by the WRDMAC 211b. Every time the writing process reaches the pixel at the last coordinate of each line 320 except the last line 320 of divided block 1300g_b, an offset value, that is, (XH-XA) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300g_b is sequentially performed by the WRDMAC 211b.

  After the writing of the image data of the divided block 1300g_b to the memory 112 is completed, the writing of the image data of the divided block 1300h_b is performed by the WRDMAC 211b. At the transition from the writing of the image data of divided block 1300 g_b to the writing of the image data of divided block 1300 h_b, the offset value is added to the address value. The offset value added here is (−XH × (YC−1) + XB). Thus, the process shifts from the writing of the image data of the divided block 1300 g_b to the writing of the image data of the divided block 1300 h_b. After this, the writing of the image data of the divided block 1300h_b is sequentially performed by the WRDMAC 211b. Each time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300h_b, the offset value, that is, (XH−XB) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300h_b is sequentially performed by the WRDMAC 211b.

  After the writing of the image data of the divided block 1300h_b into the memory 112 is completed, the writing of the image data of the divided block 1300i_b is performed by the WRDMAC 211b. At the transition from the writing of the image data of the divided block 1300h_b to the writing of the image data of the divided block 1300i_b, the offset value is added to the address value. The offset value added here is (−XH × (YC−1) + XC). Thus, the process shifts from the writing of the image data of the divided block 1300h_b to the writing of the image data of the divided block 1300i_b. Thereafter, the writing of the image data of the divided block 1300i_b is sequentially performed by the WRDMAC 211b. Every time the writing process reaches the last pixel of each line 320 except the last line 320 of the divided block 1300i_b, the offset value, that is, (XH−XC) is added to the address value. Thus, while the access address is sequentially jumped, the writing of the image data of the divided block 1300i_b is sequentially performed by the WRDMAC 211b.

  By the process as described above, the images of nine divided blocks 1300a_b to 1300i_b are sequentially written to the memory 112 by the WRDMAC 211b.

  Note that the read processing performed in the present embodiment is performed by one RDDMAC 213. The readout process performed in the present embodiment is the same as the readout process described above in the first embodiment, and thus the description will be omitted.

  Next, signals input / output between the DMAC 210a, the memory I / F 205, and the chase control unit 200a will be described with reference to FIG.

  As shown in FIG. 12, write request signals WR_REQ_a and WR_REQ_b output from the WRDMACs 211 a and 211 b included in the DMAC 210 a are input to the memory I / F 205. The write request signals WR_REQ_a and WR_REQ_b are signals for requesting the memory I / F 205 to write image data to the memory 112. The write request signals WR_REQ_a and WR_REQ_b are issued, for example, when the following occurs. That is, when the WRDMACs 211 a and 211 b receive image data of one line 320 or a part thereof from the correction processing unit 104 and can transmit image data of the one line 320 or a part thereof to the memory I / F 205 Issued to

  The acknowledge signals WR_ACK_a and WR_ACK_b output in a pulse form from the memory I / F 205 are input to the WRDMACs 211a and 211b, respectively. The acknowledge signals WR_ACK_a and WR_ACK_b are output, for example, when the following occurs. That is, the memory I / F 205 receives the write request signals WR_REQ_a and WR_REQ_b from the WRDMAC 211 a and 211 b and is output when the memory I / F 205 can receive the write data WR_DATA_a and WR_DATA_b. After receiving the acknowledge signals WR_ACK_a and WR_ACK_b respectively, the WRDMACs 211a and 211b perform the following processing. That is, the WRDMACs 211 a and 211 b write write data WR_DATA_a and WR_DATA_b, which are image data of, for example, one line 320 or a part thereof, in the memory 112 via the memory I / F 205. After receiving the acknowledge signals WR_ACK_a and WR_ACK_b, the write address generation units 212a and 212b increment the address value in preparation for the next write, and add various offset values to the address value as necessary.

  The read request signal RD_REQ from the RDDMAC 213 provided in the DMAC 210 a is input to the read coordinate calculation unit 202 and the read request mask unit 204 of the chase control unit 200 a. The read request signal RD_REQ is a signal for requesting the memory I / F 205 to read image data from the memory 112. The read request signal RD_REQ is input to the memory I / F 205 as a read request signal RD_REQ_MASK_OUT through the read request mask unit 204. The read request signal RD_REQ is issued, for example, when the RDDMAC 213 can receive image data of one line 320 or a part thereof.

  The acknowledge signal RD_ACK output in a pulse form from the memory I / F 205 is input to the RDDMAC 213. The acknowledge signal RD_ACK is output, for example, when the memory I / F 205 receives the read request signal RD_REQ_MASK_OUT and the memory I / F 205 can transmit the read data RD_DATA. After receiving the acknowledge signal RD_ACK, the RDDMAC 213 reads read data RD_DATA, which is image data of one line 320 or a part thereof, for example, from the memory 112 via the memory I / F 205. The RDDMAC 213 transmits the read data RD_DATA read from the memory 112 to the development processing units 109a and 109b. After receiving the acknowledge signal RD_ACK, the read address generation unit 214 increments the address value in preparation for the next read, and adds various offset values to the address value as necessary.

  As described above, after receiving the acknowledge signal WR_ACK, the write address generation units 212a and 212b increment the address value in preparation for the next write, and add various offset values to the address value as necessary. When the offset value is added to the address value, the write offset signals WR_OFFSET1_a to WR_OFFSET3_a are issued by the WRDMAC 211a. When the offset value is added to the address value, the write offset signals WR_OFFSET1_b to WR_OFFSET3_b are issued by the WRDMAC 211b.

  The write offset signals WR_OFFSET1_a to WR_OFFSET3_a issued by the WRDMAC 211a are input to the write coordinate calculation unit 201a and the write coordinate integration unit 1201 of the chase control unit 200. The write offset signals WR_OFFSET1_b to WR_OFFSET3_b issued by the WRDMAC 211b are input to the write coordinate calculation unit 201b and the write coordinate integration unit 1201 of the chase control unit 200a.

The writing coordinate calculation unit 201a performs the following processing based on the writing offset signals WR_OFFSET1_a to WR_OFFSET3_a. That is, the write coordinate calculating unit 201a calculates first through third write coordinates _{(H W1_a, V W1_a)} indicating whether it has reached the writing process is far _{~ (H W3_a, V} W3_a), respectively. The writing coordinate calculation unit 201b performs the following processing based on the writing offset signals WR_OFFSET1_b to WR_OFFSET3_b. That is, the write coordinate calculating unit 201b calculates first through third write coordinates _{(H W1_b, V W1_b)} indicating whether it has reached the writing process is far _{~ (H W3_b, V} W3_b), respectively. The first writing coordinates (H _{W1 _a} , V _{W1 _a} ) and (H _{W1 _b} , V _{W1 _b} ) are respectively obtained when the writing processing reaches the last pixel of the line 320 excluding the last line 320 in the divided block 1300 It will be updated. The first writing coordinates (H _{W1 — a} , V _{W1 — a} ) and (H _{W1 — b} , V _{W1 — b} ) indicate the coordinates of the last pixel of the line 320 excluding the last line 320 of the lines 320 for which the writing process has been completed. The second writing coordinates (H _{W2 _a} , V _{W2 _a} ) are updated when the writing processing reaches the last pixel of the divided block 1300 * _a excluding the last of the plurality of divided blocks 1300 * _{_} of the block line 1321 Be done. The second writing coordinates (H _{W2 _ b} , V _{W2 _ b} ) are updated when the writing processing reaches the last pixel of the divided block 1300 * _{_ b} excluding the last of the plurality of divided blocks 1300 * _{_ b} of the block line 1321 Be done. The second writing coordinates (H _{W2 _a} , V _{W2 _a} ) indicate the coordinates of the last pixel of the last divided block of the divided blocks 1300 * _a for which the writing process has been completed. The second writing coordinates (H _{W2 _ b} , V _{W2 _ b} ) indicate the coordinates of the last pixel of the last divided block of the divided blocks 1300 * _{_b} for which the writing process has been completed. The third writing coordinates (H _{W3 _a} , V _{W3 _a} ), (H _{W3 _b} , V _{W3 _b} ) are _{written to} the last pixel of the block line 1321 excluding the last block line 1321 among the plurality of block lines 1321 It will be updated when you The third writing coordinates (H _{W3 — a} , V _{W3 — a} ) and (H _{W3 — b} , V _{W — 13 b} ) indicate the coordinates of the last pixel of the block line 1321 for which the writing process has been completed. The various write offset signals WR_OFFSET1_a to WR_OFFSET3_a generated from the WRDMAC 211a are output to the High level in synchronization with the write request signal WR_REQ_a. In addition, various write offset signals WR_OFFSET1_b to WR_OFFSET3_b generated from the WRDMAC 211b are output to the High level in synchronization with the write request signal WR_REQ_b.

  As described above, the writing coordinate calculation units 201a and 201b calculate writing coordinates indicating the position of the line 320 in which writing has been completed among the plurality of blocks 320 included in the image, as writing coordinate calculation means for calculating based on the writing offset signal. It can work. The writing coordinate calculation units 201a and 201b update the writing coordinates each time the writing of the plurality of blocks 320 included in the image of one frame is completed. The read coordinate calculation unit 202 can function as a read coordinate calculation unit that calculates read coordinates indicating the end of the part to be read based on the read offset signal and the data transfer length signal.

As described above, after receiving the acknowledge signal RD_ACK, the read address generation unit 214 increments the address value in preparation for the next read, and adds the offset value to the address value as necessary. When the offset value is added to the address value, read offset signals RD_OFFSET1 to RD_OFFSET3 are issued by RDDMAC 213. The read offset signals RD_OFFSET1 to RD_OFFSET3 issued by the RDDMAC 213 are input to the read coordinate calculation unit 202 of the chase control unit 200. Reading coordinate calculation unit 202, then read request signal RD_REQ_MASK_OUT calculates the read coordinates indicating coordinates of the last pixel in the interesting portions of the reading process when it becomes High level _{(H R, V} R). The read coordinate calculation unit 202 calculates read coordinates based on the read offset signals RD_OFFSET1 to RD_OFFSET3 and the data transfer length signal RD_TRANS.

Reading coordinate calculation unit 202 increases the value of the amount corresponding _{H R} of the data transfer length indicated by the data transfer length signal RD_TRANS. Increased when receiving a read offset signal RD_OFFSET1 reads coordinate calculation unit 202, an amount corresponding with decreasing the value of _{H R} horizontal size of the divided blocks 1300 (number of pixels), the value of _{V R} by one Let When the read offset signal RD_OFFSET 2 is received, the read coordinate calculation unit 202 decreases the value of V _{R by} the value obtained by subtracting 1 from the number of the lines 320 included in the divided block 1300. Further, when receiving the read offset signal RD_OFFSET3, reading coordinate calculation unit 202, a slight proportion value of an amount corresponding _{H R} of the horizontal size of the block line 1321 (number of pixels), the value of _{V R} by one increment Let When the read request signal RD_REQ is issued from the RDDMAC 213 to the read request mask unit 204, the read coordinate calculation unit 202 updates the read coordinates (H _R , V _R ).

First to third write coordinates _{(H W1_a, V W1_a)} calculated by writing coordinate calculation unit _{201a ~ (H W3_a, V W3_a} ) is input to the write coordinate integration unit 1201. First to third write coordinates _{(H W1_b, V W1_b)} calculated by writing coordinate calculation unit _{201b ~ (H W3_b, V W3_b} ) is input to the write coordinate integration unit 1201. The writing coordinate integration unit 1201 indicates how far the writing of the image data has been completed based on the first writing coordinates (H _{W1 — a} , V _{W1 — a} ) and the first writing coordinates (H _{W1 — b} , V _{W1 — b} ). The first writing coordinates (H _W1 , V _W1 ) are identified. The writing coordinate integration unit 1201 indicates how far the writing of the image data is completed based on the second writing coordinates (H _{W2 _a} , V _{W2 _ a} ) and the second writing coordinates (H _{W2 _ b} , V _{W2 _ b} ). Identify the second writing coordinate (H _W2 , V _W2 ). The writing coordinate integration unit 1201 indicates how far the writing of the image data has been completed, based on the third writing coordinates (H _{W3 — a} , V _{W3 — a} ) and the third writing coordinates (H _{W3 — b} , V _{W3 — b} ). Identify the third writing coordinate (H _W3 , V _W3 ).

Writing coordinate calculation unit writes coordinate calculated by 201a _{(H W2_a, V} W2_a) and Write Write coordinates calculated by the coordinate calculation section 201b _{(H W2_b, V} W2_b) based on the, writing coordinates _{(H W2, V W2} ) Is determined. Write the coordinates _{(H W2_a, V} W2_a) and write the coordinates _{(H W2_b, V} W2_b) writes coordinate towards the coordinate value in the vertical direction is small among the, you are writing the coordinates _{(H W2, V} W2). However, the write coordinate _{(H W2_a, V} W2_a) and coordinate value in the vertical direction, when the writing coordinates _{(H W2_b, V} W2_b) and a coordinate value in the vertical direction of the same, is determined as follows. That is, the writing coordinate (H _W2 , V _W2 ) of the writing coordinate (H _{W2 _a} , V _{W2 _a} ) and the writing coordinate (H _{W2 _b} , V _{W2 _b} ) having the larger horizontal coordinate value is taken as the writing coordinate (H _W2 , V _W2 ). .

Writing coordinate calculation unit writes coordinate calculated by 201a _{(H W3_a, V} W3_a) and Write Write coordinates calculated by the coordinate calculation section 201b _{(H W3_b, V} W3_b) based on the, writing coordinates _{(H W3, V W3} ) Is determined. Write the coordinates _{(H W3_a, V} W3_a) and write the coordinates _{(H W3_b, V} W3_b) writes coordinate towards the coordinate value in the vertical direction is small among the, you are writing the coordinates _{(H W3, V} W3). However, the write coordinate _{(H W3_a, V} W3_a) and coordinate value in the vertical direction, when the writing coordinates _{(H W3_b, V} W3_b) and a coordinate value in the vertical direction of the same, is determined as follows. That is, the writing coordinate (H _W3 , V _W3 ) of the writing coordinate (H _{W3 _a} , V _{W3 _a} ) and the writing coordinate (H _{W3 _b} , V _{W3 _b} ) having the larger horizontal coordinate value is taken as the writing coordinate (H _W3 , V _W3 ). .

The writing coordinates (H _W1 , V _W1 ) are determined by the writing coordinates integration unit 1201 based on the writing coordinates (H _{W1_a} , V _{W1 _a} ), (H _{W1 _b} , V _{W1 _b} ) calculated by the writing coordinates calculation parts 201 a, 201 b, respectively. Be done. The write coordinate integration unit 1201 counts the write offset signals WR_OFFSET2_a and WR_OFFSET2_b respectively output from the WRDMACs 211a and 211b. The count value of the write offset signal WR_OFFSET2_a being equal to the count value of the write offset signal WR_OFFSET2_b means the following. That is, this means that the divided block 1300 * _a for which writing is performed by the WRDMAC 211a and the divided block 1300 * _b for which writing is performed by the WRDMAC 211b is included in the same divided block 1300. Therefore, when the count value of the write offset signal WR_OFFSET2_a is equal to the count value of the write offset signal WR_OFFSET2_b, the write coordinates (H _W1 , V _W1 ) are determined as follows. Write the coordinates _{(H W1_a, V} W1_a) and write the coordinates _{(H W1_b, V} W1_b) writes coordinate towards the coordinate value in the vertical direction is small among the, you are writing the coordinates _{(H W1, V} W1). Write the coordinates _{(H W1_a, V} W1_a) when the coordinate value in the vertical direction, the write coordinate _{(H W1_b, V} W1_b) and a coordinate value in the vertical direction of the same, is determined as follows. That is, the writing coordinate (H _W1 , V _W1 ) of the writing coordinate (H _{W1_a} , V _{W1 _a} ) and the writing coordinate (H _{W1 _b} , V _{W1 _b} ) having the larger horizontal coordinate value is taken as the writing coordinate (H _W1 , V _W1 ). . The difference between the count value of the write offset signal WR_OFFSET2_a and the count value of the write offset signal WR_OFFSET2_b means the following. That is, this means that the divided blocks 1300 * _a for which writing is performed by the WRDMAC 211a and the divided blocks 1300 * _b for which writing is performed by the WRDMAC 211b are respectively included in different divided blocks 1300. Count value of the write offset signal WR_OFFSET2_a is, when smaller than the count value of the write offset signal WR_OFFSET2_b writes the coordinates _{(H W1_a, V} W1_a) is a write coordinates _{(H W1, V} W1). On the other hand, the count value of the write offset signal WR_OFFSET2_b is, when smaller than the count value of the write offset signal WR_OFFSET2_a writes the coordinates _{(H W1_b, V} W1_b) is a write coordinates _{(H W1, V} W1).

  The WRDMAC 211a outputs the write completion signal WR_END_a to the write coordinate integration unit 1201 when the writing of all the image data of the plurality of divided blocks 1300 * _a included in one frame to the memory 112 is completed. The WRDMAC 211 b outputs the write completion signal WR_END_b to the write coordinate integration unit 1201 when the writing of all the image data of the plurality of divided blocks 1300 * _b included in one frame to the memory 112 is completed. When both the write complete signal WR_END_a and the write complete signal WR_END_b are input, the write coordinate integrating unit 1201 outputs the write complete signal WR_END indicating that the writing of the image for one frame is completed.

The first to third writing coordinates (H _W1 , V _W1 ) to (H _W3 , V _W3 ) specified by the writing coordinate integration unit 1201 are input to the coordinate comparison unit 203. Further, read coordinates (H _R , V _R ) calculated by the read coordinate calculation unit 202 are input to the coordinate comparison unit 203. The coordinate comparison unit 203 sets writing coordinates (H _W1 , V _W1 ) to (H _W3 , V _W3 ) for grasping the position of the line 320 for which the writing processing has been completed, and the last of the part to be read next The readout coordinates (H _R , V _R ) for grasping the position of the tail are compared. As a result of comparing the writing coordinates (H _W1 , V _W1 ) to (H _W3 , V _W3 ) and the reading coordinates (H _R , V _R ), any one of the conditional expressions (1) to (3) is obtained. When the conditions are satisfied, it is preferable that a read process be performed. Therefore, when one of the conditional expressions (1) to (3) is satisfied, the coordinate comparison unit 203 sets the request mask signal REQ_MASK output to the read request mask unit 204 to the low level. When the request mask signal REQ_MASK is set to the low level, the read request signal RD_REQ issued from the RDDMAC 213 is not masked in the read request mask unit 204, and the read processing is performed. On the other hand, when none of the conditional expressions (1) to (3) is satisfied, the reading process is not performed. Therefore, when none of the conditional expressions (1) to (3) is satisfied, the coordinate comparison unit 203 sets the request mask signal REQ_MASK output to the read request mask unit 204 to the high level.

  The determination as to whether or not any one of the conditional expressions (1) to (3) is satisfied is performed at the rising timing of the clock signal CLK. Thus, control of the request mask signal REQ_MASK is performed by the coordinate comparison unit 203.

  When the request mask signal REQ_MASK is at the low level, the read request mask unit 204 sets the read request signal RD_REQ_MASK_OUT output to the memory I / F 205 to the high level. On the other hand, when the request mask signal REQ_MASK is at the high level, the read request mask unit 204 sets the read request signal RD_REQ_MASK_OUT output to the memory I / F 205 to the low level.

  When the writing process of the image data for one frame is completed, the writing completion signal WR_END is supplied from the writing coordinate integration unit 1201 to the coordinate comparison unit 203. When receiving the write completion signal WR_END, the coordinate comparison unit 203 sets the request mask signal REQ_MASK to Low level in order to release the mask of the read request signal RD_REQ. After the writing of the image data for one frame is completed, the read request signal RD_REQ output from the RDDMAC 213 is not masked by the read request mask unit 204. The read request signal RD_REQ is output to the memory I / F as a read request signal RD_REQ_MASK_OUT signal. Note that mask control of chase control is started based on the read start signal RD_START supplied from the RDDMAC 213 to the coordinate comparison unit 203.

  The details of the operation performed by the chase control unit 200 will be described using FIGS. 14 and 15. FIG. 14 is a diagram illustrating an example of the aspect of block division in the writing process and the reading process. FIG. 14 shows an example in which the aspect of block division for write processing and the aspect of block division for read processing are different from each other. More specifically, the size of the block 320 for writing and the size of the block 320 for reading are different from each other. FIG. 14 corresponds to the case where the aspect of block division in the processing unit (functional block) for writing the image is different from the aspect of block division in the processing unit (functional block) for reading the image. Blocks for write processing are shown by solid lines, and blocks for read processing are shown by dashed lines. The number of divisions in the horizontal direction of the block for write processing is set, for example, to six, and the number of divisions in the vertical direction is set, for example, to three. That is, 18 divided blocks WR0_0_A to WR2_2_A and WR0_0_B to WR2_2_B for the writing process are set. On the other hand, the number of divisions in the horizontal direction of the block for read processing is set to 4, for example, and the number of divisions in the vertical direction is set to 3, for example. That is, twelve read divided blocks RD0_0 to RD3_2 are set.

  The number of pixels in the horizontal direction of the write divided blocks WR0 _ * _ A and WR0 _ * _ B (* is an integer of 0 to 2) is WXA. The number of pixels in the horizontal direction of the write divided blocks WR1 _ * _ A and WR1 _ * _ B (* is an integer of 0 to 2) is WXB. The number of pixels in the horizontal direction of the divided blocks WR2 _ * _ A and WR2 _ * _ B (* is an integer of 0 to 2) for writing is WXC. The sum of the number WXA of pixels in the horizontal direction of the divided block WR0 _ * _ A for writing and the number WXA of pixels in the horizontal direction of the divided block WR0 _ * _ B for writing is WXA '. The sum of the number WXB of pixels in the horizontal direction of the divided block WR1 _ * _ A for writing and the number WXB of pixels in the horizontal direction of the divided block WR1 _ * _ B for writing is WXB '. The sum of the number WXC of pixels in the horizontal direction of the divided block WR2 _ * _ A for writing and the number WXC of pixels in the horizontal direction of the divided block WR1 _ * _ B for writing is WXC '.

  The number of lines of divided blocks WR * _0_A and WR * _0_B (* is an integer of 0 to 2) for writing, that is, the number of pixels in the vertical direction is set to WYA = 4. The number of lines of the write divided blocks WR * _1_A and WR * _1_B (* is an integer from 0 to 2) is WYB = 4. The number of lines of the write divided blocks WR * _2_A and WR * _2_B (* is an integer from 0 to 2) is WYC = 6. Here, in order to simplify the description, WYA = 4, WYB = 4, and WYC = 6, but the number of lines in the vertical direction is actually much larger than these values.

The numbers of pixels in the horizontal direction of the divided blocks RD0_ *, RD1_ *, RD2_ *, RD3_ * (* is an integer from 0 to 3) for reading are RXA, RXB, RXC, and RXD, respectively. The number of lines of divided blocks RD * _0, RD * _1, and RD * _2 (* is 0 to 3) for reading, that is, the number of pixels in the vertical direction are RYA = 4, RYB = 4, and RYC = 6, respectively. . Here, in order to simplify the description, RYA = 4, RYB = 4, and RYC = 6, but in actuality, the number of lines in the vertical direction is much larger than these values. However, the number of pixels in the horizontal direction of each divided block is assumed to satisfy the following conditions (12) to (14).
RXA <WXA '(12)
(RXA + RXB) <(WXA '+ WXB') (13)
(RXA + RXB + RXC) <(WXA '+ WXB' + WXC ') (14)

  FIG. 15 is a timing chart showing the operation of the memory control unit 120a. FIG. 15 shows a period (write period) in which the write process of the divided blocks WR0_0_A to WR2_0_A and WR0_0_B to WR2_0_B for writing is performed. Further, FIG. 15 shows a period (reading period) in which the reading process of the divided blocks RD0_0 to RD3_0 for reading is performed. Here, the case where the horizontal size of each of the divided blocks WR0_0_A to WR2_0_A, WR0_0_B to WR2_0_B, and RD0_0 to RD3_0 is equal to or less than the data length transferable by one access will be described. In order to simplify the description, a case where one line of data is transferred in one request will be described as an example.

First, before the writing process and the reading process of an image of one frame are started, initialization is performed in the writing coordinate calculation units 201a and 201b and the reading coordinate calculation unit 202. That is, in the writing coordinate calculation unit 201a, the first writing coordinates (H _{W1 _a} , V _{W1 _a} ), the second writing coordinates (H _{W2 _a} , V _{W2 _a} ) and the third writing coordinates (H _{W3 _a} , V _{W3 _a} ) are (0 , 1) is initialized. In the writing coordinate calculation unit 201b, the first writing coordinates (H _{W1 _ b} , V _{W1 _ b} ), the second writing coordinates (H _{W2 _ b} , V _{W2 _ b} ) and the third writing coordinates (H _{W3 _ b} , V _{W3 _ b} ) are (0, 1). Initialized to). In reading the coordinate calculation unit 202 reads the coordinates _(H R, _{V R)} is initialized to (0,1). Then, writing of the divided block WR0_0_A for writing, writing of the divided block WR0_0_B for writing, and reading of the divided block RD0_0 for reading are started.

First, at the initial stage, the image data of any line 320 of the divided blocks for writing WR0_0_A to WR2_2_A and WR0_0_B to WR2_2_B are not written in the memory 112. Therefore, at this stage, as shown below, the image data of the first line 320 of the divided block WR0_0 for writing is not read out. That is, first, the read request signal RD_REQ output from the RDDMAC 213 is set to the high level. In addition, the first read offset signal RD_OFFSET1 output from the RDDMAC 213 becomes High level in synchronization with the read request signal RD_REQ. The read coordinate (H _R , V _R ) is updated by the read coordinate calculation unit 202 at time tr 0 of the falling edge of the read coordinate update signal output in a pulse shape in synchronization with the rising of the read request signal RD_REQ. The coordinates of the tail end of the first line 320 of the divided block RD0_0 for reading is (RXA, 1), so the reading coordinates (H _R , V _R ) are updated to (RXA, 1). At this stage, the write coordinates (H _W1 , V _W1 ) to (H _W3 , V _W3 ) are all (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK output from the coordinate comparison unit 203 is at the high level. Since the request mask signal REQ_MASK is at the high level, the read request signal RD_REQ_MASK_OUT output from the read request mask unit 204 to the memory I / F 205 is at the low level. Therefore, the image data of the first line 320 of the divided block WR0_0 for writing is not read from the memory 112.

On the other hand, writing of the image data of the first line 320 of the divided block WR0_0_A for writing into the memory 112 is performed as follows. That is, the write request signal WR_REQ_a output from the WRDMAC 211a is set to the high level. The first write offset signal WR_OFFSET1_a output from the WRDMAC 211a becomes High level in synchronization with the write request signal WR_REQ_a. An acknowledge signal WR_ACK_a is returned from the memory I / F 205 to the WRDMAC 211a, and the image data of the first line 320 of the divided block WR0_0_A for writing is written to the memory 112. The write request signal WR_REQ_a becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_a. Further, the first write offset signal WR_OFFSET1_a becomes low level in synchronization with the fall of the write request signal WR_REQ_a. At the falling time of the first writing coordinate update signal synchronized with the acknowledge signal WR_ACK_a, the first writing coordinate (H _{W1 — a} , V _{W — 1 a} ) is updated by the writing coordinate calculation unit 201 a. Since the last coordinate of the first line 320 of the divided block WR0_0_A for writing is (WXA, 1), the first writing coordinates (H _{W1_a} , V _{W1_a} ) are updated to (WXA, 1) .

Also, the image data of the first line 320 of the divided block WR0_0_B for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_b output from the WRDMAC 211 b is set to the high level. The first write offset signal WR_OFFSET1_b output from the WRDMAC 211b becomes High level in synchronization with the write request signal WR_REQ_b. The acknowledge signal WR_ACK_b is returned from the memory I / F 205 to the WRDMAC 211 b, and the image data of the first line 320 of the divided block WR0_0_B for writing is written to the memory 112. The write request signal WR_REQ_b becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_b. In addition, the first write offset signal WR_OFFSET1_b becomes low level in synchronization with the fall of the write request signal WR_REQ_b. The first writing coordinates (H _{W1 — b} , V _{W1 — b} ) are updated by the writing coordinate calculation unit 201 b at time tw0 of the fall of the first writing coordinate update signal synchronized with the acknowledge signal WR_ACK_b. Since the last coordinate of the first line 320 of the divided block WR0_0_B for writing is (WXA ', 1), the first writing coordinates (H _{W1_b} , V _{W1_b} ) are updated to (WXA', 1) Be done.

The writing coordinates (H _W1 , V _W1 ) are determined by the writing coordinates integration unit 1201 based on the writing coordinates (H _{W1_a} , V _{W1 _a} ), (H _{W1 _b} , V _{W1 _b} ) calculated by the writing coordinates calculation part 201 a, 201 b. Ru. The count value of the write offset signal WR_OFFSET2_a is 0, and the count value of the write offset signal WR_OFFSET2_b is also 0, and these count values are equal to each other. _Further , the coordinate values in the vertical direction of the writing coordinates (H _{W1_a} , V _{W1_a} ) are 1, and the coordinate values in the vertical direction of the writing coordinates (H _{W1 _b} , V _{W1 _b} ) are 1, and these vertical coordinate values are They are equal to each other. Therefore, the writing coordinate integration unit 1201 sets the writing coordinates (H _W1 , V _W1 ) as (WXA ′, 1).

  At this stage, since the conditional expression (1) is satisfied, the request mask signal REQ_MASK issued from the coordinate comparison unit 203 is at the low level. Since the request mask signal REQ_MASK is at the low level, the read request signal RD_REQ_MASK_OUT output from the read request mask unit 204 to the memory I / F 205 is at the high level. After that, the acknowledge signal RD_ACK is sent in a pulse form from the memory I / F 205 to the RDDMAC 213, and the image data of the first line 320 of the read divided block RD0_0 is read from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

Next, the read request signal RD_REQ is set to the high level. The first read offset signal RD_OFFSET1 becomes high level in synchronization with the read request signal RD_REQ. The read coordinate (H _R , V _R ) is updated by the read coordinate calculation unit 202 at time tr1 of the falling edge of the read coordinate update signal emitted in a pulse shape in synchronization with the rising of the read request signal RD_REQ. Since the reading of the image data of the first line 320 of the divided block RD0_0 for reading from the memory 112 is completed, the read target in the next reading process is the second of the read divided block RD0_0. The third line 320. The last coordinate of the second line 320 of the read divided block RD0_0 is (RXA, 2). For this reason, the readout coordinates (H _R , V _R ) are updated to (RXA, 2). At this stage, the first writing coordinates (H _W1 , V _W1 ) are (WXA ′, 1), and the second writing coordinates (H _W2 , V _W2 ) and the third writing coordinates (H _W3 , V _W3) Is all (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK issued from the coordinate comparison unit 203 is at the high level. Since the request mask signal REQ_MASK is at the high level, the read request signal RD_REQ_MASK_OUT output from the read request mask unit 204 to the memory I / F 205 is at the low level. Therefore, at this stage, the image data of the second line 320 of the divided block WR0_0 for writing is not read from the memory 112.

On the other hand, the writing of the image data of the second line 320 of the divided block WR0_0_A for writing into the memory 112 is performed as follows. That is, the write request signal WR_REQ_a is set to the high level. In synchronization with the write request signal WR_REQ_a, the first write offset signal WR_OFFSET1_a becomes High level. Thereafter, an acknowledge signal WR_ACK_a is returned, and the image data of the second line 320 of the divided block WR0_0_A for writing is written to the memory 112. The write request signal WR_REQ_a becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_a. The first write offset signal WR_OFFSET1_a becomes low level in synchronization with the fall of the write request signal WR_REQ_a. The first write coordinates (H _{W1 — a} , V _{W1 — a} ) are updated at the fall time of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK_a. Since the last coordinate of the second line 320 of the divided block WR0_0_A for writing is (WXA, 2), the first writing coordinates (H _{W1_a} , V _{W1_a} ) are updated to (WXA, 2) .

The image data of the second line 320 of the divided block WR0_0_B for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_b is set to the high level. In synchronization with the write request signal WR_REQ_b, the first write offset signal WR_OFFSET1_b becomes High level. Thereafter, the acknowledge signal WR_ACK_b is returned, and the image data of the second line 320 of the divided block WR0_0_B for writing is written to the memory 112. The write request signal WR_REQ_b becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_b. The first write offset signal WR_OFFSET1_b becomes low level in synchronization with the fall of the write request signal WR_REQ_b. The first write coordinates (H _{W1 _ b} , V _{W1 _ b} ) are updated at time tw1 of the falling edge of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK_b. Since the last coordinate of the second line 320 of the divided block WR0_0_B for writing is (WXA ', 2), the first writing coordinates (H _{W1_b} , V _{W1_b} ) are updated to (WXA', 2) Be done.

The writing coordinate integration unit 1201 determines the writing coordinates (H _W1 , V _W1 ) based on the writing coordinates (H _{W1_a} , V _{W1_a} ), (H _{W1 _b} , V _{W1 _b} ) calculated by the writing coordinates calculation units 201 a and 201 b. Ru. The count value of the write offset signal WR_OFFSET2_a is 0, and the count value of the write offset signal WR_OFFSET2_b is also 0, and these count values are equal to each other. The write coordinates _{(H W1_a, V} W1_a) coordinate value in the vertical direction is 2, the writing coordinates _{(H W1_b, V} W1_b) vertical coordinate values are also 2, the coordinate values of these vertical They are equal to each other. Therefore, the writing coordinate integration unit 1201 sets the writing coordinates (H _W1 , V _W1 ) as (WXA ′, 2).

  At this stage, since the conditional expression (1) is satisfied, the request mask signal REQ_MASK issued from the coordinate comparison unit 203 becomes low level, and the read request signal RD_REQ_MASK_OUT becomes high level. After that, the acknowledge signal RD_ACK is sent back to the RDDMAC 213, and the image data of the second line 320 of the divided block RD0_0 for reading is read from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

Next, the read request signal RD_REQ is set to the high level. The first read offset signal RD_OFFSET1 becomes high level in synchronization with the read request signal RD_REQ. The read coordinate (H _R , V _R ) is updated by the read coordinate calculation unit 202 at time tr2 of falling of the read coordinate update signal emitted in a pulse shape in synchronization with the rising of the read request signal RD_REQ. Since reading of the image data of the second line 320 of the divided block RD0_0 for reading from the memory 112 is completed, the read target in the next reading process is the third of the read divided block RD0_0. The third line 320. The last coordinate of the third line 320 of the read divided block RD0_0 is (RXA, 3). Therefore, the readout coordinates (H _R , V _R ) are updated to (RXA, 3). At this stage, the first writing coordinates (H _W1 , V _W1 ) are (WXA ′, 2), and the second writing coordinates (H _W2 , V _W2 ) and the third writing coordinates (H _W3 , V _W3) Is all (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK issued from the coordinate comparison unit 203 is at the high level. Since the request mask signal REQ_MASK is at the high level, the read request signal RD_REQ_MASK_OUT output from the read request mask unit 204 to the memory I / F 205 is at the low level. Therefore, at this stage, the image data of the third line 320 of the divided block WR0_0 for writing is not read from the memory 112.

On the other hand, the image data of the third line 320 of the divided block WR0_0_A for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_a is set to the high level. In synchronization with the write request signal WR_REQ_a, the first write offset signal WR_OFFSET1_a becomes High level. Thereafter, the acknowledge signal WR_ACK_a is returned, and the image data of the third line 320 of the divided block WR0_0_A for writing is written to the memory 112. The write request signal WR_REQ_a becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_a. The first write offset signal WR_OFFSET1_a becomes low level in synchronization with the fall of the write request signal WR_REQ_a. The first write coordinates (H _{W1 — a} , V _{W1 — a} ) are updated at the fall time of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK_a. Since the last coordinate of the third line 320 of the divided block WR0_0_A for writing is (WXA, 3), the first writing coordinates (H _{W1_a} , V _{W1_a} ) are updated to (WXA, 3) .

In addition, writing of the image data of the third line 320 of the divided block WR0_0_B for writing into the memory 112 is performed as follows. That is, the write request signal WR_REQ_b is set to the high level. In synchronization with the write request signal WR_REQ_b, the first write offset signal WR_OFFSET1_b becomes High level. Thereafter, an acknowledge signal WR_ACK_b is returned, and the image data of the third line 320 of the divided block WR0_0_B for writing is written to the memory 112. The write request signal WR_REQ_b becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_b. The first write offset signal WR_OFFSET1_b becomes low level in synchronization with the fall of the write request signal WR_REQ_b. The first write coordinates (H _{W1 _ b} , V _{W1 _ b} ) are updated at time tw2 of the fall of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK_b. Since the last coordinate of the third line 320 of the divided block WR0_0_B for writing is (WXA ', 3), the first writing coordinates (H _{W1_b} , V _{W1_b} ) are updated to (WXA', 3) Be done.

The writing coordinates (H _W1 , V _W1 ) are determined by the writing coordinates integration unit 1201 based on the writing coordinates (H _{W1_a} , V _{W1 _a} ) and (H _{W1 _b} , V _{W1 _b} ) calculated by the writing coordinates calculation parts 201 a and 201 b. Be done. The count value of the write offset signal WR_OFFSET2_a is 0, and the count value of the write offset signal WR_OFFSET2_b is also 0, and these count values are equal to each other. The write coordinates _{(H W1_a, V} W1_a) coordinate value in the vertical direction is 3, the writing coordinates _{(H W1_b, V} W1_b) vertical coordinate values are also 3, the coordinate values of these vertical They are equal to each other. Therefore, the writing coordinate integration unit 1201 sets the writing coordinates (H _W1 , V _W1 ) as (WXA ′, 3).

  At this stage, since the conditional expression (1) is satisfied, the request mask signal REQ_MASK issued from the coordinate comparison unit 203 becomes low level, and the read request signal RD_REQ_MASK_OUT becomes high level. After that, the acknowledge signal RD_ACK is sent back to the RDDMAC 213, and the image data of the third line 320 of the divided block RD0_0 for reading is read out from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

Next, the read request signal RD_REQ is set to the high level. The second read offset signal RD_OFFSET2 becomes High level in synchronization with the read request signal RD_REQ. The read coordinates (H _R , V _R ) are updated at time tr3 of falling of the read coordinate update signal emitted in a pulse shape in synchronization with the rising of the read request signal RD_REQ. Since reading of the image data of the third line 320 of the divided block RD0_0 for reading is completed, the line 320 to be read in the next reading process is the fourth of the divided blocks RD0_0 for reading. Line 320. The last coordinate of the fourth line 320 of the read divided block RD0_0 is (RXA, 4). Therefore, the readout coordinates (H _R , V _R ) are updated to (RXA, 4). At this stage, the first writing coordinates (H _W1 , V _W1 ) are (WXA ′, 3), and the second writing coordinates (H _W2 , V _W2 ) and the third writing coordinates (H _W3 , V _W3) Is all (0, 1). Since none of the conditional expressions (1) to (3) is satisfied, the request mask signal REQ_MASK is at the high level, and the read request signal RD_REQ_MASK_OUT is at the low level. Therefore, at this stage, the image data of the fourth line 320 of the divided block WR0_0 for writing is not read from the memory 112.

On the other hand, the image data of the fourth line 320 of the divided block WR0_0_A for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_a is set to the high level. The second write offset signal WR_OFFSET2_a becomes High level in synchronization with the write request signal WR_REQ_a. An acknowledge signal WR_ACK_a is returned from the memory I / F 205 to the WRDMAC 211a, and the image data of the fourth line 320 of the divided block WR0_0_A for writing is written to the memory 112. The write request signal WR_REQ_a becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_a. The second write offset signal WR_OFFSET2_a becomes low level in synchronization with the fall of the write request signal WR_REQ_a. The second write coordinates (H _{W2 _a} , V _{W2 _ a} ) are updated at the fall time of the second write coordinate update signal synchronized with the acknowledge signal WR_ACK_a. Since the last coordinate of the fourth line 320 of the divided block WR0_0_A for writing is (WXA, 4), the second writing coordinates (H _{W2 _a} , V _W2 _ a) are updated to (W XA, 4) .

Further, the image data of the fourth line 320 of the divided block WR0_0_B for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_b is set to the high level. The second write offset signal WR_OFFSET2_b becomes High level in synchronization with the write request signal WR_REQ_b. Thereafter, an acknowledge signal WR_ACK_b is returned, and the image data of the fourth line 320 of the divided block WR0_0_B for writing is written to the memory 112. The write request signal WR_REQ_b becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_b. The second write offset signal WR_OFFSET2_b becomes low level in synchronization with the fall of the write request signal WR_REQ_b. The second write coordinates (H _{W2 _ b} , V _{W2 _ b} ) are updated at time tw3 of the fall of the second write coordinate update signal synchronized with the acknowledge signal WR_ACK_b. Since the last coordinate of the fourth line 320 of the divided block WR0_0_B for writing is (WXA ', 4), the second writing coordinates (H _{W2_b} , V _{W2_b} ) are updated to (WXA', 4) Be done.

The writing coordinate integration unit 1201 determines the writing coordinates (H _W2 , V _W2 ) based on the writing coordinates (H _{W2_a} , V _{W2_a} ), (H _{W2 _b} , V _{W2 _b} ) calculated by the writing coordinates calculation units 201 a and 201 b Ru. Write the coordinates _{(H W2_a, V} W2_a) coordinate value in the vertical direction is 4, the writing coordinates _{(H W2_b, V} W2_b) a 4 also vertical coordinate values of the coordinate values of these vertical are equal . Therefore, the writing coordinate integration unit 1201 sets the writing coordinates (H _W2 , V _W2 ) as (WXA ′, 4).

  At this stage, since the conditional expression (2) is satisfied, the request mask signal REQ_MASK from the coordinate comparison unit 203 becomes low level, and the read request signal RD_REQ_MASK_OUT becomes high level. Thereafter, an acknowledge signal RD_ACK is returned to the RDDMAC 213, and the image data of the fourth line 320 of the divided block RD0_0 for reading is read from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the second read offset signal RD_OFFSET2 becomes low level in synchronization with the fall of the read request signal RD_REQ.

Next, the read request signal RD_REQ is set to the high level. The first read offset signal RD_OFFSET1 becomes high level in synchronization with the read request signal RD_REQ. The read coordinates (H _R , V _R ) are updated at a falling edge time tr4 of the read coordinate update signal emitted in a pulse shape in synchronization with the rising of the read request signal RD_REQ. Since reading of the image data of all the lines 320 of the divided block RD0_0 for reading has been completed from the memory 112, the first read process to be read in the next reading process is the first of the divided blocks RD1_0 for reading. Line 320. The last coordinate of the first line 320 of the divided block RD1_0 for reading is (RXA + RXB, 1). Therefore, the readout coordinates (H _R , V _R ) are updated to (RXA + RXB, 1). At this stage, the first writing coordinates (H _W1 , V _W1 ) are (WXA ′, 3), (H _W2 , V _W2 ) are (WXA ′, 4), and (H _W3 , V _W3 ) Is (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK is at the high level, and the read request signal RD_REQ_MASK_OUT is at the low level. Therefore, at this stage, the image data of the first line 320 of the divided block WR1_0 for writing is not read from the memory 112.

On the other hand, the image data of the first line 320 of the divided block WR1_0_A for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_a is set to the high level. The first write offset signal WR_OFFSET1_a becomes High level in synchronization with the write request signal WR_REQ_a. An acknowledge signal WR_ACK_a is returned from the memory I / F 205 to the WRDMAC 211a, and the image data of the first line 320 of the divided block WR1_0_A for writing is written to the memory 112. The write request signal WR_REQ_a becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_a. The first write offset signal WR_OFFSET1_a becomes low level in synchronization with the fall of the write request signal WR_REQ_a. The first write coordinates (H _{W1 — a} , V _{W1 — a} ) are updated at the fall time of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK_a. Since the last coordinate of the first line 320 of the divided block WR1_0_A for writing is (WXA ′ + WXB, 1), the first writing coordinates (H _{W1_a} , V _{W1_a} ) is (WXA ′ + WXB, 1) Updated to

Further, the image data of the first line 320 of the divided block WR1_0_B for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_b is set to the high level. The first write offset signal WR_OFFSET1_b becomes High level in synchronization with the write request signal WR_REQ_b. An acknowledge signal WR_ACK_b is returned from the memory I / F 205 to the WRDMAC 211a, and the image data of the first line 320 of the divided block WR1_0_b for writing is written to the memory 112. The write request signal WR_REQ_b becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_b. The first write offset signal WR_OFFSET1_b becomes low level in synchronization with the fall of the write request signal WR_REQ_b. The first write coordinates (H _{W1 _ b} , V _{W1 _ b} ) are updated at time tw4 of the fall of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK_b. Since the last coordinate of the first line 320 of the divided block WR1_0_B for writing is (WXA '+ WXB', 1), the first writing coordinates (H _{W1_b} , V _{W1_b} ) are (WXA '+ WXB', Updated to 1).

The writing coordinate integration unit 1201 determines the writing coordinates (H _W1 , V _W1 ) based on the writing coordinates (H _{W1_a} , V _{W1_a} ), (H _{W1 _b} , V _{W1 _b} ) calculated by the writing coordinates calculation units 201 a and 201 b. Ru. The count value of the write offset signal WR_OFFSET2_a is 1, and the count value of the write offset signal WR_OFFSET2_b is also 1, and these count values are equal to each other. _Further , the coordinate values in the vertical direction of the writing coordinates (H _{W1_a} , V _{W1_a} ) are 1, and the coordinate values in the vertical direction of the writing coordinates (H _{W1 _b} , V _{W1 _b} ) are 1, and these vertical coordinate values are They are equal to each other. Therefore, the writing coordinate integration unit 1201 sets the writing coordinates (H _W1 , V _W1 ) as (WXA ′ + WXB ′, 1).

At this stage, the readout coordinates (H _R , V _R ) are (RXA + RXB, 1), and the above conditional expression (1) is satisfied. Therefore, the request mask signal REQ_MASK issued from the coordinate comparison unit 203 is at the low level, and the read request signal RD_REQ_MASK_OUT is at the high level. After that, the acknowledge signal RD_ACK is sent back to the RDDMAC 213, and the image data of the first line 320 of the divided block RD1_0 for reading is read out from the memory 112. The read request signals RD_REQ and RD_REQ_MASK_OUT become Low level in synchronization with the falling of the acknowledge signal RD_ACK. Further, the first read offset signal RD_OFFSET1 becomes low level in synchronization with the fall of the read request signal RD_REQ.

Next, the read request signal RD_REQ is set to the high level. The first read offset signal RD_OFFSET1 becomes high level in synchronization with the read request signal RD_REQ. The read coordinates (H _R , V _R ) are updated at a falling edge time tr5 of the read coordinate update signal emitted in a pulse shape in synchronization with the rising of the read request signal RD_REQ. Since the reading of the image data of the first line 320 of the divided block RD1_0 for reading is completed, the line 320 to be read in the next reading process is the second of the divided blocks RD1_0 for reading. Line 320. The last coordinate of the second line 320 of the divided block RD1_0 for reading is (RXA + RXB, 2). Therefore, the readout coordinates (H _R , V _R ) are updated to (RXA + RXB, 2). At this stage, the first writing coordinates (H _W1 , V _W1 ) are (WXA ′ + WXB ′, 1), and the second writing coordinates (H _W2 , V _W2 ) are (WXA, 4). The writing coordinates (H _W3 , V _W3 ) of ₃ are (0, 1). Since none of the conditional expressions (1) to (3) are satisfied, the request mask signal REQ_MASK is at the high level, and the read request signal RD_REQ_MASK_OUT is at the low level. Therefore, at this stage, the image data of the second line 320 of the divided block WR1_0 for writing is not read from the memory 112.

On the other hand, writing of the image data of the second line 320 of the divided block WR1_0_A for writing into the memory 112 is performed as follows. That is, the write request signal WR_REQ_a is set to the high level. The first write offset signal WR_OFFSET1_a becomes High level in synchronization with the write request signal WR_REQ_a. An acknowledge signal WR_ACK_a is returned from the memory I / F 205 to the WRDMAC 211, and the image data of the second line 320 of the divided block WR1_0_A for writing is written to the memory 112. The write request signal WR_REQ_a becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_a. The first write offset signal WR_OFFSET1_a becomes low level in synchronization with the fall of the write request signal WR_REQ_a. The first writing coordinates (H _{W1 — a} , V _{W1 — a} ) are updated by the writing coordinate calculation unit 201 a at time tw5 at the falling edge of the first writing coordinate update signal synchronized with the acknowledge signal WR_ACK_a. Since the last coordinate of the second line 320 of the divided block WR1_0_A for writing is (WXA '+ WXB, 2), the first writing coordinates (H _{W1_a} , V _{W1_a} ) are (WXA' + WXB, 2) Updated to

Further, the image data of the second line 320 of the divided block WR1_0_B for writing is written to the memory 112 as follows. That is, the write request signal WR_REQ_b is set to the high level. The first write offset signal WR_OFFSET1_b becomes High level in synchronization with the write request signal WR_REQ_b. An acknowledge signal WR_ACK_b is returned from the memory I / F 205 to the WRDMAC 211, and the image data of the second line 320 of the divided block WR1_0_B for writing is written to the memory 112. The write request signal WR_REQ_b becomes low level in synchronization with the fall of the acknowledge signal WR_ACK_b. The first write offset signal WR_OFFSET1_b becomes low level in synchronization with the fall of the write request signal WR_REQ_b. At the falling time of the first write coordinate update signal synchronized with the acknowledge signal WR_ACK_b, the first write coordinate (H _{W1 _ b} , V _{W1 _ b} ) is updated by the write coordinate calculation unit 201 b. Since the last coordinate of the second line 320 of the divided block WR1_0_B for writing is (WXA '+ WXB', 2), the first writing coordinates (H _{W1_b} , V _{W1_b} ) are (WXA '+ WXB', Updated to 2).

The writing coordinate integration unit 1201 determines the writing coordinates (H _W1 , V _W1 ) based on the writing coordinates (H _{W1_a} , V _{W1_a} ), (H _{W1 _b} , V _{W1 _b} ) calculated by the writing coordinates calculation units 201 a and 201 b. Ru. The count value of the write offset signal WR_OFFSET2_a is 1, and the count value of the write offset signal WR_OFFSET2_b is also 1, and these count values are equal to each other. The write coordinates _{(H W1_a, V} W1_a) coordinate value in the vertical direction is 2, the writing coordinates _{(H W1_b, V} W1_b) vertical coordinate values are also 2, the coordinate values of these vertical They are equal to each other. Therefore, the writing coordinate integration unit 1201 sets the writing coordinates (H _W1 , V _W1 ) as (WXA ′ + WXB ′, 2).

The subsequent write process for the write divided blocks WR1_0_A and WR1_0_B is the same as the above-described write process for the write divided blocks WR0_0_A and WR0_0_B, and thus the description thereof is omitted. At time tw6, the first writing coordinates (H _W1 , V _W1 ) are updated to (WXA ′ + WXB ′, 3), and at time tw7, the second writing coordinates (H _W2 , V _W2 ) are ( It is updated to WXA '+ WXB', 4).

Further, the subsequent read process for the read divided blocks RD1_0 and RD2_0 is the same as the above-described read process for the read divided block RD0_0, and thus the description thereof will be omitted. At times tr6, tr7 and tr8, the read coordinates (H _R , V _R ) are updated to (RXA + RXB, 3), (RXA + RXB, 4), and (RXA + RXB + RXC, 1), respectively. At time tr9, tr10, tr11, read the coordinates _{(H R,} V _R) is updated to (RXA + RXB + RXC, 2 ), (RXA + RXB + RXC, 3), (RXA + RXB + RXC, 4).

The write processing for the divided blocks WR2_0_A and WR2_0_B for writing is also similar to the above-described writing processing for the divided blocks WR0_0_A and WR0_0_B for writing, and thus the description thereof will be omitted. At times tw8, tw9 and tw10, the first writing coordinates (H _W1 , V _W1 ) are (WXA ′ + WXB ′ + WXC ′, 1), (WXA ′ + WXB ′ + WXC ′, 2), (WXA ′) Each is updated to + WXB ′ + WXC ′, 3). Further, at time tw11, the third writing coordinate (H _W3 , V _W3 ) is updated to (WXA ′ + WXB ′ + WXC ′, 4).

In the read process for the read divided block RD3_0, the read coordinates (H _R , V _R ) are updated to (RXA + RXB + RXC + RXD, 1) at time tr12. The first writing coordinates (H _W1 , V _W1 ) are (WXA ′ + WXB ′ + WXC ′, 4), which satisfy the conditional expression (1). The third writing coordinates (H _W3 , V _W3 ) are (WXA ′ + WXB ′ + WXC ′, 4), which satisfy the conditional expression (3). Therefore, the request mask signal REQ_MASK is at the low level, and the read request signal RD_REQ_MASK_OUT is at the high level. Therefore, the image data is read from the first line 320 of the divided block RD3_0 for reading. At time tr13, the read coordinates (H _R , V _R ) are updated to (RXA + RXB + RXC + RXD, 2). The first writing coordinates (H _W1 , V _W1 ) are (WXA ′ + WXB ′ + WXC ′, 4), which satisfy the conditional expression (1). The third writing coordinates (H _W3 , V _W3 ) are (WXA + WXB + WXC, 4), which satisfy the conditional expression (3). Therefore, the request mask signal REQ_MASK is at the low level, and the read request signal RD_REQ_MASK_OUT is at the high level. Therefore, the image data is read from the second line 320 of the divided block RD3_0 for reading. At time tr14, the readout coordinates (H _R , V _R ) are updated to (RXA + RXB + RXC + RXD, 3). The first writing coordinates (H _W1 , V _W1 ) are (WXA ′ + WXB ′ + WXC ′, 4), and the above conditional expression (1) is satisfied. Further, the third writing coordinate (H _W3 , V _W3 ) is (WXA + WXB + WXC, 4), and the conditional expression (3) is satisfied. Therefore, the request mask signal REQ_MASK is at the low level, and the read request signal RD_REQ_MASK_OUT is at the high level. Therefore, the image data is read from the third line 320 of the divided block RD3_0 for reading. At time tr15, the read coordinates (H _R , V _R ) are updated to (RXA + RXB + RXC + RXD, 4). The first writing coordinates (H _W1 , V _W1 ) are (WXA ′ + WXB ′ + WXC ′, 4), and the above conditional expression (1) is satisfied. The third writing coordinates (H _W3 , V _W3 ) are (WXA + WXB + WXC, 4), which satisfy the conditional expression (3). Therefore, the request mask signal REQ_MASK is at the low level, and the read request signal RD_REQ_MASK_OUT is at the high level. Therefore, the image data is read from the fourth line 320 of the divided block RD3_0 for reading.

  The writing process and the reading process are performed on the divided blocks WR0_1 to WR2_2 for writing and the divided blocks RD0_1 to RD3_2 for reading in the same manner as described above.

The dots shown in FIG. 14 indicate a state in which the writing process is completed up to the third line 320 of the divided block WR2_1_A and the writing is completed up to the second line 320 of the divided block WR1_1_B. In this state, the first writing coordinates (H _W1 , V _W1 ) are (WXA ′ + WXB ′, 6), and the second writing coordinates (H _W2 , V _W2 ) are (WXA ′, 8). The third writing coordinates (H _W3 , V _W3 ) are (WXA ′ + WXB ′ + WXC ′, 4). Also, the readout coordinates (H _R , V _R ) are (RXA + RXB, 6). In this state, it is possible to read out the image data up to the second line 320 of the divided block RD1_1 for reading.

  When the write processing for the write divided blocks WR2_2_A and WR2_2_B is completed, the WRDMACs 211a and 211b respectively set the write completion signals WR_END_a and WR_END_b to High level as described above. When both the write complete signal WR_END_a and the write complete signal WR_END_b are input, the write coordinate integrating unit 1201 outputs the write complete signal WR_END indicating that the writing of the image for one frame is completed. When the write completion signal WR_END goes to the high level, the coordinate comparison unit 203 stops comparison of the coordinates based on the conditional expressions (1) to (3), and sets the request mask signal REQ_MASK to the low level. As a result, after the write process for the write divided block WR2_2 is completed, the read request signal RD_REQ output from the RDDMAC 213 is not masked by the read request mask unit 204. Therefore, after the writing process for the write divided block WR2_2 is completed, the image data of the read divided block is continuously read from the memory 112.

  Here, although the case where the size in the horizontal direction of each of the divided blocks WR0_0 to WR2_2 and RD0_0 to RD3_2 is equal to or less than the data length that can be transferred by one access is described as an example, Absent. For example, when the size in the horizontal direction of each of the divided blocks WR0_0 to WR2_2 and RD0_0 to RD3_2 is larger than the data length that can be transferred by one access, the following processing is performed. That is, when data is written to one line 320, issuance of a write request and data writing are performed a plurality of times. Further, in reading data from one line 320, issuance of a read request and reading of data are performed a plurality of times.

When data is not written to the last pixel of the line 320 in the writing, the WRDMAC 211a maintains the write offset signals WR_OFFSET1_a to WR_OFFSET3_a at Low level. When data is not written to the last pixel of the line 320 in the writing, the WRDMAC 211 b maintains the write offset signals WR_OFFSET 1 _b to WR_OFFSET 3 _b at Low level. On the other hand, when writing data in the last pixel of the line 320 in the write, the WRDMAC 211a sets one of the write offset signals WR_OFFSET1_a to WR_OFFSET3_a to the high level. When writing data to the last pixel of the line 320 in the write, the WRDMAC 211 sets one of the write offset signals WR_OFFSET1_b to WR_OFFSET3_b to the high level. The writing coordinates (HW 1 _{_a} , VW 1 _{_a} ) to (HW 3 _{_a} , VW 3 _{_a} ) are updated by the writing coordinates calculation unit 201a only when data is written to the last pixel of the line 320 in the writing. Ru. The writing coordinates ( _{HW1_b} , _{VW1_b} ) to ( _{HW3_b} , _{VW3_b} ) are updated by the writing coordinates calculation unit 201b only when the data is written to the last pixel of the line 320 in the writing. Ru.

When data is not read out from the pixel located at the tail end of the line 320 in the readout, the RDDMAC 213 maintains all of the readout offset signals RD_OFFSET1 to RD_OFFSET3 at the low level. On the other hand, when data is read from the last pixel of the line 320 in the read, the RDDMAC 213 sets one of the read offset signals RD_OFFSET1 to RD_OFFSET3 to the high level. The readout coordinates (H _R , V _R ) are updated regardless of whether data is read out from the pixel located at the end of the line 320 in the readout. When the data is not read out from the pixel located at the end of the line 320 in the readout, the readout coordinate calculation unit 202 performs the following operation. That is, the read coordinate calculation unit 202, each time the read request signal RD_REQ is supplied from RDDMAC213, updates the read coordinates _{(H R, V} R) on the basis of the data transfer length signal RD_TRANS supplied from RDDMAC213. On the other hand, when data is read out from the last pixel of the line 320 in the readout, the readout coordinate calculation unit 202 performs the following operation. That is, the read coordinate calculation unit 202, and one of the read offset signal RD_OFFSET1～RD_OFFSET3, based on the data transfer length signal RD_TRANS reads coordinates _{(H R, V} R) to update the.

  FIG. 16 is a flowchart showing the operation of the image processing apparatus according to the present embodiment. The processing shown in FIG. 16 is mainly executed by the CPU 108 and the memory control unit 120 a.

  First, in response to an instruction from the CPU 108, the WRDMACs 211a and 211b and the RDDMAC 213 start processing (step S1600).

Next, in the writing coordinate calculation unit 201a, the first writing coordinates (H _{W1 _a} , V _{W1 _a} ), the second writing coordinates (H _{W2 _a} , V _{W2 _a} ), and the third writing coordinates (H _{W3 _a} , V _{W3 _a} ) Is initialized to, for example, (0, 1). In the writing coordinate calculation unit 201b, the first writing coordinates (H _{W1 _ b} , V _{W1 _ b} ), the second writing coordinates (H _{W2 _ b} , V _{W2 _ b} ), and the third writing coordinates (H _{W3 _ b} , V _{W3 _ b} ) , For example, initialize to (0, 1). Further, the read coordinate calculation unit 202 initializes read coordinates (H _R , V _R ) to, for example, (0, 1). The initialization of these coordinate values is performed by an instruction from the CPU 108 (step S1601).

  In step S1602, the coordinate comparison unit 203 determines whether any one of the conditional expressions (1) to (3) is satisfied. If one of the conditional expressions (1) to (3) is satisfied (YES in step S1602), the process transitions to step S1603. In step S1603, the mask process for the read request signal RD_REQ from the RDDMAC 213 is canceled in the read request mask unit 204. Thereafter, the process transitions to step S1605. If none of the conditional expressions (1) to (3) is satisfied (NO in step S1602), the process transitions to step S1604. In step S 1604, the read request mask unit 204 masks the read request signal RD_REQ from the RDDMAC 213. As a result, reading of image data from the memory 112 by the RDDMAC 213 is stopped. Thereafter, the process transitions to step S1605.

In step S1605, it is determined whether or not the first write offset signals WR_OFFSET1_a and WR_OFFSET1_b output from the WRDMACs 211a and 211b are at the high level. If the first write offset signals WR_OFFSET1_a and WR_OFFSET1_b are at the high level (YES in step S1605), the process transitions to step S1608. In step S1608, the first writing coordinates (H _{W1 — a} , V _{W1 — a} ) and (H _{W1 — b} , V _{W1 — b} ) are updated to the coordinates of the last pixel of the line 320 on which the writing process has been completed. If the first write offset signals WR_OFFSET1_a and WR_OFFSET1_b are not at the high level (NO in step S1605), the process transitions to step S1606.

In step S1606, it is determined whether or not the second write offset signals WR_OFFSET2_a and WR_OFFSET2_b output from the WRDMACs 211a and 211b are at the high level. If the second write offset signals WR_OFFSET2_a and WR_OFFSET2_b are at the high level (YES in step S1606), the process transitions to step S1609. In step S1609, the second writing coordinates (H _{W2 — a} , V _{W2 — a} ) and (H _{W2 — b} , V _{W — 2 B} ) are updated to the coordinates of the last pixel of the line 320 in which the writing process has been completed. If the second write offset signals WR_OFFSET2_a and WR_OFFSET2_b are not at the high level, the process proceeds to step S1607.

In step S1607, it is determined whether the third write offset signals WR_OFFSET3_a and WR_OFFSET3_b output from the WRDMACs 211a and 211b are at the high level. If the third write offset signals WR_OFFSET3_a and WR_OFFSET3_b are at the high level (YES in step S1607), the process advances to step S1610. In step S1610, the third writing coordinates (H _{W3 — a} , V _{W3 — a} ) and (H _{W3 — b} , V _{W — 3 b} ) are updated to the coordinates of the last pixel of the line 320 in which the writing process is completed. If the third write offset signals WR_OFFSET3_a and WR_OFFSET3_b are not at the high level (NO in step S1607), the process transitions to step S1611.

In step S1611, the writing coordinate integration unit 1201 performs the following processing. That is, the write coordinate integrating unit 1201 writes the coordinates _{(H W1_a, V} W1_a) and write the coordinates _{(H W1_b, V} W1_b) based on the, to determine the write coordinates _{(H W1, V} W1). The write coordinate integrating unit 1201 writes the coordinates _{(H W2_a, V} W2_a) and write the coordinates _{(H W2_b, V} W2_b) based on the, to determine the write coordinates _{(H W2, V} W2). The write coordinate integrating unit 1201 writes the coordinates _{(H W3_a, V} W3_a) and write the coordinates _{(H W3_b, V} W3_b) based on the, to determine the write coordinates _{(H W3, V} W3). Thereafter, the process proceeds to step S1612.

  In step S1612, it is determined whether the read request signal RD_REQ from the RDDMAC 213 is at the high level. If the read request signal RD_REQ is at the high level, the process proceeds to step S1613. On the other hand, when the read request signal RD_REQ is not at the high level, the process transitions to step S1616.

In step S1613, it is determined whether any one of the first to third read offset signals RD_OFFSET1 to RD_OFFSET3 is at the high level. If one of the first to third read offset signals RD_OFFSET1 to RD_OFFSET3 is at the high level (YES in step S1613), the process proceeds to step S1614. In step S1614, the horizontal readout coordinate H _R and the vertical readout coordinate V _R are updated. Thereafter, the process proceeds to step S1616. If all of the first to third read offset signals RD_OFFSET1 to RD_OFFSET3 are not at the high level (NO in step S1613), the process proceeds to step S1615. In step S1615, the readout coordinate H _R in the horizontal direction is updated. Thereafter, the process proceeds to step S1616.

  In step S1616, the WRDMACs 211a and 211b respectively determine whether the writing process is completed, and notify the CPU 108 of the result of the determination. If the writing process is completed (YES in step S1616), the process advances to step S1617.

  In step S1617, the mask for the read request signal RD_REQ is released. Thereafter, the process transitions to step S1618. On the other hand, if the write process has not been completed (NO in step S1616), the process returns to step S1602 and the same process as described above is performed.

  In step S1618, the RDDMAC 213 performs read processing on the line 320 whose read has not been completed, and determines whether the read processing has been completed. If the read process is not completed (NO in step S1618), the read process is continuously performed on the line 320 whose read is not completed. On the other hand, when the reading process is completed (YES in step S1618), the chase control ends.

Thus, in the present embodiment, the write coordinate _{(H W1_a, V} W1_a) and write the coordinates _{(H W1_b, V} W1_b) based on the, writing coordinates _{(H W1, V} W1) is determined. The write coordinates _{(H W2_a, V} W2_a) and write the coordinates _{(H W2_b, V} W2_b) based on the, writing coordinates _{(H W2, V} W2) is determined. Write the coordinates _{(H W3_a, V} W3_a) and write the coordinates _{(H W3_b, V} W3_b) based on the, writing coordinates _{(H W3, V} W3) is determined. Then, the reading is performed based on the result of comparison between the writing coordinates (H _W1 , V _W1 ), (H _W2 , V _W2 ), (H _W3 , V _W3 ) and the reading coordinates (H _R , V _R ) . Therefore, according to the present embodiment, it is possible to provide an image processing apparatus and an image processing method capable of appropriately performing chase control even when using a plurality of WRDMACs 211a and 211b.

(Modification (Part 1))
An image processing apparatus and an image processing method according to a modification (part 1) of the embodiment will be described with reference to FIG. FIG. 17 is a diagram showing an aspect of block division in the present modification. A thick solid line in FIG. 17 conceptually shows a divided block for writing, and a thick broken line in FIG. 17 conceptually shows a divided block for reading.

  In this modification, as in the modification (part 1) of the first embodiment, the access start coordinates in the writing process are different from the access start coordinates in the reading process.

  The horizontal difference between the access start coordinates in the write process and the access start coordinates in the read process is DIFX. The vertical difference between the access start coordinates in the write process and the access start coordinates in the read process is DIFY.

In such a case, for example, the first to third writing coordinates (H _W1 , V _W1 ), (H _W2 , V _W2 ), and (H _W3 , V _W3 ) are the amounts of difference amounts DIFX and DIFY of the access start coordinates. You just have to shift it. The first to third writing coordinates (H _W1 , V _W1 ) ', (H _W2 , V _W2 )', and (H _W3 , V _W3 ) 'shifted by the difference amount DIFX of access start coordinates and DIFY are , Expressions (7) to (9). The access start coordinate in the read process is (1, 1). The write coordinates (H _W1 , V _W1 ) ′, (H _W2 , V _W2 ) ′, and (H _W3 , V _W3 ) ′ shifted by the difference amount DIFX of access start coordinates by DIFY are the write coordinate calculation unit 201. Calculated by

Here, the case where writing coordinates (H _W1 , V _W1 ), (H _W2 , V _W2 ), and (H _W3 , V _W3 ) are shifted by an amount corresponding to the difference amounts DIFX and DIFY of access start coordinates will be described as an example. However, it is not limited to this. For example, the writing coordinates (H _R , V _R ) may be shifted by the difference amount DIFX of the access start coordinates, and the DIFY. The write coordinates (H _R , V _R ) ′ shifted by the difference amount DIFX of the access start coordinate, DIFY by the above equation (10) when the access start coordinate in the write process is (1, 1) expressed. The read coordinates (H _R , V _R ) ′ shifted by the difference amount DIFX of the access start coordinates and DIFY are calculated by the read coordinates calculation unit 202.

  Thus, the access start coordinates in the write process may be different from the access start coordinates in the read process.

(Modification (Part 2))
An image processing apparatus and an image processing method according to a modification (part 2) of the present embodiment will be described with reference to FIG. FIG. 18 is a diagram showing an aspect of block division in the present modification. A thick solid line in FIG. 18 conceptually shows a divided block for writing, and a thick broken line in FIG. 18 conceptually shows a divided block for reading.

  This modification shows the case where adjacent divided blocks overlap. The overlap amount in the horizontal direction of adjacent read divided blocks RD * _ * is OLX. The overlapping amount in the vertical direction of adjacent read divided blocks RD * _ * is OLY.

In such a case, for example, when the divided block RD * _ * to be read is switched, the read coordinates (H _R , V _R ) may be shifted by the amount of overlap OLX, OLY. The readout coordinates (H _R , V _R ) ′ shifted by the amount of overlap OLX, OLY are expressed by equation (11). The read coordinate (H _R , V _R ) ′ shifted by the overlap amount OLX, OLY is calculated by the read coordinate calculation unit 202.

  Thus, adjacent divided blocks may overlap. Here, although the case where adjacent divided blocks for reading RD * _ * overlap is described as an example, adjacent divided blocks for writing WR * _ * may be overlapped.

The jump of the access coordinates when the access reaches the end of the divided block is the same as the modification (part 2) of the first embodiment described with reference to FIG. When access reaches the pixels 311 and 312 at the last coordinate (H ₂ , V ₂ ) of the divided block, as in the modification (part 2) of the first embodiment described using FIG. The offset value is added to the address value. The offset value added here is (−XH × (YA−1) −OLX).

Adjacent divided blocks may overlap in both the horizontal and vertical directions. When access reaches the pixel at the coordinate (H ₃ , V ₃ ) at the tail end of the block line, as in the modification (part 2) of the first embodiment described using FIG. The offset value is added to the address value. The offset value added here is (−XH × OLY).

  Thus, adjacent divided blocks may overlap. Also in this modification, it is possible to provide an image processing apparatus capable of appropriately performing chase control on the memory 112.

[Modified embodiment]
As mentioned above, although the preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

For example, in the above embodiment, the read processing is performed when any of the conditional expressions (1) to (3) is satisfied, but the conditional expressions used are limited to (1) to (3). It is not a thing. For example, the following conditional expressions (15) to (17) may be used instead of the conditional expressions (1) to (3). In this case, the read process is delayed by the amount of L _GAP .
H _W1 HH _R and V _W1 > (V _R + L _GAP ) (15)
H _W2 HH _R and V _W2 > (V _R + L _GAP ) (16)
H _W3 HH _R and V _W3 > (V _R + L _GAP ) (17)

  Further, in the second embodiment, although the case where the number of WRDMACs is two has been described as an example, the present invention is not limited to this, and the number of WRDMACs may be three or more.

  The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a recording medium, and one or more processors in a computer of the system or apparatus read and execute the program. Can also be realized. It can also be implemented by a circuit (eg, an ASIC) that implements one or more functions.

201, 201a, 201b ... writing coordinate calculation unit 202 ... reading coordinate calculation unit 203 ... coordinate comparison unit 211, 211a, 211b ... WRDMAC
213, 213a, 213b ... RD DMAC
320 ... block 1201 ... writing coordinate integration unit

Claims (14)

A writing unit that writes image data to the memory in units of the first block;
The reading unit reads image data from the memory in units of the second block, and the writing unit is writing to the memory while the image data of one frame is written to the memory by the writing unit. A readout unit for outputting a readout request for the image data of the frame, and reading out the image data from the memory in response to permission of the readout request;
The pixel for which writing has been completed in response to the writing unit having performed writing of a pixel at a predetermined position among the plurality of first blocks included in the image data of the frame being written to the memory A writing coordinate acquisition unit that acquires writing coordinates corresponding to the position of
A read coordinate acquisition unit for acquiring read coordinates corresponding to the position of the second block to be read out of the plurality of second blocks in a frame being written to the memory A reading coordinate acquisition unit that updates the reading coordinates according to a data transfer length;
Controlling whether or not to permit the read request from the reading unit based on a positional relationship between the writing coordinate acquired by the writing coordinate acquiring unit and the read coordinate acquired by the reading coordinate acquiring unit; A control unit having a control unit that controls not to permit the read request from the read unit when the positional relationship between the write coordinates and the read coordinates does not satisfy a predetermined condition; Image processing device characterized by A plurality of writing units each writing the image data to the memory in units of the first block, the plurality of writing units including the first writing unit and the second writing unit;
The reading unit reads image data from the memory in units of the second block, and while the image data of one frame is being written to the memory by the plurality of writing units, the plurality of writing units perform the plurality of writing operations. A reading unit that outputs a read request for the image data of the frame being written to the memory, and reads the image data from the memory in response to the read request being permitted;
The first writing unit is responsive to writing of a pixel at a predetermined position of the plurality of first blocks included in the image data of the frame being written to the memory. A writing unit that acquires writing coordinates corresponding to the position of the pixel whose writing has been completed, and a pixel at a predetermined position among the plurality of first blocks included in the image data of the frame being written to the memory A writing coordinate acquisition unit that acquires writing coordinates corresponding to the position of the pixel for which writing has been completed by the second writing unit, in response to writing performed by the second writing unit;
A reading coordinate acquisition unit that acquires reading coordinates corresponding to the position of the second block to be read out of the plurality of second blocks in the frame being written to the memory;
Controlling whether or not to permit the read request from the reading unit based on a positional relationship between the writing coordinate acquired by the writing coordinate acquiring unit and the read coordinate acquired by the reading coordinate acquiring unit; The control unit has a control unit that controls not to permit the read request from the read unit when the positional relationship between the write coordinate and the read coordinate does not satisfy a predetermined condition. Image processing device.   The image processing apparatus according to claim 2, wherein the read coordinate acquisition unit updates the read coordinate in accordance with a data transfer length at the time of read.   The image processing apparatus according to any one of claims 1 to 3, wherein a data transfer length at the time of reading is shorter than a data length corresponding to the size of the second block. The writing coordinate acquisition unit writes the first writing coordinates corresponding to the position of the latest line written in the first block to be written, and all the pixels included in the first block. A second writing coordinate corresponding to the last position of the latest first block of the first blocks, and the latest first of the first blocks written at the end of the frame Get the 3rd writing coordinate corresponding to the position of the tail end of 1 block,
The control unit is configured such that the first writing coordinates and the reading coordinates do not satisfy a first condition, and the second writing coordinates and the reading coordinates do not satisfy a second condition; The control method according to any one of claims 1 to 4, wherein, when the third writing coordinate and the reading coordinate do not satisfy the third condition, the reading request from the reading unit is not permitted. An image processing apparatus according to claim 1. The first writing coordinates include horizontal coordinates H _w1 and vertical coordinates V _w1, and the second writing coordinates include horizontal coordinates H _w2 and vertical coordinates V _w2 . The third writing coordinate includes a horizontal coordinate H _w3 and a vertical coordinate V _w3, and the read-out coordinate includes a horizontal coordinate H _R and a vertical coordinate V _R.
The first condition is that H _w1 is H _R or more and V _w1 is V _R or more, and the second condition is that H _w2 is H _R or more and V _w2 is V _R or more. The image processing apparatus according to claim 5, wherein the third condition is that H _w3 is H _R or more and V _w3 is V _R or more. The writing coordinate acquisition unit acquires the writing coordinates based on the writing request output from the writing unit,
The image processing apparatus according to any one of claims 1 to 6, wherein the read coordinate acquisition unit acquires the read coordinate based on the read request output from the read unit. The writing unit writes the plurality of first blocks included in the image data of the one frame to the memory in a predetermined order;
The image according to any one of claims 1 to 7, wherein the reading unit reads the plurality of second blocks included in the image data of the one frame from the memory in the predetermined order. Processing unit.   When all the writing of the plurality of first blocks included in the image data of the one frame is completed, the control unit causes the reading unit to read the data from the reading unit regardless of the positional relationship between the writing coordinates and the reading coordinates. The image processing apparatus according to any one of claims 1 to 8, wherein the read request is permitted.   The coordinates at which writing is started by the writing unit when writing one frame of image data and the coordinates at which reading is started by the reading unit when reading one frame of image data are different from each other. The image processing apparatus according to any one of to 9.   The said writing coordinate acquisition part is characterized by acquiring the said writing coordinate based on the positional relationship of the coordinate by which the writing is started by the said writing part, and the coordinate by which the reading is started by the said reading part. The image processing apparatus according to any one of 1 to 10. An imaging unit,
A first processing unit that performs predetermined processing on image data acquired by the imaging unit;
And a second processing unit that performs predetermined processing on the image data read by the reading unit;
The writing unit writes the image data output from the first processing unit to the memory;
The image processing apparatus according to any one of claims 1 to 11, wherein the reading unit outputs the image data read from the memory to the second processing unit. Writing image data to the memory in units of the first block;
A step of reading image data from the memory in units of a second block, wherein the image data read request of the frame being written to the memory while the image data of one frame is being written to the memory Outputting the image data from the memory in response to the read request being permitted;
Corresponds to the position of the pixel for which writing has been completed in response to writing of a pixel at a predetermined position among the plurality of first blocks included in the image data of the frame being written to the memory Obtaining writing coordinates,
Acquiring the read coordinates corresponding to the position of the second block to be read out of the plurality of second blocks in the frame being written to the memory, the data transfer length at the time of the read Updating the readout coordinates according to
It is a step of controlling whether or not to permit the read request based on the positional relationship between the write coordinate and the read coordinate, wherein the positional relationship between the write coordinate and the read coordinate does not satisfy a predetermined condition And controlling the read request not to be permitted. And writing the image data into the memory by a plurality of writing units in units of a first block, wherein the plurality of writing units include a first writing unit and a second writing unit.
Reading the image data from the memory in units of the second block, the frame being written to the memory while the image data of one frame is being written to the memory by the plurality of writing units; Outputting a read request for the image data, and reading the image data from the memory in response to the read request being permitted;
The first writing is performed in response to writing by a first writing unit of a pixel at a predetermined position among the plurality of first blocks included in the image data of the frame being written. A writing coordinate corresponding to the position of the pixel for which writing has been completed by the unit, and writing the pixel at a predetermined position among the plurality of first blocks included in the image data of the frame being written to the memory Obtaining writing coordinates corresponding to the position of the pixel for which writing has been completed by the second writing unit, in response to the second writing unit performing the writing;
Acquiring a read coordinate corresponding to a position of the second block to be read out of the plurality of second blocks in the frame being written to the memory;
It is a step of controlling whether or not to permit the read request based on the positional relationship between the write coordinate and the read coordinate acquired in the step of acquiring the write coordinate, the write coordinate and the read coordinate And controlling the read request not to be permitted if the positional relationship between and does not satisfy a predetermined condition.

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