JP5622990B2 - Image processing apparatus, image display system, and image processing method - Google Patents

Description

  The present invention relates to a technique for processing an image.

  The video signal used for display on the display device includes images (frames) at a predetermined cycle. An image processing apparatus that processes such a video signal generally uses a frame memory that stores an image in order to adjust the synchronization timing of the video signal. For example, the image processing apparatus periodically writes an image included in the video signal in the frame memory. The image processing apparatus can adjust the synchronization timing of the video signal by periodically reading out images from the frame memory at a predetermined timing.

  The frame memory is provided with a plurality of banks each capable of storing an image. The image processing apparatus prevents an image being written from being read by making the bank to which the image is to be written different from the bank to which the image is to be read.

  Note that there is Patent Document 1 as a document disclosing a technology related to the technology described in this specification.

JP 2001-356916 A

  By the way, the synchronization signal that defines the timing for writing the image to the frame memory and the synchronization signal that defines the timing for reading the image are generated based on different crystal oscillators. There are individual differences in crystal units. For this reason, even if the image writing cycle and the image reading cycle are matched in design, the relative relationship between the image writing timing and the image reading timing changes with time.

  Due to such a change in timing, there is a possibility that the bank to which the image is to be written and the bank from which the image is to be read compete (that is, the same). When such a bank conflict occurs, an incomplete image in the middle of writing may be read.

  For this reason, the conventional image processing apparatus constantly monitors whether or not the bank to be written and the bank to be read conflict, and if there is a conflict, the bank to be read is changed to another bank. Such a conflict was avoided by a complicated method.

  However, when such a complicated method is employed, the circuit scale of the control unit that controls the frame memory increases, which may lead to an increase in cost and a circuit design error.

  The present invention has been made in view of the above problems, and an object of the present invention is to provide a technique capable of avoiding bank competition by a simple method.

In order to solve the above-mentioned problem, the invention of claim 1 is an image processing apparatus for processing an image, comprising: a memory having a plurality of banks assigned consecutive identification numbers; and a first selection of the plurality of banks Writing means for periodically writing an image at a write timing based on a first synchronization signal to a bank of identification numbers corresponding to the values, and a bank of identification numbers corresponding to a second selected value among the plurality of banks , Reading means for periodically reading the image at a reading timing based on a second synchronizing signal different from the first synchronizing signal ; changing means for changing the first selection value in numerical order at each writing timing; and the reading Setting means for setting, as the second selection value, a value obtained by adding a certain offset value to the first selection value at each timing .

  According to a second aspect of the present invention, in the image processing apparatus according to the first aspect, the offset value is -1.

According to a third aspect of the present invention, there is provided an image processing apparatus comprising: a memory having a plurality of banks; and a write based on a first synchronization signal in a write target bank which is one of the plurality of banks. The image is written at a read timing based on a second synchronization signal different from the first synchronization signal from a writing means for periodically writing an image at a timing and a read target bank which is one of the plurality of banks. complete reading means for periodically reading and changing means for changing the write target banks for each of the write timing, the last write of the image by the writing means of the plurality of banks for each of the read timing Setting means for setting the bank as the read target bank.

  According to a fourth aspect of the present invention, there is provided an image display system for displaying an image, wherein the image processing apparatus according to any one of the first to third aspects and an image read by the reading means of the image processing apparatus. Display means for displaying.

The invention of claim 5 is an image processing method for processing an image, wherein (a) a bank of identification numbers corresponding to a first selection value among a plurality of banks to which consecutive identification numbers provided in a memory are allocated. in the step of writing image periodically by the write timing based on the first synchronization signal, and (b) from the bank identification number corresponding to the second selected value of the plurality of banks, the first synchronization signal A step of periodically reading out the image at a read timing based on a different second synchronization signal ; (c) a step of changing the first selection value in numerical order at each write timing ; and (d) at each read timing. Setting a value obtained by adding a certain offset value to the first selection value as the second selection value.

According to a sixth aspect of the present invention, there is provided an image processing method for processing an image, wherein: (a) a write based on a first synchronization signal is written in a write target bank which is one of a plurality of banks included in a memory . A step of periodically writing an image at a read timing ; and (b) from a read target bank, which is one of the plurality of banks, at a read timing based on a second synchronization signal different from the first synchronization signal. A step of periodically reading an image, (c) a step of changing the bank to be written at each write timing , and (d) the step (a) of the plurality of banks at each read timing. And a step of setting a bank in which image writing has been completed most recently as the bank to be read.

  According to the first to fifth aspects of the present invention, a value obtained by adding a certain offset value to the first selection value is set as the second selection value, so that bank competition can be avoided by a simple method.

  In particular, according to the invention of claim 2, since the value obtained by subtracting 1 from the first selection value is set as the second selection value, the image can be read from the bank where the image writing has been completed most recently. Can be processed promptly.

  In particular, according to the invention of claim 3, since the bank in which the writing of the image by the writing means has been completed most recently is set as the reading target bank, bank competition can be avoided by a simple method.

FIG. 1 is a diagram illustrating a schematic configuration of an image display system. FIG. 2 is a diagram illustrating a detailed configuration of the image processing apparatus. FIG. 3 is a diagram illustrating the flow of processing of the processing unit on the writing side of the memory control unit. FIG. 4 is a diagram showing a bank into which successive frames are written. FIG. 5 is a diagram showing the flow of processing of the processing unit on the reading side of the memory control unit. FIG. 6 is a diagram illustrating an example of a relationship between a write target bank and a read target bank. FIG. 7 is a diagram illustrating another example of the relationship between the write target bank and the read target bank.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<1. System configuration>
FIG. 1 is a diagram showing a schematic configuration of an image display system 10 according to the present embodiment. The image display system 10 is mounted on a vehicle such as an automobile, and has a function of displaying an image showing a state of the periphery of the vehicle in a vehicle interior. More specifically, the image display system 10 includes an in-vehicle camera 1 provided behind the vehicle and a display device 3 provided in the vehicle interior, and displays an image showing the rear of the vehicle acquired by the in-vehicle camera 1. It functions as a back monitor system for displaying on the display device 3.

  The image display system 10 includes an image processing device 2 together with the in-vehicle camera 1 and the display device 3. The image processing device 2 adjusts the image acquired by the in-vehicle camera 1 so as to be suitable for display, and causes the display device 3 to display the image. The image processing apparatus 2 includes an image acquisition unit 21, a memory control unit 22, an image output unit 23, and a frame memory 24.

  The image acquisition unit 21 acquires an analog image from the in-vehicle camera 1 at a predetermined cycle and converts the image into a digital image (A / D conversion). Thereby, the image acquisition part 21 outputs the video signal which contains a digital image with a predetermined period. This video signal corresponds to the interlace system, and includes interlaced images (fields) having every other horizontal line at a predetermined period.

  The memory control unit 22 is an integrated circuit such as an ASIC, for example. The memory control unit 22 uses the frame memory 24 to convert a video signal corresponding to the interlace format into a progressive format video signal. At the same time, the memory control unit 22 adjusts the synchronization timing of the video signal so as to match the synchronization timing of the display device 3. Thereby, the memory control unit 22 outputs a video signal that includes a progressive image (frame) having all horizontal lines at a predetermined cycle and whose synchronization timing is adjusted to suit the display.

  The image output unit 23 outputs the video signal output from the memory control unit 22 to the display device 3. Thereby, an image showing a state behind the vehicle is displayed on the display device 3.

  Further, the image display system 10 includes a system control unit 5 that controls the entire system in an integrated manner. The system control unit 5 indicates a vehicle shift position ("P (parking)", "D (forward)", "N (neutral)", "R (reverse)", etc.)) from a shift sensor 9 provided in the vehicle. Receive a signal. Then, when the shift position is “R (reverse)”, the system control unit 5 activates the in-vehicle camera 1, the image processing device 2, and the display device 3, and displays an image indicating the state behind the vehicle. 3 is displayed. Thereby, the user can confirm the state behind the vehicle in substantially real time when the vehicle is moved backward.

<2. Image processing device>
Next, the image processing apparatus 2 will be described in more detail. FIG. 2 is a diagram illustrating a detailed configuration of the image processing apparatus 2.

  As shown in the figure, the frame memory 24 includes four banks B1 to B4. Each of these four banks B1 to B4 is a part of the storage area of the frame memory 24, and these are set in different parts. Each of the four banks B1 to B4 has a storage capacity capable of storing one frame of the video signal.

  Different identification numbers are assigned to the four banks B1 to B4, respectively. Successive integers are adopted for the four identification numbers assigned to the four banks B1 to B4. For example, the identification number of the first bank B1 is “1”, the identification number of the second bank B2 is “2”, the identification number of the third bank B3 is “3”, and the identification number of the fourth bank B4 is “4”. It has become.

  As shown in the figure, the memory control unit 22 includes an image writing unit 41, a write counter 42, an image reading unit 43, and a reading setting unit 44.

  The image writing unit 41 periodically writes an image included in a video signal output from the image acquisition unit 21 (hereinafter referred to as “input video signal”) in the frame memory 24. As described above, the input video signal corresponds to the interlace method, and includes odd fields and even fields alternately. A combination of the odd and even fields is one frame. The input video signal includes a field every 1/60 seconds, for example. Therefore, the input video signal includes a frame every 1/30 seconds.

  The image writing unit 41 periodically writes a frame included in the input video signal to the frame memory 24 (every 1/30 seconds). The image writing unit 41 writes one set of an odd field and an even field to write one frame (a progressive image made up of a set of an odd field and an even field) to the frame memory 24. The image writing unit 41 writes one frame into any one of the four banks B1 to B4.

  The image reading unit 43 periodically reads the progressive image formed in the frame memory 24 from the frame memory 24. The video signal including the image read by the image reading unit 43 in this way is output to the display device 3 via the image output unit 23, and an image included in the video signal (hereinafter referred to as “output video signal”). It is displayed on the display device 3.

  The image reading unit 43 reads frames (progressive images) from any one of the four banks B1 to B4 every 1/30 seconds in accordance with the synchronization timing of the display device 3. As a result, the image reading unit 43 generates an output video signal that includes a frame every 1/30 seconds and whose synchronization timing is adjusted to suit the display.

  The write counter 42 changes a first selection value V1 that is a variable used by the image writing unit 41 to select a bank to which an image is to be written. The writing counter 42 increments the first selection value V1 by 1 in the numerical order every time the image writing unit 41 writes one frame. Specifically, the write counter 42 changes the first selection value V1 in the order of “1”, “2”, “3”, “4”, and when the first selection value V1 is “4” Change to “1”.

  The image writing unit 41 writes the frame in the bank having the identification number corresponding to the first selection value V1. Specifically, when the first selection value V1 is “1”, the image writing unit 41 writes the frame in the first bank B1 having the identification number “1”. Similarly, the image writing unit 41 sets the second bank B2 when the first selection value V1 is “2” and the third bank B3 and the first selection value V1 when the first selection value V1 is “3”. When “4”, the frame is written to the fourth bank B4.

  Further, the read setting unit 44 sets a second selection value V2, which is a variable used by the image reading unit 43 to select a bank from which a frame is to be read. The image reading unit 43 reads the frame from the bank having the identification number corresponding to the second selection value V2 set by the reading setting unit 44. Specifically, the image reading unit 43 reads a frame from the first bank B1 having the identification number “1” when the second selection value V2 is “1”. Similarly, when the second selection value V2 is “2”, the image reading unit 43 sets the second bank B2, and when the second selection value V2 is “3”, the third bank B3 and the second selection value V2 are “2”. In the case of “4”, each frame is read out from the fourth bank B4.

  The cycle in which the image writing unit 41 writes the frame and the cycle in which the image reading unit 43 reads the frame are both 1/30 seconds in design. Therefore, theoretically, the relative relationship between the frame write timing and the frame read timing is constant, and there is no change in the timing interval. However, the synchronization signal that defines the frame write timing and the synchronization signal that defines the frame read timing are generated based on different crystal oscillators. And since there are individual differences in crystal resonators, there is a slight difference between the frame writing cycle and the frame reading cycle, and the relative relationship between the frame writing timing and the frame reading timing increases with time. Change.

  Due to such a change in timing, when the bank to which the frame is to be written competes with the bank from which the frame is to be read (that is, the same), the image writing unit 41 is incomplete during writing. There is a risk that the image reading unit 43 reads a correct image. For example, there is a possibility that the image reading unit 43 reads an image in which the odd lines are the data after overwriting and the even lines are the data before overwriting as a frame.

  The read setting unit 44 sets the second selection value V2 based on the first selection value V1 so as to avoid such bank conflicts. Specifically, the read setting unit 44 sets a value obtained by adding a certain offset value to the first selection value V1 as the second selection value V2, which will be described in detail later.

<3. Processing>
Next, the processing flow of the memory control unit 22 will be specifically described. First, the processing flow of the processing unit (image writing unit 41 and write counter 42) on the writing side of the memory control unit 22 will be described. FIG. 3 is a diagram illustrating a processing flow of the processing unit on the writing side of the memory control unit 22.

  First, based on the synchronization signal of the input video signal, it is determined whether or not it is a write timing for writing one frame of the input video signal (step S11).

  In the case of the write timing (Yes in step S11), first, the write counter 42 increments the first selection value V1 by 1 (step S12). Subsequently, the image writing unit 41 writes one frame in the bank having the identification number corresponding to the first selection value V1. That is, the image writing unit 41 writes a set of an odd field and an even field of the input video signal to one bank (step S13).

  Such processing of the processing unit on the writing side of the memory control unit 22 (steps S12 and S13) is repeated at every writing timing (every 1/30 seconds).

  FIG. 4 is a time chart showing banks in which successive frames F included in the input video signal are written. The write counter 42 sets the first selection value V1 in numerical order (“1”, “2”, “3”, “3”) at every writing timing, that is, every time the image writing unit 41 writes one frame F. 4 ”,“ 1 ”,“ 2 ”... Thereby, the write counter 42 substantially changes the bank to be written by the image writing unit 41 (hereinafter referred to as “write target bank”).

  Therefore, the write target bank is changed in the order of the identification numbers of the four banks B1 to B4. That is, as shown in FIG. 4, the image writing unit 41 selects consecutive frames F (a set of odd and even fields) included in the input video signal in the order of identification numbers (“1”, “2”). , “3”, “4”, “1”, “2”...) Are sequentially written in the four banks B1 to B4.

  Next, a processing flow of the processing unit (image reading unit 43 and reading setting unit 44) on the reading side of the memory control unit 22 will be described. FIG. 5 is a diagram illustrating a processing flow of the processing unit on the reading side of the memory control unit 22.

  First, it is determined whether or not it is the read timing at which one frame of the output video signal is to be read based on the synchronization signal that matches the synchronization timing of the display device 3 (step S21).

  In the case of the read timing (Yes in step S21), first, the read setting unit 44 sets the second selection value V2 based on the first selection value V1. Specifically, the read setting unit 44 acquires from the write counter 42 the first selection value V1 indicating the write target bank at that time. Then, the read setting unit 44 sets a value obtained by adding “+3”, which is a constant offset value, to the first selection value V1 as the second selection value V2 (step S22).

  If the result of adding “3” to the first selection value V1 exceeds “4”, the read setting unit 44 subtracts the total number of banks “4” from the result to the second selection value V2. Set. Accordingly, when the first selection value V1 is “1”, the second selection value V2 is “4”, and when the first selection value V1 is “2”, the second selection value V2 is “1”, and the first selection value. When V1 is “3”, the second selection value V2 is set to “2”, and when the first selection value V1 is “4”, the second selection value V2 is set to “3”.

  Then, the image reading unit 43 reads one frame of the output video signal from the bank having the identification number corresponding to the second selection value V2 (step S23).

  Such processing of the processing unit on the reading side of the memory control unit 22 (steps S22 and S23) is repeated at every reading timing (every 1/30 seconds).

  In the above description, the value obtained by adding the offset value “+3” to the first selection value V1 is set as the second selection value V2. However, in this process, the offset value “−1” is added to the first selection value V1. This is synonymous with setting the value to the second selection value V2. In other words, it can be said that this process is to set a value obtained by subtracting the offset value “+1” from the first selection value V1 as the second selection value V2.

  In other words, the read setting unit 44 substantially sets the bank that the image reading unit 43 reads from the bank that is immediately before the writing target bank in the order of the identification number (hereinafter referred to as “reading”). It is called “Target Bank”). As described above, the write target bank is changed in the order of the identification numbers of the four banks B1 to B4. Accordingly, the read setting unit 44 sets the bank (the previous write target bank) in which the writing of the frame F has been completed most recently as the read target bank.

  In the image display system 10 as described above, the readout setting unit 44 sets a value obtained by adding a certain offset value to the first selection value V1 as the second selection value V2, thereby avoiding bank conflicts.

  FIG. 6 is a time chart showing the relationship between the write target bank and the read target bank when the cycle in which the image writing unit 41 writes the frame is shorter than the cycle in which the image reading unit 43 reads the frame. For convenience of explanation, in the figure, a clear difference is provided between the cycle of writing a frame and the cycle of reading a frame. However, in fact, these differences are slight differences.

  Since the first selection value V1 is changed in order of numbers (“1”, “2”, “3”, “4”, “1”, “2”...) At each writing timing, Are changed in the order of the identification numbers of the four banks B1 to B4.

  On the other hand, the read target bank is set based on the first selection value V1 at the time points T11 to T14 which is the read timing.

  At time T11, the first selection value V1 is “1”, so the second selection value V2 is “4”, and the read target bank is the fourth bank B4. At time T12, since the first selection value V1 is “2”, the second selection value V2 is “1”, and the read target bank is the first bank B1. At time T13, since the first selection value V1 is “4”, the second selection value V2 is “3”, and the read target bank is the third bank B3. At time T14, since the first selection value V1 is “1”, the second selection value V2 is “4”, and the read target bank is the fourth bank B4.

  In this way, at any time point T11 to T14 that is the read timing, the bank in which the writing of the frame F has been completed most recently (the previous write target bank) is set as the read target bank. Therefore, there is no bank conflict. At time T13, the bank to be read moves from the first bank B1 to the third bank B3, and the frames recorded in the second bank B2 are thinned out.

  FIG. 7 is a time chart showing the relationship between the write target bank and the read target bank when the cycle in which the image writing unit 41 writes the frame is longer than the cycle in which the image reading unit 43 reads the frame. For convenience of explanation, in the figure, a clear difference is provided between the cycle of writing a frame and the cycle of reading a frame. However, in fact, these differences are slight differences.

  Also in this case, the first selection value V1 is changed in order of numbers (“1”, “2”, “3”, “4”, “1”, “2”...) At each writing timing. The write target banks are changed in the order of the identification numbers of the four banks B1 to B4.

  Further, the bank to be read is set based on the first selection value V1 at the time points T21 to T26 that are the read timing.

  At time T21, since the first selection value V1 is “1”, the second selection value V2 is “4”, and the read target bank is the fourth bank B4. At time T22, since the first selection value V1 is “2”, the second selection value V2 is “1”, and the read target bank is the first bank B1. At time T23, since the first selection value V1 is “3”, the second selection value V2 is “2”, and the read target bank is the second bank B2. At time T24, since the first selection value V1 is “3”, the second selection value V2 is “2”, and the read target bank is the second bank B2. At time T25, the first selection value V1 is “4”, so the second selection value V2 is “3”, and the read target bank is the third bank B3. At time T26, since the first selection value V1 is “1”, the second selection value V2 is “4”, and the read target bank is the fourth bank B4.

  In this way, at any time T21 to T26 that is the read timing, the bank in which writing of the frame F has been completed most recently (previous write target bank) is set as the read target bank. Therefore, there is no bank conflict. At time T24, the bank to be read is maintained as the second bank B2, and the frames recorded in the second bank B2 are read out redundantly.

  As described above, in the image display system 10, the frame memory 24 has a plurality of banks B1 to B4 to which consecutive identification numbers are assigned. The image writing unit 41 periodically writes the frame in the bank having the identification number corresponding to the first selection value V1. On the other hand, the image reading unit 43 periodically reads frames from the bank having the identification number corresponding to the second selection value V2. The writing counter 42 changes the first selection value V1 in numerical order every time the image writing unit 41 writes a frame. The read setting unit 44 sets a value obtained by adding a certain offset value to the first selection value V1 as the second selection value V2, thereby avoiding bank conflicts. Accordingly, bank conflicts can be avoided by a very simple method of adding a fixed offset value to the first selection value V1. As a result, the circuit scale of the memory control unit 22 that controls the frame memory 24 can be reduced, so that costs can be reduced and circuit design errors can be prevented.

  Further, the read setting unit 44 sets a value obtained by adding “−1” as an offset value to the first selection value V1 as the second selection value V2. That is, the read setting unit 44 sets a bank that has been most recently written by the image writing unit 41 as a read target bank. Therefore, bank conflicts can be avoided by a simple method, and a frame for which writing has been completed can be quickly processed.

<4. Modification>
Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and various modifications are possible. Below, such a modification is demonstrated. All forms including those described in the above embodiment and those described below can be combined as appropriate.

  In the above embodiment, the offset value is described as “+3” or “−1”, but other values may be used.

  Further, in the above-described embodiment, it has been described that the frame writing cycle and the frame reading cycle are identical in design, but the technique described above is applied even when these cycles are different. It is possible.

  In the above-described embodiment, the image display system 10 mounted on the vehicle has been specifically described. However, any image processing apparatus using a frame memory may be used as described above. Can be adopted.

3 Display Device 22 Memory Control Unit 24 Frame Memory 41 Image Writing Unit 42 Write Counter 43 Image Reading Unit 44 Read Setting Unit B1 to B4 Bank F Frame

Claims (6)

An image processing apparatus for processing an image,
A memory having a plurality of banks assigned consecutive identification numbers;
A writing means for periodically writing an image to a bank having an identification number corresponding to a first selection value among the plurality of banks at a writing timing based on a first synchronization signal ;
Reading means for periodically reading the image at a reading timing based on a second synchronization signal different from the first synchronization signal from a bank having an identification number corresponding to a second selection value among the plurality of banks;
Changing means for changing the first selection value in numerical order at each writing timing ;
Setting means for setting, as the second selection value, a value obtained by adding a certain offset value to the first selection value at each reading timing ;
An image processing apparatus comprising: The image processing apparatus according to claim 1.
The image processing apparatus, wherein the offset value is -1. An image processing apparatus,
A memory having a plurality of banks;
Writing means for periodically writing an image to a writing target bank, which is one of the plurality of banks, at a writing timing based on a first synchronization signal ;
Reading means for periodically reading the image from a reading target bank, which is one of the plurality of banks, at a reading timing based on a second synchronization signal different from the first synchronization signal ;
Changing means for changing the write target bank at each write timing ;
Setting means for setting, as the read target bank, a bank in which writing of the image by the writing means has been completed most recently among the plurality of banks at each reading timing ;
An image processing apparatus comprising: An image display system for displaying an image,
An image processing apparatus according to any one of claims 1 to 3,
Display means for displaying the read image on the reading means of the image processing apparatus;
An image display system comprising: An image processing method for processing an image,
(A) a step of periodically writing an image at a write timing based on a first synchronization signal in a bank having an identification number corresponding to the first selection value among a plurality of banks to which consecutive identification numbers provided in the memory are allocated; ,
(B) periodically reading the image at a read timing based on a second synchronization signal different from the first synchronization signal from a bank having an identification number corresponding to a second selection value among the plurality of banks;
(C) changing the first selection value in numerical order at each writing timing ;
(D) setting a value obtained by adding a certain offset value to the first selection value at each read timing as the second selection value;
An image processing method comprising: An image processing method for processing an image,
(A) periodically writing an image at a write timing based on a first synchronization signal to a write target bank that is one of a plurality of banks included in the memory;
(B) periodically reading the image at a read timing based on a second synchronization signal different from the first synchronization signal from a read target bank that is one of the plurality of banks;
(C) changing the write target bank at each write timing ;
(D) setting the bank in which the writing of the image in step (a) was completed most recently among the plurality of banks at each read timing as the read target bank;
An image processing method comprising:

Images