JP2019083348A - Semiconductor device - Google Patents

Abstract

To suppress a data hold time without increasing a circuit area excessively.SOLUTION: A semiconductor device comprises a data buffer 31 and a flip-flop 34 each configured by a fin FET. On a path of a data signal from a data output node of the data buffer 31 to a data input node of the flip-flop 34, gate wiring G on the same layer as gate electrodes of the fin FETs is provided as a delay line 32.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, and for example, is suitably used for a semiconductor device using a fin type field effect transistor (FET).

  In timing design of a semiconductor integrated circuit that operates in synchronization with a clock, it is important that the setup time and hold time of the data signal be within a predetermined range. Therefore, in the conventional semiconductor integrated circuit, the timing time is adjusted by providing a plurality of data buffers in series to the data signal lines (see, for example, Japanese Patent Laid-Open No. 7-66293 (Patent Document 1)).

Japanese Patent Application Laid-Open No. 7-66293

  As the miniaturization of semiconductor integrated circuits progresses, the increase in the data hold time has become a problem in particular because the delay amount of the clock signal line increases. In particular, in a semiconductor integrated circuit using a fin-type FET (referred to as a fin FET: finFET), an increase in data hold time is remarkable. To address this problem, if it is attempted to adjust the delay amount of the data signal by providing a plurality of data buffers in series as in the prior art, a large number of data buffers are required, resulting in an increase in circuit area.

  Other problems and novel features will be apparent from the description of the present specification and the accompanying drawings.

  A semiconductor device according to one embodiment includes a data buffer and a flip flop configured of a fin FET. In the path of the data signal from the data output node of the data buffer to the data input node of the flip flop, the gate wiring of the same layer as the gate electrode of the fin FET is provided as a delay line.

  According to the above embodiment, the data hold time can be suppressed without excessively increasing the circuit area.

1 is a block diagram showing a schematic configuration of a semiconductor device according to a first embodiment. It is a block diagram which shows the structure of the memory circuit of FIG. It is a timing chart for explaining setup time and hold time. It is a perspective view which shows the structure of fin FET typically. It is a top view which shows the concrete structure of the data input part of the data buffer of FIG. 2, a delay line, and a flip flop. FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 5; FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5; FIG. 6 is an equivalent circuit diagram of data buffers 31 and 33 and a delay line 32 of FIG. 5. It is a figure which shows the simulation result of data setup time and data hold time in a table form. It is a figure which shows typically the relationship between data hold time and PVT conditions. It is a block diagram which shows the structure of a memory circuit in the semiconductor device of 2nd Embodiment. It is a block diagram which shows the structure of a memory circuit in the semiconductor device of 3rd Embodiment. It is a block diagram which shows the structure of a memory circuit in the semiconductor device of 4th Embodiment.

  Hereinafter, each embodiment will be described in detail with reference to the drawings. Hereinafter, a computer chip is taken as an example of the semiconductor device, and the input / output circuit of the memory device in the computer chip will be specifically described. However, the following techniques are not limited to memory devices, and can generally be widely applied to semiconductor circuits operating in synchronization with a clock signal.

  In the drawings of the following embodiments, the same or corresponding parts may be denoted by the same reference characters and description thereof may not be repeated. For ease of illustration, the dimensions in plan, cross-sectional, and perspective views showing the structure of the semiconductor device are not proportional to the actual dimensions of the semiconductor device.

First Embodiment
[Overall configuration of semiconductor device]
FIG. 1 is a block diagram showing a schematic configuration of a semiconductor device according to the first embodiment. In FIG. 1, a microcomputer chip is taken as an example of the semiconductor device 1. Referring to FIG. 1, a semiconductor device 1 includes a CPU (Central Processing Unit) 2, a memory circuit 3, an interface (I / O: Input and Output) circuit 4, other peripheral circuits not shown, and the like. And an internal bus 5 for connecting the components.

  The CPU 2 controls the entire semiconductor device 1 by operating according to a program. The memory circuit 3 functions as a main storage device such as a random access memory (RAM) and a read only memory (ROM). Although only one memory circuit 3 is representatively shown in FIG. 1, a plurality of memory circuits such as a dynamic random access memory (DRAM), a static random access memory (SRAM), and a flash memory are actually included. The interface circuit 4 is used for connection with the outside of the semiconductor device. Each component exchanges data signal D, address signal ADR, control signal CS, etc. with each other through internal bus 5.

[Configuration of memory circuit]
FIG. 2 is a block diagram showing the configuration of the memory circuit of FIG. Referring to FIG. 2, memory circuit 3 includes a memory cell array 10, an input / output circuit 11, a word line driver 12, and a control circuit 13. Each transistor constituting the memory circuit 3 is configured by a fin FET.

  Memory cell array 10 includes a plurality of memory cells (not shown) arranged in a matrix along row direction (Y direction) and column direction (X direction). Each memory cell stores one bit of information. In the memory cell array, word lines (not shown) are provided corresponding to the respective rows, and bit lines BL [0] to BL [127] are provided corresponding to the respective columns. The number of bit lines is an example, and the number is not limited to this number.

  The input / output circuit 11 is an interface for inputting write data and outputting read data between the internal bus 5 of FIG. 1 and the memory cell array 10. In FIG. 2, only a circuit portion for inputting write data is shown. Specifically, input / output circuit 11 receives data signals D [0] to D [127] of 128 bits from internal bus 5 of FIG. 1, and applies them to corresponding bit lines BL [0] to BL [127], respectively. Output.

  As shown in FIG. 2, the input / output circuit 11 includes data buffers 31 and 33, a delay line 32, and a D-type flip flop 34 corresponding to each data signal D. Data signal D for each bit input to memory circuit 3 is input to the data input node of flip flop 34 via data buffer 31, delay line 32 and data buffer 33. The data buffer 33 is provided to shape the data signal after passing through the delay line 32, but this is not necessarily required. The more detailed structures of the data buffers 31 and 33 and the delay line 32 will be described with reference to FIGS. As will be described later, in the present embodiment, the delay line 32 is configured by utilizing the structure characteristic of the fin FET.

  Note that a D-type latch circuit may be used instead of the D-type flip flop 34 of FIG. The D-type flip flop 34 responds to an edge (e.g., rising edge) of the clock signal to hold the immediately preceding input signal. On the other hand, the D-type latch circuit bypasses a signal when, for example, the clock signal is high level (H level), and holds an input signal immediately before the clock signal is switched to low level (L level) H level and L level may be reversed). The flip flop 34 and the latch circuit are common in that they are logic circuits for holding the data signal D in synchronization with the clock signal CLK.

  The word line driver 12 activates a word line (not shown) of a row to be read or written. Thereby, each memory cell of the row to be read or written is connected to the corresponding bit line BL.

  The control circuit 13 receives a control signal CS from the CPU 2 of FIG. 1 or a DMA (Direct Memory Access) controller (not shown) via the internal bus 5 and controls the overall operation of the memory circuit 3 based on the control signal CS. . The control signal CS includes a clock signal CLK supplied to each flip flop 34 provided in the input / output circuit 11. The clock signal CLK is input to the clock input node (reference numeral CKin in FIG. 8) of each flip-flop 34 via the clock buffer 20 provided in the control circuit 13.

Timing Control Issues
The problem of timing control in the input / output circuit 11 of the memory circuit 3 of FIG. 2 will be described below.

  FIG. 3 is a timing chart for explaining the setup time and the hold time. The timing diagram of FIG. 3 shows the clock signal CLK and the data signal D input to each flip-flop 34 of FIG.

  Referring to FIG. 3, it is assumed that flip-flop 34 takes in data signal D at the rising edge (time t1) of clock signal CLK. In order to ensure that the data signal D is taken in, data must be determined a predetermined time before the rising edge of the clock signal. This time is called the setup time TSU of the data signal D (from time t0 to time t1). Conversely, after the rising edge of the clock signal, the time to hold the data signal is referred to as the hold time TH of the data signal D (from time t1 to time t2).

  As shown in FIG. 2, in the input / output circuit 11 of the memory circuit 3, the transmission path (clock path 25) of the clock signal CLK is usually longer than the transmission path (data path) of the data signal D. Therefore, the hold time TH is defined as a value obtained by subtracting the delay time DLY (D) of the data signal from the delay time DLY (CLK) of the clock signal as expressed by the following equation (1).

TH = delay (CLK) -delay (D) (1)
The delay time of the clock signal CLK is given by the sum of the delay time DLY (CLK; Tr) of the clock buffer 20 of FIG. 2 and the delay time DLY (CLK; wire) of the clock path. On the other hand, the delay time of the data signal D is the delay time n × DLY (D; Tr) of the data buffer 31, 33 (where n is the number of data buffer stages) and the delay time DLY (D; line) of the delay line 32. Given by and sum. Since the delay time of the data path itself is short, it does not matter. Therefore, the above equation (1) is rewritten as the following equation (2).

TH = DLY (CLK; Tr) + DLY (CLK; wire)-n x DLY (D; Tr)-DLY (D; line) (2)
In the case where each data buffer and flip-flop 34 are configured by a fin FET, an increase in wire resistance due to thinning of wires, and parasitic capacitance between a local wire (LIC: Local Interconnect) and the gate electrode of the fin FET Both the increase and the decrease affect the wire delay DLY (CLK; wire). Therefore, the data hold time TH tends to be larger than that of the conventional planar FET.

  As a countermeasure, if a large number of data buffers 31 and 33 are connected in series without providing the delay line 32 of FIG. 2, the circuit area is increased. Furthermore, when many data buffers 31 and 33 are connected in series, even if the PVT conditions (process, voltage, temperature) conditions are set so as to minimize the delay amount (referred to as MIN conditions), the data hold time There is also a problem that the Because, in the case of the MIN condition, both of the delay time DLY (CLK; Tr) of the clock buffer and the delay time n × DLY (D; Tr) of the data buffer decrease, but the delay time DLY (CLK; wire) hardly decreases.

  In the present embodiment, in consideration of the above points, the delay line 32 is provided in the path of the data signal D of each bit. As described with reference to FIGS. 5 to 7, in the present embodiment, the area reduction of the delay line 32 is realized by utilizing the characteristic structure of the fin FET.

[FinFET configuration]
First, the structure of the fin FET and the method of manufacturing the same will be briefly described.

  FIG. 4 is a perspective view schematically showing the structure of the fin FET. Referring to FIG. 4, the fin FET includes, for example, a plurality of fin interconnections F1 and F2 provided on a P-type semiconductor substrate SUB. Each fin wiring F1, F2 extends in the X direction along the substrate plane. Each fin interconnection F1, F2 is formed by selectively etching the surface of semiconductor substrate SUB. For example, a silicon oxide film formed by using a CVD (Chemical Vapor Deposition) method is provided as an element isolation film ISO between adjacent fin wires F (portions where the fin wires F1 and F2 are not formed). There is.

  The gate electrode G is formed to cover the upper surface and the side surface of each of the fin interconnections F1 and F2 via the gate insulating film GI. The gate electrode G extends in the Y direction which is a direction intersecting the fin interconnections F1 and F2. For the gate electrode G, for example, a semiconductor such as polycrystalline silicon, a conductive compound such as titanium nitride, a single metal such as tungsten, or a laminated film of any of these is used.

  After formation of the gate electrode G, impurities are implanted into the fin wiring F using the gate electrode G as a mask, whereby source and drain regions (not shown) are formed in portions other than the channel region surrounded by the gate electrode G. Here, in the case of fabricating a PMOS (P-channel Metal Oxide Semiconductor) transistor, the fin interconnection F is formed on the N-type well, and a P-type impurity is implanted into the fin interconnection F. In the case of manufacturing an NMOS (N-channel MOS) transistor, the fin wiring F is formed on the P-type substrate or the P-type well, and an N-type impurity is implanted into the fin wiring F.

  A single metal such as tungsten is used to form local interconnections (LIC: Local Inter-Connect) LA1, LA2 extending in the Y direction so as to be in ohmic contact with the upper surfaces and the side surfaces of these source and drain regions. . That is, the local interconnects LA1 and LA2 function as a source electrode and a drain electrode, respectively. Gate interconnection G, source electrode LA1, and drain electrode LA2 are further directly connected to a local interconnection (not shown) extending in the X direction, or an upper layer through a via hole formed in an interlayer insulating layer not shown. Or connected to the metal wiring layer (not shown) of

[Delay line and data buffer structure]
Based on the above-described structure of the fin FET, the data buffers 31, 33, the delay line 32, and the flip flop 34 of FIG. 2 are configured.

  FIG. 5 is a plan view showing a specific structure of the data buffer, the delay line, and the data input portion of the flip flop of FIG. 6 is a cross-sectional view taken along line VI-VI of FIG. 7 is a cross-sectional view taken along the line VII-VII in FIG. FIG. 8 is an equivalent circuit diagram of the data buffers 31 and 33 and the delay line 32 of FIG. 5 to 7 show a CMOS inverter composed of a PMOS transistor and an NMOS transistor as a data input portion of the flip flop 34. In the plan view of FIG. 5, in order to facilitate the illustration, the fin interconnections F1 to F18 are hatched with hatched patterns, and the N-type wells NW1 and NW2 are hatched with dot patterns. 5 to 7, the in-plane direction of the substrate is taken as an X direction and a Y direction, and the direction perpendicular to the substrate is taken as a Z direction.

  5 to 7, a plurality of fin interconnections F1 to F18 extending in the X direction are formed on P type semiconductor substrate SUB (including the regions of N type wells NW1 and NW2). There is. The fin interconnections F1 to F18 have equal widths and are basically formed at equal intervals to improve patterning accuracy. There is also a portion where fin wiring is not formed in a partial region on the substrate. Fin wires F1 and F2 used as PMOS transistors are formed on the N-type well NW1. Similarly, fin interconnections F11, F12, F15, and F16 used as PMOS transistors are formed on the N-type well NW2.

  A plurality of gate lines G1 to G16 are formed to extend in the Y direction intersecting with the extending direction (X direction) of the fin lines F1 to F18. In order to improve the patterning accuracy, the gate wirings G1 to G16 have equal widths and are arranged at equal intervals in the X direction. A gate insulating film GI is interposed between the gate wirings G1 to G3, G5 to G8, G10 to G12, and G14 to G16 and the fin wiring F.

  As the gate wirings G1 to G16, those used as gate electrodes of the fin FET (G2, G11, G15), those used only as local wirings (G1, G3, G4, G5, G8, G9, G9, G10, G12, G13) , G14, G16), and those used as both gate electrodes and local interconnections (G6, G7). In FIG. 5 and FIG. 6, although the gate interconnections G1, G3, G5, G8, G10, G12, G14 and G16 used only as local interconnections are also connected via the fin interconnection F and the gate insulating film GI, It is not necessary that the gate wiring of the first embodiment is electrically connected to the fin wiring.

  Each of the local interconnects LA1 to LA9 is provided so as to cover a part of the fin interconnect F between the adjacent gate interconnects G, and is in ohmic contact with the fin interconnect F. Each of local interconnections LA1 to LA9 is formed to extend in the Y direction (along the extending direction of gate interconnection G).

  An insulating film (not shown) such as a silicon oxide film formed by using a CVD method is filled between the adjacent gate wiring G and the local wiring LA and between the adjacent gate wiring G. Each of local interconnections LB1 to LB9 is formed to extend in the X direction on the above-described filled insulating film. The local interconnects LB1 to LB9 extending in the X direction connect between the adjacent gate interconnects G or between the adjacent gate interconnects G and the local interconnects LA extending in the Y direction. In this case, each local interconnection LB is directly connected to the local interconnection LA (ie, not via a via hole formed in the interlayer insulating layer). Each local interconnection LB is also connected directly to gate interconnection G (that is, without via holes formed in the insulating layer).

  For example, in FIG. 7, the local wiring LB2 is directly connected to the upper surfaces of the gate wirings G3 and G4. The local wiring LB4 is directly connected to the top surfaces of the gate wirings G5 and G6. The local interconnection LB6 is directly connected to the upper surfaces of the gate interconnections G7 and G8. The local interconnection LB8 is directly connected to the upper surfaces of the gate interconnections G9 and G10. The local interconnection LB10 is directly connected to the side surface of the local interconnection LA9 extending in the Y direction, and is also directly connected to the upper surface of the gate interconnection G12. The local interconnection LB12 is directly connected to the upper surfaces of the gate interconnections G13 and G14.

  As shown in FIG. 8, inverters INV1 and INV2 are used as data buffers 31 and 33, respectively. 5 to 7, inverter INV1 (data buffer 31) includes fin interconnections F1 to F4, gate interconnection G2, and local interconnections LA1 to LA3. The fin interconnections F1 and F2 are used as a channel region, a source region, and a drain region of the PMOS transistor constituting the inverter INV1. The local interconnection LA1 is used as a source electrode of the PMOS transistor, and a power supply interconnection (not shown) provided in an upper metal interconnection layer through a via hole (not shown) formed in the interlayer insulating layer (not shown) Connected Thus, power supply potential VDD is applied to local interconnection LA1.

  Similarly, the fin interconnections F3 and F4 are used as a channel region, a source region, and a drain region of the NMOS transistor constituting the inverter INV1. The local interconnection LA2 is used as a source electrode of the NMOS transistor, and is provided with a ground interconnection (not shown) provided in the upper metal interconnection layer via a via hole (not shown) formed in the interlayer insulating layer (not shown). Connected As a result, the ground potential VSS is applied to the local interconnection LA1. Gate interconnection G2 corresponds to data input node Nin1 of inverter INV1 in FIG. 8, and is used as a common gate electrode of the PMOS transistor and the NMOS transistor constituting inverter INV1. Local interconnection LA3 (particularly, portions between fin interconnections F1 to F4 indicated by arrow 40 in FIG. 5) corresponds to data output node Nout1 of inverter INV1 in FIG. 8 and is a common drain electrode of the PMOS and NMOS transistors described above. Used as

  Inverter INV2 (data buffer 33) includes fin interconnections F11 to F14, gate interconnection G11, and local interconnections LA7 to LA9. The fin interconnections F11 and F12 are used as a channel region, a source region, and a drain region of the PMOS transistor constituting the inverter INV2. The local interconnection LA7 is used as a source electrode of the PMOS transistor, and a power interconnection (not shown) provided in the upper metal interconnection layer through a via hole (not shown) formed in the interlayer insulating layer (not shown). Connected Thus, power supply potential VDD is applied to local interconnection LA7.

  Similarly, the fin interconnections F13 and F14 are used as a channel region, a source region, and a drain region of the NMOS transistor constituting the inverter INV2. The local interconnection LA8 is used as a source electrode of the NMOS transistor, and is provided with a ground interconnection (not shown) provided in an upper metal interconnection layer via a via hole (not shown) formed in the interlayer insulating layer (not shown). Connected Thus, the ground potential VSS is applied to the local interconnect LA7. Gate interconnection G11 corresponds to data input node Nin2 of inverter INV2 in FIG. 8, and is used as a common gate electrode of the PMOS transistor and the NMOS transistor described above. The local interconnection LA9 corresponds to the data output node Nout2 of the inverter INV2 of FIG. 8, and is used as a common drain electrode of the PMOS transistor and the NMOS transistor described above.

  Further, an inverter 34 _Din which constitutes an input portion of the flip flop 34 is described in FIG. 5. The inverter 34 _Din constituting the input unit includes fin interconnections F15 to F18, a gate interconnection G15, and local interconnections LA10 to LA12. Fin interconnections F15 and F16 are used as a channel region, a source region, and a drain region of a PMOS transistor forming inverter 34_Din. The local interconnection LA10 is used as a source electrode of the PMOS transistor, and a power interconnection (not shown) provided in an upper metal interconnection layer via a via hole (not shown) formed in the interlayer insulating layer (not shown). Connected Thus, power supply potential VDD is applied to local interconnection LA10.

  Similarly, the fin interconnections F17 and F18 are used as a channel region, a source region, and a drain region of the NMOS transistor constituting the inverter 34_Din. The local interconnection LA11 is used as a source electrode of the NMOS transistor, and is provided with a ground interconnection (not shown) provided in the upper metal interconnection layer via a via hole (not shown) formed in the interlayer insulating layer (not shown). Connected As a result, the ground potential VSS is applied to the local interconnect LA11. Gate interconnection G15 (particularly, portions from fin interconnections F15 to F18 indicated by arrow 41 in FIG. 5) corresponds to data input node Din of flip-flop 34 in FIG. 8 and is a common gate of the PMOS and NMOS transistors described above. It is used as an electrode.

  The delay line 32 is provided between the data output node Nout1 (local wiring LA3) of the inverter INV1 (data buffer 31) and the data input node Nin2 (gate wiring G11) of the inverter INV2 (data buffer 33). Delay line 32 includes gate lines G3 to G10 and local lines LB2 to LB8 connecting adjacent gate lines. Gate interconnection G3 is connected to output node Nout1 (local interconnection LA3) of inverter INV1 (data buffer 31) via local interconnection LB1. Gate interconnection G10 is connected to data input node Nin2 (gate interconnection G11) of inverter INV2 (data buffer 33) via local interconnection LB9. Therefore, the data signal is transmitted to local interconnection LB1, gate interconnection G3, local interconnection LB2, gate interconnection G4, local interconnection LB3, gate interconnection G5, local interconnection LB4, gate interconnection G6, local interconnection LB5, gate interconnection G7, local interconnection LB6, The gate wiring G8, the local wiring LB7, the gate wiring G9, the local wiring LB8, the gate wiring G10, and the local wiring LB9 are transmitted in this order.

  Here, data signal D from data output node Nout1 (portion of arrow 40 of local interconnection LA3) of output buffer 31 (inverter INV1) to data input node Din (portion of arrow 41 of gate interconnection G15) is provided. Of the gate lines pass through the gate lines G3 to G14 and the local lines LB1 to LB13. Therefore, when the semiconductor substrate SUB is planarly viewed from the substrate vertical direction (Z direction), the path length of the data signal D from the data output node Nout1 to the data input node Din connects the data output node Nout1 and the data input node Din. Longer than straight path 42. The linear path 42 is from the right end (+ X direction side) of the local wiring LA3 to the left end (−X direction side) of the gate wiring G15 as shown in FIG. As shown in FIG. 5, the straight path 42 is not limited to the path along the X direction, but may have an oblique direction (as long as it is a straight line passing through the arrow 40 and the arrow 41).

  Further, as shown in FIG. 8, preferably, delay line 32 is connected to a ground node (ground wiring) for supplying ground potential VSS via capacitive elements T1 and T2. The delay time by the delay line 32 can be further increased by the CR delay by the capacitive element.

  The capacitive elements T1 and T2 are configured using the gate capacitance of the fin FET. Specifically, as shown in FIGS. 5 and 6, the fin FET as the capacitive element T1 includes the fin interconnections F5 to F10, the gate interconnection G6 used as the gate electrode, and the locals used as the source electrode and the drain electrode. Wirings LA4 and LA5 are included. The fin FET as the capacitive element T2 includes fin wirings F5 to F10, a gate wiring G7 used as a gate electrode, and local wirings LA5 and LA6 used as a source electrode and a drain electrode. Fin interconnections F5 to F10 and local interconnection LA5 are shared by both fin FETs. Local interconnections LA4 to LA6 are connected to a ground interconnection (not shown) provided in the upper metal interconnection layer through a via hole (not shown) formed in the interlayer insulating layer (not shown). As a result, ground potential VSS is applied to local interconnections LA4 to LA6.

[Effect of First Embodiment]
As described above, by providing the delay line 32 in the path of the data signal D and configuring the delay line 32 including the gate wiring G, the wiring length of the data path can be made longer. The entire circuit area can be reduced as compared with the case where the delay time is adjusted only by the conventional data buffer.

  The gate wiring G is preferably formed using a metal material such as tungsten. The voltage and temperature dependence of the delay time of the metal gate wiring is similar to the voltage and temperature dependence of the delay time of the metal wiring of the upper layer, so the PVT (process, voltage, temperature) dependence of the data hold time is large. can do. This will be described in detail with reference to the simulation results shown in FIGS. 9 and 10 below.

  FIG. 9 is a table showing simulation results of data setup time and data hold time. FIG. 10 schematically shows the relationship between the data hold time and the PVT condition. In FIGS. 9 and 10, the case where the delay line 32 described in FIGS. 5 to 8 is provided is compared with the case where a data buffer is provided instead of the delay line 32. FIG.

  Referring to FIGS. 9 and 10, the MIN condition is a condition under which the delay of the data signal is minimized. Specifically, in the case of the MIN condition, the process condition of the semiconductor device is a condition such that the switching speed of the PMOS transistor and the NMOS transistor is the fastest (the drain current is maximized), and the operating condition of the semiconductor device is a high voltage (0 .88 V) and high temperature (125 ° C.). The MAX condition is a condition under which the delay of the data signal is maximized. Specifically, in the case of the MAX condition, the process condition of the semiconductor device is such a condition that the switching speed of the PMOS transistor and the NMOS transistor is minimized (the drain current is minimized), and the operating condition of the semiconductor device is low voltage (0 .72 V) and low temperature (-40.degree. C.).

  As shown in FIG. 9, when the delay circuit is configured by serially connecting a large number of data buffers without using the above-mentioned delay line 32, even if the PVT condition is changed from the MAX condition to the MIN condition, the data hold is The time (the difference between the delay time of the clock path and the delay time of the data path) decreases only to 88%. On the other hand, by using the delay line 32 of this embodiment, the data hole time is reduced to 54% when the PVT condition is changed from the MAX condition to the MIN condition.

  As described above, according to the semiconductor device of the present embodiment, the delay time of the data path, which has been increased by using a large number of data buffers in the prior art, is provided by providing the delay line 32 instead of the data buffer (ie, Increase the delay time by lengthening the data path wiring. As a result, even when the PVT condition is the MIN condition, the delay time of the data path is not significantly reduced, and therefore, it can be offset with the wiring delay of the clock path. As a result, the data hold time can be shortened.

  Furthermore, since the number of data buffers can be reduced by using the delay line 32 as compared with the case where a delay circuit is configured by connecting a large number of data buffers in series, the effect of reducing the circuit area can be obtained. is there. In particular, in the present embodiment, the area is further reduced by using, as the delay line 32, the gate wiring G in the same wiring layer as the gate electrode used for the fin FET.

Second Embodiment
FIG. 11 is a block diagram showing the configuration of a memory circuit in the semiconductor device of the second embodiment. The input / output circuit 11 in the memory circuit 3 of FIG. 11 differs from the input / output circuit 11 of FIG. 2 in that the repeater buffer 21 is inserted in the middle of the clock path 25 for transmitting the clock signal CLK. Specifically, in FIG. 11, the repeater buffer 21 is provided between the flip flop 34 [63] for the data signal D [63] and the flip flop 34 [64] for the data signal D [64]. The clock signal CLK shaped by the clock buffer 20 is further shaped by the repeater buffer 21. The other points in FIG. 11 are the same as those in FIG. 2 and, therefore, the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated.

  By providing the repeater buffer 21, the number of flip-flops 34 to be driven by the clock buffer 20 is halved, and the wiring length of the clock path 25 is also halved. The remaining half flip-flops 34 and half clock paths 25 are driven by the repeater buffer 21. Therefore, even if the gate delay of repeater buffer 21 increases, the wiring delay and the parasitic capacitance due to the gate of the transistor can be further reduced, thereby further reducing the delay time of the entire transmission path of the clock signal. .

  By reducing the delay time DLY (CLK; wire) of the clock path in the above equation (2), the data hold time can be made shorter when the PVT condition is the MIN condition. Furthermore, if the delay time of the clock path is shortened, the delay time of the data path by the delay line 32 can be shortened accordingly, so the area of each delay line 32 can be further reduced.

Third Embodiment
FIG. 12 is a block diagram showing the configuration of a memory circuit in the semiconductor device of the third embodiment. The input / output circuit 11 in the memory circuit 3 of FIG. 12 differs from the input / output circuit 11 of FIG. 2 in that the clock path 25 is configured in a tree shape. That is, in the case of the third embodiment, the clock signal CLK is input to the plurality of flip flops 34 [0] to 34 [127] through the tree-like signal path. A repeater buffer is provided at a branch point of the clock signal CLK.

  Specifically, in the case of FIG. 12, the clock path is branched into two. One clock path is connected to each clock input node of the flip flops 34 [0] to 34 [63] via the repeater buffer 22. The other clock path is connected to each clock input node of the flip flops 34 [64] to 34 [127] via the repeater buffer 22. The other points in FIG. 12 are the same as in FIG. 2, and therefore the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated.

  By providing the repeater buffers 22 and 23, as in the second embodiment, the delay time of the entire transmission path of the clock signal can be reduced. Therefore, the data hold time can be further shortened when the PVT condition is the MIN condition. Since the delay time of the data path by the delay line 32 can be shortened accordingly by shortening the delay time of the clock path, the area of each delay line 32 can be reduced.

  Furthermore, by configuring the clock paths in a tree shape, it is possible to equalize the path lengths of the clock paths from the clock buffer 20 to the clock input node of each flip-flop 34. Therefore, since the delay time of the clock signal for each flip flop 34 can be made uniform, the data hold time can be improved.

Fourth Embodiment
FIG. 13 is a block diagram showing the configuration of a memory circuit in the semiconductor device of the fourth embodiment. The input / output circuit 11 in the memory circuit 3 of FIG. 13 has a delay line 32 connected to the data output node as the path length of the clock signal from the data output node of the clock buffer 20 to the clock input node of each flip flop 34 becomes longer. This is different from the input / output circuit 11 of FIG. Specifically, in the case of FIG. 13, the delay time of the delay line 32 [127] for the data signal D [127] is the longest, and the delay time of the delay line 32 [0] for the data signal D [0] is the shortest. The delay time of the delay line 32 increases as the path length of the delay line is lengthened, or as the number of capacitive elements connected or the capacitance value increases. The other points in FIG. 13 are the same as those in FIG. 2 and, therefore, the same or corresponding portions are denoted by the same reference characters and description thereof will not be repeated.

  The delay time of the clock signal input to each flip flop 34 increases as the path length from the clock output node of the clock buffer 20 becomes longer. Therefore, the data hold time can be further shortened by increasing the delay time of the data signal in accordance with the delay time of the clock signal.

  As mentioned above, although the invention made by the present inventor was concretely explained based on an embodiment, the present invention is not limited to the above-mentioned embodiment, and can be variously changed in the range which does not deviate from the gist. Needless to say.

  Reference Signs List 1 semiconductor device, 2 CPU, 3 memory circuit, 4 interface circuit, 5 internal bus, 10 memory cell array, 11 input / output circuit, 12 word line driver, 13 control circuit, 20 clock buffer, 21, 22, 23 repeater buffer, 25 Clock path 31, 33 data buffer, 32 delay line, 34 flip flop, CLK clock signal, D data signal, D in flip flop data input node, F1 to F14 fin wiring, G1 to G12 gate wiring, GI gate insulating film, INV1, INV2 inverter, ISO isolation film, LA1 to LA9 local wiring (extending in Y direction), LB1 to LB9 local wiring (extending in X direction), data output node of Nout1 data buffer, NW1, NW2 N type well SUB P-type semiconductor substrate, T1, T2 capacitive element, VDD power supply potential, VSS ground potential.

Claims (19)

A logic circuit having a first data input node for receiving a data signal and a clock input node for receiving a clock signal, and storing the data signal in response to a transition of the clock signal;
A first data buffer having a first data output node connected to the first data input node of the logic circuit to output the data signal;
Equipped with
The logic circuit includes a first transistor formed of a fin-type field effect transistor,
The first transistor has a gate electrode formed of a portion of a first gate interconnection for the first data input node,
The first gate line is formed on a first protrusion of a semiconductor substrate,
In a plan view, the first protrusion extends in a first direction, and the first gate line extends in a second direction orthogonal to the first direction.
The first data buffer includes a second transistor formed of a fin-type field effect transistor,
The second transistor has a drain electrode formed of a portion of a first local interconnection for the first data output node,
The first local wiring is formed on a second protrusion of the semiconductor substrate,
In a plan view, the second protrusion extends along the first direction, and the first local wire extends along the second direction.
A path of the data signal from the first data output node to the first data input node includes a plurality of wirings arranged in the same layer as the first gate wiring and the first local wiring.
The semiconductor device according to claim 1, wherein a length of the path is longer than a distance along the first direction from the first local interconnect to the first gate interconnect in a plan view.   The semiconductor device according to claim 1, wherein the plurality of wirings include first and second wirings extending along the second direction, and a third wiring extending along the first direction. The first wiring is connected to the second wiring via the third wiring,
The semiconductor device according to claim 2, wherein the third wiring is disposed on the first and second wirings.   The semiconductor device according to claim 1, wherein a capacitive element is connected to the plurality of wirings. The plurality of wires have a second gate wire formed on a third protrusion of the semiconductor substrate,
The capacitive element has a gate electrode formed of a part of the second gate wiring, and a source electrode or a drain electrode formed of a part of the second local wiring.
The semiconductor device according to claim 4, wherein the second gate interconnection and the second local interconnection extend along the second direction.   The semiconductor device according to claim 5, wherein the second local wiring is disposed adjacent to the second gate wiring and supplies a ground voltage. The semiconductor device further includes a second data buffer having a second data input node connected to the first data output node, and a second data output node connected to the first data input node.
The plurality of wires are disposed between the second data input node and the first data output node,
The second data buffer includes a third transistor formed of a fin field effect transistor.
The third transistor is formed of a gate electrode formed by a part of a second gate line for the second data input node, and a part of a second local line for the second data output node. And a drain electrode,
The second gate line and the second local line are formed on a third protrusion of the semiconductor substrate,
The semiconductor device according to claim 1, wherein the second gate interconnection and the second local interconnection extend along the second direction in plan view.   The semiconductor device according to claim 1, wherein the logic circuit includes a D-type flip flop or a D-type latch circuit. The semiconductor device further comprises a memory array,
The memory array has a plurality of memory cells,
The plurality of memory cells are connected to a bit line and a word line,
The logic circuit according to claim 1, wherein the logic circuit receives a data signal via the first data input node, receives the clock signal via the clock input node, and supplies the data signal to the bit line. Semiconductor devices. A logic circuit having a first data input node for receiving a data signal and a clock input node for receiving a clock signal, and storing the data signal in response to a transition of the clock signal;
A first data buffer having a first data output node connected to the first data input node of the logic circuit to output the data signal;
Equipped with
The logic circuit includes a first transistor formed of a fin-type field effect transistor,
A path of the data signal from the first data output node to the first data input node includes a plurality of wires.
The semiconductor device according to claim 1, wherein a path of the data signal is meandered by the plurality of wirings in a plan view. The logic circuit includes the first transistor having a gate electrode for the first data input node,
The first data buffer includes a second transistor having a drain electrode for the first data output node,
The semiconductor device according to claim 10, wherein one of the plurality of wirings is disposed in the same layer as the gate electrode and the drain electrode.   The semiconductor device according to claim 11, wherein each of the first and second transistors is a fin field effect transistor. The gate electrode of the first transistor is composed of a part of a first gate line,
The first gate line is formed on a first protrusion of a semiconductor substrate,
In a plan view, the first protrusion extends in a first direction, and the first gate line extends in a second direction orthogonal to the first direction.
The drain electrode of the second transistor is configured of a portion of a first local wiring,
The first local wiring is formed on a second protrusion of the semiconductor substrate,
The semiconductor device according to claim 12, wherein in a plan view, the second protrusion extends along the first direction, and the first local wiring extends along the second direction.   The semiconductor device according to claim 13, wherein the length of the path of the data signal in plan view is longer than a distance along the first direction from the first local interconnection to the first gate interconnection. The plurality of wirings include first and second wirings extending along the second direction, and a third wiring extending along the first direction,
The first wiring is connected to the second wiring via the third wiring,
The semiconductor device according to claim 13, wherein the third wiring is disposed on the first and second wirings.   The semiconductor device according to claim 10, wherein a capacitive element is connected to the plurality of wirings. The semiconductor device further includes a second data buffer having a second data input node connected to the first data output node, and a second data output node connected to the first data input node.
The semiconductor device according to claim 10, wherein the plurality of wires are disposed between the second data input node and the first data output node.   The semiconductor device according to claim 10, wherein the logic circuit includes a D-type flip flop or a D-type latch circuit. The semiconductor device further comprises a memory array,
The memory array has a plurality of memory cells,
The plurality of memory cells are connected to a bit line and a word line,
The logic circuit according to claim 10, wherein the logic circuit receives a data signal via the first data input node, receives the clock signal via the clock input node, and supplies the data signal to the bit line. Semiconductor devices.

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