JP2008130792A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the decrease of obtainable number of chips even when the number of output terminals of a semiconductor chip increases in a LCD driver in which a memory circuit is constituted by a SRAM. <P>SOLUTION: The plane shape of a SRAM cell is rectangle of which the size of one side in parallel to the long side (the direction of X) of the semiconductor chip is longer than the size of the one side in parallel to the short side (the direction of Y). Each gate electrode 7a, 7b, 8a, 8b of six MISFETs consisting the SRAM cell is extending therethrough in a line along the parallel direction (the direction of X) to the long side of the semiconductor chip. Thereby, since the short side of the SRAM cell becomes short, the size of the short side of the semiconductor chip becomes short. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a technique effective when applied to a memory cell layout of an SRAM (Static Random Access Memory) built in an LCD driver.

  Japanese Patent Application Laid-Open No. 09-270468 (Patent Document 1) discloses two driving nMOS transistors (QN1, QN2), two transfer nMOS transistors (QN3, QN4), and two load pMOS transistors (QP1, QP2) discloses a complete CMOS SRAM having memory cells.

  The planar shape of the SRAM cell is a rectangle having a longitudinal direction (X direction). The nMOS transistors (QN1, QN3) are arranged in one end side region (13A) in the X direction, and the nMOS transistors (QN2, QN4) are arranged in a region (13B) opposite to the one end side, and the pMOS transistors (QP1). , QP2) are arranged at the center of the rectangle. Element isolation regions (14A and 14B) are formed between the region (13A) and the region (12) and between the region (13B) and the region (12). The pMOS transistors (QP1, QP2) are arranged on the nMOS transistor (QN1) side and (QN2) side in the region (12), respectively. The bit line direction is perpendicular to the X direction (Y direction), and the word line direction is parallel to the X direction. Furthermore, the nMOS transistors (QN1, QN4) and the pMOS transistor (QP1) are arranged on one end side in the Y direction of the regions (13A, 13B, and 12), respectively. The nMOS transistors (QN3, QN2) and the pMOS transistor (QP2) are It is arranged on the opposite side to the one end side.

  The nMOS transistors (QN3, QN4) each have gates (W10, W20) extending in the X direction. The nMOS transistor (QN1) and the pMOS transistor (QP1) have a common gate (G10) extending in the X direction. The nMOS transistor (QN2) and the pMOS transistor (QP2) have a common gate (G20) extending in the X direction. That is, the gates (W10, W20, G10, G20) of the six MOS transistors all extend in the X direction, and the gates (W10, G20) and the gates (W20, G10) are in the Y direction. Arranged in two rows.

According to the layout described above, the width of the SRAM cell in the Y direction is shortened, and the bit line extending in the Y direction is shortened. Therefore, the capacity and resistance of the bit line are reduced, and the access speed of the complete CMOS SRAM cell is reduced. The effect of improving is acquired.
JP 09-270468 A

  The number of output terminals of an LCD driver built in a mobile phone is increasing as the functionality of the mobile phone increases and the size of a liquid crystal screen increases. Since the output terminal of the LCD driver is arranged along the long side of the semiconductor chip, when the number of output terminals increases, the long side of the semiconductor chip becomes longer and the number of chips obtained from one semiconductor wafer decreases. To do. In order to suppress such a decrease in the number of acquired chips, it is effective to further shorten the length of the short side of the semiconductor chip.

  An LCD driver for a mobile phone includes a memory circuit portion, a logic circuit portion, an input / output circuit portion, an input / output terminal, and the like. The memory circuit portion includes an SRAM that operates with low power consumption in consideration of battery life. Is used.

  The SRAM has a high area occupying ratio among the circuits constituting the LCD driver. Therefore, in order to further shorten the length of the short side of the semiconductor chip, the SRAM having a high area efficiency corresponding to the planar shape of the semiconductor chip. It is required to devise a cell layout.

  An object of the present invention is to provide a technique capable of suppressing a decrease in the number of obtained chips even in the case where the number of output terminals of a semiconductor chip is increased in an LCD driver in which a memory circuit portion is constituted by an SRAM.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  (1) A semiconductor device of the present invention is a semiconductor device in which an SRAM circuit is formed on a main surface of a rectangular semiconductor chip having a pair of long sides and a pair of short sides, and includes a plurality of components constituting the SRAM circuit. Each of the SRAM cells is formed in the first n-type well adjacent to the first p-type well along the long side direction, and the first driving MISFET and the first transfer MISFET formed in the first p-type well. Completely composed of a first load MISFET and a second load MISFET, and a second drive MISFET and a second transfer MISFET formed in a second p-type well adjacent to the first n-type well along the long side direction A first inverter comprising a CMOS type and comprising the first driving MISFET and the first load MISFET, and the second driving MISFET And a second inverter composed of the second load MISFET are cross-coupled to form a flip-flop circuit. The first gate electrode of the first transfer MISFET, the first drive MISFET, and the first load The second gate electrode common to the MISFET for use, the third gate electrode common to the second drive MISFET and the second load MISFET, and the fourth gate electrode of the second transfer MISFET are the long sides, respectively. It extends along the direction and is arranged so as not to overlap each other in the short side direction.

  (2) A semiconductor device according to the present invention is a semiconductor device in which an SRAM circuit is formed on a main surface of a rectangular semiconductor chip having a pair of long sides and a pair of short sides, and a plurality of components constituting the SRAM circuit. Each of the SRAM cells includes a first drive MISFET and a first transfer MISFET formed in the first active region of the first p-type well, and a first n-type adjacent to the first p-type well along the long side direction. The first load MISFET and the second load MISFET formed in the second active region of the well and the third active region of the second p-type well adjacent to the first n-type well along the long side direction. The first driving MISFET and the first load MISFET are configured as a complete CMOS type including the second driving MISFET and the second transfer MISFET. An inverter and a second inverter composed of the second driving MISFET and the second load MISFET are cross-coupled to form a flip-flop circuit, and the first, second, and third active regions are respectively It extends along the long side direction.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  An SRAM cell layout with high area efficiency commensurate with the planar shape of the semiconductor chip constituting the LCD driver can be realized.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is an overall plan view of a semiconductor chip constituting an LCD driver (liquid crystal display driving semiconductor device) for a mobile phone according to the present embodiment.

  The semiconductor chip 1A is made of, for example, a single crystal silicon substrate having a long side (X direction) of 20 to 30 mm and a short side (Y direction) of 1 to 2 mm, and on its main surface, a circuit (SRAM mat) constituting an LCD driver. 101, logic circuit unit 102, input circuit unit 103, and output circuit unit 104). The total number of bits of the SRAM mat 101 is, for example, 1.6 megabits (Mbit). Although not shown, the input circuit portion 103 has a plurality of input terminals arranged in a line along the long side direction of the semiconductor chip 1A, and the output circuit portion 104 has a length of the semiconductor chip 1A. A plurality of output terminals are arranged in one or two rows along the side direction.

FIG. 2 is an equivalent circuit diagram showing an SRAM cell formed on the SRAM mat 101. As shown in FIG. The SRAM cell includes a pair of driving MISFETs (Qd ₁ , Qd ₂ ) and a pair of load MISFETs (Qp) arranged at the intersections of a pair of complementary data lines (DL, / DL) and a word line (WL). ₁ , Qp ₂ ) and a pair of transfer MISFETs (Qt ₁ , Qt ₂ ). The driving MISFETs (Qd ₁ , Qd ₂ ) and the transfer MISFETs (Qt ₁ , Qt ₂ ) are composed of n-channel type MISFETs, and the load MISFETs (Qp ₁ , Qp ₂ ) are composed of p-channel type MISFETs. . That is, the SRAM cell is configured as a complete CMOS type using four n-channel MISFETs and two p-channel MISFETs.

Of the six MISFETs constituting the SRAM cell, the driving MISFET Qd ₁ and the load MISFET Qp ₁ constitute a _first inverter (INV ₁ ), and the driving MISFET Qd ₂ and the load MISFET Qp ₂ constitute a second inverter ( INV ₂ ). The pair of inverters (INV ₁ , INV ₂ ) are cross-coupled in the memory cell to form a flip-flop circuit as an information storage unit that stores 1-bit information.

One output terminal of the flip-flop circuit, the source of the transfer MISFET Qt _1, is connected to one of the drain, the other input terminal, the source of the transfer MISFET Qt _2, is connected to one of the drain. The other of the source and drain of the transfer MISFET Qt ₁ is connected to the data line DL, and the other of the source and drain of the transfer MISFET Qt ₂ is connected to the data line / DL. Further, one end of the flip-flop circuit (one of the sources and drains of the _two load MISFETs Qp ₁ and Qp ₂ ) is connected to a power supply voltage (Vcc) of 1.5 V, for example, and the other end (two drives) The source MISFETs Qd ₁ and Qd ₂ are connected to a reference voltage (Vss) of 0V, for example.

  Next, a specific configuration of the SRAM cell formed on the SRAM mat 101 will be described with reference to FIGS. 3 to 7 are plan views showing a region for one memory cell (a rectangular region surrounded by four + marks), and FIG. 8 is a cross-sectional view taken along line AA in FIG. is there. In order to make the drawings easier to see, the plan views (FIGS. 3 to 7) show only a connection hole connecting a part of the conductive layer constituting the memory cell and the conductive layer, and an insulating film separating the conductive layers. The illustration of is omitted. That is, FIG. 3 mainly shows the gate electrode, the first layer metal wiring, the second layer metal wiring, and their connection positions. FIG. 4 mainly shows a planar layout of the gate electrode. FIG. 5 mainly shows the gate electrode, the first layer metal wiring, and their connection positions. FIG. 6 mainly shows the first layer metal wiring, the second layer metal wiring, and their connection positions. FIG. 7 mainly shows the second-layer metal wiring, the third-layer metal wiring, and their connection positions.

  The SRAM cell is formed in the p-type wells 2p and 3p and the n-type well 4n on the main surface of the silicon substrate 1. Between these wells (p-type wells 2p, 3p and n-type well 4n) and silicon substrate 1, a buried n-type well 4dn is formed to electrically isolate these wells from the wells of other circuits. Has been. The planar shape of the SRAM cell is a rectangle in which the dimension of one side parallel to the long side (X direction) of the semiconductor chip 1A is longer than the dimension of one side parallel to the short side (Y direction).

  The n-type well 4n is formed in a region sandwiched between two p-type wells 2p and 3p. The p-type wells 2p and 3p and the n-type well 4n are separated from each other by an element isolation trench 5 in which an insulating film such as a silicon oxide film is embedded. The p-type wells 2p and 3p, the n-type well 4n, the buried n-type well 4dn, and the element isolation trench 5 are manufactured by a known manufacturing process.

Of the six MISFETs constituting the memory cell, a transfer MISFET Qt ₁ and a driving MISFET Qd ₁ constituted by an n-channel type are formed in the p-type well 2p. The transfer MISFET Qt ₁ is formed on an n-type semiconductor region (source / drain) 9a formed in the p-type well 2p, a gate oxide film 6 formed on the surface of the p-type well 2p, and an upper portion of the gate oxide film 6. And the gate electrode 7a. The driving MISFET Qd ₁ includes an n-type semiconductor region (source / drain) 9a formed in the p-type well 2p, a gate oxide film 6 formed on the surface of the p-type well 2p, and an upper portion of the gate oxide film 6. And the gate electrode 8a formed on the substrate. N-type semiconductor region (source, drain) of the transfer MISFET Qt ₁ one and 9a, the n-type semiconductor region (source, drain) of the driving MISFET Qd ₁ and one 9a is shared with each other.

The p-type well 3p, transfer MISFET Qt ₂ and the driving MISFET Qd ₂ is formed composed of n-channel type. The transfer MISFET Qt ₂ is formed on the n-type semiconductor region (source / drain) 9 b formed in the p-type well 3 p, the gate oxide film 6 formed on the surface of the p-type well 3 p, and the gate oxide film 6. And the gate electrode 7b formed. The driving MISFET Qd ₂ includes an n-type semiconductor region (source / drain) 9b formed in the p-type well 3p, a gate oxide film 6 formed on the surface of the p-type well 3p, and an upper portion of the gate oxide film 6. And the gate electrode 8b formed on the substrate. N-type semiconductor region (source, drain) of the transfer MISFET Qt ₂ one and 9b, the n-type semiconductor region (source, drain) of the driving MISFET Qd ₂ and one of 9b is shared with each other.

In the n-type well 4n, load MISFETs Qp ₁ and Qp ₂ constituted by a p-channel type are formed. The load MISFET Qp ₁ is formed on the p-type semiconductor region (source / drain) 10 a formed in the n-type well 4 n, the gate oxide film 6 formed on the surface of the n-type well 4 n, and the gate oxide film 6. Gate electrode 8a. Further, load MISFET Qp ₂ is, n-type well p type semiconductor region (source, drain) formed in the 4n and 10b, a gate oxide film 6 formed on the surface of the n-type well 4n, the top of the gate oxide film 6 And the gate electrode 8b formed on the substrate. The gate electrode 8a of the load MISFET Qp _1, the are formed on the gate electrode 8a integral with the driving MISFET Qd _1, the gate electrode 8b of the load MISFET Qp ₂ are formed integrally with the gate electrode 8b of the driving MISFET Qd ₂ Has been.

  The six MISFETs constituting the memory cell can be manufactured by a known manufacturing process. For example, each gate oxide film 6 of six MISFETs is formed by thermally oxidizing the surface of a well (p-type wells 2p, 3p, n-type well 4n). The gate electrodes 7a, 7b, 8a and 8b of the six MISFETs are formed by depositing a polycrystalline silicon film on the gate oxide film 6 by the CVD method, and then using the photoresist film as a mask. The silicon film is formed by dry etching. An n-type impurity such as phosphorus is introduced into the polycrystalline silicon film constituting the gate electrodes 7a, 7b, 8a and 8b at the time of film formation. The gate electrodes 7a, 7b, 8a, and 8b can be formed of a polycide film in which a metal silicide film is stacked on a polycrystalline silicon film, a polymetal film in which a metal film is stacked on a polycrystalline silicon film, or the like.

Further, each of the n-type semiconductor region (source, drain) 9a of the n-channel type transfer MISFET Qt ₁ and the driving MISFET Qd ₁ consists in, n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 2p The n-type semiconductor regions (sources and drains) 9b of the transfer MISFET Qt ₂ and the drive MISFET Qd ₂ are formed by ion-implanting n-type impurities (phosphorus or arsenic) into the p-type well 3p. . On the other hand, each of the p-type semiconductor regions (sources and drains) 10a and 10b of the load MISFETs Qp ₁ and Qp ₂ configured by the p-channel type ionizes p-type impurities (boron or boron fluoride) in the n-type well 4n. Form by injecting.

  As shown in FIG. 4, the gate electrodes 7a, 7b, 8a, 8b of the six MISFETs extend in a line along the long side direction (X direction).

  An interlayer insulating film 20 made of a silicon oxide film or the like deposited by the CVD method is formed on the upper part of the memory cell composed of the six MISFETs. A first layer is formed on the interlayer insulating film 20. Metal wiring is formed. As shown in FIG. 5, the first layer metal wirings are the pad layers 11 a, 11 b, 12 a, 12 b, 13 a, 13 b, the first layer local wirings 14 a, 14 b, 15 a, 15 b and the power supply voltage line 16. Further, contact holes 21a, 21b, 22a, 22b, 23a, 23b, 24a, 24b, 25a, 25b, 26a, and 26b are formed in the interlayer insulating film 20 to connect the first layer metal wiring and the MISFET. ing. Plugs 17 made of a tungsten film or the like are formed inside these contact holes.

The gate electrode 7a and the pad layer 11a of the transfer MISFET Qt ₁ are connected to each other via a contact hole 21a, and the gate electrode 7b and the pad layer 11b of the transfer MISFET Qt _2, are connected to each other through the contact hole 21b. N-type semiconductor region (source, drain) of the transfer MISFET Qt ₁ and one pad layer 12a of 9a are connected to each other through the contact hole 22a, the n-type semiconductor region (source, drain) of the transfer MISFET Qt ₂ 9b of One and the pad layer 12b are mutually connected through the contact hole 22b. N-type semiconductor region (source, drain) of the driving MISFET Qd ₁ and one pad layer 13a of 9a are connected to each other through the contact hole 23a, the n-type semiconductor region (source, drain) of the driving MISFET Qd ₂ 9b of One side and the pad layer 13b are mutually connected through the contact hole 23b.

The gate electrode 8a and the first layer local wiring 14a are connected to each other through the contact hole 24a, and the gate electrode 8b and the first layer local wiring 14b are connected to each other through the contact hole 24b. The power supply voltage line 16 extending across the memory cell in the Y direction is connected to _one of the p-type semiconductor regions (source, drain) 10a of the load MISFET Qp1 through the contact hole 27c, and is connected to the load MISFET Qp through the contact hole 27d. _It is connected to one of the _two p-type semiconductor regions (source, drain) 10b.

The n-type semiconductor region 9a shared by the transfer MISFET Qt ₁ and the drive MISFET Qd ₁ and the first layer local wiring 15a are connected to each other through the contact hole 25a, and the p-type semiconductor region (source, MISFET Qp ₁₎ of the load MISFET Qp ₁ is connected. One of the drain) 10a and the first layer local wiring 15a are connected to each other through the contact hole 26a. That is, the transfer MISFET Qt ₁ and p-type semiconductor region (source, drain) of the driving MISFETQd load MISFET Qp ₁ and n-type semiconductor region 9a, which is shared by _a one A of 10a, through the first layer local wiring 15a Are connected to each other.

The n-type semiconductor region 9b shared by the transfer MISFET Qt ₂ and the drive MISFET Qd ₂ and the first layer local wiring 15b are connected to each other through the contact hole 25b, and the p-type semiconductor region (source, drain) of the load MISFET Qp ₂ One of 10b and the first layer local wiring 15b are connected to each other through a contact hole 26b. That is, the transfer MISFET Qt ₂ and the n-type semiconductor region 9b which is shared by the driving MISFET Qd ₂ p-type semiconductor region (source, drain) of the load MISFET Qp ₂ one A of 10b, through the first layer local wiring 15b Are connected to each other.

  The first layer metal wiring (pad layers 11 a, 11 b, 12 a, 12 b, 13 a, 13 b, first layer local wiring 14 a, 14 b, 15 a, 15 b and power supply voltage line 16) is sputtered, for example, on the interlayer insulating film 20. An aluminum alloy film is deposited by the method, and then this aluminum alloy film is formed by dry etching using the photoresist film as a mask.

  An interlayer insulating film 30 made of a silicon oxide film or the like deposited by CVD is formed on the first layer metal wiring, and a second layer metal wiring is formed on the interlayer insulating film 30. ing. As shown in FIG. 6, the second layer metal wirings are the reference voltage lines 27a and 27b, the pad layers 28a and 28b, the second layer local wirings 29a and 29b, and the data lines DL and / DL. Further, in the interlayer insulating film 30, through holes 31a, 31b, 32a, 32b, 33a, 33b, 34a, 34b, 35a, and 35b are formed for connecting the second layer metal wiring and the first layer metal wiring. Has been. Plugs 18 made of a tungsten film or the like are formed inside these through holes.

  The pad layer 28a and the pad layer 11a are connected to each other through the through hole 31a, and the pad layer 28b and the pad layer 11b are connected to each other through the through hole 31b. Data line DL and pad layer 12a are connected to each other through through hole 32a, and data line / DL and pad layer 12b are connected to each other through through hole 32b. The reference voltage line 27a and the pad layer 13a are connected to each other through the through hole 33a, and the reference voltage line 27b and the pad layer 13b are connected to each other through the through hole 33b. The data lines DL and / DL and the reference voltage lines 27a and 27b extend in the Y direction across the memory cells.

The second layer local wiring 29a and the first layer local wiring 15a are connected to each other through the through hole 35a, and the second layer local wiring 29a and the first layer local wiring 14b are connected to each other through the through hole 34b. Yes. That is, the transfer MISFET Qt ₁ and p-type semiconductor region (source, drain) of the driving MISFETQd load MISFET Qp ₁ and n-type semiconductor region 9a, which is shared by _one and one and the gate electrode 8b of the 10a, the first layer local wiring 15a, the second layer local wiring 29a, and the first layer local wiring 14b are connected to each other.

The second layer local wiring 29b and the first layer local wiring 14a are connected to each other through a through hole 34a, and the second layer local wiring 29b and the first layer local wiring 15b are connected to each other through a through hole 35b. Yes. That is, the transfer MISFET Qt ₂ and the n-type semiconductor region 9b which is shared by the driving MISFET Qd ₂ p-type semiconductor region (source, drain) of the load MISFET Qp ₂ and one gate electrode 8a of the 10b, the first layer local wiring 14a, the second layer local wiring 29b, and the first layer local wiring 15b are connected to each other.

  The second layer metal wiring is formed, for example, by depositing an aluminum alloy film on the interlayer insulating film 30 by sputtering, and then dry etching the aluminum alloy film using the photoresist film as a mask.

An interlayer insulating film 40 made of a silicon oxide film or the like deposited by the CVD method is formed on the second layer metal wiring. On the interlayer insulating film 40, in the X direction across the memory cell. An extending third-layer metal wiring is formed. This third layer metal wiring constitutes a word line WL. As shown in FIG. 7, the word line WL and the pad layer 28a are connected to each other through the through hole 41a, and the word line WL and the pad layer 28b are connected to each other through the through hole 41b. Plugs 19 made of a tungsten film or the like are formed in the through holes 41a and 41b. That is, the word line WL, the pad layer 28a (second layer metal wiring) and 11a is connected to the gate electrode 7a of the transfer MISFET Qt ₁ via a (first-layer metal wiring), the pad layer 28b (second layer and it is connected to the gate electrode 7b of the transfer MISFET Qt ₂ via a metal wiring) and 11b (first-layer metal wiring). The word line WL (third layer metal wiring) is formed, for example, by depositing an aluminum alloy film on the interlayer insulating film 40 by a sputtering method and then dry etching the aluminum alloy film using the photoresist film as a mask. Is done.

  As described above, the LCD driver of the present embodiment is configured so that the gate electrodes 7a, 7b, 8a, and 8b of the six MISFETs constituting the SRAM cell are parallel to the long side of the semiconductor chip 1A (X direction). Extends in a row along the line. With this configuration, the size of the short side of the SRAM cell is shorter than before, so the size of the short side of the semiconductor chip 1A is also shorter than before.

  Therefore, as the number of output terminals of the LCD driver increases and the long side dimension of the semiconductor chip 1A becomes longer as the mobile phone becomes more functional and the liquid crystal screen becomes larger, it is obtained from a single semiconductor wafer. It is possible to suppress a decrease in the number of chips.

  In this embodiment, the gate electrodes 7a, 7b, 8a, 8b of the six MISFETs constituting the SRAM cell are arranged in a line along the X direction. However, the gate electrodes 7a, 7b, 8a, 8b They may be arranged shifted in the Y direction within a range in which some of these do not overlap each other.

(Embodiment 2)
The LCD driver according to the present embodiment is different from the first embodiment in the layout of the conductive layers (gate electrode, first layer metal wiring, second layer metal wiring, and third layer metal wiring) constituting the SRAM cell. Yes.

  Hereinafter, a specific configuration of the SRAM cell will be described with reference to FIGS. FIG. 9 mainly shows the gate electrode, the first layer metal wiring, the second layer metal wiring, and their connection positions. FIG. 10 mainly shows a planar layout of the gate electrode. FIG. 11 mainly shows the gate electrode, the first layer metal wiring, and their connection positions. FIG. 12 mainly shows the first layer metal wiring, the second layer metal wiring, and their connection positions. FIG. 13 mainly shows the second-layer metal wiring, the third-layer metal wiring, and their connection positions. 14 is a cross-sectional view taken along line BB in FIG. In order to make the drawings easy to see, the plan views (FIGS. 9 to 13) show only a connection hole connecting a part of the conductive layer constituting the memory cell and the conductive layer, and an insulating film separating the conductive layers. The illustration of is omitted.

As in the first embodiment, the memory cell includes a driving MISFET (Qd ₁ , Qd ₂ ) and a transfer MISFET (Qt ₁ , Qt ₂ ) formed in the p-type wells 2 p and 3 p on the main surface of the silicon substrate 1. And a load MISFET (Qp ₁ , Qp ₂ ) formed in the n-type well 4n. As shown in FIG. 10, the transfer MISFET Qt ₁ and the drive MISFET Qd ₁ are formed in the active region L ₁ of the p-type well 2p, and the transfer MISFET Qt ₂ and the drive MISFET Qd ₂ are formed of the active region L of the p-type well 3p. _The load MISFETs (Qp ₁ , Qp ₂ ) are formed in the active region L ₃ of the n-type well 4n.

Of the six MISFETs constituting the memory cell, the transfer MISFET Qt ₁ includes an n-type semiconductor region (source / drain) 53a formed in the p-type well 2p and a gate formed on the surface of the p-type well 2p. The oxide film 6 includes a gate electrode 50 a formed on the gate oxide film 6. The driving MISFET Qd ₁ includes an n-type semiconductor region (source / drain) 53a formed in the p-type well 2p, a gate oxide film 6 formed on the surface of the p-type well 2p, and an upper portion of the gate oxide film 6. And the gate electrode 51a formed on the substrate. N-type semiconductor region (source, drain) of the transfer MISFET Qt ₁ one and 53a, n-type semiconductor region (source, drain) of the driving MISFET Qd ₁ and one 53a is shared with each other. Further, n-type semiconductor region (source, drain) of the driving MISFET Qd ₁ 53a other is connected to a reference voltage (Vss).

The transfer MISFET Qt ₂ is formed on an n-type semiconductor region (source / drain) 53b formed in the p-type well 3p, a gate oxide film 6 formed on the surface of the p-type well 3p, and an upper portion of the gate oxide film 6. Gate electrode 50b. The driving MISFET Qd ₂ includes an n-type semiconductor region (source / drain) 53b formed in the p-type well 3p, a gate oxide film 6 formed on the surface of the p-type well 3p, and an upper portion of the gate oxide film 6. And the gate electrode 51b formed on the substrate. N-type semiconductor region (source, drain) of the transfer MISFET Qt ₂ one and 53b, the n-type semiconductor region (source, drain) of the driving MISFET Qd ₂ and one 53b is shared with each other. Further, n-type semiconductor region (source, drain) of the driving MISFET Qd ₂ 53b other is connected to a reference voltage (Vss).

The load MISFET Qp ₁ is formed on the p-type semiconductor region (source, drain) 54 formed in the n-type well 4 n, the gate oxide film 6 formed on the surface of the n-type well 4 n, and the gate oxide film 6. Gate electrode 52a. Further, load MISFET Qp ₂ is, n-type well p type semiconductor region (source, drain) formed 4n and 54, a gate oxide film 6 formed on the surface of the n-type well 4n, the top of the gate oxide film 6 And the gate electrode 52b formed on the substrate. _One of the p-type semiconductor regions (source, drain) 54 of the load MISFET Qp _{1 and one} of the p-type semiconductor regions (source, drain) 54 of the load MISFET Qp ₂ are shared with each other and connected to the power supply voltage (Vcc). Has been.

  The six MISFETs constituting the memory cell can be manufactured by a known manufacturing process. For example, the gate electrodes 50a, 50b, 51a, 51b, 52a, 52b of each of the six MISFETs are formed by depositing a polycrystalline silicon film on the gate oxide film 6 by the CVD method, and then using the photoresist film as a mask. The polycrystalline silicon film is formed by dry etching. An n-type impurity such as phosphorus is introduced into the polycrystalline silicon film constituting the gate electrodes 50a, 50b, 51a, 51b, 52a, and 52b at the time of film formation. The gate electrodes 50a, 50b, 51a, 51b, 52a, and 52b may be formed of a polycide film in which a metal silicide film is stacked on a polycrystalline silicon film, a polymetal film in which a metal film is stacked on a polycrystalline silicon film, or the like. it can.

Further, each of the n-type semiconductor region (source, drain) 53a of the n-channel type transfer MISFET Qt ₁ and the driving MISFET Qd ₁ consists in, n-type impurity (phosphorus or arsenic) is ion-implanted into the p-type well 2p The n-type semiconductor regions (source and drain) 53b of the transfer MISFET Qt ₂ and the drive MISFET Qd ₂ are formed by ion-implanting n-type impurities (phosphorus or arsenic) into the p-type well 3p. . On the other hand, in each of the p-type semiconductor regions (sources and drains) 54 of the load MISFETs Qp ₁ and Qp ₂ constituted by the p-channel type, p-type impurities (boron or boron fluoride) are ion-implanted into the n-type well 4n. By forming.

As shown in FIG. 10, the active region _L 1, n-type well active region _{L 2} of the active region _{L 3} and p-type well 3p of 4n of p-type well 2p extends along the X direction. Further, p-type well and the gate electrode 50a of the gate electrode 51a and the transfer MISFET Qt ₁ active region _{L 1} driving MISFET Qd ₁ formed on the 2p, load formed on the n-type well 4n active region _{L 3} The gate electrodes 52a and 52b of the MISFETs (Qp ₁ , Qp ₂ ), the gate electrode 51b of the driving MISFET Qd ₂ formed on the active region L ₂ of the p-type well 3p, and the gate electrode 50b of the transfer MISFET Qt ₂ are Each extends along the Y direction.

  An interlayer insulating film 20 made of a silicon oxide film or the like deposited by the CVD method is formed on the upper part of the memory cell composed of the six MISFETs. An aluminum alloy film is formed on the interlayer insulating film 20. A first layer metal wiring made of, for example, is formed. As shown in FIG. 11, the first layer metal wirings are pad layers 55a, 55b, 56a, 56b and first layer local wirings 57a, 57b, 58a, 58b, 59a, 59b. In addition, contact holes 60a, 60b, 61a, 61b, 62a, 62b, 63a, 63b, 64a, 64b, 65a, and 65b are formed in the interlayer insulating film 20 to connect the first layer metal wiring and the MISFET. ing. Plugs 17 made of a tungsten film or the like are formed inside these contact holes.

The gate electrode 50a and the pad layer 55a of the transfer MISFET Qt ₁ are connected to each other via a contact hole 60a, and the gate electrode 50b and the pad layer 55b of the transfer MISFET Qt _2, are connected to each other through the contact hole 60b. N-type semiconductor region (source, drain) of the transfer MISFET Qt ₁ and one pad layer 56a of 53a are connected to each other through the contact hole 61a, the n-type semiconductor region (source, drain) of the transfer MISFET Qt ₂ 53b of One and the pad layer 56b are connected to each other through the contact hole 61b.

The n-type semiconductor region 53a shared by the transfer MISFET Qt ₁ and the drive MISFET Qd ₁ and the first layer local wiring 57a are connected to each other through the contact hole 62a, and are shared by the transfer MISFET Qt ₂ and the drive MISFET Qd ₂ . The type semiconductor region 53b and the first layer local wiring 57b are connected to each other through the contact hole 62b.

The gate electrode 51a of the driving MISFET Qd ₁ and the first layer local interconnection 58a, are connected to each other via a contact hole 63a, the gate electrode 51b of the drive MISFET Qd ₂ and the first layer local wiring 58b, via a contact hole 63b Are connected to each other.

_One of the p-type semiconductor regions (source, drain) 54 of the load MISFET Qp1 and the first layer local wiring 59a are connected to each other through a contact hole 64a. The gate electrode 52b of the load MISFET Qp ₂ and the first layer local wiring 59a, are connected to each other through the contact hole 65a. Ie, p-type semiconductor region (source, drain) of the load MISFET Qp ₁ and one gate electrode 52b of the load MISFET Qp ₂ 54 are connected to each other via the first-layer local wiring 59a.

P-type semiconductor region (source, drain) of the load MISFET Qp ₂ and one first layer local wiring 59b 54 are connected to each other through the contact hole 64b. The gate electrode 52a of the load MISFET Qp ₁ and the first layer local wiring 59b, are connected to each other through the contact hole 65b. Ie, p-type semiconductor region (source, drain) of the load MISFET Qp ₂ and one gate electrode 52a of the load MISFET Qp ₁ 54 are connected to each other via the first-layer local wiring 59b.

  An interlayer insulating film 30 made of a silicon oxide film or the like deposited by the CVD method is formed on the upper part of the first layer metal wiring, and a second layer made of an aluminum alloy film or the like is formed on the interlayer insulating film 30. A layer metal wiring is formed. As shown in FIG. 12, the second layer metal wirings are pad layers 71a, 71b, second layer local wirings 70a, 70b, 72a, 72b, 73a, 73b and data lines DL, / DL. The interlayer insulating film 30 has through holes 74a, 74b, 75a, 75b, 76a, 76b, 77a, 77b, 78a, 78b, and 79a that connect the second layer metal wiring and the first layer metal wiring. 79b are formed. Plugs 18 made of a tungsten film or the like are formed inside these through holes.

  The pad layer 71a and the pad layer 55a are connected to each other through the through hole 74a, and the pad layer 71b and the pad layer 55b are connected to each other through the through hole 74b. Data line DL and pad layer 56a are connected to each other through through hole 75a, and data line / DL and pad layer 56b are connected to each other through through hole 75b.

  The second layer local wiring 70a and the first layer local wiring 57a are connected to each other through a through hole 76a, and the second layer local wiring 70b and the first layer local wiring 57b are connected to each other through a through hole 76b. Yes. The second layer local wiring 72a and the first layer local wiring 59a are connected to each other through the through hole 78b, and the second layer local wiring 72b and the first layer local wiring 59b are connected to each other through the through hole 78a. Yes.

  Second-layer local wiring 73a and first-layer local wiring 58a are connected to each other through through hole 77a. The second layer local wiring 73a and the first layer local wiring 59b are connected to each other through the through hole 79a. That is, the first layer local wiring 58a and the first layer local wiring 59b are connected to each other through the second layer local wiring 73a.

  Second-layer local wiring 73b and first-layer local wiring 58b are connected to each other through through hole 77b. The second layer local wiring 73b and the first layer local wiring 59a are connected to each other through the through hole 79b. That is, the first layer local wiring 58b and the first layer local wiring 59a are connected to each other through the second layer local wiring 73b.

  An interlayer insulating film 40 made of a silicon oxide film or the like deposited by the CVD method is formed on the second layer metal wiring, and a third layer made of an aluminum alloy film or the like is formed on the interlayer insulating film 40. A layer metal wiring is formed. As shown in FIG. 13, the third layer metal wirings are third layer local wirings 80a and 80b and word lines WL. The interlayer insulating film 40 is formed with through holes 81a, 81b, 82a, 82b, 83a, 83b for connecting these third layer metal wiring and the second layer metal wiring. A plug 19 made of a tungsten film or the like is formed inside.

The word line WL and the pad layer 71a are connected to each other through the through hole 83a, and the word line WL and the pad layer 71b are connected to each other through the through hole 83b. That is, the word line WL, for transfer through the pad layer 71a and is connected to the lower layer of the gate electrode 50a of the pad layer 55a for transfer over the MISFET Qt _1, and the pad layer 71b and the lower pad layer 55b thereof It is connected to the gate electrode 50b of the MISFET Qt _2.

  Third-layer local wiring 80a and second-layer local wiring 70a are connected to each other through through hole 81a. The third layer local wiring 80a and the second layer local wiring 72a are connected to each other through the through hole 82a. That is, the second layer local wiring 70a and the second layer local wiring 72a are connected to each other through the third layer local wiring 80a.

  Third-layer local wiring 80b and second-layer local wiring 70b are connected to each other through through hole 81b. The third layer local wiring 80b and the second layer local wiring 72b are connected to each other through the through hole 82b. That is, the second layer local wiring 70b and the second layer local wiring 72b are connected to each other through the third layer local wiring 80b.

Thus, LCD driver of the present embodiment, the p-type well 2p to six MISFET constituting the SRAM cell is formed the active region _L 1, n-type well 4n active region _{L 3} and p-type well 3p the active region L _2, extends along the X direction. With this configuration, the size of the short side of the SRAM cell is shorter than before, so the size of the short side of the semiconductor chip 1A is also shorter than before.

  Therefore, as the number of output terminals of the LCD driver increases and the long side dimension of the semiconductor chip 1A becomes longer as the mobile phone becomes more functional and the liquid crystal screen becomes larger, it is obtained from a single semiconductor wafer. It is possible to suppress a decrease in the number of chips.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is not limited to the LCD driver for mobile phones, and can be applied to general LCD drivers in which the memory circuit portion is configured by SRAM.

  The present invention can be used for an LCD driver in which the memory circuit portion is configured by SRAM.

1 is an overall plan view of a semiconductor chip constituting an LCD driver for a mobile phone according to an embodiment of the present invention. It is an equivalent circuit diagram showing an SRAM cell formed on the SRAM mat. It is a top view which shows a part (gate electrode, 1st layer metal wiring, 2nd layer metal wiring) of those conductive layers of a memory cell, and those connection positions. It is a top view which shows the plane layout of a gate electrode. It is a top view which shows a part (gate electrode, 1st layer metal wiring) of the conductive layer of a memory cell, and those connection positions. It is a top view which shows a part (1st layer metal wiring, 2nd layer metal wiring) of those conductive layers of a memory cell, and those connection positions. It is a top view which shows a part of conductive layer of a memory cell (2nd layer metal wiring, 3rd layer metal wiring) and those connection positions. It is sectional drawing along the AA line of FIG. It is a top view which shows a part (gate electrode, 1st layer metal wiring, 2nd layer metal wiring) of those conductive layers of a memory cell, and those connection positions. It is a top view which shows the plane layout of a gate electrode. It is a top view which shows a part (gate electrode, 1st layer metal wiring) of the conductive layer of a memory cell, and those connection positions. It is a top view which shows a part (1st layer metal wiring, 2nd layer metal wiring) of those conductive layers of a memory cell, and those connection positions. It is a top view which shows a part of conductive layer of a memory cell (2nd layer metal wiring, 3rd layer metal wiring) and those connection positions. It is sectional drawing along the BB line of FIG.

Explanation of symbols

1 silicon substrate 1A semiconductor chip 2p p-type well 3p p-type well 4n n-type well 4dn buried n-type well 5 element isolation trench 6 gate oxide film 7a, 7b gate electrode 8a, 8b gate electrode 9a, 9b n-type semiconductor region (source ,drain)
10a, 10b p-type semiconductor region (source, drain)
11a, 11b Pad layers 12a, 12b Pad layers 13a, 13b Pad layers 14a, 14b First layer local wiring 15a, 15b First layer local wiring 16 Power supply voltage lines 17, 18, 19 Plug 20 Interlayer insulating films 21a, 21b Contact holes 22a, 22b Contact hole 23a, 23b Contact hole 24a, 24b Contact hole 25a, 25b Contact hole 26a, 26b Contact hole 27a, 27b Reference voltage line 27c, 27d Contact hole 28a, 28b Pad layer 29a, 29b Second layer local wiring 30 Interlayer insulating films 31a, 31b Through holes 32a, 32b Through holes 33a, 33b Through holes 34a, 34b Through holes 35a, 35b Through holes 40 Interlayer insulating films 41a, 41b Through holes 50a, 0b gate electrode 51a, 51b gate electrode 52a, 52b gate electrode 53a, 53b n-type semiconductor region (source, drain)
54 p-type semiconductor region (source, drain)
55a, 55b Pad layers 56a, 56b Pad layers 57a, 57b First layer local wiring 58a, 58b First layer local wiring 59a, 59b First layer local wiring 60a, 60b Contact holes 61a, 61b Contact holes 62a, 62b Contact holes 63a 63b Contact holes 64a, 64b Contact holes 65a, 65b Contact holes 70a, 70b Second layer local wiring 71a, 71b Pad layers 72a, 72b Second layer local wiring 73a, 73b Second layer local wiring 74a, 74b Through hole 75a, 75b Through hole 76a, 76b Through hole 77a, 77b Through hole 78a, 78b Through hole 79a, 79b Through hole 80a, 80b Third layer local wiring 81a, 81b Through hole 82a, 82b Through hole 3a, 83 b through hole 101 SRAM mat 102 the logic circuit section 103 the input circuit section 104 output circuit DL, / DL data lines _INV 1, INV ₂ inverters Qd ₁ driver MISFET
Qd ₂ drive MISFET
Qp ₁ load MISFET
Qp ₂ load MISFET
Qt ₁ transfer MISFET
Qt ₂ transfer MISFET
WL Word line

Claims (11)

A semiconductor device in which an SRAM circuit is formed on a main surface of a rectangular semiconductor chip having a pair of long sides and a pair of short sides,
Each of the plurality of SRAM cells constituting the SRAM circuit is adjacent to the first p-type well along the long side direction with the first driving MISFET and the first transfer MISFET formed in the first p-type well. A first load MISFET and a second load MISFET formed in the first n-type well; a second drive MISFET formed in a second p-type well adjacent to the first n-type well along the long side direction; It is composed of a complete CMOS type consisting of the second transfer MISFET,
A first inverter composed of the first drive MISFET and the first load MISFET and a second inverter composed of the second drive MISFET and the second load MISFET are cross-coupled to form a flip-flop circuit. And
The first gate electrode of the first transfer MISFET, the second gate electrode common to the first drive MISFET and the first load MISFET, and the same to the second drive MISFET and the second load MISFET The third gate electrode and the fourth gate electrode of the second transfer MISFET are arranged so as to extend along the long side direction and not overlap each other in the short side direction. A featured semiconductor device.   2. The semiconductor device according to claim 1, wherein the first, second, third, and fourth gate electrodes extend in a line along the long side direction.   2. The SRAM circuit constitutes a part of an LCD driver circuit, and a plurality of output terminals are arranged along the long side direction on a main surface of the semiconductor chip. The semiconductor device described.   2. The semiconductor device according to claim 1, wherein the first, second, third and fourth gate electrodes are formed by patterning a conductive film of the same layer.   5. A multi-layered metal wiring including a local wiring for forming the flip-flop circuit is formed on the first, second, third and fourth gate electrodes. The semiconductor device described.   The plurality of layers of metal wiring includes a pair of complementary data lines, a power supply voltage line and a reference voltage line extending along the short side direction, and a word line extending along the long side direction. The semiconductor device according to claim 5. A semiconductor device in which an SRAM circuit is formed on a main surface of a rectangular semiconductor chip having a pair of long sides and a pair of short sides,
Each of the plurality of SRAM cells constituting the SRAM circuit includes a first drive MISFET and a first transfer MISFET formed in the first active region of the first p-type well, and the first p along the long side direction. A first load MISFET and a second load MISFET formed in the second active region of the first n-type well adjacent to the well, and a second p-type well adjacent to the first n-type well along the long side direction A second CMOS MISFET and a second transfer MISFET formed in the third active region of the second active MISFET.
A first inverter composed of the first drive MISFET and the first load MISFET and a second inverter composed of the second drive MISFET and the second load MISFET are cross-coupled to form a flip-flop circuit. And
Each of the first, second, and third active regions extends along the long side direction.   8. The SRAM circuit forms part of an LCD driver circuit, and a plurality of output terminals are arranged along the long side direction on the main surface of the semiconductor chip. The semiconductor device described.   The first gate electrode of the first transfer MISFET, the second gate electrode of the first drive MISFET, the third gate electrode of the first load MISFET, and the fourth gate electrode of the second load MISFET 8. The fifth gate electrode of the second transfer MISFET and the sixth gate electrode of the second drive MISFET respectively extend along the short side direction. Semiconductor device.   10. The semiconductor device according to claim 9, wherein the first, second, third, fourth, fifth and sixth gate electrodes are formed by patterning a conductive film of the same layer.   A plurality of layers of metal wiring including a local wiring for forming the flip-flop circuit is formed on the first, second, third, fourth, fifth and sixth gate electrodes. The semiconductor device according to claim 10, wherein:

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