JP2019079528A5 - - Google Patents

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Publication number
JP2019079528A5
JP2019079528A5 JP2018197233A JP2018197233A JP2019079528A5 JP 2019079528 A5 JP2019079528 A5 JP 2019079528A5 JP 2018197233 A JP2018197233 A JP 2018197233A JP 2018197233 A JP2018197233 A JP 2018197233A JP 2019079528 A5 JP2019079528 A5 JP 2019079528A5
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JP
Japan
Prior art keywords
instruction
tiles
tile
processing system
group
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JP2018197233A
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English (en)
Japanese (ja)
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JP2019079528A (ja
JP6797881B2 (ja
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Priority claimed from GB1717291.7A external-priority patent/GB2569269B/en
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Publication of JP2019079528A5 publication Critical patent/JP2019079528A5/ja
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JP2018197233A 2017-10-20 2018-10-19 マルチタイル処理配列における同期化 Active JP6797881B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB1717291.7A GB2569269B (en) 2017-10-20 2017-10-20 Synchronization in a multi-tile processing arrangement
GB1717291.7 2017-10-20

Publications (3)

Publication Number Publication Date
JP2019079528A JP2019079528A (ja) 2019-05-23
JP2019079528A5 true JP2019079528A5 (https=) 2019-09-05
JP6797881B2 JP6797881B2 (ja) 2020-12-09

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JP2018197233A Active JP6797881B2 (ja) 2017-10-20 2018-10-19 マルチタイル処理配列における同期化

Country Status (10)

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US (2) US10564970B2 (https=)
JP (1) JP6797881B2 (https=)
KR (1) KR102262483B1 (https=)
CN (1) CN110214317B (https=)
CA (1) CA3021416C (https=)
DE (1) DE102018126004A1 (https=)
FR (1) FR3072800B1 (https=)
GB (1) GB2569269B (https=)
TW (1) TWI700634B (https=)
WO (1) WO2019076714A1 (https=)

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US12112175B1 (en) 2018-02-08 2024-10-08 Marvell Asia Pte Ltd Method and apparatus for performing machine learning operations in parallel on machine learning hardware
US10970080B2 (en) 2018-02-08 2021-04-06 Marvell Asia Pte, Ltd. Systems and methods for programmable hardware architecture for machine learning
DE102018205392A1 (de) * 2018-04-10 2019-10-10 Robert Bosch Gmbh Verfahren und Vorrichtung zur Fehlerbehandlung in einer Kommunikation zwischen verteilten Software Komponenten
DE102018205390A1 (de) * 2018-04-10 2019-10-10 Robert Bosch Gmbh Verfahren und Vorrichtung zur Fehlerbehandlung in einer Kommunikation zwischen verteilten Software Komponenten
US10929778B1 (en) 2018-05-22 2021-02-23 Marvell Asia Pte, Ltd. Address interleaving for machine learning
US11016801B1 (en) 2018-05-22 2021-05-25 Marvell Asia Pte, Ltd. Architecture to support color scheme-based synchronization for machine learning
US10997510B1 (en) 2018-05-22 2021-05-04 Marvell Asia Pte, Ltd. Architecture to support tanh and sigmoid operations for inference acceleration in machine learning
US10929779B1 (en) * 2018-05-22 2021-02-23 Marvell Asia Pte, Ltd. Architecture to support synchronization between core and inference engine for machine learning
GB2575294B8 (en) * 2018-07-04 2022-07-20 Graphcore Ltd Host Proxy On Gateway
GB2580165B (en) 2018-12-21 2021-02-24 Graphcore Ltd Data exchange in a computer with predetermined delay
KR102670905B1 (ko) * 2019-08-22 2024-05-31 구글 엘엘씨 전파 지연 감소
CN112416053B (zh) * 2019-08-23 2023-11-17 北京希姆计算科技有限公司 多核架构的同步信号产生电路、芯片和同步方法及装置
GB2590658A (en) * 2019-12-23 2021-07-07 Graphcore Ltd Communication in a computer having multiple processors
GB2590661B (en) * 2019-12-23 2022-02-09 Graphcore Ltd Sync network
GB2591106B (en) * 2020-01-15 2022-02-23 Graphcore Ltd Control of data transfer between processors
GB2593756B (en) * 2020-04-02 2022-03-30 Graphcore Ltd Control of data transfer between processing nodes
GB2596872B (en) * 2020-07-10 2022-12-14 Graphcore Ltd Handling injected instructions in a processor
GB2597078B (en) 2020-07-14 2022-07-13 Graphcore Ltd Communication between host and accelerator over network
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