TWI700634B - 具有在多微磚處理配置中之同步的處理系統、操作處理系統之方法、以及相關電腦程式產品 - Google Patents

具有在多微磚處理配置中之同步的處理系統、操作處理系統之方法、以及相關電腦程式產品 Download PDF

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TWI700634B
TWI700634B TW107136463A TW107136463A TWI700634B TW I700634 B TWI700634 B TW I700634B TW 107136463 A TW107136463 A TW 107136463A TW 107136463 A TW107136463 A TW 107136463A TW I700634 B TWI700634 B TW I700634B
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micro
synchronization
brick
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bricks
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TW107136463A
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TW201923556A (zh
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賽門 克里斯汀 諾爾斯
艾倫 葛拉漢 亞歷山大
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英商葛夫科有限公司
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087—Synchronisation or serialisation instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17306—Intercommunication techniques
    • G06F15/17325—Synchronisation; Hardware support therefor
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/80—Architectures of general purpose stored program computers comprising an array of processing units with common control, e.g. single instruction multiple data processors
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30076—Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/3009—Thread control instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/461—Saving or restoring of program or task context
    • G06F9/462—Saving or restoring of program or task context with multiple register sets
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
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    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/48—Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806—Task transfer initiation or dispatching
    • G06F9/4843—Task transfer initiation or dispatching by program, e.g. task dispatcher, supervisor, operating system
    • G06F9/4881—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
    • G06F9/4887—Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues involving deadlines, e.g. rate based, periodic
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/52—Program synchronisation; Mutual exclusion, e.g. by means of semaphores
    • G06F9/522—Barrier synchronisation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N20/00—Machine learning
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/10—Interfaces, programming languages or software development kits, e.g. for simulating neural networks
    • G06N3/105—Shells for specifying net layout
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N5/00—Computing arrangements using knowledge-based models
    • G06N5/02—Knowledge representation; Symbolic representation
    • G06N5/022—Knowledge engineering; Knowledge acquisition
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    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/08—Learning methods
    • G06N3/084—Backpropagation, e.g. using gradient descent

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • Mathematical Physics (AREA)
  • Multimedia (AREA)
  • Data Mining & Analysis (AREA)
  • Artificial Intelligence (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Medical Informatics (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • Biophysics (AREA)
  • General Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • Advance Control (AREA)
  • Executing Machine-Instructions (AREA)
  • Multi Processors (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
TW107136463A 2017-10-20 2018-10-17 具有在多微磚處理配置中之同步的處理系統、操作處理系統之方法、以及相關電腦程式產品 TWI700634B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
??1717291.7 2017-10-20
GB1717291.7A GB2569269B (en) 2017-10-20 2017-10-20 Synchronization in a multi-tile processing arrangement
GB1717291.7 2017-10-20

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TW201923556A TW201923556A (zh) 2019-06-16
TWI700634B true TWI700634B (zh) 2020-08-01

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US (2) US10564970B2 (https=)
JP (1) JP6797881B2 (https=)
KR (1) KR102262483B1 (https=)
CN (1) CN110214317B (https=)
CA (1) CA3021416C (https=)
DE (1) DE102018126004A1 (https=)
FR (1) FR3072800B1 (https=)
GB (1) GB2569269B (https=)
TW (1) TWI700634B (https=)
WO (1) WO2019076714A1 (https=)

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US10970080B2 (en) 2018-02-08 2021-04-06 Marvell Asia Pte, Ltd. Systems and methods for programmable hardware architecture for machine learning
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US11016801B1 (en) 2018-05-22 2021-05-25 Marvell Asia Pte, Ltd. Architecture to support color scheme-based synchronization for machine learning
US10997510B1 (en) 2018-05-22 2021-05-04 Marvell Asia Pte, Ltd. Architecture to support tanh and sigmoid operations for inference acceleration in machine learning
US10929779B1 (en) * 2018-05-22 2021-02-23 Marvell Asia Pte, Ltd. Architecture to support synchronization between core and inference engine for machine learning
GB2575294B8 (en) * 2018-07-04 2022-07-20 Graphcore Ltd Host Proxy On Gateway
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KR102670905B1 (ko) * 2019-08-22 2024-05-31 구글 엘엘씨 전파 지연 감소
CN112416053B (zh) * 2019-08-23 2023-11-17 北京希姆计算科技有限公司 多核架构的同步信号产生电路、芯片和同步方法及装置
GB2590658A (en) * 2019-12-23 2021-07-07 Graphcore Ltd Communication in a computer having multiple processors
GB2590661B (en) * 2019-12-23 2022-02-09 Graphcore Ltd Sync network
GB2591106B (en) * 2020-01-15 2022-02-23 Graphcore Ltd Control of data transfer between processors
GB2593756B (en) * 2020-04-02 2022-03-30 Graphcore Ltd Control of data transfer between processing nodes
GB2596872B (en) * 2020-07-10 2022-12-14 Graphcore Ltd Handling injected instructions in a processor
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CA3021416A1 (en) 2019-04-20
KR20190044570A (ko) 2019-04-30
TW201923556A (zh) 2019-06-16
JP2019079528A (ja) 2019-05-23
JP6797881B2 (ja) 2020-12-09
DE102018126004A1 (de) 2019-04-25
CN110214317A (zh) 2019-09-06
US20200089499A1 (en) 2020-03-19
CN110214317B (zh) 2023-05-02
FR3072800B1 (fr) 2024-01-05
GB2569269B (en) 2020-07-15
GB201717291D0 (en) 2017-12-06
US11593185B2 (en) 2023-02-28
CA3021416C (en) 2021-03-30
GB2569269A (en) 2019-06-19
KR102262483B1 (ko) 2021-06-08
WO2019076714A1 (en) 2019-04-25
US10564970B2 (en) 2020-02-18
US20190121641A1 (en) 2019-04-25
FR3072800A1 (fr) 2019-04-26

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