JP2019074822A - Semiconductor chip - Google Patents

Abstract

To provide a semiconductor chip which can be reset by a clock terminal.SOLUTION: In a semiconductor chip not always provided with a terminal for receiving an external reset request, clock signal receiving means for receiving a clock signal, and pulse width counting means for counting a pulse width of the clock signal and outputting a reset request signal when the count value satisfies a predetermined condition; and reset means for resetting the semiconductor chip when receiving the reset request signal are provided.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a semiconductor chip.

  In recent years, in order to reduce the size of a semiconductor chip, the same external terminal has a plurality of roles. Patent Document 1 discloses a method of setting the operation mode of the microcomputer with a small number of terminals by counting and decoding the number of changes in the signal level input to the operation mode setting terminal.

  Also, for example, in a semiconductor chip such as a serial flash ROM, a function is switched to a data terminal and used while operating a terminal used as a reset immediately after power-on reset is released to improve read performance. Are known.

JP, 2009-99109, A

  However, the prior art disclosed in the above-mentioned Patent Document 1 can not be applied to the clock terminal in order to count the number of level changes. This is because it can not be determined whether the clock is an operation clock. In the serial flash ROM, since the reset terminal is used as a data terminal, it can not be reset.

  Therefore, an object of the present invention is to provide a semiconductor chip capable of performing reset at a clock terminal.

In order to achieve the above object, a semiconductor chip according to the present invention is
In a semiconductor chip not always provided with a terminal for receiving an external reset request, clock signal receiving means for receiving a clock signal, and the pulse width of the clock signal are counted, and the count value satisfies a predetermined condition And a reset means for outputting the reset request signal, and a reset means for resetting the semiconductor chip when the reset request signal is received.

  According to the present invention, it is possible to provide a semiconductor chip which can be reset without separately providing a terminal for receiving an external reset request.

Semiconductor chip in Example 1 Clock waveform in the first embodiment Operation Flow of Pulse Width Counting Unit in Embodiment 1

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.

  The first embodiment will be described below with reference to FIGS. 1 to 3.

  A part of the configuration of the semiconductor chip of the embodiment is shown in FIG.

  In FIG. 1, a semiconductor chip 100 receives a clock 101 and a chip select signal (not shown) as external inputs, and has a clock signal receiving unit 111, a pulse width counting unit 112, a reset unit 113, and a transmitting circuit 114. The semiconductor chip 100 is, for example, a serial flash ROM or the like.

  The clock signal reception unit 111 is an IO buffer of the semiconductor chip 100, and receives the clock 101 from the outside of the semiconductor chip 100. The pulse width counting unit 112 measures the high width and the low width of the clock received by the clock signal receiving unit 111, and determines whether a predetermined condition is satisfied. By operating the pulse width counting unit 112 only when the chip select signal (not shown) is in the enable period, it is possible to select a desired semiconductor chip 100 when a plurality of semiconductor chips 100 are connected in parallel. . Details of the operation flow will be described later. The pulse width counting unit 112 has a memory unit (not shown) that holds the count value. The transmission circuit 114 generates a clock for counting of the pulse width counting unit 112. The transmission circuit 114 is configured by, for example, a ring oscillator. The reset unit 113 resets the semiconductor chip 100 when the pulse width counting unit 112 satisfies a predetermined condition.

  FIG. 2 shows an example of the clock 101 received by the semiconductor chip 100.

  In FIG. 2, reference numeral 201 denotes a high width of the clock signal 101, and reference numeral 202 denotes a low width of the clock signal 101. Further, reference numeral 211 denotes a disable period of a chip select signal (not shown in FIG. 1) which is an input signal of the semiconductor chip 100, and reference numeral 212 denotes an enable period. The pulse width counting unit 112 counts the High width 201 and the Low width 202 for a plurality of cycles.

  FIG. 3 is an operation flow of the pulse width counting unit 112.

  In S300, it is determined whether a chip select signal (not shown in FIG. 1), which is an input signal of the semiconductor chip 100, indicates Enable 212. In the case of YES, the process proceeds to S301, and in the case of NO, the flow of FIG. 3 is ended.

  In S301, the high width 201 and the low width 202 of the clock 101 are measured. The measurement is performed using a clock generated by the transmission circuit 114. In step S302, the frequency of the clock 101 is calculated using the result of measurement in step S301, and it is determined whether the frequency is equal to or less than a predetermined frequency. The frequency can be calculated by 1 / (High width 201 + Low width 202). Here, the predetermined frequency is assumed to be a low frequency that is not normally used in the semiconductor chip 100. For example, when the semiconductor chip 100 is a serial flash ROM, a predetermined frequency is 1 MHz because a frequency of MHz order is used for processing such as READ, and YES is processed when a frequency lower than that is input. If YES, the process proceeds to S303, and if NO, the flow of FIG. 3 is ended.

  In step S303, the duty ratio of the clock 101 is calculated using the result of measurement in step S301, and it is determined whether it is equal to or less than a predetermined duty ratio. The duty ratio can be calculated by Low width 202 / High width 201. Here, the predetermined DUTY ratio is assumed to be a DUTY ratio not normally used in the semiconductor chip 100. For example, when the semiconductor chip 100 is a serial flash ROM, since a clock with a duty ratio of about 50% is used for processing such as READ, a predetermined duty ratio is set to 10%, and a duty ratio smaller than that is input. Process as YES in the case. In S303, it is determined whether or not the predetermined DUTY ratio is equal to or less than the predetermined duty ratio, but it may be determined based on whether or not the predetermined DUTY ratio is equal to or more. For example, if the predetermined duty ratio is 90% and the clock 101 having a duty ratio higher than 90% is input, it can be determined as YES. In S303, in the case of YES, the process proceeds to S304, and in the case of NO, the flow of FIG. 3 is ended.

  Although only one cycle of the clock 101 is measured in the process of S300 to S303 in the operation flow of FIG. 3, a plurality of cycles may be measured. In that case, the process of performing the processes of S300 to S303 multiple times is performed. By performing the process of S304 only when the condition determination of S303 becomes YES continuously in a plurality of cycles, it is possible to prevent a malfunction due to noise or the like of the clock 101. In S304, the semiconductor chip 100 is reset.

  From the operation flow shown in FIG. 3, it can be determined whether the clock for actual operation or the clock for reset is required, and the semiconductor chip 100 can be reset even when the semiconductor chip 100 does not always have a reset terminal. It becomes.

  As mentioned above, although the preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

100 semiconductor chips, 101 clocks, 111 clock signal reception units,
112 pulse width counting unit, 113 reset unit, 114 transmitting circuit

Claims (5)

In a semiconductor chip not always provided with a terminal for receiving an external reset request,
Clock signal receiving means for receiving a clock signal;
Pulse width counting means for counting the pulse width of the clock signal and outputting a reset request signal when the count value satisfies a predetermined condition;
Reset means for resetting the semiconductor chip when receiving the reset request signal;
A semiconductor chip characterized by having. The pulse width counting means counts the HIGH width and the LOW width of the clock signal one or more times,
The frequency of the clock signal obtained from the HIGH width and the LOW width is less than an arbitrary threshold, and the duty ratio of the clock signal obtained from the HIGH width and the LOW width is an arbitrary threshold The semiconductor chip according to claim 1, wherein the reset request signal is output when the duty ratio is equal to or higher than a duty upper limit threshold. The pulse width counting means counts the HIGH width and the LOW width of the clock signal one or more times,
The frequency of the clock signal obtained from the HIGH width and the LOW width is less than an arbitrary threshold, and the duty ratio of the clock signal obtained from the HIGH width and the LOW width is an arbitrary threshold The semiconductor chip according to claim 1, wherein the reset request signal is output when the duty ratio is lower than or equal to the DUTY lower limit threshold.   The pulse width counting means outputs the reset request signal when it continuously detects that the duty ratio is equal to or more than the DUTY upper limit threshold or equal to or less than the DUTY lower limit threshold a predetermined number of times. Or the semiconductor chip of Claim 3. It also has a chip select terminal,
The semiconductor chip according to any one of claims 1 to 4, wherein the pulse width counting unit operates only when the chip select terminal indicates "enable".