JP2019047104A - Motor drive circuit, semiconductor apparatus, and electronic device - Google Patents

Abstract

To suppress an increase in a circuit area while preventing structural breakdown caused by a parasitic bipolar transistor in a motor drive circuit.SOLUTION: An H bridge circuit connected to nodes N1 and N2 for a power source and nodes N3 and N4 for a motor includes, in a P-type semiconductor substrate, a PchMOS transistor that is disposed in an N-type first region and is connected between N1 and N3, an NchMOS transistor that is disposed in an N-type second region and is connected between N2 and N3, a PchMOS transistor that is disposed in an N-type third region and is connected between N1 and N4, and the NchMOS transistor that is disposed in an N-type fourth region and is connected between N2 and N4. A distance between the N-type first region and the N-type third region is smaller than a distance between the N-type first region and the N-type second region, smaller than a distance between the N-type third region and the N-type fourth region, and smaller than a distance between the N-type second region and the N-type fourth region.SELECTED DRAWING: Figure 5

Description

  The present invention relates to a motor drive circuit for driving a motor. Furthermore, the present invention relates to a semiconductor device incorporating such a motor drive circuit, an electronic device using such a semiconductor device, and the like.

  For example, in a motor driver IC, driving a direct current motor is performed using a motor drive circuit having a bridge circuit configured by connecting a high side transistor and a low side transistor in series. Generally, an H bridge circuit (also referred to as a full bridge circuit) is configured by combining two sets of high side and low side transistors, and the connection point of the first set of transistors and the connection point of the second set of transistors Two terminals of the motor are connected between them. Thereby, the direction of the current flowing to the motor can be set arbitrarily.

  In order to flow a large current to the motor, the high side transistor may be configured by a P channel ED (Extended Drain) MOS transistor, and the low side transistor may be configured by an N channel LD (Lateral Double-diffused) MOS transistor. In that case, the high-side transistor and the low-side transistor are disposed, for example, in an N-type first impurity region and an N-type second impurity region provided on a P-type semiconductor substrate. As a result, a parasitic NPN bipolar transistor is formed with the N-type first impurity region as a collector, the P-type semiconductor substrate as a base, and the N-type second impurity region as an emitter.

  A high potential side power supply potential (for example, +42 V) is supplied to the first impurity region, and a low potential side power supply potential (for example, 0 V) is supplied to the semiconductor substrate. In the second impurity region, the N-type drain of the low-side transistor is disposed, and one terminal of the motor is electrically connected to the drain. When the regenerative current flows in the high speed decay (decay) mode, a negative potential (for example, about −1 V) is applied from one terminal of the motor to the second impurity region.

  As a result, current flows from the base to the emitter of the parasitic transistor, and the parasitic transistor conducts. When hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current exceeding the allowable limit may flow to cause structural destruction of the IC. In the prior art, in order to keep the hFE of the parasitic transistor below the allowable value, measures are taken to make the distance between the plurality of transistors sufficiently large.

  As a related technology, Patent Document 1 discloses a semiconductor device including an H-bridge circuit which is configured by four power transistors per channel and is used for drive control of a motor. In FIG. 8 of Patent Document 1, the horizontal spacing and the vertical spacing of the cell portions 21 22 25 26 corresponding to the four power transistors forming the H bridge circuit are all equal and represented as Z. There is.

  Further, Patent Document 2 discloses a power supply device that includes a bridge rectification circuit configured of four transistors, and rectifies an AC voltage to supply DC power. In paragraphs 0069-0070 and FIG. 2 of Patent Document 2, as a measure against latch-up caused by the parasitic transistor being conductive, the P channel transistors P1 and P2 are surrounded by the high potential side power supply line LVdd, and the N channel transistor N3 and It is described that the N4 is surrounded by the low potential side power supply line LVss, and the distance between the transistors P1, P2, N3 and N4 is sufficiently separated.

JP, 2009-181996, A (paragraph 0001-0002, 0049-0050, FIG. 8) Unexamined-Japanese-Patent No. 2003-309978 (Paragraphs 0001-0003, 0069-0070, FIG. 2)

  However, as described in Patent Document 2, if the distance between the plurality of transistors is sufficiently separated and the transistors are separated, it is possible to prevent the latch-up caused by the parasitic transistors becoming conductive. The circuit area (chip size) increases. Further, Patent Documents 1 and 2 do not disclose that the high-side transistor and the low-side transistor are disposed in a plurality of impurity regions (wells and the like) of the same conductivity type.

  Therefore, in view of the above-described points, a first object of the present invention is to provide a motor drive circuit including a plurality of impurity regions of the same conductivity type in which a plurality of transistors forming an H bridge circuit are arranged or conductive and the opposite conductivity. It is an object to suppress an increase in circuit area while preventing a structural breakdown caused by a parasitic bipolar transistor formed with a semiconductor substrate of the type becoming conductive. A second object of the present invention is to provide a semiconductor device incorporating such a motor drive circuit. Furthermore, a third object of the present invention is to provide an electronic device and the like using such a semiconductor device.

  In order to solve at least a part of the above problems, a motor drive circuit according to a first aspect of the present invention includes a first node supplied with a first power supply potential, and a voltage lower than the first power supply potential. A first H bridge connected to a second node to which a second power supply potential is supplied and to a third node and a fourth node respectively connected to two terminals of a motor to be driven A first H bridge circuit disposed in an N-type first impurity region in a P-type semiconductor substrate, the first P-bridge circuit connected between the first node and the third node; A channel MOS transistor and an N-type second impurity region in the semiconductor substrate, or an N-type second impurity region disposed directly on the semiconductor substrate and having a second node and a third node First N channel connected between the A MOS transistor, a second P-channel MOS transistor disposed in an N-type third impurity region in the semiconductor substrate and connected between the first node and the fourth node, and N-type in the semiconductor substrate A second impurity region disposed in the fourth impurity region or directly disposed in the semiconductor substrate, having an N-type fourth impurity region, and connected between the second node and the fourth node An N-channel MOS transistor, and the distance between the first impurity region and the third impurity region is smaller than the distance between the first impurity region and the second impurity region, The distance is smaller than the distance between the impurity region and the fourth impurity region, and smaller than the distance between the second impurity region and the fourth impurity region.

  Here, the first P channel MOS transistor is an EDMOS transistor, the second P channel MOS transistor is an EDMOS transistor, the first N channel MOS transistor is an LDMOS transistor, and the second N channel is The MOS transistor may be an LDMOS transistor.

  In the motor drive circuit according to the second aspect of the present invention, a first node supplied with a first power supply potential and a second power supply potential lower than the first power supply potential are supplied A first H-bridge circuit includes a first H-bridge circuit connected to a second node and to a third node and a fourth node respectively connected to two terminals of a motor to be driven. A first N-channel EDMOS transistor disposed in the P-type first impurity region in the N-type semiconductor substrate and connected between the second node and the third node; and P-type in the semiconductor substrate A first P-channel LDMOS transistor disposed in the second impurity region and connected between the first node and the third node, and disposed in the P-type third impurity region in the semiconductor substrate; 2 nodes and 4th A second N-channel EDMOS transistor connected between the node and the second N-channel EDMOS transistor disposed in a P-type fourth impurity region in the semiconductor substrate and connected between the first node and the fourth node And the distance between the first impurity region and the third impurity region is smaller than the distance between the first impurity region and the second impurity region, The distance is smaller than the distance between the impurity region and the fourth impurity region, and smaller than the distance between the second impurity region and the fourth impurity region.

  According to the first or second aspect of the present invention, in the motor drive circuit, a plurality of impurity regions of the same conductivity type in which a plurality of transistors forming the H bridge circuit are arranged or configured and a semiconductor of the opposite conductivity type Possibility that the parasitic transistor can be conducted on the circuit operation while suppressing the hFE (DC current amplification factor) of the parasitic bipolar transistor formed by the substrate to a permissible value or less to prevent the structural breakdown caused by the parasitic transistor becoming conductive. By reducing the distance between the low first impurity region and the low third impurity region, an increase in circuit area can be suppressed and the cost can be suppressed.

  Here, the distance between the first impurity region and the second impurity region, the distance between the third impurity region and the fourth impurity region, and the second impurity region and the fourth impurity region And the distance between and may be equal to each other. Thus, between the first impurity region and the second impurity region, between the third impurity region and the fourth impurity region, and between the second impurity region and the fourth impurity region. The layout efficiency can be improved by making the hFE of the parasitic transistors respectively formed substantially the same.

  In the semiconductor substrate, the motor drive circuit further includes a side of the first impurity region on the side of the second impurity region, and a portion of the second impurity region between the first impurity region and the second impurity region. At least one first guard region of the same conductivity type as the semiconductor substrate, extending along the side on the first impurity region side, and the third impurity region and the fourth impurity region in the semiconductor substrate And extends along a side of the third impurity region on the side of the fourth impurity region and a side of the fourth impurity region on the side of the third impurity region, at least having the same conductivity type as the semiconductor substrate. The side of the second impurity region on the fourth impurity region side, and the fourth impurity, between one second guard region and the semiconductor substrate between the second impurity region and the fourth impurity region Extends along the side of the second impurity region side of the region, and It may further comprise at least one third guard region of one conductivity type. Thereby, between the first impurity region and the second impurity region, between the third impurity region and the fourth impurity region, and between the second impurity region and the fourth impurity region. The depletion layer can be prevented from spreading to cause punch-through.

  In that case, the motor drive circuit includes a plurality of first guard regions, a plurality of second guard regions, and a plurality of third guard regions, and the first impurity region and the Extending along the side of the first impurity region on the side of the third impurity region and the side of the third impurity region on the side of the first impurity region between the third impurity region and the semiconductor substrate; And at least one fourth guard region of the same conductivity type, wherein the number of fourth guard regions is less than the number of first guard regions and less than the number of second guard regions. The number may be smaller than the number of guard areas. Thus, the number of fourth guard regions provided between the first impurity region and the third impurity region, which are less likely to cause punch-through on the circuit operation, is reduced to suppress an increase in circuit area. can do.

  Alternatively, in the semiconductor substrate, the motor drive circuit may include a side of the first impurity region on the third impurity region side and a third impurity region between the first impurity region and the third impurity region. The semiconductor device further includes a fourth guard region of the same conductivity type as the semiconductor substrate, extending along the side on the first impurity region side, and the width of the fourth guard region is larger than the width of the first guard region. It may be smaller, smaller than the width of the second guard area, and smaller than the width of the third guard area. As a result, the width of the fourth guard region provided between the first impurity region and the third impurity region, which is less likely to cause punch-through on the circuit operation, is reduced to suppress an increase in the circuit area. can do.

  In the above, the motor drive circuit further includes a second H bridge circuit having the same configuration as the first H bridge circuit, and the first to fourth impurity regions and the second H of the first H bridge circuit. The distance between the first to fourth impurity regions of the bridge circuit may be equal to or greater than the distance between the second impurity region and the fourth impurity region in the first or second H bridge circuit. . Thereby, a parasitic bipolar transistor formed of a plurality of impurity regions of the same conductivity type and a semiconductor substrate of the opposite conductivity type, in which a plurality of transistors forming the first and second H bridge circuits are arranged or configured The hFE can be suppressed below the allowable value to prevent structural damage caused by the parasitic transistor conducting.

  Alternatively, the motor drive circuit extends between the first H bridge circuit and the second H bridge circuit in the semiconductor substrate, with the second H bridge circuit having the same configuration as the first H bridge circuit. And a plurality of fifth guard regions of the same conductivity type as the semiconductor substrate, wherein the number of fifth guard regions is equal to or greater than the number of first guard regions, and equal to or greater than the number of second guard regions. And may be equal to or more than the number of third guard areas. Thereby, punch-through between the first H bridge circuit and the second H bridge circuit can be effectively prevented.

  Alternatively, the motor drive circuit extends between the first H bridge circuit and the second H bridge circuit in the semiconductor substrate, with the second H bridge circuit having the same configuration as the first H bridge circuit. And a fifth guard region of the same conductivity type as the semiconductor substrate, wherein the width of the fifth guard region is greater than or equal to the width of the first guard region and greater than or equal to the width of the second guard region. , And may be equal to or more than the width of the third guard area. Thereby, punch-through between the first H bridge circuit and the second H bridge circuit can be effectively prevented.

  According to a third aspect of the present invention, there is provided a semiconductor device according to any one of the above motor driving circuits and the fifth impurity region disposed in the fifth impurity region in the semiconductor substrate or directly disposed in the semiconductor substrate. And a switching regulator control circuit including a transistor disposed in the sixth impurity region in the semiconductor substrate or directly disposed in the semiconductor substrate and having the sixth impurity region. The distance between the fifth impurity region and the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region, and the sixth impurity region and the first The distance between the fourth impurity region and the fourth impurity region is equal to or greater than the distance between the second impurity region and the fourth impurity region.

  According to a third aspect of the present invention, there is provided a parasitic bipolar formed by a plurality of impurity regions of the same conductivity type in which a plurality of transistors forming the H bridge circuit are arranged or configured and a semiconductor substrate of the opposite conductivity type. A drive control circuit and a switching regulator control circuit that are resistant to the effects of noise even when the motor drive circuit performs a switching operation are incorporated, together with a motor drive circuit that suppresses an increase in circuit area while preventing structural damage caused by conduction of transistors. The semiconductor device can be provided.

  An electronic device according to a fourth aspect of the present invention includes any one of the motor drive circuits described above, and a motor having two terminals respectively connected to a third node and a fourth node.

  According to a fourth aspect of the present invention, there is provided a parasitic bipolar formed of a plurality of impurity regions of the same conductivity type in which a plurality of transistors forming an H bridge circuit are arranged or configured and a semiconductor substrate of the opposite conductivity type. A highly reliable and compact electronic device can be provided by using a motor drive circuit in which an increase in a circuit area is suppressed while preventing a structural breakdown caused by conduction of a transistor.

FIG. 2 is a circuit diagram showing a configuration example of a part of the electronic device according to the first embodiment of the present invention. FIG. 2 is a circuit diagram for explaining an operation example of the motor drive circuit shown in FIG. 1; FIG. 2 is a cross-sectional view showing a specific example of the motor drive circuit shown in FIG. 1; The figure which shows the example of change of hFE of a parasitic transistor. FIG. 2 is a plan view showing an example of the layout of a motor drive circuit shown in FIG. 1; FIG. 7 is a circuit diagram showing a configuration example of a part of an electronic device according to a second embodiment of the present invention. FIG. 7 is a plan view showing a first example of the layout of the semiconductor device shown in FIG. 6; FIG. 7 is a plan view showing a second example of the layout of the semiconductor device shown in FIG. 6; FIG. 7 is a plan view showing a third example of the layout of the semiconductor device shown in FIG. 6; FIG. 7 is a plan view showing a fourth example of the layout of the semiconductor device shown in FIG. 6; Sectional drawing which shows the example of the motor drive circuit in 3rd Embodiment. Sectional drawing which shows the example of the motor drive circuit in 4th Embodiment. Sectional drawing which shows the example of the motor drive circuit in 5th Embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that the same reference numerals are given to the same components, and redundant description will be omitted.
First Embodiment
FIG. 1 is a circuit diagram showing an exemplary configuration of part of an electronic device according to a first embodiment of the present invention. Examples of the electronic device include a printer including a motor, a scanner, and a projector. In the following, the printer will be described as an example.

  As shown in FIG. 1, this electronic device includes a motor 100, a semiconductor device (motor driver IC) 200 according to the first embodiment of the present invention, a SoC (System on a Chip) 300, and a resistor R1. It contains. Note that some of the components shown in FIG. 1 may be omitted or changed, or other components may be added to the components shown in FIG.

  The motor 100 is a direct current brush motor, a direct current brushless motor, a stepping motor or the like. For example, the motor 100 is used to move a carriage on which a print head of a printer is mounted, or to transport a print medium (such as paper) to be printed using ink ejected from the print head.

  The semiconductor device 200 includes a drive control circuit 201 and a motor drive circuit 202 that drives the motor 100 under the control of the drive control circuit 201. Note that at least a part of components of the drive control circuit 201 and the motor drive circuit 202 may be configured by discrete components.

  For example, the semiconductor device 200 is configured by housing an IC chip in which a circuit is formed on a silicon substrate in a package. In that case, the first to sixth nodes N1 to N6 of the semiconductor device 200 may be pads (terminals) of an IC chip or pins (terminals) provided in a package.

  The resistor R1 is a resistor for measuring the drive current flowing to the motor drive circuit 202, and has a small resistance value of, for example, about 1 Ω. Although the resistor R1 is shown in FIG. 1 as an external component of the semiconductor device 200, the resistor R1 may be incorporated in the semiconductor device 200. Alternatively, if other means are used to measure the drive current, the resistor R1 may be omitted.

  The SoC 300 includes a processor, a memory, and the like, and controls each part of the electronic device. Here, the SoC is a semiconductor device in which a series of functions (systems) required for electronic devices and the like are integrated in one semiconductor chip. The SoC 300 communicates with the semiconductor device 200 by the serial interface method to supply control data DATA necessary to drive the motor 100 to the semiconductor device 200 together with the clock signal CLK.

<Configuration of motor driver>
The motor drive circuit 202 has a first node N1 to which the first power supply potential VBB (for example, +42 V) is supplied, and a second power supply potential VSS lower than the first power supply potential VBB (in FIG. , An H bridge circuit connected to a second node N2 supplied with a ground potential of 0 V and a third node N3 and a fourth node N4 respectively connected to two terminals of the motor 100 to be driven Is equipped.

  The second power supply potential VSS is also supplied to the fifth node N5. As shown in FIG. 1, when the resistor R1 is connected between the fifth node N5 and the second node N2, the second power supply potential VSS is supplied via the resistor R1 to the second node N2 Supplied to

  The H bridge circuit is connected between a first P-channel MOS transistor QP1 connected between the first node N1 and the third node N3, and between the second node N2 and the third node N3. And a first N-channel MOS transistor QN1. The H-bridge circuit further includes a second P-channel MOS transistor QP2 connected between the first node N1 and the fourth node N4, and between the second node N2 and the fourth node N4. And a second N channel MOS transistor QN2 connected.

  In the first embodiment, the first P channel MOS transistor QP1 is an EDMOS transistor, the second P channel MOS transistor QP2 is an EDMOS transistor, and the first N channel MOS transistor QN1 is an LDMOS transistor. The second N channel MOS transistor QN2 is an LDMOS transistor.

  The high side transistor QP1 has a source connected to the first node N1, a drain connected to the third node N3, and a gate to which the drive signal T11 is supplied. The low side transistor QN1 has a drain connected to the third node N3, a source connected to the second node N2, and a gate to which the drive signal T12 is supplied.

  The high side transistor QP2 has a source connected to the first node N1, a drain connected to the fourth node N4, and a gate to which the drive signal T21 is supplied. The low side transistor QN2 has a drain connected to the fourth node N4, a source connected to the second node N2, and a gate to which the drive signal T22 is supplied.

  The drive control circuit 201 generates a drive signal T11 according to the control signal S11, a low side predriver 12 generates the drive signal T12 according to the control signal S12, and a drive signal T21 according to the control signal S21. It includes a side predriver 21 and a low side predriver 22 that generates a drive signal T22 according to a control signal S22.

  Further, the drive control circuit 201 includes a comparator 30 and a switching control circuit 40. The comparator 30 compares the voltage generated across the resistor R1 when current flows in the motor 100 with the set control voltage VC, and generates a comparison result signal COMP representing the comparison result.

  The switching control circuit 40 is formed of, for example, a logic circuit including an RS flip-flop or the like. The switching control circuit 40 operates in accordance with the data DATA supplied from the SoC 300 and the clock signal CLK, and pulse width modulation (PWM) is performed by performing pulse width modulation (PWM) based on the comparison result signal COMP output from the comparator 30. The control signals S11 to S22 are generated. Thereby, the current flowing to the motor 100 is controlled.

<Operation of motor driver>
FIG. 2 is a circuit diagram for explaining an operation example of the motor drive circuit shown in FIG. Since the motor 100 has an inductance component, it is represented by a symbol of an inductor in FIG. The motor 100 has two terminals respectively connected to the third node N3 and the fourth node N4.

  In the charge mode shown in FIG. 2A, the transistors QP1 and QN2 are controlled to the on state (ON), and the transistors QN1 and QP2 are controlled to the off state (OFF). Thus, current flows from the first node N1 to the fifth node N5 via the transistor QP1, the motor 100, the transistor QN2 and the resistor R1, and the motor 100 is rotated.

  In the charge mode, the current flowing to the motor 100 gradually increases, and the voltage across the resistor R1 also gradually increases. In order to control the number of rotations or torque of motor 100, transistors QP1 and QN2 are intermittently turned on. When the voltage across the resistor R1 becomes larger than the control voltage VC, the comparison result signal COMP of the comparator 30 is activated to a high level. Thereby, the switching control circuit 40 shifts from the charge mode to the high-speed decay mode.

  In the fast decay mode shown in FIG. 2B, the transistors QP1 and QN2 are controlled to be in the off state, and the transistors QN1 and QP2 are controlled to be in the on state. Alternatively, if there is a forward parasitic diode from the source to the drain of the transistor QN1 and there is a parasitic diode from the drain to the source of the transistor QP2, the transistors QN1 and QP2 are controlled to the off state It may be done.

  In the fast decay mode, the back electromotive force of the motor 100 causes a current to flow from the fifth node N5 to the first node N1 via the resistor R1, the transistor QN1, the motor 100, and the transistor QP2. Thereby, the speed adjustment of the motor 100 is performed, and the power regeneration operation is performed. At this time, for example, the potential of the third node N3 drops to about −1 V, and the potential of the fourth node N4 rises to about +43 V. Thus, a negative potential is applied to the drains of the transistors QP1 and QN1 electrically connected to the third node N3.

  Since the energy stored in the motor 100 is released by the power regeneration operation, the current flowing to the motor 100 gradually decreases. For example, when the current flowing to the motor 100 approaches zero or a certain period of time elapses from the start of the fast decay mode, the switching control circuit 40 shifts from the fast decay mode to the slow decay mode. The switching control circuit 40 may restart the charge mode by omitting the low-speed decay mode.

  In the slow decay mode shown in FIG. 2C, the transistors QP1 and QP2 are controlled to be in the off state, and the transistors QN1 and QN2 are controlled to be in the on state. Alternatively, when a forward parasitic diode is present from the source to the drain of the transistor QN1, the transistor QN1 may be controlled to be in the off state.

  In the slow decay mode, the back electromotive force of the motor 100 causes a current to flow from the fourth node N4 to the third node N3 via the transistors QN2 and QN1. As a result, the motor 100 is braked and the energy stored in the motor 100 is released, so the current flowing to the motor 100 gradually decreases.

  For example, the switching control circuit 40 shifts from the slow decay mode to the charge mode when the current flowing to the motor 100 approaches zero or a fixed period elapses from the start of the slow decay mode. Thereafter, the charge mode and the damping mode are repeated to perform control such that the peak value of the current flowing through the motor 100 becomes constant, whereby the rotational speed or torque of the motor 100 can be maintained substantially constant.

  On the other hand, by controlling the transistors QN1 and QP2 to be in the on state and controlling the transistors QP1 and QN2 to be in the off state, from the first node N1, through the transistor QP2, the motor 100, the transistor QN1 and the resistor R1. Current flows to the fifth node N5, and the motor 100 reverses. Even when the motor 100 is reversely rotated, the rotational speed or torque of the motor 100 can be kept substantially constant by performing the same control as in the case where the motor 100 is rotated forward.

<Specific example of motor drive circuit>
FIG. 3 is a cross-sectional view showing a specific example of the motor drive circuit shown in FIG. In the specific example shown in FIG. 3, a P-type semiconductor substrate (for example, a silicon substrate containing a P-type impurity such as boron) 210 is used. The first P-channel MOS transistor QP1 is an EDMOS transistor, and is disposed in the N-type first impurity region 211 in the semiconductor substrate 210. The first N-channel MOS transistor QN1 is an LDMOS transistor, and is disposed in the N-type second impurity region 212 in the semiconductor substrate 210.

  Although not shown in FIG. 3, the second P-channel MOS transistor QP2 is an EDMOS transistor and is disposed in the N-type third impurity region in the semiconductor substrate 210. The second N-channel MOS transistor QN2 is an LDMOS transistor, and is disposed in the semiconductor substrate 210 in the N-type fourth impurity region. In the following, the configuration of the transistors QP1 and QN1 will be described as an example, but the transistors QP2 and QN2 also have the same configuration.

  In the first impurity region 211, an N-type contact region 221, a P-type impurity region 222 forming the source of the transistor QP1, a P-type impurity region 223 forming the extended drain of the transistor QP1, and the transistor QP1. And a P-type impurity region 224 constituting the drain of the transistor. The P-type impurity region 224 has an impurity concentration higher than that of the P-type impurity region 223.

  In the second impurity region 212, a P-type body region 231 and an N-type impurity region 232 forming the drain of the transistor QN1 are disposed. In the P-type body region 231, a P-type contact region 233 and an N-type impurity region 234 forming the source of the transistor QN1 are disposed.

A P-type impurity region (P ⁺ ) 217 having an impurity concentration higher than that of the semiconductor substrate 210 is disposed between the first impurity region 211 and the second impurity region 212 in the semiconductor substrate 210. In the impurity region 217 of the mold, a P-type contact region 218 is disposed. The P-type impurity region 217 corresponds to a guard region for preventing the occurrence of punch-through due to the depletion layer spreading between the first impurity region 211 and the second impurity region 212.

  Further, on the semiconductor substrate 210, the gate electrode 241 of the transistor QP1 and the gate electrode 242 of the transistor QN1 are disposed via the gate insulating film. Furthermore, on the semiconductor substrate 210 on which the gate electrodes 241 and 242 and the like are disposed, a wiring layer including a plurality of wirings is disposed via an interlayer insulating film. The interlayer insulating film and the wiring layer may have a multilayer structure as necessary.

  The N-type contact region 221 and the P-type impurity region 222 are connected to the first node N1 through a wire. The P-type contact region 218 is connected to the fifth node N5 via a wire. The P-type contact region 233 and the N-type impurity region 234 are connected to the second node N2 through a wire. The P-type impurity region 224 and the N-type impurity region 232 are connected to the third node N3 through a wiring.

  Here, as shown in FIG. 3, a parasitic NPN bipolar transistor is formed using the N-type first impurity region 211 as a collector, the P-type semiconductor substrate 210 as a base, and the N-type second impurity region 212 as an emitter. It is done. The first power supply potential VBB (for example, +42 V) is supplied to the first impurity region 211 from the first node N1 via the N-type contact region 221, and the fifth substrate N5 is supplied to the semiconductor substrate 210. The second power supply potential VSS (for example, 0 V) is supplied from the P-type contact region 218 and the P-type impurity region 217.

  In the fast decay mode shown in FIG. 2B, when the regenerative current flows from the fifth node N5 to the first node N1 via the transistors QN1 and QP2, etc., the negative potential (the third node N3) For example, about -1 V) is applied. Therefore, a negative potential is applied to the second impurity region 212 from the third node N3 through the N-type impurity region 232.

  As a result, the parasitic transistor becomes conductive, and a parasitic current Ip flows from the first impurity region 211 to the second impurity region 212 via the semiconductor substrate 210. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, which may cause the structural destruction of the IC.

  FIG. 4 is a diagram showing an example of the change of hFE of the parasitic transistor with respect to the distance between the two transistors shown in FIG. In FIG. 4, the horizontal axis represents the distance Dw between the first impurity region 211 in which the transistor QP1 shown in FIG. 3 is arranged and the second impurity region 212 in which the transistor QN1 is arranged, and the vertical axis Represents hFE of a parasitic transistor.

  As shown in FIG. 4, the smaller the distance Dw between the first impurity region 211 and the second impurity region 212, the larger the hFE of the parasitic transistor. Therefore, by setting the distance Dw between the first impurity region 211 and the second impurity region 212 to a predetermined distance or more, the hFE of the parasitic transistor is suppressed to the allowable value or less at which IC structural breakdown does not occur. Can. In the example shown in FIG. 4, if the distance Dw between the first impurity region 211 and the second impurity region 212 is about 40 μm or more, the hFE of the parasitic transistor can be suppressed to the allowable value or less.

<Layout>
FIG. 5 is a plan view showing an example of the layout of the motor drive circuit shown in FIG. FIG. 5 shows a layout area 210 a of the H bridge circuit in the semiconductor substrate 210. In the layout region 210a, a first impurity region 211 in which the transistor QP1 is disposed, a second impurity region 212 in which the transistor QN1 is disposed, a third impurity region 213 in which the transistor QP2 is disposed, and a transistor A fourth impurity region 214 in which QN2 is disposed is provided.

  The second power supply potential VSS is supplied to the semiconductor substrate 210, and the first power supply potential VBB is supplied to the first impurity region 211 and the third impurity region 213. Thus, there is a low possibility that the parasitic NPN bipolar transistor formed by the N-type first impurity region 211, the P-type semiconductor substrate 210, and the N-type third impurity region 213 conducts.

  Therefore, the distance A between the first impurity region 211 and the third impurity region 213 can be set smaller than the predetermined distance. The distance A is set based on various device characteristic values such as the breakdown voltage of the PN junction. In the present application, “distance” means the shortest distance between two regions.

  On the other hand, in the fast decay mode shown in FIG. 2B, when a negative potential is applied to second impurity region 212, N-type first impurity region 211, P-type semiconductor substrate 210, and N The parasitic NPN bipolar transistor formed by the second impurity region 212 of the type may become conductive. Therefore, the distance B1 between the first impurity region 211 and the second impurity region 212 needs to be a predetermined distance or more.

  Similarly, in the fast decay mode, when a negative potential is applied to the fourth impurity region 214, the N-type third impurity region 213, the P-type semiconductor substrate 210, and the N-type fourth impurity A parasitic NPN bipolar transistor formed by the region 214 may conduct. Therefore, the distance B2 between the third impurity region 213 and the fourth impurity region 214 needs to be equal to or greater than a predetermined distance.

  In the fast decay mode, a negative potential is applied to the second impurity region 212 and a positive potential is applied to the fourth impurity region 214, and a positive potential is applied to the second impurity region 212. When a negative potential is applied to the fourth impurity region 214 at the same time as the application of the second impurity region 214, the N-type second impurity region 212, the P-type semiconductor substrate 210, and the N-type fourth impurity region 214 The parasitic NPN bipolar transistor formed by Therefore, the distance C between the second impurity region 212 and the fourth impurity region 214 needs to be equal to or greater than a predetermined distance.

From the above, the following equations (1) to (3) are derived.
A <B1 (1)
A <B2 (2)
A <C (3)
That is, in the present embodiment, the distance A between the first impurity region 211 and the third impurity region 213 is greater than the distance B1 between the first impurity region 211 and the second impurity region 212. To be smaller than the distance B2 between the third impurity region 213 and the fourth impurity region 214 and smaller than the distance C between the second impurity region 212 and the fourth impurity region 214. It is set. For example, the distance A may be set to 1/2 or less of the distance B1, 1/2 or less of the distance B2, and 1/2 or less of the distance C.

  Thus, in the motor drive circuit 202, hFE (DC current) of a parasitic NPN bipolar transistor formed of a plurality of N-type impurity regions in which a plurality of transistors constituting an H bridge circuit are arranged and a P-type semiconductor substrate 210 The first impurity region 211 and the third impurity region have a low amplification factor, and the structural breakdown caused by conduction of the parasitic transistor is suppressed while keeping the amplification factor lower than the allowable value. By reducing the distance between T.213 and T.213, an increase in circuit area can be suppressed and the cost can be suppressed.

Further, a maximum voltage applied between the first impurity region 211 and the second impurity region 212, and a maximum voltage applied between the third impurity region 213 and the fourth impurity region 214; The maximum voltage applied between the second impurity region 212 and the fourth impurity region 214 is substantially equal. Therefore, as expressed by the following equation (4), the distance B1 between the first impurity region 211 and the second impurity region 212, the third impurity region 213 and the fourth impurity region 214 The distance B2 between them and the distance C between the second impurity region 212 and the fourth impurity region 214 may be set to be equal to each other.
B1 = B2 = C (4)

  Thus, between the first impurity region 211 and the second impurity region 212, between the third impurity region 213 and the fourth impurity region 214, and between the second impurity region 212 and the fourth impurity. The layout efficiency can be improved by making the hFE of parasitic transistors respectively formed between the regions 214 substantially the same.

  Specifically, the distance A may be set to about 20 μm, and each of the distance B1, the distance B2, and the distance C may be set to about 60 μm. The boundary on the left side of the first impurity region 211 in the drawing and the boundary on the left side of the second impurity region 212 do not have to be on a straight line, and the third impurity region 213 on the right side in the drawing. The boundary and the boundary on the right side in the drawing of the fourth impurity region 214 do not have to be on a straight line.

Second Embodiment
FIG. 6 is a circuit diagram showing a configuration example of a part of the electronic device according to the second embodiment of the present invention. As shown in FIG. 6, this electronic device includes at least one motor 100a or 100b, a semiconductor device (motor driver IC) 200 according to a second embodiment of the present invention, a SoC 300, an analog circuit IC 400, and a power supply. And the circuit 500. Note that part of the components shown in FIG. 6 may be omitted or changed, or other components may be added to the components shown in FIG.

  The semiconductor device 200 incorporates at least one motor drive circuit 202a or 202b for driving at least one motor 100a or 100b, and a drive control circuit 203. In FIG. 6, as an example, a motor drive circuit 202a for driving a carriage motor 100a for moving a carriage on which a print head of a printer is mounted, and a print medium (paper) printed using ink discharged from the print head And the like, and a motor drive circuit 202b for driving the sheet feeding motor 100b for transporting the sheet.

  The motor drive circuits 202a and 202b respectively include a first H bridge circuit and a second H bridge circuit similar to the H bridge circuit of the motor drive circuit 202 in the first embodiment shown in FIG. A resistor R1 (FIG. 1) may be externally attached to each of the motor drive circuits 202a and 202b. The drive control circuit 203 is composed of a logic circuit and an analog circuit, and includes two drive control circuits 201 (FIG. 1) for controlling the motor drive circuits 202a and 202b, and further controls other parts of the electronic device. Control circuit may be included.

  The semiconductor device 200 also incorporates a switching regulator control circuit 204. The switching regulator control circuit 204 is composed of a logic circuit and an analog circuit, and peripheral components such as a diode D1, an inductor L1, a capacitor C1 and resistors R2 and R3 are externally attached to configure a switching regulator. The switching regulator steps down the power supply voltage (for example, 42 V) supplied from the power supply circuit 500 to generate the power supply voltage (for example, 3.3 V) supplied to the SoC 300 and the analog circuit IC 400 and the like.

<Layout 1>
FIG. 7 is a plan view showing a first example of the layout of the semiconductor device shown in FIG. 7, in the semiconductor substrate 210, a layout area 210a in which the first H bridge circuit (Ch1) is arranged, a layout area 210b in which the second H bridge circuit (Ch2) is arranged, and a drive control circuit 203. And a layout area 210d in which the switching regulator control circuit 204 is arranged.

  In each of layout regions 210a and 210b, N-type first impurity region 211 to fourth impurity region 214 are provided. Further, an N-type fifth impurity region 215 is provided in the layout region 210c, and an N-type sixth impurity region 216 is provided in the layout region 210d. In FIG. 7, the layout area 210a and the layout area 210b are arranged on the left and right in the figure, but the layout area 210a and the layout area 210b may be arranged on the upper and lower sides in the figure. In addition, the layout area 210c and the layout area 210d may be arranged in reverse, or may be arranged vertically in the figure.

  Among the transistors constituting the first H bridge circuit (Ch1), the first P channel MOS transistor is arranged in the first impurity region 211 in the layout region 210a, and the first N channel MOS transistor is arranged in the layout The region 210 a is disposed in the second impurity region 212. The second P-channel MOS transistor is disposed in the third impurity region 213 in the layout region 210a, and the second N-channel MOS transistor is disposed in the fourth impurity region 214 in the layout region 210a.

  Among the transistors forming the second H bridge circuit (Ch2), the first P channel MOS transistor is arranged in the first impurity region 211 in the layout region 210b, and the first N channel MOS transistor is In the region 210 b, the second impurity region 212 is disposed. The second P-channel MOS transistor is disposed in the third impurity region 213 in the layout region 210b, and the second N-channel MOS transistor is disposed in the fourth impurity region 214 in the layout region 210b.

  The layout conditions of the first H bridge circuit (Ch1) and the second H bridge circuit (Ch2) are the same as the layout conditions of the H bridge circuit in the first embodiment. In FIG. 7, the distance between the second impurity region 212 and the fourth impurity region 214 in the layout regions 210a and 210b is represented by "C". Further, the first impurity region 211 to the fourth impurity region 214 of the first H bridge circuit (Ch1) and the first impurity region 211 to the fourth impurity region 214 of the second H bridge circuit (Ch2) The distance between them (the shortest distance) is represented by "D".

  Since motor drive circuit 202a and motor drive circuit 202b operate asynchronously, in the example shown in FIG. 7, the second N channel MOS transistor of the first H bridge circuit (Ch1) is arranged in layout region 210a. And the potential of the second impurity region 212 in which the first N channel MOS transistor of the second H bridge circuit (Ch2) is arranged in the layout region 210b. It does not decide whether it will be.

  Thus, in the present embodiment, the first impurity region 211 to the fourth impurity region 214 of the first H bridge circuit (Ch1) and the first impurity region 211 to the first H region of the second H bridge circuit (Ch2) are provided. Distance D between the second impurity region 214 and the fourth impurity region 214 in the first H bridge circuit (Ch1) or the second H bridge circuit (Ch2). It is set to a distance C or more.

  Thereby, it is formed of a plurality of N-type impurity regions in which a plurality of transistors constituting the first H bridge circuit (Ch1) and the second H bridge circuit (Ch2) are disposed and the P-type semiconductor substrate 210. The hFE of the parasitic NPN bipolar transistor can be suppressed below the allowable value to prevent structural damage caused by the parasitic transistor becoming conductive.

  In addition, drive control circuit 203 includes a P-channel MOS transistor disposed in fifth impurity region 215 in semiconductor substrate 210 or directly disposed in semiconductor substrate 210 and having fifth impurity region 215. . In FIG. 7, when the fifth impurity region 215 is disposed closest to the layout region 210a or 210b in the layout region 210c, the fifth impurity region 215 and the first impurity regions 211 to the fourth impurity regions are arranged. The distance between it and 214 is represented by "E".

  Similarly, the switching regulator control circuit 204 is disposed in the sixth impurity region 216 in the semiconductor substrate 210 or is directly disposed in the semiconductor substrate 210 and has a P channel MOS transistor (P Channel EDMOS transistors may be included). In FIG. 7, when the sixth impurity region 216 is disposed closest to the layout region 210a or 210b in the layout region 210d, the sixth impurity region 216 and the first impurity regions 211 to the fourth impurity regions The distance between it and 214 is represented by "F".

  In this embodiment, the distance E between the fifth impurity region 215 and the first to fourth impurity regions 211 to 214 is between the second impurity region 212 and the fourth impurity region 214. The distance F between the sixth impurity region 216 and the first to fourth impurity regions 211 to 214 is equal to or less than the distance C between the second impurity region 212 and the fourth impurity region 214. And the distance C between them.

  Thereby, even if a plurality of transistors constituting the first H bridge circuit (Ch1) or the second H bridge circuit (Ch2) perform switching operation to generate noise, the drive control circuit 203 and the switching regulator control circuit The effect of noise on 204 is reduced.

  Therefore, a plurality of N-type impurity regions in which a plurality of transistors forming the first H bridge circuit (Ch1) or the second H bridge circuit (Ch2) are disposed and the P-type semiconductor substrate 210 are formed. Drive control that is hard to be affected by noise even if the motor drive circuit 202a or 202b performs switching operation together with the motor drive circuit 202a or 202b that suppresses increase in circuit area while preventing structural breakdown caused by conduction of parasitic bipolar transistors. A semiconductor device 200 incorporating the circuit 203 and the switching regulator control circuit 204 can be provided.

<Layout 2>
FIG. 8 is a plan view showing a second example of the layout of the semiconductor device shown in FIG. In FIG. 8, the first impurity region 211 to the fourth impurity region 214 of the first H bridge circuit (Ch1) and the first impurity region 211 and the second impurity region of the second H bridge circuit (Ch2) are shown. A portion of the impurity region 212 is shown.

  In the second example, at least one guard region of the same conductivity type as the semiconductor substrate is provided between two adjacent impurity regions. For example, in the case where the P-type semiconductor substrate 210 is used, the guard region is formed of a P-type impurity region having an impurity concentration higher than that of the semiconductor substrate 210, and a terminal (a pad ) Is electrically connected to P1 to P3. In other respects, the second example may be similar to the first example shown in FIG.

  As shown in FIG. 8, layout regions for arranging elements of other circuits are provided between or around first impurity region 211 to fourth impurity region 214, so that each impurity region is provided. The shape of is not limited to a rectangle. In such a case, for example, the distance between the first impurity region 211 and the second impurity region 212 is the distance between the side of the first impurity region 211 and the second impurity region 212 which are closest to each other. It means the distance between the sides.

  In the semiconductor substrate 210, a side of the first impurity region 211 on the side of the second impurity region 212 and a second impurity region 212 between the first impurity region 211 and the second impurity region 212. At least one first guard region 251 is provided extending along the side of the first impurity region 211 side.

  In addition, between the third impurity region 213 and the fourth impurity region 214, the side on the fourth impurity region 214 side of the third impurity region 213, and the third impurity of the fourth impurity region 214. At least one second guard area 252 is provided extending along the side on the area 213 side.

  Furthermore, a side of the second impurity region 212 on the fourth impurity region 214 side between the second impurity region 212 and the fourth impurity region 214, and a second impurity of the fourth impurity region 214. At least one third guard area 253 is provided extending along the side on the area 212 side.

  Thus, between the first impurity region 211 and the second impurity region 212, between the third impurity region 213 and the fourth impurity region 214, and between the second impurity region 212 and the fourth impurity. Between the region 214 and the region 214, the depletion layer can be prevented from spreading to cause punch-through.

  Further, in the semiconductor substrate 210, the side of the first impurity region 211 on the third impurity region 213 side, and the third impurity region 213, between the first impurity region 211 and the third impurity region 213. At least one fourth guard region 254 may be provided to extend along the side on the side of the first impurity region 211 of the

  In the case where the plurality of first guard regions 251, the plurality of second guard regions 252, and the plurality of third guard regions 253 are provided in the semiconductor substrate 210, the number of fourth guard regions 254 However, the number may be smaller than the number of first guard regions 251, smaller than the number of second guard regions 252, and smaller than the number of third guard regions 253. For example, in FIG. 8, one fourth guard region 254, two first guard regions 251, two second guard regions 252, and two third guard regions 253 are provided. There is.

  Thus, the number of fourth guard regions 254 provided between the first impurity region 211 and the third impurity region 213 which are less likely to cause punch-through on the circuit operation is The number of the third guard regions 253 can be smaller than the number of each to prevent an increase in circuit area.

  Alternatively, in the semiconductor substrate 210, a plurality of fifth guard regions 255 extending between the first H bridge circuit (Ch1) and the second H bridge circuit (Ch2) may be provided. In that case, the number of fifth guard regions 255 is equal to or greater than the number of first guard regions 251, equal to or greater than the number of second guard regions 252, and equal to or greater than the number of third guard regions 253. Also good.

  For example, in FIG. 8, three fifth guard regions 255, two first guard regions 251, two second guard regions 252, and two third guard regions 253 are provided. There is. Thereby, punch-through between the first H bridge circuit (Ch1) and the second H bridge circuit (Ch1) can be effectively prevented.

  Furthermore, a layout area 210a or 210b in which the first H bridge circuit (Ch1) or the second H bridge circuit (Ch2) shown in FIG. 7 is arranged, and a layout area 210c or switching regulator in which the drive control circuit 203 is arranged. A sixth guard area 256 or a seventh guard area 257 may be provided between the control circuit 204 and the layout area 210d.

<Layout 3>
FIG. 9 is a plan view showing a third example of the layout of the semiconductor device shown in FIG. In the third example, the semiconductor substrate 210 is provided with two fifth guard regions 255 extending between the first H bridge circuit (Ch1) and the second H bridge circuit (Ch2). There is. Otherwise, the third example may be similar to the second example shown in FIG.

  According to the third example, the distance C between the second impurity region 212 and the fourth impurity region 214 in the first H bridge circuit (Ch1) and the second H bridge circuit (Ch2) (see FIG. 7). See, the first impurity region 211 to the fourth impurity region 214 of the first H bridge circuit (Ch1) and the first impurity region 211 to the fourth impurity region of the second H bridge circuit (Ch2) And the distance D (see FIG. 7) between 214 and 214 can be made equal.

<Layout 4>
FIG. 10 is a plan view showing a fourth example of the layout of the semiconductor device shown in FIG. In the fourth example, the shape and number of guard areas are different from those in the second example. In the other points, the fourth example may be similar to the second example shown in FIG.

  As shown in FIG. 10, in the semiconductor substrate 210, a first guard region 251 extending between the first impurity region 211 and the second impurity region 212 is provided, and the third impurity region 213 and the A second guard region 252 extending between the fourth impurity region 214 and a third guard region 253 extending between the second impurity region 212 and the fourth impurity region 214 are provided. It is done.

  Furthermore, in the semiconductor substrate 210, a fourth guard region 254 extending between the first impurity region 211 and the third impurity region 213 may be provided. In that case, the width of the fourth guard area 254 is smaller than the width of the first guard area 251, smaller than the width of the second guard area 252, and smaller than the width of the third guard area 253. Also good.

  Thus, the width of the fourth guard region 254 provided between the first impurity region 211 and the third impurity region 213 which is less likely to cause punch-through in the circuit operation corresponds to that of the first guard region 251 to The width of each of the third guard regions 253 can be smaller than that of each to prevent an increase in circuit area.

  Alternatively, in the semiconductor substrate 210, a fifth guard region 255 extending between the first H bridge circuit (Ch1) and the second H bridge circuit (Ch2) may be provided. In that case, the width of the fifth guard area 255 is equal to or larger than the width of the first guard area 251, equal to or larger than the width of the second guard area 252, and equal to or larger than the width of the third guard area 253 Also good. Thereby, punch-through between the first H bridge circuit (Ch1) and the second H bridge circuit (Ch1) can be effectively prevented.

  The fifth guard region 255 is a first guard region located between the third impurity region 213 of the first H bridge circuit (Ch1) and the first impurity region 211 of the second H bridge circuit (Ch2). A second portion 255b located between the portion 255a and the fourth impurity region 214 of the first H bridge circuit (Ch1) and the second impurity region 212 of the second H bridge circuit (Ch2); Have.

  In FIG. 10, in order to facilitate the layout, the width of the first portion 255a of the fifth guard area and the width of the second portion 255b are the same. However, the width of the first portion 255a of the fifth guard region may be equal to or greater than the width of the fourth guard region 254, and may be smaller than the width of the second portion 255b of the fifth guard region. . In addition, elements of another circuit may be disposed between the first H bridge circuit (Ch1) and the second H bridge circuit (Ch2).

Third Embodiment
FIG. 11 is a cross-sectional view showing a specific example of the motor drive circuit in the third embodiment. In the third embodiment, in the H bridge circuit shown in FIG. 1, EDMOS transistors are used as the transistors QN1 and QN2. In other respects, the third embodiment may be similar to the first or second embodiment.

  As shown in FIG. 11, the first P-channel MOS transistor QP1 is an EDMOS transistor, and is disposed in the N-type first impurity region 211 in the semiconductor substrate 210. The first N-channel MOS transistor QN1 is an EDMOS transistor, and has the N-type second impurity region 235 in the semiconductor substrate 210.

  Although not shown in FIG. 11, the second P-channel MOS transistor QP2 is an EDMOS transistor, and is arranged in the N-type third impurity region in the semiconductor substrate 210. The second N-channel MOS transistor QN2 is an EDMOS transistor, and has an N-type fourth impurity region in the semiconductor substrate 210. In the following, the configuration of the transistors QP1 and QN1 will be described as an example, but the transistors QP2 and QN2 also have the same configuration.

  In the semiconductor substrate 210, a second impurity region 235 constituting an extended drain of the transistor QN1, an N-type impurity region 236 constituting a drain of the transistor QN1, and an N-type impurity region 237 constituting a source of the transistor QN1. And a P-type contact region 238 are arranged. The N-type impurity region 236 has an impurity concentration higher than that of the second impurity region 235.

A P-type impurity region (P ⁺ ) 217 having an impurity concentration higher than that of the semiconductor substrate 210 is disposed between the first impurity region 211 and the second impurity region 235 in the semiconductor substrate 210. In the impurity region 217 of the mold, a P-type contact region 218 is disposed. The P-type impurity region 217 corresponds to a guard region for preventing the occurrence of punch-through due to the depletion layer spreading between the first impurity region 211 and the second impurity region 235.

  Further, on the semiconductor substrate 210, the gate electrode 241 of the transistor QP1 and the gate electrode 243 of the transistor QN1 are disposed via the gate insulating film. Furthermore, on the semiconductor substrate 210 on which the gate electrodes 241 and 243 and the like are disposed, a wiring layer including a plurality of wirings is disposed via an interlayer insulating film. The interlayer insulating film and the wiring layer may have a multilayer structure as necessary.

  The N-type contact region 221 and the P-type impurity region 222 are connected to the first node N1 through a wire. The P-type contact region 218 is connected to the fifth node N5 via a wire. The N-type impurity region 237 and the P-type contact region 238 are connected to the second node N2 through a wire. The P-type impurity region 224 and the N-type impurity region 236 are connected to the third node N3 via a wiring. The resistance value of the semiconductor substrate 210 between the P-type contact region 238 and the P-type impurity region 217 is sufficiently larger than the resistance value of the resistor R1, so the P-type contact region 238 and the P-type Almost no current flows between the impurity region 217 and the

  Here, as shown in FIG. 11, a parasitic NPN bipolar transistor is formed using the N-type first impurity region 211 as a collector, the P-type semiconductor substrate 210 as a base, and the N-type second impurity region 235 as an emitter. It is done. The first power supply potential VBB (for example, +42 V) is supplied to the first impurity region 211 from the first node N1 via the N-type contact region 221, and the fifth substrate N5 is supplied to the semiconductor substrate 210. The second power supply potential VSS (for example, 0 V) is supplied from the P-type contact region 218 and the P-type impurity region 217.

  In the fast decay mode shown in FIG. 2B, when the regenerative current flows from the fifth node N5 to the first node N1 via the transistors QN1 and QP2, etc., the negative potential (the third node N3) For example, about -1 V) is applied. Therefore, a negative potential is applied to the second impurity region 235 from the third node N3 through the N-type impurity region 236.

  As a result, the parasitic transistor becomes conductive, and a parasitic current Ip flows from the first impurity region 211 to the second impurity region 235 via the semiconductor substrate 210. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, which may cause the structural destruction of the IC.

  The smaller the distance Dw between the first impurity region 211 and the second impurity region 235, the larger the hFE of the parasitic transistor. Therefore, by setting the distance Dw between the first impurity region 211 and the second impurity region 235 to a predetermined distance or more, the hFE of the parasitic transistor is suppressed to the allowable value or less at which IC structural breakdown does not occur. Can.

  Alternatively, in the third embodiment, general MOS transistors may be used as the transistors QN1 and QN2. In that case, an N-type offset region is provided instead of the extended drain of the transistor QN1 shown in FIG. 11, and the N-type offset region corresponds to a second impurity region. Further, an N-type offset region is provided instead of the extended drain of the transistor QN2, and the N-type offset region corresponds to a fourth impurity region.

Fourth Embodiment
FIG. 12 is a cross-sectional view showing a specific example of the motor drive circuit in the fourth embodiment. In the fourth embodiment, in the H bridge circuit shown in FIG. 1, general MOS transistors are used as the transistors QP1 and QP2. In the other points, the fourth embodiment may be the same as any of the first to third embodiments.

  As shown in FIG. 12, the first P-channel MOS transistor QP1 is a general MOS transistor, and is disposed in the N-type first impurity region 211 in the semiconductor substrate 210. The first N-channel MOS transistor QN1 is an LDMOS transistor, and is disposed in the N-type second impurity region 212 in the semiconductor substrate 210.

  Although not shown in FIG. 12, the second P-channel MOS transistor QP2 is a general MOS transistor, and is arranged in the N-type third impurity region in the semiconductor substrate 210. The second N-channel MOS transistor QN2 is an LDMOS transistor, and is disposed in the semiconductor substrate 210 in the N-type fourth impurity region. In the following, the configuration of the transistors QP1 and QN1 will be described as an example, but the transistors QP2 and QN2 also have the same configuration.

  In the first impurity region 211, an N-type contact region 221, a P-type impurity region 222 forming the source of the transistor QP1, a P-type offset region 225, and a P-type impurity region 226 are arranged. ing. The P-type impurity region 226 has a higher impurity concentration than the P-type offset region 225, and constitutes the drain of the transistor QP1 together with the P-type offset region 225.

A P-type impurity region (P ⁺ ) 217 having an impurity concentration higher than that of the semiconductor substrate 210 is disposed between the first impurity region 211 and the second impurity region 212 in the semiconductor substrate 210. In the impurity region 217 of the mold, a P-type contact region 218 is disposed. The P-type impurity region 217 corresponds to a guard region for preventing the occurrence of punch-through due to the depletion layer spreading between the first impurity region 211 and the second impurity region 212.

  Further, on the semiconductor substrate 210, the gate electrode 244 of the transistor QP1 and the gate electrode 242 of the transistor QN1 are disposed via the gate insulating film. Furthermore, on the semiconductor substrate 210 on which the gate electrodes 244 and 242 and the like are disposed, a wiring layer including a plurality of wirings is disposed via an interlayer insulating film. The interlayer insulating film and the wiring layer may have a multilayer structure as necessary.

  The N-type contact region 221 and the P-type impurity region 222 are connected to the first node N1 through a wire. The P-type contact region 218 is connected to the fifth node N5 via a wire. The P-type contact region 233 and the N-type impurity region 234 are connected to the second node N2 through a wire. The P-type impurity region 226 and the N-type impurity region 232 are connected to the third node N3 via a wiring.

  Here, as shown in FIG. 12, a parasitic NPN bipolar transistor is formed using the N-type first impurity region 211 as a collector, the P-type semiconductor substrate 210 as a base, and the N-type second impurity region 212 as an emitter. It is done. The first power supply potential VBB (for example, +42 V) is supplied to the first impurity region 211 from the first node N1 via the N-type contact region 221, and the fifth substrate N5 is supplied to the semiconductor substrate 210. The second power supply potential VSS (for example, 0 V) is supplied from the P-type contact region 218 and the P-type impurity region 217.

  In the fast decay mode shown in FIG. 2B, when the regenerative current flows from the fifth node N5 to the first node N1 via the transistors QN1 and QP2, etc., the negative potential (the third node N3) For example, about -1 V) is applied. Therefore, a negative potential is applied to the second impurity region 212 from the third node N3 through the N-type impurity region 232.

  As a result, the parasitic transistor becomes conductive, and a parasitic current Ip flows from the first impurity region 211 to the second impurity region 212 via the semiconductor substrate 210. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, which may cause the structural destruction of the IC.

  The smaller the distance Dw between the first impurity region 211 and the second impurity region 212, the larger the hFE of the parasitic transistor. Therefore, by setting the distance Dw between the first impurity region 211 and the second impurity region 212 to a predetermined distance or more, the hFE of the parasitic transistor is suppressed to the allowable value or less at which IC structural breakdown does not occur. Can.

Fifth Embodiment
FIG. 13 is a cross-sectional view showing a specific example of the motor drive circuit in the fifth embodiment. In the fifth embodiment, an N-type semiconductor substrate (for example, a silicon substrate containing an N-type impurity such as phosphorus or arsenic) 260 is used instead of the P-type semiconductor substrate 210 shown in FIG. Accordingly, the P-type region and the N-type region in the semiconductor substrate are reversed, the P-channel transistor and the N-channel transistor are reversed, and the connection relationship between the circuits is changed accordingly. In the other points, the fifth embodiment may be similar to any of the first to fourth embodiments.

  The motor drive circuit according to the fifth embodiment includes a first node N1 to which a first power supply potential VBB (for example, 0 V) is supplied, and a second power supply potential VSS lower than the first power supply potential VBB. And a third node N3 and a fourth node N4 (see FIG. 1) respectively connected to the two terminals of the motor 100 to be driven. It has an H bridge circuit connected.

  The first power supply potential VBB is also supplied to the seventh node N7. As shown in FIG. 13, when the resistor R1 is connected between the seventh node N7 and the first node N1, the first power supply potential VBB is coupled to the first node N1 via the resistor R1. Supplied to

  The H bridge circuit in the fifth embodiment is obtained by replacing the P channel EDMOS transistor with a P channel LDMOS transistor and replacing the N channel LDMOS transistor with an N channel EDMOS transistor in the H bridge circuit shown in FIG.

  Therefore, the first N-channel MOS transistor QN1 is an EDMOS transistor, and is disposed in the semiconductor substrate 260 in the P-type first impurity region 261. The first P-channel MOS transistor QP 1 is an LDMOS transistor, and is disposed in the P-type second impurity region 262 in the semiconductor substrate 260.

  Although not shown in FIG. 13, the second N-channel MOS transistor QN2 is an EDMOS transistor, and is disposed in the P-type third impurity region in the semiconductor substrate 260. The second P-channel MOS transistor QP2 is an LDMOS transistor, and is arranged in the P-type fourth impurity region in the semiconductor substrate 260. In the following, as an example, the configuration of transistors QN1 and QP1 will be described, but transistors QN2 and QP2 also have the same configuration.

  The first impurity region 261 includes a P-type contact region 271, an N-type impurity region 272 forming the source of the transistor QN1, an N-type impurity region 273 forming the extended drain of the transistor QN1, and a transistor QN1. And an N-type impurity region 274 forming the drain of the transistor. The N-type impurity region 274 has an impurity concentration higher than that of the N-type impurity region 273.

  In the second impurity region 262, an N-type body region 281 and a P-type impurity region 282 forming the drain of the transistor QP1 are arranged. In the N-type body region 281, an N-type contact region 283 and a P-type impurity region 284 constituting the source of the transistor QP1 are arranged.

An N-type impurity region (N ⁺ ) 265 having an impurity concentration higher than that of the semiconductor substrate 260 is disposed between the first impurity region 261 and the second impurity region 262 in the semiconductor substrate 260. In the impurity region 265 of the mold, an N-type contact region 266 is disposed. The N-type impurity region 265 corresponds to a guard region for preventing the occurrence of punch-through due to the depletion layer spreading between the first impurity region 261 and the second impurity region 262.

  Further, on the semiconductor substrate 260, the gate electrode 291 of the transistor QN1 and the gate electrode 292 of the transistor QP1 are disposed via the gate insulating film. Furthermore, on the semiconductor substrate 260 on which the gate electrodes 291 and 292 are disposed, a wiring layer including a plurality of wirings is disposed via an interlayer insulating film.

  The N-type contact region 283 and the P-type impurity region 284 are connected to the first node N1 through a wire. The N-type contact region 266 is connected to the seventh node N7 through a wire. The P-type contact region 271 and the N-type impurity region 272 are connected to the second node N2 through a wire. The P-type impurity region 282 and the N-type impurity region 274 are connected to the third node N3 via a wiring.

  Here, as shown in FIG. 13, a parasitic PNP bipolar transistor is formed using the P-type second impurity region 262 as an emitter, the N-type semiconductor substrate 260 as a base, and the P-type first impurity region 261 as a collector. It is done. The second power supply potential VSS (for example, -42 V) is supplied to the first impurity region 261 from the second node N2 via the P-type contact region 271, and the seventh node is supplied to the semiconductor substrate 260. First power supply potential VBB (for example, 0 V) is supplied from N7 through N-type contact region 266 and N-type impurity region 265.

  When the regenerative current flows from the second node N2 to the seventh node N7 via the transistors QN2 and QP1 and the like in the fast decay mode, a positive potential (for example, about +1 V) is applied to the third node N3. Be done. Therefore, a positive potential is supplied to the second impurity region 262 from the third node N3 through the P-type impurity region 282.

  As a result, the parasitic transistor becomes conductive, and a parasitic current Ip flows from the second impurity region 262 toward the first impurity region 261 via the semiconductor substrate 260. When the hFE (DC current amplification factor) of the parasitic transistor is large, a large parasitic current Ip exceeding the allowable limit may flow, which may cause the structural destruction of the IC.

  Therefore, the first to fourth embodiments are also applied to the fifth embodiment by reversing the P type region and the N type region in the semiconductor substrate in FIGS. 4 to 12 and the description thereof. Ru. That is, instead of the N-type first impurity region 211 to the sixth impurity region 216 shown in FIGS. 5 and 7 to 10, P-type first to sixth impurity regions are provided.

  For example, the distance A between the first impurity region and the third impurity region is smaller than the distance B1 between the first impurity region and the second impurity region, and the third impurity region And the distance C between the second impurity region and the fourth impurity region.

  Thereby, in the motor drive circuit, hFE of a parasitic PNP bipolar transistor formed of a plurality of P-type impurity regions in which a plurality of transistors forming an H bridge circuit are arranged and an N-type semiconductor substrate 260 is less than an allowable value. To reduce the distance between the first impurity region and the third impurity region, which is less likely to become conductive in circuit operation, while preventing structural breakdown caused by the parasitic transistor being conductive. Thus, the increase in circuit area can be suppressed and the cost can be suppressed.

  Further, when the N-type semiconductor substrate 260 is used, the guard region is formed of an N-type impurity region having an impurity concentration higher than that of the semiconductor substrate 260, and a terminal (a pad (pad) to which the first power supply potential VBB is supplied. Electrically connected). Therefore, instead of the P-type first guard area 251 to the seventh guard area 257 shown in FIGS. 8 to 10, N-type first to seventh guard areas are provided.

  Furthermore, according to the first to fifth embodiments of the present invention, a plurality of impurity regions of the same conductivity type in which a plurality of transistors forming an H bridge circuit are arranged or configured, and a semiconductor substrate of the opposite conductivity type A highly reliable and compact electronic device can be provided by using a motor drive circuit in which an increase in a circuit area is suppressed while preventing a structural breakdown caused by a parasitic bipolar transistor formed in the above.

  The present invention is not limited to the embodiments described above, and many modifications can be made within the technical concept of the present invention by those skilled in the art. For example, it is also possible to combine and implement a plurality of embodiments selected from the embodiments described above.

  11, 21 ... high side predriver, 12, 22 ... low side predriver, 30 ... comparator, 40 ... switching control circuit, 100 ... motor, 100a ... carriage motor, 100b ... sheet feeding motor, 200 ... semiconductor device, 201, 203: drive control circuit, 202, 202a, 202b: motor drive circuit, 204: switching regulator control circuit, 210, 260: semiconductor substrate, 210a to 210d, layout area, 211 to 216, 232, 234 to 237, 265, 272 ~ 274 ... N-type impurity region, 217, 222 to 224, 226, 261, 262, 282, 284 ... P-type impurity region, 218, 221, 233, 238, 266, 271, 283 ... contact region, 225 ... Offset area, 23 , 281: Body region, 241 to 244, 291, 292: Gate electrode, 251 to 257, Guard region, 300: SoC, 400: Analog circuit IC, 500: Power supply circuit, QP1, QP2: P-channel transistor, QN1, QN2 ... N-channel transistor, R1 ... resistance, D1 ... diode, L1 ... inductor, C1 ... capacitor, P1 to P3 ... terminal

Claims (12)

Two nodes of a first node to which a first power supply potential is supplied, a second node to which a second power supply potential lower than the first power supply potential is supplied, and a motor to be driven A motor drive circuit comprising a first H-bridge circuit connected to a third node and a fourth node respectively connected to the first and second H-bridge circuits;
A first P-channel MOS transistor disposed in an N-type first impurity region in a P-type semiconductor substrate and connected between the first node and the third node;
The semiconductor substrate is disposed in an N-type second impurity region or directly disposed in the semiconductor substrate and has an N-type second impurity region, and the second node and the third A first N channel MOS transistor connected between the node and
A second P-channel MOS transistor disposed in the N-type third impurity region in the semiconductor substrate and connected between the first node and the fourth node;
The semiconductor device is disposed in an N-type fourth impurity region in the semiconductor substrate, or has an N-type fourth impurity region disposed directly in the semiconductor substrate, and the second node and the fourth A second N channel MOS transistor connected between the node and
Including
The distance between the first impurity region and the third impurity region is smaller than the distance between the first impurity region and the second impurity region, and the third impurity region and the third impurity region A motor drive circuit, wherein the distance between the second impurity region and the fourth impurity region is smaller than the distance between the fourth impurity region and the distance between the second impurity region and the fourth impurity region. The first P channel MOS transistor is an EDMOS transistor,
The second P channel MOS transistor is an EDMOS transistor,
The first N channel MOS transistor is an LDMOS transistor,
The second N channel MOS transistor is an LDMOS transistor.
The motor drive circuit according to claim 1. Two nodes of a first node to which a first power supply potential is supplied, a second node to which a second power supply potential lower than the first power supply potential is supplied, and a motor to be driven A motor drive circuit comprising a first H-bridge circuit connected to a third node and a fourth node respectively connected to the first and second H-bridge circuits;
A first N-channel EDMOS transistor disposed in a P-type first impurity region in an N-type semiconductor substrate and connected between the second node and the third node;
A first P-channel LDMOS transistor disposed in a P-type second impurity region in the semiconductor substrate and connected between the first node and the third node;
A second N-channel EDMOS transistor disposed in a P-type third impurity region in the semiconductor substrate and connected between the second node and the fourth node;
A second P-channel LDMOS transistor disposed in a P-type fourth impurity region in the semiconductor substrate and connected between the first node and the fourth node;
Including
The distance between the first impurity region and the third impurity region is smaller than the distance between the first impurity region and the second impurity region, and the third impurity region and the third impurity region A motor drive circuit, wherein the distance between the second impurity region and the fourth impurity region is smaller than the distance between the fourth impurity region and the distance between the second impurity region and the fourth impurity region.   The distance between the first impurity region and the second impurity region, the distance between the third impurity region and the fourth impurity region, the second impurity region, and the fourth The motor drive circuit according to any one of claims 1 to 3, wherein the distances between the first and second impurity regions are equal to one another. In the semiconductor substrate, between the first impurity region and the second impurity region, the side of the first impurity region on the second impurity region side, and the side of the second impurity region At least one first guard region of the same conductivity type as the semiconductor substrate extending along the side on the first impurity region side;
In the semiconductor substrate, between the third impurity region and the fourth impurity region, the side of the third impurity region on the side of the fourth impurity region, and the side of the fourth impurity region At least one second guard region of the same conductivity type as the semiconductor substrate extending along the side on the third impurity region side;
In the semiconductor substrate, a side of the second impurity region on the fourth impurity region side, and a side of the fourth impurity region, between the second impurity region and the fourth impurity region. At least one third guard region of the same conductivity type as the semiconductor substrate extending along the side on the second impurity region side;
The motor drive circuit according to any one of claims 1 to 4, further comprising:   A plurality of the first guard regions, a plurality of the second guard regions, and a plurality of the third guard regions, and the first impurity region and the third impurity in the semiconductor substrate The semiconductor extends along the side of the first impurity region on the side of the third impurity region and the side of the third impurity region on the side of the first impurity region, with the region; The semiconductor device further comprises at least one fourth guard region of the same conductivity type as the substrate, wherein the number of the fourth guard regions is less than the number of the first guard regions, and the number of the second guard regions is smaller than the number of the second guard regions. 6. The motor drive circuit according to claim 5, wherein the number is less than the number of the third guard areas.   In the semiconductor substrate, between the first impurity region and the third impurity region, a side of the first impurity region on the side of the third impurity region, and the side of the third impurity region The semiconductor device further comprises a fourth guard region of the same conductivity type as the semiconductor substrate, extending along the side on the first impurity region side, and the fourth guard region has a width that corresponds to that of the first guard region. The motor drive circuit according to claim 5, wherein the width is smaller than the width of the second guard area and smaller than the width of the third guard area.   The semiconductor device further includes a second H bridge circuit having the same configuration as the first H bridge circuit, and the first to fourth impurity regions of the first H bridge circuit and the second H bridge circuit The distance between the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region in the first or second H bridge circuit. The motor drive circuit of any one of 1-7. A second H bridge circuit having the same configuration as the first H bridge circuit;
A plurality of fifth guard regions of the same conductivity type as the semiconductor substrate, extending between the first H bridge circuit and the second H bridge circuit on the semiconductor substrate;
And the number of fifth guard areas is equal to or greater than the number of first guard areas, equal to or greater than the number of second guard areas, and equal to or greater than the number of third guard areas. A motor drive circuit according to claim 5 or 6. A second H bridge circuit having the same configuration as the first H bridge circuit;
A fifth guard region of the same conductivity type as the semiconductor substrate, which extends between the first H bridge circuit and the second H bridge circuit in the semiconductor substrate;
The width of the fifth guard area is equal to or greater than the width of the first guard area, equal to or greater than the width of the second guard area, and equal to or greater than the width of the third guard area. The motor drive circuit according to claim 5 or 7. The motor drive circuit according to any one of claims 1 to 10.
A drive control circuit including a transistor disposed in a fifth impurity region in the semiconductor substrate or directly disposed in the semiconductor substrate and having a fifth impurity region;
A switching regulator control circuit including a transistor disposed in a sixth impurity region in the semiconductor substrate or directly disposed in the semiconductor substrate and having a sixth impurity region;
The distance between the fifth impurity region and the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region. And the distance between the sixth impurity region and the first to fourth impurity regions is equal to or greater than the distance between the second impurity region and the fourth impurity region. . The motor drive circuit according to any one of claims 1 to 10.
The motor having the two terminals respectively connected to the third node and the fourth node;
An electronic device comprising the

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