JP2019046964A - Semiconductor device manufacturing method - Google Patents

Abstract

To improve performance of a semiconductor device.SOLUTION: A semiconductor device manufacturing method of an embodiment includes the steps of: preparing a semiconductor wafer which has a pad (electrode pad) 11T and a pad (electrode pad) 11c, which are composed of aluminum, and a cover film 15 which is composed of a conductive material harder than aluminum and formed to partially cover the pad 11T; bringing a probe needle in contact with the cover film 15 and subsequently forming an insulation film 22 so as to cover the cover film 15; and forming, on a surface of the insulation film 22, rewiring (conductor pattern) 21 electrically connected with the pad 11c in such a manner that the rewiring 21 partially overlaps the cover film 15.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor device, for example, a technique effective when applied to a method for manufacturing a semiconductor device including a step of electrically connecting an electrode pad and a probe needle.

  In the manufacturing method of a semiconductor device, there is a technique in which a probe needle is brought into contact with a pad of a semiconductor wafer for inspection. Further, there is a technique in which a wiring layer is further formed on the pad formation layer, and an external terminal is formed at a position different from the pad in a plan view (JP 2009-246218 A). No. 92305 (see Patent Document 2).

JP 2009-246218 A JP-A-2006-92305

  There is a step of performing an electrical inspection by pressing a probe needle against a pad of a semiconductor wafer. When the probe needle is rubbed against an aluminum pad, the contact resistance between the probe needle and the pad can be reduced by the probe needle breaking through the oxide film on the pad surface and biting into the pad. Further, when the probe needle is rubbed against the pad, a part of the aluminum constituting the pad is pushed out around or above the pad.

  Further, there is a technique for improving the layout flexibility of external terminals of a semiconductor chip by providing a wiring layer (redistribution layer) on the pad formation layer of the semiconductor wafer (semiconductor chip). When forming a rewiring layer in a semiconductor device manufacturing process including the electrical inspection process described above, avoid contact between the rewiring layer and a part of the aluminum extruded around or above the pad. There is a need to.

  Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  A manufacturing method of a semiconductor device according to an embodiment is formed of a first electrode pad and a second electrode pad made of aluminum, and a conductive material harder than aluminum, and covering a part of the first electrode pad. Preparing a semiconductor wafer having the first cover film formed. The method for manufacturing a semiconductor device includes a step of forming an insulating film so as to cover the first cover film after the first cover film and the probe needle are brought into contact with each other. Further, in the method of manufacturing a semiconductor device, the first conductor pattern is placed on the surface of the insulating film so that a part of the first conductor pattern electrically connected to the second electrode pad overlaps the first cover film. Forming the step.

  According to the one embodiment, the performance of the semiconductor device can be improved.

It is a top view by the side of the mounting surface of the semiconductor device which is one embodiment. It is sectional drawing of the AA line of FIG. It is an enlarged plan view of the B section shown in FIG. It is an expanded sectional view of the AA line of FIG. FIG. 2 is an explanatory diagram showing an example of a manufacturing process flow of the semiconductor device shown in FIG. 1. FIG. 6 is a plan view of a semiconductor wafer prepared in the wafer preparation process shown in FIG. 5. It is an enlarged plan view of the A part of FIG. It is an expanded sectional view along the AA line of FIG. It is an expanded sectional view which shows the state which formed the cover film | membrane on the pad shown in FIG. FIG. 10 is an enlarged cross-sectional view of the pad shown in FIG. 9. It is a modification with respect to FIG. 10, Comprising: It is an expanded sectional view at the time of forming the electrically conductive film on a pad by the electroplating method. It is an expanded sectional view at the time of forming the electrically conductive film which is a modification with respect to FIG. 10 by the electroless-plating method. FIG. 6 is an enlarged cross-sectional view schematically showing a state where a semiconductor wafer pad and a probe needle for inspection are electrically connected in the wafer inspection step shown in FIG. 5. It is an expanded sectional view which shows the structure of the front-end | tip part of the probe needle shown in FIG. It is an enlarged plan view of a pad periphery after a wafer inspection process. FIG. 16 is an enlarged cross-sectional view showing a state in which an insulating film covering the pad is formed in the cross section along the line AA in FIG. 15. It is an expanded sectional view which shows the state which formed the opening part in the insulating film shown in FIG. FIG. 18 is an enlarged plan view showing a state where a rewiring is formed on the insulating film shown in FIG. 17. FIG. 18 is an enlarged cross-sectional view illustrating a state in which rewiring is formed on the insulating film illustrated in FIG. 17. It is an expanded sectional view which shows the state which covered the rewiring shown in FIG. 19 with the insulating film. FIG. 6 is an enlarged cross-sectional view showing a state where an opening is formed on a land portion of a rewiring in the second opening forming step shown in FIG. 5. FIG. 22 is an enlarged cross-sectional view showing a state where a conductive film is formed in an opening on a land portion of the rewiring shown in FIG. 21. FIG. 6 is an enlarged plan view showing a state in which a plurality of external terminals are formed on a rewiring layer of a semiconductor wafer in the external terminal forming step shown in FIG. 5. FIG. 9 is a plan view of a mounting surface side of a semiconductor device which is a modification example of FIG. 1. It is sectional drawing of the AA line of FIG. FIG. 25 is an enlarged plan view showing an example of a connection relationship between pads and terminals by rewiring provided in the semiconductor device shown in FIG. 24. FIG. 27 is an explanatory diagram showing an example of a manufacturing process flow of the semiconductor device shown in FIGS. 24 to 26. FIG. 4 is an enlarged plan view of a semiconductor device which is a modified example with respect to FIG. 3. FIG. 5 is an enlarged cross-sectional view of a semiconductor device that is a modification example of FIG. 4.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

<Structure of semiconductor device>
First, the structure of the semiconductor device of this embodiment will be described. FIG. 1 is a plan view of the mounting surface side of the semiconductor device of the present embodiment. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is an enlarged plan view of a portion B shown in FIG. FIG. 4 is an enlarged sectional view taken along line AA in FIG. In FIG. 3, the pad 11, the cover film 15, and the rewiring 21 are indicated by dotted lines.

  In this embodiment, a semiconductor device to which a rewiring technique is applied is described in which a rewiring layer is formed over a semiconductor chip so that terminals are provided at positions different from the electrode pads of the semiconductor chip in plan view. As an example, a semiconductor package called WPP (Wafer Process Package) or WLP (Wafer Level Package) will be described.

  A semiconductor device PAC1 shown in FIG. 1 has a main surface PMSt and a main surface PMSb (see FIG. 2) opposite to the main surface PMSt. In plan view, main surface PMSt forms a quadrilateral. Specifically, the main surface PMSt includes a side PS1 extending in the X direction, a side PS2 opposite to the side PS1, a side PS3 extending in the Y direction intersecting the X direction, and a side PS4 opposite to the side PS3. In plan view, the side PS1 intersects with each of the side PS3 and the side PS4, and the side PS2 intersects with each of the side PS3 and the side PS4.

  The semiconductor device PAC1 has a plurality of terminals (external terminals, protruding electrodes, solder balls) SB arranged on the main surface PMSt. In the present embodiment, each of the plurality of terminals SB is a solder ball made of a solder material formed in a substantially spherical shape. The semiconductor device PAC1 will be described by taking a solder ball as an example of the terminal SB, but there are various modifications to the structure of the terminal SB. For example, a columnar conductor (pillar bump) formed in a column shape may be used. In the case of a columnar conductor, for example, a solder layer is laminated on the tip of a columnar conductor whose main component is copper (Cu). In the example illustrated in FIG. 1, the plurality of terminals SB are arranged along the X direction and the Y direction. A semiconductor device in which a plurality of external terminals are arranged on the main surface PMSt like the semiconductor device PAC1 is called an area array type semiconductor device. The area array type semiconductor device is mounted with the main surface PMSt facing a mounting surface of a mounting substrate (not shown). In this case, the mounting area of the semiconductor device can be reduced and the number of terminals can be increased.

  As shown in FIG. 2, the semiconductor device PAC1 includes a semiconductor chip 10 and a rewiring unit 20 formed on the semiconductor chip 10. The semiconductor chip 10 includes a plurality of semiconductor elements such as transistors and diodes, and a plurality of pads 11 (see FIG. 4) electrically connected to the plurality of semiconductor elements. The rewiring unit 20 includes a rewiring 21 (see FIG. 4) that is disposed between the plurality of terminals SB and the semiconductor chip 10 and electrically connects the semiconductor chip 10 and the terminals SB. In the semiconductor device PAC1 having the rewiring unit 20, the terminal SB can be arranged at a position different from the pad 11 of the semiconductor chip 10 in plan view.

  A semiconductor chip 10 shown in FIG. 4 includes a semiconductor substrate 12 made of a semiconductor material such as silicon (Si). The semiconductor substrate 12 is a base material for the semiconductor chip 10 and the semiconductor device PAC1. The semiconductor substrate 12 has a semiconductor element formation surface (main surface) 12t, and the plurality of semiconductor elements described above are formed on the semiconductor element formation surface 12t. Although not shown in FIG. 4, the semiconductor substrate 12 also has a main surface on the side opposite to the semiconductor element formation surface 12t. The main surface opposite to the semiconductor element formation surface 12t is the same surface as the main surface PMSb shown in FIG.

  A wiring layer (chip wiring layer) 13 is laminated on the semiconductor element formation surface 12t. The wiring layer 13 has a main surface (electrode pad forming surface) 13t that is a pad forming surface, and a plurality of pads (electrode pads, aluminum pads) 11 of the semiconductor chip 10 are formed on the main surface 13t. The wiring layer 13 includes wiring that electrically connects the semiconductor element of the semiconductor substrate 12 and the pad 11. In other words, the pad 11 is electrically connected to the semiconductor element through the wiring layer 13. The wiring formed in the wiring layer 13 is made of a conductive material such as copper (Cu), for example. The wiring layer 13 has a plurality of wirings, and each of the plurality of wirings is embedded in an insulating layer made of an inorganic material and insulated from each other. The wiring layer 13 is not limited to a single layer, and a plurality of wiring layers 13 may be laminated.

Each of the plurality of pads 11 formed on the main surface 13t of the wiring layer 13 is made of aluminum. An insulating film 14 is formed on the main surface 13t. The insulating film 14 is a passivation film that protects the main surface 13 t side (of the wiring layer 13) of the semiconductor chip 10. The insulating film 14 is an inorganic film made of an inorganic material. Examples of the insulating film 14 made of an inorganic film include a silicon oxide film (SiO ₂ film), a silicon nitride film (SiN film), or a laminated film thereof.

  The insulating film 14 has an opening that exposes a part of the pad 11. Each of the plurality of pads 11 is partially exposed from the insulating film 14 in the opening of the insulating film 14 and the other part is covered with the insulating film 14. A cover film (conductive film) 15 is formed in the opening of the insulating film 14. Details of the cover film 15 will be described later.

  In addition, as shown in FIG. 3, the plurality of pads 11 are arranged along the peripheral edge of the main surface PMSt. In the example shown in FIG. 3, the plurality of pads 11 are arranged along the side PS1. Although not shown, in the case of the semiconductor device PAC1, a plurality of pads 11 (see FIG. 3) are arranged along each of the sides PS2, PS3, and PS4 shown in FIG. However, the pads 11 may be arranged along some of the sides PS1, PS2, PS3, and PS4 shown in FIG.

  Main circuits configured by semiconductor elements such as transistors and diodes are arranged in a central region of the main surface PMSt in plan view. On the other hand, an input / output circuit including a plurality of pads 11 is arranged in a peripheral region of main surface PMSt. In the case of the semiconductor device PAC1, each of the plurality of terminals SB is arranged in a region inside the plurality of pads 11 in plan view. However, as a modification, some of the plurality of terminals SB may be arranged at a position overlapping the pad 11 or at a position outside the pad 11.

  As shown in FIG. 4, the terminal SB and the pad 11 are electrically connected via the rewiring 21 of the rewiring unit 20. The rewiring unit 20 includes an insulating film (organic insulating film) 22 formed on the upper surface (main surface, surface) 14 t of the insulating film 14. The rewiring unit 20 includes a rewiring 21 formed on the insulating film 22. The rewiring unit 20 includes an insulating film (organic insulating film) 23 that is formed on the insulating film 22 and covers the rewiring 21.

  The rewiring 21 includes a contact portion 21C electrically connected to the pad 11 via the cover film 15, a land portion 21L connected to the terminal SB via the conductive film UBM, a contact portion 21C and a land portion 21L. And a wiring portion 21W for connecting the two. Although illustration is omitted, there is a semiconductor device in which the contact portion 21C is connected to the pad 11 without the cover film 15 as a modification to the semiconductor device PAC1. As another modification, there is a semiconductor device in which the land portion 21L is connected to the terminal SB without using the conductive film UBM.

  The rewiring 21 includes, for example, a seed layer 21S formed on the insulating film 22 and a conductor layer 21M stacked on the seed layer 21S. The seed layer 21S is formed on the insulating film 22 that is an organic insulating film by, for example, sputtering. The conductor layer 21M is a metal film mainly composed of copper (Cu), for example, and is selectively formed on the seed layer 21S by, for example, a plating method.

  Further, the insulating film 22 constitutes a base layer of the rewiring 21. It is made of an organic material having a lower dielectric constant than the insulating film 14 made of an inorganic material. In the present embodiment, the insulating film 22 is made of, for example, polyimide resin. By using an organic insulating film as the insulating film 22, the parasitic capacitance formed between the rewiring 21 and the wiring layer 13 can be reduced. The thickness of the insulating film 22 (distance from the adhesion interface with the insulation film 23 to the adhesion interface with the insulation film 14) is about 3 to 5 μm.

  The insulating film 22 includes an opening 22H that penetrates the insulating film 22 in the thickness direction. A contact portion 21C of the rewiring 21 is embedded in the opening 22H. The opening 22H is formed on the pad 11C (on the cover film 15C in the example shown in FIG. 4). A part of the cover film 15C is exposed from the insulating film 22 in the opening 22H. With this configuration, the contact portion 21C and the cover film 15C can be electrically connected.

  The insulating film 23 is formed so as to cover the rewiring 21 and functions as a protective film for protecting the rewiring 21. The insulating film 23 is made of an organic insulating film such as a polyimide film. The insulating film 23 has the main surface PMSt of the semiconductor device PAC1. Adhesiveness with the insulating film 22 can be improved by using the insulating film 23 as an organic insulating film.

  The insulating film 23 includes an opening 23H that penetrates the insulating film 23 in the thickness direction. A conductive film UBM is embedded in the opening 23H. The opening 23H is formed on the land portion 21L of the rewiring 21. A part of the land portion 21L is exposed from the insulating film 23 in the opening 23H. With this configuration, the conductive film UBM and the land portion 21L can be electrically connected.

  Further, as shown in FIG. 4, the cover film 15T has a scratch mark (probe mark) SCR. Although details will be described later, the scratch mark SCR is a mark obtained by pressing the probe needle against the cover film 15T when an electrical inspection is performed in the manufacturing process of the semiconductor device PAC1. As shown in FIG. 4, in the case of the present embodiment, the scratch mark SCR and the rewiring 21 are overlapped in the thickness direction. In other words, the wiring part 21W of the rewiring 21 and the scratch mark SCR overlap in plan view. As will be described in detail later, in the case of the semiconductor device PAC1 of the present embodiment, the probe needle is brought into contact with the cover film 15T formed on the pad 11T. Thereby, the unevenness | corrugation of abrasion trace SCR can be made small.

<Method for Manufacturing Semiconductor Device>
Next, a method for manufacturing the semiconductor device of the present embodiment will be described. In this section, the manufacturing process of the semiconductor device PAC1 will be described along the manufacturing process flow shown in FIG. FIG. 5 is an explanatory diagram showing an example of a manufacturing process flow of the semiconductor device shown in FIG. The manufacturing process flow shown in FIG. 5 is an example, and there are various modifications. For example, you may implement another process in the middle of each process shown in FIG. Further, for example, the order of the steps may be changed within a range that does not impair the technical idea described below. Further, in the following description, the wafer preparation process, the cover film forming process for forming the cover film 15 covering the pad 11, and the wafer inspection process for performing electrical inspection of the circuit formed on the wafer are respectively separate processes. Will be described. However, as a modification, the cover film forming process can be regarded as a part of the wafer preparation process. Further, the cover film forming process and the wafer inspection process can be regarded as a part of the wafer preparation process.

<Wafer preparation process>
The manufacturing method of the semiconductor device according to the present embodiment includes a wafer preparation process. In the wafer preparation process, for example, a wafer WH1 shown in FIGS. 6 to 8 is prepared. FIG. 6 is a plan view of the semiconductor wafer prepared in the wafer preparation process shown in FIG. FIG. 7 is an enlarged plan view of a portion A in FIG. FIG. 8 is an enlarged cross-sectional view along the line AA in FIG.

  A wafer WH1 shown in FIG. 6 has a main surface WHt having a substantially circular planar shape. The main surface WHt of the wafer WH1 corresponds to the upper surface 14t of the insulating film 14 of the semiconductor chip 10 shown in FIG. The wafer WH1 has a plurality of chip areas WHc, and each chip area WHc corresponds to the semiconductor chip 10 shown in FIG. In the plurality of chip regions WHc, a semiconductor element, a pad 11, a semiconductor substrate 12, a wiring layer 13, and an insulating film 14 included in the semiconductor chip 10 shown in FIG. 4 are formed.

  In addition, a scrub region WHs is formed between adjacent chip regions WHc among the plurality of chip regions WHc. The scrub region WHs is formed in a lattice shape, and divides the main surface WHt of the wafer WH1 into a plurality of chip regions WHc. Each of the plurality of chip regions WHc includes sides PS1, PS2, PS3, and PS4 corresponding to the sides of the main surface PMSt shown in FIG. That is, the chip region WHc includes a side PS1 extending in the X direction, a side PS2 opposite to the side PS1, a side PS3 extending in the Y direction intersecting the X direction, and a side PS4 opposite to the side PS3. Although not shown, a plurality of conductor patterns may be formed in the scrub region WHs. This conductor pattern includes a TEG (Test Element Group) for confirming whether or not a semiconductor element or the like formed in the chip region WHc is correctly formed.

  The wafer preparation process for preparing the wafer WH1 shown in FIGS. 6 to 8 includes the following processes. First, the wafer preparation step includes a semiconductor substrate preparation step of preparing a semiconductor substrate 12 (see FIG. 4) serving as a base material. The semiconductor substrate 12 is a substantially circular wafer (for example, a silicon wafer). The semiconductor substrate 12 includes a plurality of chip regions WHc shown in FIG. 6 in plan view. Note that the chip region WHc shown in FIG. 6 is a region that becomes the semiconductor chip 10 (see FIG. 2) by dicing, and the boundary between the chip region WHc and the scrub region WHs is visually recognized as shown in FIG. It does not have to be partitioned in a possible state.

  The wafer preparation step includes a semiconductor element formation step of forming a plurality of semiconductor elements on the semiconductor element formation surface 12t (see FIG. 4) of the semiconductor substrate 12 after the semiconductor substrate preparation step. The wafer preparation step includes a chip wiring layer forming step of forming a wiring layer (chip wiring layer) 13 (see FIG. 4) on the semiconductor element forming surface 12t (see FIG. 4) after the semiconductor element forming step. . The wiring layer 13 includes a wiring electrically connected to the semiconductor element and an insulating layer 13i (see FIG. 8) that insulates between adjacent wirings.

  Further, the wafer preparation process includes a pad forming process for forming the pad 11 on the main surface 13t of the wiring layer 13 as the pad forming surface, as shown in FIG. 8, after the chip wiring layer forming process. In the pad forming step, a pad 11 which is a metal film made of a metal material (aluminum or aluminum alloy) containing aluminum as a main component is formed on the main surface 13t. In the present application, the metal film constituting the main part of the pad 11 is called a film made of aluminum or an aluminum film. The film made of aluminum or the aluminum film is made of aluminum, in addition to a metal film made only of aluminum. Also includes alloy films. Although not shown in FIG. 8, as shown in FIG. 10 to be described later, a barrier such as titanium nitride (TiN) or chromium nitride (CrN) is provided between the pad 11 that is an aluminum film and the main surface 13t. A metal film 11BM may be interposed. The barrier metal film 11BM may be formed on the upper layer of the aluminum film (on the upper surface 11t).

  The pad 11 formed in the pad forming process includes a pad 11T and a pad 11C. Different potentials or signals are supplied to the pad 11T and the pad 11C. For example, the pad 11T is supplied with an inspection signal for circuit inspection or an inspection potential in the wafer inspection process shown in FIG. The pad 11C is connected to a semiconductor element formed on the semiconductor element formation surface 12t via an input / output circuit (not shown). When the pad 11C is a signal control system pad, an input signal to the semiconductor element or an output signal from the semiconductor element is supplied to the pad 11C. When the pad 11C is a power supply system pad for driving the circuit, the power supply potential or the reference potential supplied to the power supply system circuit is supplied to the pad 11C. The pad 11T and the pad 11C are connected to different circuits. Further, the circuit for supplying a potential or signal to the pad 11T and the circuit for supplying a potential or signal to the pad 11C are electrically separated.

The wafer preparation step includes a protective film forming step of forming an insulating film 14 as a protective film so as to cover the main surface 13t of the wiring layer 13 and the pad 11 after the pad forming step. In the protective film forming step, the insulating film 14 made of an inorganic insulating material such as silicon oxide (SiO ₂ ) or silicon nitride (SiN) is formed. The insulating film 14 may be a laminated film of a plurality of layers of inorganic insulating films. In the protective film forming step, the whole of the plurality of pads 11 is covered with the insulating film 14.

  Further, the wafer preparation process includes an opening forming process in which a plurality of openings 14H are formed in the insulating film 14 after the protective film forming process, and a part of each of the plurality of pads 11 is exposed in the opening 14H. The pad 11 has a lower surface (back surface) 11 b facing the main surface 13 t of the wiring layer 13 and an upper surface (front surface) 11 t opposite to the lower surface. In the opening forming step, a part of the upper surface 11t of the pad 11 is exposed. However, the peripheral edge of the upper surface of the pad 11 does not overlap with the opening 14H. In other words, the periphery of the upper surface of the pad 11 is covered with the insulating film 14 even after the opening forming step. In the opening forming process, the aluminum film of the pad 11 is exposed. For example, as described above, when the barrier metal film 11BM (see FIG. 10 described later) is formed on the upper surface 11t of the aluminum film, a part of the barrier metal film 11BM is removed in the opening forming step. As a result, a part of the upper surface 11t of the aluminum film (a central portion inside the peripheral edge) is exposed from the insulating film 14 and the barrier metal film 11BM.

<Cover film formation process>
Further, the method for manufacturing the semiconductor device of the present embodiment includes a cover film forming step shown in FIG. In the cover film forming step, as shown in FIG. 9, a cover film 15 that is a cover film is formed so as to cover a portion of the pad 11 exposed from the insulating film 14. FIG. 9 is an enlarged cross-sectional view showing a state in which a cover film is formed on the pad shown in FIG. FIG. 10 is an enlarged cross-sectional view of the pad shown in FIG. FIG. 11 is a modified example of FIG. 10 and is an enlarged cross-sectional view when the conductive film on the pad is formed by electrolytic plating. FIG. 12 is an enlarged cross-sectional view when a conductive film which is a modification example of FIG. 10 is formed by an electroless plating method.

  Before explaining the details of the cover film forming step, the reason for carrying out the cover film forming step will be described. In the wafer inspection process shown in FIG. 5, an electrical test (inspection) of a circuit formed on the wafer is performed by electrically connecting the probe needle and the pad 11. At this time, when the probe needle is directly rubbed against the pad 11 made of aluminum, a part of the pad 11 is rejected by the probe needle, and a metal piece (aluminum piece) rises around the probe needle. As shown in FIG. 3, when the rewiring 21 connected to the pad 11 </ b> C and the pad 11 </ b> T overlap in a plan view, the rewiring 21 may come into contact with the metal piece rejected by the probe needle. It turns out that there is.

  Since different potentials or different signals are supplied to the pad 11C and the pad 11T as described above, it is necessary to avoid contact between the metal piece connected to the pad 11T and the rewiring 21 connected to the pad 11C. . This inventor examined the short-circuit avoidance measure of the pad 11C and the pad 11T.

  First, as a measure for avoiding a short circuit between the pad 11C and the pad 11T, a method of limiting the layout of the rewiring 21 so that the rewiring 21 connected to the pad 11C and the pad 11T do not overlap in a plan view can be considered. . In this case, even if a metal piece is generated by bringing the probe needle and the aluminum film into contact with each other in the wafer inspection process, a short circuit can be avoided if the distance between the pad 11T and the rewiring 21 is sufficiently large. However, in this method, the layout of the rewiring 21 is restricted. In particular, in recent years, the number of pads included in one semiconductor chip tends to increase as the functionality of semiconductor devices increases. Along with this, the number of rewirings 21 also increases. Therefore, when the layout of the rewirings 21 is restricted, an increase in the number of pads is hindered. Alternatively, the planar size of the semiconductor chip increases in order to secure a space for routing the rewiring 21.

  As another method, there is a method of increasing the thickness of the insulating film 22 shown in FIG. 4 (distance from the adhesive interface with the insulating film 23 to the adhesive interface with the insulating film 14) (for example, the insulating film 22). Thickness is greater than 5 μm). In the case of this method, a part of the pad 11 is rejected by the probe needle PR1 (see FIG. 13 described later), and the rewiring 21 connected to the pad 11C is replaced with the pad 11T, that is, a part of the rejected pad 11 ( The insulating film 22 is interposed between a part of the rejected pad 11 and the rewiring 21 even if it is routed so as to pass through the vicinity (upper side) of the metal piece (excluded by the probe needle PR1). Can do. For this reason, it can suppress that the metal piece and the rewiring 21 which were rejected with the probe needle PR1 mutually contact (short-circuit). However, in the case of this method, the aspect ratio of the opening 22H formed in the insulating film 22 for connecting the rewiring 21 to the pad 11C is increased, that is, the opening 22H is larger than the width of the opening 22H. The depth increases. Accordingly, there is a concern that the rewiring 21 is disconnected in the opening 22H.

  Therefore, from the viewpoint of increasing the density of the pads 11, reducing the size of the semiconductor chip, or rewiring reliability, the generation of metal pieces is suppressed in the wafer inspection process or the size of the metal pieces generated in the wafer inspection process. A technique for reducing the above is preferable.

  One of the reasons why aluminum is largely rejected by the probe needle in the wafer inspection process is that aluminum is a soft metal material. In addition, one of the reasons why a large amount of aluminum is eliminated by the probe needle in the wafer inspection process is that the aluminum film has a characteristic that an aluminum oxide film is easily formed on the surface. In this case, from the viewpoint of reducing the contact resistance between the probe needle and the pad 11, it is necessary to bite the probe needle so as to penetrate the oxide film formed on the surface of the pad 11 made of aluminum. As a result, the probe needle is rubbed against the pad 11 with a strong force, and as a result, a lot of aluminum is eliminated, and the size of the metal piece increases.

  Therefore, the cover film 15 formed in the cover film forming step of the present embodiment includes a conductive material harder than aluminum. For example, the cover film 15 contains palladium (Pd) as a main component. Specifically, as shown in FIG. 10, the cover film 15 is a laminated film of a conductive film 15L1 made of nickel (Ni) and a conductive film 15L2 made of palladium. Palladium and nickel are both harder than aluminum (in other words, have a higher Young's modulus). For this reason, when the probe needle is rubbed against the cover film 15 in a wafer inspection process to be described later, the amount of metal eliminated can be reduced compared to the case where the probe needle is rubbed against the pad 11.

  For example, when a probe needle is rubbed against an aluminum pad 11, a metal piece having a height exceeding 3 μm is formed so as to rise from the upper surface 11 t of the pad 11. On the other hand, when the probe needle is rubbed against the conductive film 15L2, even if a metal piece is generated, its height is 0.5 μm or less.

  Palladium is a conductive material that is less likely to be oxidized than aluminum (in other words, has a lower ionization tendency). For this reason, even if the probe needle does not bite into the conductive film 15L2, the contact resistance between the probe needle and the conductive film 15L2 is small. Further, since the contact resistance between the probe needle and the conductive film 15L2 is small, the force for rubbing the probe needle against the conductive film 15L2 can be reduced. Thereby, a metal piece can be made hard to generate | occur | produce further. As a result, the thickness of the insulating film 22 can be reduced. In the present embodiment, as described above, the thickness of the insulating film 22 is about 3 to 5 μm. However, the thickness may be thinner if it is thicker (if higher) than the metal piece. .

  Note that the cover film 15 may be a single-phase film of a conductive film 15L2 made of palladium. However, considering the bonding characteristics between the palladium film and the aluminum film, it is preferable that a nickel film is interposed between the palladium film and the aluminum film. Therefore, in the present embodiment, the conductive film 15L1 is interposed between the conductive film 15L2 and the pad 11 as shown in FIG.

  The cover film 15 is formed by a plating method. Specifically, in the case of the present embodiment, the cover film 15 is formed by an electroless plating method. The cover film 15 can also be formed by an electrolytic plating method. However, from the following viewpoint, the cover film 15 is preferably formed by an electroless plating method.

  In the case of the electrolytic plating method, as shown in FIG. 11, a mask (plating mask) PM is disposed so as to cover the insulating film 14. The mask PM has an opening PMH, and the cover film 15 is grown on the plated surface exposed in the opening PMH. For this reason, when the alignment accuracy between the opening 14H of the insulating film 14 and the opening PMH of the mask PM is low, the positional deviation between the cover film 15 and the pad 11 increases. When the arrangement density of the pads 11 is high as in the present embodiment, the pads 11 arranged adjacent to each other may be short-circuited via the cover film 15 depending on the degree of positional deviation between the cover film 15 and the pad 11. There is a concern.

  On the other hand, when the cover film 15 is formed by an electroless plating method as in the present embodiment, the cover film 15 is a portion of the upper surface 11t of the pad 11 exposed from the insulating film 14 as shown in FIG. Selectively grow on top. In other words, in the case of the electroless plating method, the position where the cover film 15 is formed is controlled by the opening 14 </ b> H provided in the insulating film 14. Therefore, in the case of the electroless plating method, it is not necessary to consider the positional deviation between the cover film 15 and the pad 11 described above.

  However, even when the cover film 15 is formed by the electroless plating method, the cover film 15 spreads on the insulating film 14 if the cover film 15 continues to grow. And if the cover film | membrane 15 spreads excessively, the adjacent pads 11 may short-circuit. In the case of the present embodiment, as shown in FIG. 3, the cover film 15 is in the opening 14H and not outside (outside) the opening 14H in plan view. Thus, if the range in which the cover film 15 is formed is inside the opening 14 </ b> H in plan view, the adjacent pads 11 can be prevented from being short-circuited via the cover film 15.

  When the film is formed by the electroless plating method, as shown in FIG. 10, the thickness of the cover film 15 in the central portion of the opening 14H may be larger than the thickness of the cover film 15 in the peripheral portion. In this case, in the thickness direction of the cover film 15 (Z direction shown in FIG. 10), the thickest portion may rise to a position higher than the upper surface 14t of the insulating film 14 at the peripheral edge of the opening 14H.

  Further, as a modification of the film forming method for forming the cover film 15, in addition to the electroless plating method described in the present embodiment, the film forming method by the electroplating method shown in FIG. There are various modifications. However, as described above, from the viewpoint of preventing adjacent pads 11 from being short-circuited via the cover film 15, a conductive film is selectively formed in a region where a conductive material such as a metal material is exposed. A method that can be used is preferred. For this reason, it is particularly preferable that the cover film 15 is formed by an electroless plating method.

  Further, as described above, the cover film 15 is a film formed to suppress the generation of metal pieces when the probe needle is brought into contact in the wafer inspection process. Therefore, the cover film 15 may not be formed on all the pads 11. For example, in the wafer inspection process described later, when there is a pad 11 that does not contact the probe needle, the cover film 15 may or may not be formed on the pad 11. When the cover film 15 is formed by electrolytic plating, the number of openings PMH of the mask PM shown in FIG. 11 can be reduced. On the other hand, when the cover film 15 is formed by the electroless plating method, the efficiency of the cover film forming process is better when the cover film 15 is formed on all the pads 11.

  There are various modifications to the configuration of the conductive material constituting the cover film 15 shown in FIGS. For example, as shown in FIG. 12, the cover film 15 may have a three-layer structure of a conductive film 15L1, a conductive film 15L2, and a conductive film 15L3.

  In the example shown in FIG. 12, the conductive film 15L2 contains a conductive material (for example, palladium) harder than aluminum as a main component. In addition, the conductive film 15L3 includes a conductive material (for example, gold (Au)) that is less likely to be oxidized (has a lower ionization tendency) than aluminum as a main component. The conductive film 15L1 between the conductive film 15L2 and the pad 11 contains, for example, nickel as a main component. Of the cover film 15 that is a laminated film, the conductive film 15L3 laminated on the uppermost layer has a lower electrical resistivity than the pad 11, the conductive film 15L1, and the conductive film 15L2. For this reason, in the wafer inspection process, the contact resistance between the probe needle and the cover film 15 can be reduced. The Young's modulus of gold is smaller than that of palladium or nickel (in other words, gold is soft). In the case where a conductive material containing gold as a main component is used for the conductive film 15L3, the thickness of the conductive film 15L3 is preferably thinner than the thickness of the conductive film 15L1, as shown in FIG. In the example shown in FIG. 12, the thickness of the conductive film 15L3 is about the same as the thickness of the conductive film 15L2, for example, about 0.5 μm. On the other hand, the thickness of the conductive film 15L1 is about 1 to 2 μm.

  Further, as shown in FIG. 10, FIG. 11 or FIG. 12, when the cover film 15 is a laminated film of a plurality of types of conductive films, among the plurality of conductive films 15L1, 15L2, 15L3 (see FIG. 11 and FIG. 12). The thickest conductive film 15L1 is preferably made of a conductive material harder than aluminum (in other words, having a higher Young's modulus).

  Further, as described above, nickel is harder than aluminum (in other words, has a higher Young's modulus). Accordingly, the conductive film 15L2 and the conductive film 15L1 shown in FIG. 12 may be formed of a conductive material containing nickel as a main component. In this case, as shown in FIG. 12, the uppermost layer of the cover film 15 is covered with a conductive film 15L3 formed of a conductive material that is less likely to be oxidized than nickel, such as gold (low ionization tendency). Is preferred.

  Further, the conductive film 15L3 may be formed of a conductive material mainly containing titanium (Ti) or a conductive material mainly containing chromium (Cr). Alternatively, the conductive film 15L3 may be a stacked film of conductive films made of a plurality of types of conductive materials among the conductive materials described above. In other words, the cover film 15 may be a laminated film of four or more conductive films. The structure of the conductive film is the same when the film is formed by electrolytic plating as shown in FIG.

  As an example of forming the cover film 15 by sputtering, a laminated film of a titanium (Ti) film (a conductive film containing titanium as a main component) and a palladium film (a conductive film containing palladium as a main component), or titanium nitride ( A laminated film of a (TiN) film (a conductive film containing titanium nitride as a main component) and a palladium film can also be exemplified.

<Wafer inspection process>
Further, the method for manufacturing a semiconductor device of the present embodiment includes a wafer inspection process shown in FIG. In the wafer inspection process, as shown in FIG. 13, the cover film 15T and the probe needle PR1 are brought into contact with each other to conduct an electrical test on the circuit formed on the wafer. FIG. 13 is an enlarged cross-sectional view schematically showing a state in which the pad of the semiconductor wafer and the probe needle for inspection are electrically connected in the wafer inspection step shown in FIG. FIG. 14 is an enlarged cross-sectional view showing the structure of the tip portion of the probe needle shown in FIG. FIG. 15 is an enlarged plan view of the periphery of the pad after the wafer inspection process.

  As schematically shown in FIG. 13, the probe needle PR1 is electrically connected to an inspection circuit (circuit) TC1. When the probe needle PR1 and the cover film 15T are brought into contact with each other in the wafer inspection process, the pad 11T and the inspection circuit TC1 are electrically connected. The pad 11T is electrically connected to the circuit WC1 formed in the chip region WHc of the wafer WH1. When the probe needle PR1 and the cover film 15T are brought into contact with each other in the wafer inspection process, the inspection circuit TC1 and the circuit WC1 are electrically connected. The pad 11T is, for example, a test pad. For example, a signal (inspection signal) or a potential (inspection potential) used for an electrical test of the circuit WC1 is supplied from the inspection circuit TC1 to the pad 11T. . Alternatively, the test output signal or potential output from the circuit WC1 is supplied to the pad 11T.

  As shown in FIG. 14, the probe needle PR1 includes a contact part PRc that contacts the cover film 15 and an extension part PRw that extends along the Y direction. Between the contact part PRc and the extension part PRw, There is a bent portion PRb that bends at an angle greater than 90 degrees. The probe needle PR1 having the structure shown in FIG. 14 is called a cantilever. When the probe needle PR1 is pushed down in the direction approaching the cover film 15 along the Z direction in FIG. 14, the tip of the contact portion PRc moves (slides) in the Y direction while being pressed against the cover film 15 (hereinafter referred to as a sliding operation). Called). By this sliding operation, a part of the contact portion PRc bites into the upper surface (exposed surface, surface) 15t of the cover film 15, and a good contact state (a state in which the contact resistance is reduced) is obtained. On the other hand, a scratch mark (probe mark, contact mark) SCR (see FIG. 15), which is a contact mark with the probe needle PR1, is formed on the upper surface 15t of the cover film 15.

  In the above-described sliding operation, a strong load is applied from the probe needle PR1. Therefore, when the cover film 15T as in the present embodiment is not provided and the probe needle PR1 and the pad 11 that is an aluminum film are brought into direct contact, a large amount of aluminum is eliminated by the above-described sliding operation. As a result, the unevenness of the scratch mark SCR becomes large, and a part thereof swells around the pad 11 as a metal piece. However, according to the present embodiment, the contact film 15 made of a conductive material harder than aluminum and the probe needle PR1 are brought into contact with each other, so that the unevenness of the scratch mark SCR can be suppressed.

  In the present embodiment, the probe needle PR1 (see FIG. 13) is brought into contact with each of the cover film 15T and the cover film 15C shown in FIG. Therefore, scratch marks SCR are formed on the cover film 15C and the cover film 15T, respectively. However, as a modification, the probe needle PR1 may be brought into contact with a part of the plurality of cover films 15. In this case, the scratch mark SCR is not formed on the cover film 15 that is not in contact with the probe needle PR1.

<Rewiring part formation process>
In addition, the method for manufacturing the semiconductor device of the present embodiment includes a rewiring part forming step shown in FIG.

  The rewiring portion forming step shown in FIG. 5 includes the following steps. First, in the rewiring portion forming process, as shown in FIG. 16, after the wafer inspection process, the insulating film 22 is formed on the upper surface 14t of the insulating film 14 so as to cover the pads 11T and 11C. Forming step. FIG. 16 is an enlarged cross-sectional view showing a state where an insulating film covering the pad is formed in the cross section taken along the line AA of FIG.

  In the present embodiment, as described above, the insulating film 22 is formed with the cover film 15 formed on each of the plurality of pads 11. Therefore, in the first insulating film forming step, the insulating film 22 is formed so as to cover the cover film 15T and the cover film 15C.

  The insulating film 22 formed on the insulating film 14 in this step is made of an organic material having a dielectric constant lower than that of the insulating film 14. In the present embodiment, the insulating film 22 is made of, for example, polyimide resin. As described above, by using an organic insulating film as the insulating film 22, the parasitic capacitance formed between the rewiring 21 and the wiring layer 13 shown in FIG. 4 can be reduced. Further, from the viewpoint of reducing the influence of parasitic capacitance on the rewiring 21, it is preferable to make the thickness of the insulating film 22 uniform. In this embodiment, as a method for making the thickness of the insulating film 22 uniform, the insulating film 22 is formed by a spin coating method.

  When the insulating film 22 is formed by the spin coating method, first, a liquid organic material (a liquid containing a polyimide resin and a solvent, which is hereinafter referred to as a raw material liquid) that is a raw material of the insulating film 22 is formed on the insulating film 14. Apply to. Thereafter, the raw material liquid is spread on the insulating film 14 by rotating the wafer WH1 and utilizing the centrifugal force. Thereafter, the solvent component contained in the raw material liquid is evaporated and the resin component is cured to obtain the insulating film 22 made of polyimide resin. Other methods for forming the insulating film 22 include a method of applying the raw material liquid by discharging it from a nozzle, and a method of applying the raw material liquid with an inkjet head. The spin coating method is excellent in that the film thickness of the obtained film can be made uniform and the film thickness can be reduced as compared with the above modification. As another method for forming the insulating film 22, there is a method in which the insulating film 22 formed in a film shape is attached to the insulating film 14 in advance. However, from the viewpoint of improving the adhesion between the insulating film 22 and the insulating film 14, the insulating film 22 is preferably formed by spin coating as in the present embodiment.

  When the insulating film 22 is formed by the spin coating method, the raw material liquid is diffused by centrifugal force. For this reason, if a metal piece remains on the pad 11, depending on the size of the metal piece, the entire metal piece cannot be covered with the insulating film 22, and a part of the metal piece is exposed from the insulating film 22. May end up. The insulating film 22 is a base layer of the rewiring 21 shown in FIG. For this reason, if a part of the metal piece is exposed from the insulating film 22, the rewiring 21 and the metal piece come into contact with each other. Alternatively, the layout restriction of the rewiring 21 increases.

  In the case of the present embodiment, the probe needle PR1 is brought into contact with the cover film 15 as described with reference to FIG. In this case, the height of the unevenness of the scratch mark SCR shown in FIG. 4 can be reduced. For this reason, according to the present embodiment, even when the spin coating method is employed as the method of forming the insulating film 22, it is possible to prevent a part of the scratch mark SCR from being exposed from the insulating film 22. If the scratch mark SCR is covered with the insulating film 22, the rewiring 21 and the scratch mark SCR shown in FIG. Therefore, as shown in FIG. 4, the scratch mark SCR of the cover film 15T and the rewiring 21 connected to the pad 11C overlap (in other words, the scratch mark SCR of the cover film 15T and the pad 11C in plan view). Even in the state where the rewiring 21 connected to is overlapped), the pad 11T and the pad 11C are not short-circuited. In other words, according to the present embodiment, the degree of freedom of layout of the rewiring 21 can be improved.

  Further, in the rewiring portion forming step, as shown in FIG. 17, after the first insulating film forming step, an opening 22H is formed in the insulating film 22 so that a part of the upper surface 15t of the cover film 15C is exposed from the insulating film 22. Including a first opening forming step. FIG. 17 is an enlarged cross-sectional view showing a state in which an opening is formed in the insulating film shown in FIG.

  In the first opening forming step, the upper surface 15t of the cover film 15C formed on the pad 11C is exposed in order to electrically connect the pad 11C to the terminal SB (see FIG. 4) which is an external terminal. As a modification of the present embodiment, the cover film 15C may not be formed on the pad 11C (when the probe needle PR1 shown in FIG. 13 is not brought into contact with the pad 11C in the wafer inspection process). In this case, in the first opening forming step, the opening 22H is formed so that the upper surface 11t of the pad 11 is exposed from the insulating film 22.

  The opening 22H is formed by etching, for example. The opening area of the opening 22H (specifically, the opening area of the bottom) is smaller than the plane area of the cover film 15 shown in FIG. 15 (in other words, the opening area of the opening 14H shown in FIG. 7).

  In the present embodiment, the pad 11T shown in FIG. 17 is an inspection pad used in the wafer inspection process, and is not connected to the plurality of terminals SB shown in FIG. In this case, the opening 22H is not formed on the cover film 15T, and the cover film 15T is entirely covered with the insulating film 22.

  However, as a modification of the present embodiment, in the case where the pad 11T is electrically connected to the terminal SB shown in FIG. 2, in this step, the opening 22H is also formed on the cover film 15T, and the cover film A part of the upper surface 15t of 15T is exposed from the insulating film 22 in the opening 22H.

  Further, the rewiring portion forming step includes a rewiring forming step of forming a rewiring (conductor pattern) 21 on the insulating film 22 after the first opening forming step as shown in FIGS. 18 and 19. . FIG. 18 is an enlarged plan view showing a state in which a rewiring is formed on the insulating film shown in FIG. FIG. 19 is an enlarged cross-sectional view showing a state in which rewiring is formed on the insulating film shown in FIG.

  As shown in FIGS. 18 and 19, the rewiring 21 electrically connected to the pad 11C is formed so that the contact portion 21C overlaps the pad 11C. The contact portion 21C is formed in the opening 22H of the insulating film 22 and in the vicinity thereof. In addition, each of the wiring portion 21W connected to the contact portion 21C and the land portion 21L (see FIG. 18) connected to the contact portion via the wiring portion 21W is formed on the upper surface 22t of the insulating film 22. In the case of the present embodiment, a metal piece or the like generated in the wafer inspection process is not exposed on the upper surface 22t of the insulating film 22. For this reason, the wiring part 21W and the land part 21L are efficiently arranged on the upper surface 22t of the insulating film 22 regardless of the structure of the lower layer of the insulating film 22.

  For example, as shown in FIGS. 18 and 19, the wiring portion 21W of the rewiring 21 electrically connected to the pad 11C is arranged at a position overlapping the pad 11T to which a signal or potential different from the pad 11C is supplied. ing. In the example shown in FIGS. 18 and 19, the wiring portion 21W of the rewiring 21 that is electrically connected to the pad 11C is disposed at a position overlapping the cover film 15T formed on the pad 11T. Further, as shown in FIG. 18, in the example of the present embodiment, the wiring portion 21W of the rewiring 21 electrically connected to the pad 11C overlaps the scratch mark (contact mark) SCR remaining on the cover film 15T. Is arranged.

  As described above, according to the present embodiment, since the degree of unevenness in the scratch mark SCR can be reduced, the wiring portion 21W of the rewiring 21 is arranged even at a position overlapping with the scratch mark SCR or a peripheral region thereof. can do.

  In the rewiring forming step, first, a seed layer 21S is formed in the upper surface 22t and the opening 22H of the insulating film 22. The seed layer 21S is a conductive thin film such as copper or nickel, and is formed by, for example, a sputtering method. Next, the seed layer 21S is patterned using a photolithography technique. Thereafter, the conductor layer 21M is stacked on the patterned seed layer 21S. The conductor layer 21M is a metal film mainly composed of copper, for example, and is formed by, for example, an electrolytic plating method.

  Further, in the rewiring portion forming step, as shown in FIG. 20, after the rewiring forming step, an insulating film 23 is formed on the insulating film 22 so as to cover the rewiring 21 and the insulating film 22. Including a film forming step. FIG. 20 is an enlarged cross-sectional view showing a state where the rewiring shown in FIG. 19 is covered with an insulating film. As described above, the insulating film 23 is made of an organic insulating film such as a polyimide film. The insulating film 23 functions as a protective film that protects the rewiring 21. By making the insulating film 23 an organic insulating film, the adhesion between the insulating film 22 and the insulating film 23 is improved, so that moisture and impurities can be prevented from entering the rewiring 21 from the outside. The insulating film 23 is made of a material harder (having a larger Young's modulus) than the insulating film 22. Thereby, the structural member of semiconductor device PAC1 (refer FIG. 4) including the rewiring 21 can be protected from external force.

  Further, in the rewiring portion forming step, as shown in FIG. 21, after the second insulating film forming step, an opening 23H is formed so that a part of the rewiring 21 (land portion 21L) is exposed from the insulating film 23. A second opening forming step. FIG. 21 is an enlarged cross-sectional view showing a state in which the opening is formed on the land portion of the rewiring in the second opening forming step shown in FIG. The opening 23H is formed in a region of the rewiring 21 that overlaps the land 21L. A part of the upper surface (front surface) 21Lt of the land portion 21L is exposed from the insulating film 23 in the opening 23H.

  In addition, as shown in FIG. 22, the rewiring portion forming step includes a conductive film forming step of forming a conductive film UBM on the land portion 21L of the rewiring exposed in the opening after the second opening forming step. Including. FIG. 22 is an enlarged cross-sectional view showing a state in which a conductive film is formed in the opening on the land portion of the rewiring shown in FIG. The conductive film UBM is disposed between the terminal SB (see FIG. 4) and the rewiring 21 and is called an under bump metal, and is formed by, for example, an electrolytic plating method or an electroless plating method. The conductive film UBM is made of a conductive material having a high solder barrier property, and by providing the conductive film UBM, diffusion of solder from the terminal SB can be suppressed. However, as a modification, the terminal SB may be joined to a portion exposed from the insulating film 23 of the land portion 21L without providing the conductive film UBM. In this case, the conductive film forming step in the rewiring portion forming step can be omitted.

<External terminal formation process>
Further, the method for manufacturing the semiconductor device of the present embodiment includes an external terminal forming step shown in FIG. FIG. 23 is an enlarged plan view showing a state in which a plurality of external terminals are formed on the rewiring layer of the semiconductor wafer in the external terminal forming step shown in FIG. In FIG. 23, one of the plurality of chip regions WHc included in the wafer WH1 is shown enlarged.

  As shown in FIG. 23, in the present embodiment, each of the terminals SB is inside the peripheral edge of the chip region WHc in plan view. Specifically, each of the plurality of terminals SB is inside the chip region WHc. Sides PS1, PS2, PS3, and PS4 are included in the peripheral portion of the chip region WHc. Further, the peripheral portion of the chip region WHc can be defined as a boundary between the chip region WHc and the scrub region WHs. A WLP in which a plurality of terminals SB are arranged inside the peripheral portion of the chip region WHc as in the present embodiment is referred to as FIWLP (Fan-In Wafer Level Package). On the other hand, as will be described later as a modified example, a WLP in which a part of the plurality of external terminals is arranged outside the chip region is referred to as FOWLP (Fan-Out Wafer Level Package).

  The terminal SB is electrically connected to the rewiring 21 (see FIG. 22), for example, by the following method. First, flux is supplied to the conductive film UBM (see FIG. 22) formed on the land portion 21L (see FIG. 22) of the rewiring 21 by printing or a transfer method. Next, a plurality of solder balls are aligned on the flux and placed on the land portion 21L. Next, in a reflow process of heating the wafer WH1, each solder ball is melted and joined to the conductive film UBM, and then radiated to obtain the terminal SB shown in FIG.

<Individualization process>
In addition, the method for manufacturing a semiconductor device according to the present embodiment includes an individualization step shown in FIG. In the individualization step, the wafer WH1 is cut along the scrub region WHs shown in FIG. 23, and individualized for each chip region WHc. As a method for cutting the wafer WH1, a general dicing technique for obtaining a plurality of semiconductor chips by dividing a semiconductor wafer can be applied. For example, in the present embodiment, the scrubbing region WHs is cut using a cutting jig called a dicing blade and separated into a plurality of semiconductor devices PAC1. However, when the insulating film 22 or the insulating film 23 shown in FIG. 20 is formed in the scrub region WHs, it is preferable to remove the organic insulating film in advance by laser irradiation or the like before cutting with the dicing blade.

  After the singulation process, necessary inspections and tests such as an appearance inspection and an electrical test are performed, and what has passed is a completed semiconductor device PAC1 shown in FIGS. The semiconductor device PAC1 is shipped or mounted on a mounting board (not shown).

  In addition, although some modifications were demonstrated also in the said embodiment, below, the typical modifications other than the modification demonstrated in the said embodiment are demonstrated.

<Modification 1>
For example, in FIGS. 1 to 23, the FIWLP in which the plurality of terminals SB are arranged inside the peripheral portion of the chip region WHc has been described. However, the technique for avoiding the adjacent pads 11 from short-circuiting due to contact between the rewiring and the metal piece can be applied to various WLPs. For example, the above-described technique may be applied to FOWLP in which some of a plurality of terminals are arranged outside the chip region WHc. FIG. 24 is a plan view of the mounting surface side of the semiconductor device which is a modified example with respect to FIG. 25 is a cross-sectional view taken along line AA in FIG. FIG. 26 is an enlarged plan view showing an example of a connection relationship between pads and terminals by rewiring provided in the semiconductor device shown in FIG. In FIG. 26, a part of the plurality of rewirings 21 included in the rewiring unit 20, the outline of the semiconductor chip 10 below the rewiring unit 20, and the outline of the pad 11 are shown by solid lines.

  The semiconductor device PAC2 shown in FIGS. 24 to 26 is shown in FIGS. 1 to 4 in that the periphery of the semiconductor chip 10 in plan view and the back surface 10b of the semiconductor chip 10 are sealed by the sealing body 30. Different from PAC1. Further, the semiconductor chip 10 includes a side CS1 extending along the side PS1 of the main surface PMSt, a side CS2 opposite to the side CS1, a side CS3 extending in the Y direction intersecting the X direction, and a side CS4 opposite to the side CS3. Is provided. In plan view, the side CS1 intersects with each of the sides CS3 and CS4, and the side CS2 intersects with each of the sides CS3 and CS4. Each of sides CS1, CS2, CS3, and CS4 is inside the peripheral edge of main surface PMSt.

  Further, as shown in FIG. 24, the semiconductor device PAC2 is different from the semiconductor device PAC1 shown in FIG. 1 in that some of the plurality of terminals SB are outside the semiconductor chip 10 (chip region) in plan view. Specifically, in the case of the semiconductor device PAC2, a part of the plurality of terminals SB is outside the semiconductor chip 10 (chip region) in plan view, and the other part of the plurality of terminals SB is the semiconductor chip 10. Located inside the periphery. That is, the semiconductor device PAC2 is FOWLP.

  The positional relationship between the semiconductor chip 10 and the peripheral edge of the semiconductor chip 10 may be expressed as follows. That is, at least some of the plurality of terminals SB of the semiconductor device PAC2 are between the side CS1 of the semiconductor chip 10 and the side PS1 of the semiconductor device PAC2, between the side CS2 and the side PS2, and between the side CS3 and the side PS3. Or between the side CS4 and the side PS4. Further, at least a part of the plurality of terminals SB of the semiconductor device PAC2 is in a region surrounded by the sides CS1, CS2, CS3, and CS4.

  As shown in FIG. 26, in the case of FOWLP, the plurality of pads 11 are arranged inside the semiconductor chip 10, and the terminals SB are outside and inside the semiconductor chip 10. For this reason, the layout of the rewiring 21 is complicated. For this reason, as shown in FIG. 26, a part of the rewiring 21 (wiring portion 21W) electrically connected to the pad 11C and the pad 11T to which a signal or potential different from the pad 11C is supplied are seen in a plan view. In some cases, the layout of the rewiring 21 can be made efficient by arranging the rewiring 21 so as to overlap each other.

  Therefore, also in this modification, as shown in FIG. 13 described in the above wafer inspection process, it is preferable that the probe needle PR1 is brought into contact with the cover film 15 in a state where the cover film 15 is formed on the pad 11T. As a result, the size of the unevenness of the scratch mark SCR (see FIG. 4) formed by the sliding operation of the probe needle PR1 can be reduced, so that even at a position overlapping the scratch mark SCR or its peripheral region. The wiring portion 21W of the rewiring 21 can be disposed.

  The manufacturing process of the semiconductor device PAC2 shown in FIGS. 24 to 26 is different from the manufacturing process shown in FIG. 5 in the following points, for example. FIG. 27 is an explanatory diagram showing an example of a manufacturing process flow of the semiconductor device shown in FIGS.

  As shown in FIG. 27, in this modification, the singulation process is performed after the wafer inspection process and before the rewiring portion forming process. Moreover, in this modification, a sealing process is implemented after an individualization process and before a rewiring part formation process. In the sealing step, the side surface and the back surface 10b of the semiconductor chip 10 shown in FIG. Specifically, in the sealing step, a substrate (not shown) is attached to the upper surface (upper surface 14t shown in FIG. 25) of the semiconductor chip 10 before resin sealing. This substrate is a base material that prevents the upper surface 14t side of the semiconductor chip 10 from being resin-sealed. For this reason, the substrate has a larger area than the upper surface 14t, and the entire upper surface 14t is covered with the substrate. In this state, the semiconductor chip 10 attached to the substrate is sealed with resin. The sealing body 30 is sealed by a transfer mold method using, for example, a sealing material containing a thermosetting resin as a main component as a raw material. According to this manufacturing method, as shown in FIG. 25, the rewiring portion 20 is formed not only on the upper surface 14 t of the semiconductor chip 10 but also on the upper surface 30 t of the sealing body 30. In this case, some of the plurality of terminals SB are disposed above the upper surface 30 t of the sealing body 30.

  Except for the above differences, the semiconductor device PAC2 shown in FIGS. 24 to 26 is the same as the semiconductor device PAC1 shown in FIGS. 27 is the same as the method for manufacturing the semiconductor device shown in FIG. Therefore, the overlapping description is omitted.

<Modification 2>
For example, in FIG. 18 and FIG. 26, the embodiment in which the wiring part 21W of the rewiring 21 electrically connected to the pad 11C overlaps the pad 11T has been described. However, overlapping with the pad 11T is not limited to the wiring part 21W. For example, as in the semiconductor device PAC3 illustrated in FIG. 28, the land portion 21L of the rewiring 21 connected to the pad 11C may overlap the pad 11T. FIG. 28 is an enlarged plan view of a semiconductor device which is a modification to FIG. The semiconductor device PAC3 is the same as the semiconductor device PAC1 except that the land portion 21L overlaps the pad 11T in plan view.

<Modification 3>
Further, for example, in the example shown in FIG. 18, the contact portion 21 </ b> C of the rewiring 21 is connected to the pad 11 </ b> C at a position different from the region where the probe needle PR <b> 1 (see FIG. 13) contacts. This is a layout for preventing the resistance of the bonding interface between the contact portion 21C and the cover film 15 from increasing due to the contact portion 21C being formed on the scratch mark SCR.

  However, as described above, when the probe needle PR1 is brought into contact with the cover film 15, the unevenness of the scratch mark SCR can be reduced. For this reason, even if the contact portion 21 </ b> C is bonded onto the scratch mark SCR on the cover film 15, the increase in resistance at the bonding interface can be reduced. For example, in the case of the semiconductor device PAC4 shown in FIG. 29, the contact portion 21C is bonded onto the scratch mark SCR on the cover film 15. 29 is an enlarged cross-sectional view of a semiconductor device which is a modification to FIG.

  In the method for manufacturing the semiconductor device PAC4, the semiconductor wafer has a cover film 15C that is a conductive film formed so as to cover a portion of the pad 11C exposed from the insulating film 14. In the wafer inspection process described with reference to FIG. 5, the cover film 15C and the probe needle PR1 (see FIG. 13) are brought into contact with each other to electrically connect the pad 11C and the inspection circuit TC1 (see FIG. 13). The process of carrying out is included. Further, in the rewiring portion forming step described with reference to FIG. 5, an opening 22H is formed in a portion of the insulating film 22 that overlaps the cover film 15C, and the contact portion 21C of the rewiring 21 has a scratch mark SCR of the cover film 15C. Connected to the probe needle.

  As described above, when the contact portion 21 </ b> C is bonded onto the scratch mark SCR on the cover film 15, the area of the cover film 15 can be reduced. Thereby, the plane area of the semiconductor chip 10 can be reduced in size.

  The semiconductor device PAC4 shown in FIG. 29 is the same as the semiconductor device PAC1 except for the differences described above. Therefore, the overlapping description is omitted.

<Modification 4>
For example, as described above, various modified examples have been described, but the above-described modified examples can be applied in combination.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the above embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  Further, if the technical idea of the semiconductor device described in the above embodiment is extracted, it can be expressed as follows.

[Appendix 1]
Main surface,
A first electrode pad formed on the main surface and made of aluminum and supplied with a first signal or a first potential;
A second electrode pad formed on the main surface and made of aluminum and supplied with a second signal or a second potential different from the first signal or the first potential;
A first insulating film formed on the main surface and having a first opening exposing a part of the first electrode pad and a second opening exposing a part of the second electrode pad;
A first cover film made of a conductive material harder than aluminum and formed so as to cover a portion exposed from the first insulating film of the first electrode pad, and a scratch mark is formed;
A second insulating film containing an organic material and arranged to cover the first insulating film and the first electrode pad;
A first conductor pattern disposed on the second insulating film and electrically connected to the second electrode pad;
Have
The semiconductor device, wherein the first conductor pattern overlaps the first electrode pad in plan view.

10 Semiconductor chip 10b Back surface 11, 11C, 11T pad (electrode pad, aluminum pad)
11b Bottom (back)
11BM Barrier metal film 11t Upper surface (surface)
12 Semiconductor substrate 12t Semiconductor element formation surface (main surface)
13 Wiring layer (chip wiring layer)
13i Insulating layer 13t Main surface (electrode pad forming surface)
14 Insulating film (inorganic insulating film)
14H Opening 14t Upper surface (main surface, surface)
15, 15C, 15T Cover film (conductive film)
15L1, 15L2, 15L3 Conductive film 15t Upper surface (exposed surface, surface)
20 Rewiring section 21 Rewiring (conductor pattern)
21C Contact portion 21L Land portion 21Lt Upper surface (front surface)
21M Conductive layer 21S Seed layer 21W Wiring parts 22, 23 Insulating film (organic insulating film)
22H, 23H Opening 22t Upper surface 30 Sealing body 30t Upper surface CS1, CS2, CS3, CS4, PS1, PS2, PS3, PS4 Side PAC1, PAC2, PAC3, PAC4 Semiconductor device PM Mask (plating mask)
PMH Opening PMSb, PMSt Main surface PR1 Probe needle PRb Bending part PRc Contacting part PRw Extension part SB Terminal (external terminal, protruding electrode, solder ball)
SCR scratch mark (probe mark, contact mark)
TC1 Inspection circuit (circuit)
UBM Conductive film WC1 Circuit WH1 Wafer WHc Chip area WHs Scrub area WHt Main surface

Claims (11)

A semiconductor device manufacturing method including the following steps:
(A) a main surface, a first electrode pad formed on the main surface and made of aluminum and supplied with a first signal or a first potential; and formed on the main surface; A second electrode pad made of aluminum and supplied with a second signal or a second potential different from the first signal or the first potential; and formed on the main surface; and And a first insulating film having a first opening exposing a part of the first electrode pad and a second opening exposing a part of the second electrode pad, and a conductive material harder than aluminum. And preparing a semiconductor wafer having a first cover film formed to cover a portion of the first electrode pad exposed from the first insulating film;
(B) After the step (a), the step of bringing the first cover film into contact with the probe needle;
(C) After the step (b), a step of forming a second insulating film on the surface of the first insulating film so as to cover the first cover film;
(D) After the step (c), the first conductor pattern is moved to the second cover so that a part of the first conductor pattern electrically connected to the second electrode pad overlaps the first cover film. Forming on the surface of the insulating film; In claim 1,
The step (c) includes a step of spreading the organic material on the first insulating film by rotating the semiconductor wafer after applying a liquid organic material which is a raw material of the second insulating film. Manufacturing method. In claim 1,
The first cover film is a laminated film including a first conductive film made of a conductive material harder than aluminum and a second conductive film made of a conductive material hard to be oxidized than aluminum,
In the step (b), the probe needle is in contact with the second conductive film. In claim 3,
The first cover film has a third conductive film between the first conductive film and the first electrode pad,
The method of manufacturing a semiconductor device, wherein the second conductive film has a lower electrical resistivity than each of the first electrode pad, the first conductive film, and the third conductive film. In claim 1,
The semiconductor wafer further includes a second cover film that is a conductive film formed so as to cover a portion of the second electrode pad exposed from the first insulating film,
The method for manufacturing a semiconductor device, wherein the first cover film and the second cover film are formed by an electroless plating method. In claim 5,
The method of manufacturing a semiconductor device, wherein the first cover film is not outside the first opening in a plan view. In claim 1,
In the step (b), a contact mark of the probe needle is formed on the first cover film,
The method of manufacturing a semiconductor device, wherein the first conductor pattern overlaps the contact trace in a plan view. In claim 1,
(E) after the step (d), further comprising a step of connecting an external terminal to a part of the first conductor pattern;
The method of manufacturing a semiconductor device, wherein the external terminal overlaps the first electrode pad in a plan view. In claim 1,
The semiconductor wafer has a chip region,
(E) after the step (d), further comprising a step of connecting an external terminal to a part of the first conductor pattern;
The method of manufacturing a semiconductor device, wherein the external terminal is formed inside a peripheral portion of the chip region in a plan view. In claim 1,
The semiconductor wafer has a chip region,
(E) after the step (d), further comprising a step of connecting an external terminal to a part of the first conductor pattern;
The method of manufacturing a semiconductor device, wherein the external terminal is located outside a peripheral portion of the chip region in a plan view. In claim 1,
The semiconductor wafer further includes a second cover film that is a conductive film formed so as to cover a portion of the second electrode pad exposed from the first insulating film,
The step (b) includes a step of bringing the second cover film and the probe needle into contact with each other and electrically connecting the second electrode pad and the inspection circuit,
In the step (d), a third opening is formed in a portion of the second insulating film that overlaps the second cover film, and the first conductor pattern is a portion of the second cover film that is in contact with the probe needle A method for manufacturing a semiconductor device connected to a semiconductor device.

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