JP2019040898A - Substrate for semiconductor growth, semiconductor element, semiconductor light-emitting element and method of manufacturing semiconductor element - Google Patents

Abstract

To provide a substrate for semiconductor growth, a semiconductor element, a semiconductor light-emitting element and a method of manufacturing a semiconductor element capable of growing a high-quality a-plane GaN layer that has a good crystallinity and that is excellent in surface flatness.SOLUTION: A substrate for semiconductor growth uses an r-plane of sapphire (1) as a principal surface, and nano-sized unevenness (1a) is formed on the principal surface. The maximum dimension in an in-plane direction of the principal surface of the unevenness (1a) is less than 1 μm.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method, and more particularly to a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method for growing an a-plane GaN crystal layer.

  A compound semiconductor of a gallium nitride (GaN) -based material is generally used as an LED that emits purple to blue light used for illumination. In recent years, as an illuminating device using a light emitting diode (LED) has become widespread, it has been desired to increase the brightness of the LED chip. In order to increase the brightness of LEDs, the thickness of the light-emitting layer is increased to reduce the carrier density inside the light-emitting layer so that electrons and holes can efficiently recombine even when the current density is increased. There is a need.

  However, in a GaN-based semiconductor material having a c-plane as a main surface that is generally used, a piezoelectric electric field is generated in the c-axis direction. Therefore, a potential difference is generated in the thickened light emitting layer, and electrons and holes are spatially separated. As a result, there is a problem of the droop characteristic that the efficiency of light emission recombination is significantly reduced.

  In order to solve this problem, the light emitting layer is formed of a GaN-based material with a nonpolar or semipolar plane orientation as the main surface, thereby eliminating the influence of the piezoelectric field in the stacking direction and increasing the film thickness. Techniques that enable light emission with current have also been proposed. In a GaN-based semiconductor layer, the a-plane and m-plane are nonpolar planes, and r-planes are typical examples of antipolar planes.

  Patent Document 1 discloses a technique for growing an a-plane GaN layer on an r-plane of a sapphire substrate using a metal organic chemical vapor deposition method (MOCVD method: Metal Organic Chemical Vapor Deposition). The a-plane GaN layer formed on the r-plane sapphire substrate is used as an underlayer, and an n-type layer, a light-emitting layer, and a p-type layer are grown sequentially to increase the thickness of the main surface of the light-emitting layer as the a-plane. The droop characteristics of the LED can be improved.

  Conventionally, when a nitride-based semiconductor layer is grown on a c-plane sapphire substrate, an uneven structure is formed on the sapphire substrate (PSS: Patterned Sapphire Substrate) to reduce the defect density of the nitride semiconductor layer. Technology is used. In a PSS substrate having a c-plane as a main surface, the main surface of the semiconductor layer to be grown is also a c-plane having a small in-plane anisotropy, so that the growth proceeds isotropically and the semiconductor grows laterally on the concavo-convex structure. Dislocations bend in the layer, reducing dislocations and defects that continue to the surface of the semiconductor layer.

JP 2008-214132 A

  However, in the a-plane GaN formed on the r-plane sapphire, the + c-axis direction, the -c-axis direction, and the m-axis direction exist in the growth plane, and the in-plane anisotropy is large, and the r-plane is the main surface. Even when a PSS substrate is used, abnormal growth occurs on the concavo-convex structure, and it is difficult to obtain a high-quality a-plane GaN layer having good crystallinity and excellent surface flatness.

  FIG. 9 is an SEM image showing the state of the a-plane GaN layer in the case where a PSS substrate having irregularities of several μm size formed on the main surface of the r-plane sapphire substrate, and FIG. 9A shows the irregularities formed. FIG. 9B is an entire image of the a-plane GaN layer, FIG. 9C is a partially enlarged cross section, and FIG. 9D is a partially enlarged surface. As shown in FIG. 9A, when a plurality of conical protrusions having a height and width of several μm are formed on the main surface of the r-plane sapphire substrate, an AlN buffer layer and an a-plane GaN layer are grown. An a-plane GaN layer having a surface state such as 9 (b) was obtained.

  As indicated by the white arrows in the partially enlarged cross section of FIG. 9C, an abnormal growth region is generated inside the a-plane GaN layer above the irregularities. Further, FIG. 9D is an enlarged view of the region indicated by the black circles in FIG. 9B, and the influence of abnormal growth remains on the surface of the a-plane GaN layer. It can be seen that the crystallinity and surface flatness are not good.

  Accordingly, the present invention has been made in view of the above-described conventional problems, and a semiconductor growth substrate and semiconductor element capable of growing a high-quality a-plane GaN layer having good crystallinity and excellent surface flatness. An object of the present invention is to provide a semiconductor light emitting device and a semiconductor device manufacturing method.

  In order to solve the above problems, the semiconductor growth substrate of the present invention is characterized in that the r-plane of sapphire is the main surface, and nano-sized irregularities are formed on the main surface.

  In such a semiconductor growth substrate of the present invention, since the sapphire r-plane has nano-sized irregularities, the irregular growth of irregularities is suppressed, the crystallinity is good, and the surface flatness is high quality. An a-plane GaN layer can be grown.

  In one embodiment of the present invention, the unevenness has a maximum dimension in the in-plane direction of the main surface of less than 1 μm.

  In one embodiment of the present invention, an a-plane GaN layer is provided on the main surface.

  In one embodiment of the present invention, an AlN buffer layer is provided between the main surface and the a-plane GaN layer.

  In one embodiment of the present invention, a plurality of the irregularities are arranged in a triangular lattice pattern on the main surface.

  In order to solve the above-mentioned problems, a semiconductor element of the present invention is characterized in that the semiconductor growth substrate according to any one of the above is used and a functional layer is provided on the semiconductor growth substrate.

  In order to solve the above problems, a semiconductor light emitting device according to the present invention is characterized by using the semiconductor growth substrate according to any one of the above and having an active layer on the semiconductor growth substrate.

  In order to solve the above problems, a method for manufacturing a semiconductor device of the present invention includes a step of forming nano-sized irregularities on sapphire having an r-plane as a main surface, and a step of growing a nitride semiconductor layer on the main surface. It is characterized by providing.

  In such a semiconductor element manufacturing method of the present invention, nano-sized irregularities are formed on the r-plane of sapphire, so that the abnormal growth of irregularities is suppressed, the crystallinity is good, and the surface flatness is high quality. An a-plane GaN layer can be grown.

  The present invention provides a semiconductor growth substrate, a semiconductor element, a semiconductor light emitting element, and a semiconductor element manufacturing method capable of growing a high-quality a-plane GaN layer having good crystallinity and excellent surface flatness. it can.

It is a schematic diagram which shows the board | substrate for semiconductor growth in 1st Embodiment, Fig.1 (a) is a schematic cross section, FIG.1 (b) is a schematic plan view. It is process drawing which shows the formation method of the nanosized unevenness | corrugation 1a in 1st Embodiment, FIG.2 (a) is a resist application process, FIG.2 (b) is a nanoimprint and patterning process, FIG.2 (c) is an etching process, FIG. 2D shows a resist removal process. It is a figure which shows the growth sequence of the a-plane GaN layer 3 in 1st Embodiment. FIG. 4A is a SEM image showing a semiconductor growth substrate of Example 1, FIG. 4A is a planar image of an r-plane sapphire substrate (NPSS) on which nano-sized irregularities 1a are formed, and FIG. 4B is a nano-size image. 4 (c) is an enlarged perspective view showing the projections and recesses 1a in an enlarged manner, FIG. 4 (c) is an enlarged cross-section after the a-plane GaN layer 3 is grown, and FIG. 4 (d) is a diagram showing the growth of the a-plane GaN layer 3. It is a bird's-eye view after. It is a graph which shows the half value width of the result of having carried out the X-ray rocking curve measurement of the a-plane GaN layer 3 about Example 1 and a comparative example. FIGS. 6A and 6B are schematic cross-sectional views showing structures of Examples 1 and 2 and Comparative Examples 1 and 2. FIG. 6A is Comparative Example 2, FIG. 6B is Example 2, and FIG. FIG. 6B shows the first embodiment. FIG. 7A shows the results of X-ray rocking curve measurement for Examples 1 and 2 and Comparative Examples 1 and 2, and FIG. 7A shows the results of measuring (11-20) diffraction from the c-axis direction. ) Is the result of measuring (11-20) diffraction from the m-axis direction, and FIG. 7C is the result of measuring (10-12) diffraction. It is a schematic cross section which shows LED10 which is a semiconductor device of 2nd Embodiment. FIG. 9A is an SEM image showing the state of the a-plane GaN layer when using a PSS substrate having irregularities of several μm size formed on the main surface of the r-plane sapphire substrate, and FIG. 9A is an r-plane sapphire substrate having irregularities formed thereon. FIG. 9B is an overall image of the a-plane GaN layer, FIG. 9C is a partially enlarged cross section, and FIG. 9D is a partially enlarged surface.

(First embodiment)
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. FIG. 1 is a schematic view showing a semiconductor growth substrate in the first embodiment of the present invention, FIG. 1 (a) is a schematic cross-sectional view, and FIG. 1 (b) is a schematic plan view.

  As shown in FIG. 1A, the semiconductor growth substrate of this embodiment includes an r-plane sapphire substrate 1 having a hexagonal r-plane as a main surface, and an AlN buffer layer formed on the r-plane sapphire substrate 1. 2 and an a-plane GaN layer 3 formed on the AlN buffer layer 2 and having an a-plane as a main surface. In addition, nano-sized irregularities 1a are formed on the main surface of the r-plane sapphire substrate 1 (NPSS: Nano-Patterned Sapphire Substrate). Here, a just substrate having an inclination angle of 0 degrees is shown as the r-plane sapphire substrate 1, but an r-plane may be an off-substrate that is inclined several degrees in a predetermined plane orientation.

  The nano-sized unevenness 1a is a nanosized uneven structure formed by processing the main surface of the r-plane sapphire substrate 1, and includes, for example, a structure in which a plurality of conical protrusions are periodically arranged. Here, that the unevenness 1a is nano-sized means that the height or depth of the concave portion or the convex portion constituting the unevenness 1a and the size in the width direction are less than 1 μm. In the example shown in FIG. 1B, a plurality of nano-sized irregularities 1a are arranged on the main surface in a triangular lattice shape, and the c-axis direction of the a-plane GaN layer 3 grown on the r-plane sapphire substrate 1 Is parallel to one side of the triangular lattice. The pitch between adjacent irregularities 1a may be 1 μm or more, but in order to improve the crystal quality of the a-plane GaN layer 3, it is preferably formed with a pitch of less than 1 μm.

  The AlN buffer layer 2 is a layer for relaxing the difference in lattice constant between the r-plane sapphire substrate 1 and the a-plane GaN layer 3. The thickness of the AlN buffer layer 2 is preferably in the range of 5 to 300 nm, more preferably in the range of 5 to 90 nm, and still more preferably in the range of 5 to 30 nm because the crystal quality of the a-plane GaN layer 3 is deteriorated if the thickness is too large. . Here, an example in which the AlN buffer layer 2 is formed between the r-plane sapphire substrate 1 and the a-plane GaN layer 3 has been shown, but the r-plane sapphire substrate 1 of the r-plane sapphire substrate 1 is not required to be interposed as will be described later. By forming the nano-sized irregularities 1a on the main surface, the crystal quality of the a-plane GaN layer 3 can be improved and the surface flatness can be improved.

  The a-plane GaN layer 3 is a base layer grown so that the main surface is an a-plane, and is a layer for epitaxially growing a nitride semiconductor layer thereon. As a method for forming the a-plane GaN layer 3, a known method such as MOCVD method or HVPE method (hydride vapor phase epitaxy) can be used, but MOCVD method is preferably used. The thickness of the a-plane GaN layer 3 is not particularly limited, but is preferably 1 μm or more.

  Next, a method for manufacturing a semiconductor growth substrate in the present invention will be described with reference to FIGS. 2A and 2B are process diagrams showing a method for forming the nano-sized irregularities 1a in the present embodiment. FIG. 2A is a resist coating process, FIG. 2B is a nanoimprint and patterning process, and FIG. The etching process, FIG. 2D is a resist removal process. FIG. 3 is a diagram showing a growth sequence of the a-plane GaN layer 3 in the present embodiment.

  First, as shown in FIG. 2A, in the resist coating process, a single crystal sapphire substrate 1 having an r-plane as a main surface is prepared, and a resist is formed on the main surface of the sapphire substrate 1 by using a spin coat method or the like. The film 4 is applied. The type of the resist film 4 is not limited, and may be a thermosetting type or a UV curable type as long as nano-size patterning is possible.

  Next, as shown in FIG. 2B, in the nanoimprinting and patterning step, the pattern is transferred to the resist film 4 by using the nanoimprint technique using the mold 5 on which a predetermined pattern is formed. As a pattern transfer method, the mold 5 on which nano-sized irregularities are formed is pressed against the resist 4 and the resist film 4 is cured using a known method such as heat curing or UV curing. The material of the mold 5 is not limited as long as nano-size patterning is possible. In the example shown in FIG. 2B, an example in which the concave portion of the mold 5 is a circle having a diameter of less than 1 μm is shown.

Next, as shown in FIG. 2C, in the etching step, the sapphire substrate 1 is etched using the patterned resist film 4. The etching method of the sapphire substrate 1 is not particularly limited, but dry etching using a chlorine-based gas such as BCl ₃ can be used. As the etching of the sapphire substrate 1 proceeds, the resist film 4 is also etched, the size of the patterned resist film 4 gradually decreases, and the etched surface of the sapphire substrate 1 has a tapered shape.

  Next, as shown in FIG. 2D, in the resist removal step, the resist film 4 is removed and the surface of the sapphire substrate 1 is cleaned. By etching the sapphire substrate 1 in the etching step, a plurality of nano-sized irregularities 1 a are formed on the main surface of the sapphire substrate 1. Although FIG. 2D shows an example in which the upper part of the nano-sized unevenness 1a is a flat surface, the shape of the nano-sized unevenness 1a is adjusted by adjusting the thickness of the resist film 4 and the area to be patterned. Can be a conical protrusion with a sharp top.

  2A to 2D, a semiconductor growth substrate (NPSS) in which a plurality of nano-sized irregularities 1a are formed on the main surface of the sapphire substrate 1 whose main surface is the r-plane is obtained. . In the sapphire substrate 1 whose main surface is the r-plane on which the nano-sized irregularities 1a shown in FIG. 2D are formed, a high-quality a-plane GaN having excellent crystallinity and excellent surface flatness as described later. It is possible to grow layers.

Next, an AlN buffer layer 2 having a thickness of, for example, about 30 nm is formed on a sapphire substrate 1 (NPSS) on which a plurality of nano-sized irregularities 1a are formed. As a method for forming the AlN buffer layer 2, a known method such as an MOCVD method or a sputtering method can be used, but a sputtering method is preferably used. As a sputtering method for forming the AlN buffer layer 2, a reactive sputtering method using N ₂ and Ar gas with Al as a target material may be employed, but it is more preferable to use Ar gas with AlN as a target material. The AlN used as the target material may be a single crystal substrate or a powder fired body, and its state and form are not limited.

In the case where the AlN buffer layer 2 is formed using N ₂ and Ar gas with Al as the target material by reactive sputtering, in addition to the physical deposition process of the AlN film, the reaction between the Al target material and N ₂ gas. Process needs to be considered. Therefore, in the reactive sputtering method, the difficulty of setting and controlling the film forming conditions for obtaining the desired AlN buffer layer 2 is increased. In particular, when the area of a semiconductor substrate is increased, the in-plane distribution on the surface of the substrate needs to be taken into consideration, so that the difficulty becomes higher.

On the other hand, when the AlN buffer layer 2 is formed by sputtering using Ar gas with AlN as the target material, there is no need to consider the reaction process between the Al target material and N ₂ , and the Ar gas flow rate and the degree of vacuum in the chamber It is only necessary to optimize parameters such as. Therefore, it is easier to set and control the film formation conditions when forming the AlN buffer layer 2 by using the sputtering method using Ar gas with AlN as the target material than forming the AlN buffer layer 2 by the reactive sputtering method. Therefore, it is easy to cope with an increase in area.

Next, after cleaning the surface of the AlN buffer layer 2, hydrogen and nitrogen are used as a carrier gas, ammonia (NH ₃ ) is used as a group V source, and TMG (Trimethyl Gallium) is used as a group III source by MOCVD. The a-plane GaN layer 3 is grown by about 4 μm. At this time, the growth sequence is composed of two stages as shown in FIG. 3. After the temperature is raised to 1010 ° C., the growth temperature is kept constant in steps (I) and (II), the reactor pressure and the V / III ratio are increased. And changing the growth time. In step (I), for example, the V / III ratio is set to about 4000 to 5000, the pressure is set to 900 to 1000 hPa and maintained for about 10 to 20 minutes, and in step (II), for example, the V / III ratio is set to about 100 to 200 and the pressure is set. Maintain 100-150 hPa for 90-120 minutes. After the a-plane GaN layer 3 is grown and cooled to room temperature, a plurality of nano-sized irregularities 1a are formed on the main surface of the r-plane sapphire substrate 1, and the AlN buffer layer 2 and the a-plane GaN layer 3 are formed. In addition, the semiconductor growth substrate of this embodiment can be obtained.

Example 1
FIG. 4 is an SEM image showing the semiconductor growth substrate of Example 1, and FIG. 4A is a planar image of an r-plane sapphire substrate (NPSS) on which nano-sized irregularities 1a are formed, and FIG. ) Is an enlarged perspective view showing the nano-sized irregularities 1a in an enlarged manner, FIG. 4C is an enlarged cross-section after the a-plane GaN layer 3 is grown, and FIG. 4D is an a-plane GaN layer. It is a bird's-eye view after growing 3.

  As shown in FIGS. 4A and 4B, as Example 1, a conical protrusion having a width D of 900 nm and a height H of 600 nm on the main surface of the sapphire substrate 1 having the r-plane as the main surface. Was formed in a triangular lattice shape to obtain NPSS. The interval P between adjacent protrusions is 100 nm. On this NPSS, as described above, an AlN buffer layer 2 having a thickness of 30 nm was formed by sputtering, and an a-plane GaN layer 3 was grown by 4 μm by MOCVD. Abnormal growth did not occur in the a-plane GaN layer 3 as shown in FIG. 4C, and the surface condition was good as shown in FIG.

(Comparative Example 1)
Using a sapphire substrate having a flat r-plane as a main surface without forming irregularities, the AlN buffer layer 2 was formed to 30 nm by the sputtering method in the same manner as in Example 1, and the a-plane GaN layer 3 was grown to 4 μm by the MOCVD method.

  FIG. 5 is a graph showing the full width at half maximum as a result of measuring the X-ray rocking curve of the a-plane GaN layer 3 in Example 1 and Comparative Example 1. The vertical axis | shaft in a graph has shown the half value width (XRC-FWHM: X-ray Rocking Curve Width at Half Maximum) of a X-ray rocking curve measurement. On the horizontal axis of the graph, as a result of measuring (11-20) diffraction from the c-axis direction from the left, as a result of measuring (11-20) diffraction from the m-axis direction, and as a result of measuring (10-12) diffraction. Show. Further, Comparative Example 1 is shown on the left side with a-GaN / AlN / FSS, and Example 1 is shown on the right side with a-GaN / AlN / NPSS. As shown in the graph of FIG. 5, it can be seen that the a-plane GaN layer 3 having a smaller full width at half maximum of Example 1 than that of Comparative Example 1 and good crystallinity is formed in measurement from any direction. .

(Example 2)
Next, an a-plane GaN layer 3 was directly grown on an r-plane sapphire substrate (NPSS) on which nano-sized irregularities 1a were formed. A semiconductor growth substrate of Example 2 was obtained in the same manner as in Example 1 except that the a-plane GaN layer 3 was directly grown without using a buffer layer.

(Comparative Example 2)
Moreover, the a-plane GaN layer 3 was directly grown using a sapphire substrate having a flat r-plane as a main surface without forming irregularities. A semiconductor growth substrate of Comparative Example 2 was obtained in the same manner as Comparative Example 1 except that the a-plane GaN layer 3 was directly grown without using a buffer layer.

  6 is a schematic cross-sectional view showing the structures of Examples 1 and 2 and Comparative Examples 1 and 2. FIG. 6 (a) is Comparative Example 2, FIG. 6 (b) is Example 2, and FIG. FIG. 6 shows Comparative Example 1, and FIG. FIG. 7 shows the results of X-ray rocking curve measurement for Examples 1 and 2 and Comparative Examples 1 and 2, and FIG. 7 (a) is the result of measuring (11-20) diffraction from the c-axis direction. FIG. 7B shows the results of measuring (11-20) diffraction from the m-axis direction, and FIG. 7C shows the results of measuring (10-12) diffraction. In the graph of FIG. 7, the result of Example 1 is indicated by a solid line, the result of Example 2 is indicated by a large broken line, the result of Comparative Example 1 is indicated by a one-dot chain line, and the result of Comparative Example 2 is indicated by a small broken line. Yes. Table 1 shows the half width of each measurement result. The column of the sample structure in the table corresponds to the structure shown in FIG.

  As shown in Table 1, it can be seen that even in Example 2 in which no AlN buffer layer was provided, the a-plane GaN layer 3 having a smaller half width than that of Comparative Example 2 and having good crystallinity was formed. Moreover, in the result measured from the c-axis direction for (11-20) diffraction and the result measured for (10-12) diffraction, compared to Comparative Example 1 in which the AlN buffer layer 2 was formed without providing irregularities on the main surface, It can be seen that the NPSS of Example 2 in which the nano-sized unevenness 1a is formed without providing the AlN buffer layer has a smaller half-value width, and the crystallinity is the same in Example 2 and Comparative Example 1. Therefore, it can be seen that in the NPSS of the present invention, the crystallinity of the a-plane GaN layer 3 can be improved without providing the AlN buffer layer 2, and the crystallinity can be further improved by providing the AlN buffer layer 2.

  As described above, in the present invention, since the nano-sized irregularities 1a are formed on the main surface of the sapphire substrate 1 having the r-plane as the main surface, the crystallinity of the a-plane GaN layer 3 grown thereon is good. In addition, it suppresses abnormal growth and becomes high quality with excellent surface flatness.

(Second Embodiment)
Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 8 is a schematic cross-sectional view showing the LED 10 which is the semiconductor device of the present embodiment. As shown in FIG. 8, the LED 10 includes a sapphire substrate 11 having an r-plane as a main surface, nano-sized irregularities 11a, an AlN buffer layer 12, an a-plane GaN layer 13, an n-type semiconductor layer 14, a light-emitting layer 15, and a p-type semiconductor. It has a layer 16, an n-side electrode 17, and a p-side electrode 18.

  As in the first embodiment, a sapphire substrate 11 having an r-plane as a main surface is prepared, nano-sized irregularities 11a are formed, an AlN buffer layer 12 is formed on the sapphire substrate 11 by sputtering, and MOCVD is used. An a-plane GaN layer 13 is epitaxially grown on the AlN buffer layer 12. Subsequently, the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are sequentially grown by MOCVD to obtain a semiconductor substrate.

  Next, a part of the p-type semiconductor layer 16 and the light emitting layer 15 are removed by photolithography and etching using a predetermined mold pattern to expose a part of the n-type semiconductor layer 14. Next, an electrode material is formed on the exposed surfaces of the n-type semiconductor layer 14 and the p-type semiconductor layer 16 by vapor deposition or the like, and the LED 10 is obtained by dicing into individual chips.

  Here, the n-type semiconductor layer 14 and the p-type semiconductor layer 16 have been described as single layers. However, the n-type semiconductor layer 14 and the p-type semiconductor layer 16 may include a plurality of layers having different materials and compositions. The layer 16 may include a cladding layer, a contact layer, a current diffusion layer, an electron block layer, a waveguide layer, and the like. Moreover, although the light emitting layer 15 was demonstrated with the single layer, you may comprise by multiple layers, such as a multiple quantum well structure (MQW: Multi Quantum Well).

  The n-type semiconductor layer 14 is a semiconductor layer epitaxially grown on the a-plane GaN layer 13 and doped with an n-type impurity whose main surface is the a-plane. Electrons are injected from the n-side electrode 17 into the light emitting layer 15. It is a layer that supplies electrons. Examples of the material constituting the n-type semiconductor layer 14 include GaN, AlGaN, InGaN, AlInGaN and the like as the III-V group compound semiconductor layer, and Si and the like as the n-type impurity.

  The light emitting layer 15 is a semiconductor layer that is epitaxially grown on the n-type semiconductor layer 14 and has the a-plane as a main surface, and the LEDs 10 emit light by recombination of electrons and holes in the layer. The light emitting layer 15 is made of a material having a smaller band gap than the n-type semiconductor layer 14 and the p-type semiconductor layer 16, and examples thereof include InGaN and AlInGaN. The light emitting layer 15 may be intentionally non-doped without impurities, or may be n-type containing n-type impurities or p-type containing p-type impurities. Since the light-emitting layer 15 is a semiconductor layer having an a-plane as a main surface, even if the film is thickened, electrons and holes are not easily separated by a piezoelectric field, and even if the current density is increased, electrons and positive electrons are efficiently generated. The holes can recombine with light emission.

  The p-type semiconductor layer 16 is a semiconductor layer that is epitaxially grown on the light-emitting layer 15 and has the a-plane as a main surface, and is a layer that injects holes from the p-side electrode 18 and supplies holes to the light-emitting layer 15. . Examples of the material constituting the p-type semiconductor layer 16 include GaN, AlGaN, InGaN, and AlInGaN as the III-V compound semiconductor layer, and examples of the p-type impurity include Zn and Mg.

  Also in the present embodiment, the LED 10 forms the AlN buffer layer 12 by sputtering on the sapphire substrate 11 (NPSS) whose main surface is the r-plane on which the nano-sized irregularities 11a are formed, and the a-plane GaN layer 13 is disposed below. An n-type semiconductor layer 14, a light-emitting layer 15, and a p-type semiconductor layer 16 are epitaxially grown as the ground layer. Therefore, as described in the first embodiment, the a-plane GaN layer 13 has good crystallinity and surface flatness, and the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 grown thereon are also included. Crystallinity and surface flatness are improved. Thereby, the characteristics of the n-type semiconductor layer 14, the light emitting layer 15, and the p-type semiconductor layer 16 are also improved, and an improvement in the external quantum efficiency of the LED 10 is expected.

(Third embodiment)
As described above, the LED 10 which is a semiconductor device of the present invention has low droop due to a piezoelectric field, low anisotropy in the a plane, and good crystal quality. When used for a lamp such as a lamp, it is possible to reduce the number of chips and increase the output.

(Fourth embodiment)
In the second embodiment, the LED 10 has a structure including the sapphire substrate 11 and the AlN buffer layer 12 on which the r-plane is the main surface and the nano-sized irregularities 11a are formed. The sapphire substrate 11 and the AlN buffer layer 12 may be removed using a technique such as laser ablation. Further, the n-side electrode 17 may be provided on the side from which the r-plane sapphire substrate 11 is removed, and the p-side electrode 18 and the n-side electrode 17 may be opposed to each other.

  Further, the semiconductor device is not limited to the LED, and may be other applications such as a semiconductor laser or a high electron mobility transistor (HEMT).

  The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope shown in the claims, and embodiments obtained by appropriately combining technical means disclosed in different embodiments. Is also included in the technical scope of the present invention.

1,11 ... Sapphire substrate 10 ... LED
1a, 11a ... irregularities 2, 12 ... AlN buffer layers 3, 13 ... a-plane GaN layer 4 ... resist film 5 ... mold 14 ... n-type semiconductor layer 15 ... light emitting layer 16 ... p-type semiconductor layer 17 ... n-side electrode 18 ... p-side electrode

Claims (8)

  A substrate for semiconductor growth, wherein the r-plane of sapphire is a main surface, and nano-sized irregularities are formed on the main surface. A semiconductor growth substrate according to claim 1,
The substrate for semiconductor growth, wherein the unevenness has a maximum dimension in the in-plane direction of the main surface of less than 1 μm. A semiconductor growth substrate according to claim 1 or 2,
A semiconductor growth substrate comprising an a-plane GaN layer on the main surface. The semiconductor growth substrate according to claim 3,
A semiconductor growth substrate comprising an AlN buffer layer between the main surface and the a-plane GaN layer. A semiconductor growth substrate according to any one of claims 1 to 4,
A substrate for semiconductor growth, wherein a plurality of the irregularities are arranged in a triangular lattice pattern on the main surface. Using the semiconductor growth substrate according to any one of claims 1 to 5,
A semiconductor element comprising a functional layer on the semiconductor growth substrate. Using the semiconductor growth substrate according to any one of claims 1 to 5,
A semiconductor light emitting device comprising an active layer on the semiconductor growth substrate. forming nano-sized irregularities on sapphire having an r-plane as a main surface;
And a step of growing a nitride semiconductor layer on the main surface.