JP2019032727A - Input/output device for communication - Google Patents

Abstract

To inhibit a reduction in effective throughput related to DRAM access.SOLUTION: A recording device 30 comprises a second DRAM access unit 38, records queue control information on a queue with an individual row address of queue control memory 33 corresponding to the queue, in writing communication data in a queue to be written, selects, from banks in the queue control memory 33, a bank in which a row address to be written corresponding to the queue to be written is in an active state as a bank to be written and writes the queue control information, when the bank in which the row address to be written is in an active state is not present, selects a bank in which the row address to be written is in an inactive state as the bank to be written, and activates the row address to be written before writing the queue control information.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a data communication technique, and more particularly to a memory access control technique used in a communication input / output device that inputs and outputs communication data (frame data).

Conventionally, for example, a configuration as disclosed in Patent Document 1 has been proposed as a communication input / output device that is used in data communication such as the Internet to input / output communication data such as Ethernet (registered trademark) frame data. ing. FIG. 28 is a block diagram showing a configuration of a conventional communication input / output device (built-in memory).
This communication input / output device includes a multiplexing device MUX, a recording device MEM, and a demultiplexing device DEMUX.

The MUX adds the queue designation information corresponding to the output destination of the frame data to the input frame data by the queue designation information addition section provided for each input port, and then multiplexes it by the multiplexing section. Output.
The MEM receives the frame data output from the MUX by time division multiplexing by the write control unit, refers to the queue designation information and the queue map added to each frame data, and stores the frame data in the built-in data memory. Of the queues logically provided for each output destination, the frame data is written to the queue address corresponding to the queue designation information. Further, in response to a read instruction from the DEMUX, the MEM reads frame data from the corresponding queue by the read control unit and outputs the frame data to the DEMUX.

  The DEMUX reads out the frame data from the output destination queue corresponding to the priority output port in the MEM based on the priority control logic for each output port by the reading unit, and distributes the frame data to the corresponding output port by the distribution unit. The data is converted into the communication speed of the output port by a speed conversion unit provided for each output.

  FIG. 29 is an explanatory diagram showing the correspondence between queues and output ports, and shows the case where the number of output ports is three. In FIG. 29A, queues and output ports are associated one-to-one, but as illustrated in FIG. 29B, one frame data is associated with a plurality of output ports. Can be handled when In addition, as shown in FIG. 29C, a queue corresponding to the read priority can be associated with each output port.

JP 2011-0101095 A

  In such a communication input / output device, the storage capacity required by the MEM increases as the output system increases, so a DRAM is used as a data memory. However, since DRAM access has a waiting time due to the activation of the row address in each bank, in some cases, the effective throughput of the DRAM access is extremely reduced to follow the processing speed of frame data. There is a problem that communication quality is deteriorated because communication cannot be performed.

  In general, in a DRAM, when writing data to an arbitrary row address of an arbitrary bank, it is necessary to activate the row address in the bank. When accessing a different row address of the same bank, the row address is Since it is necessary to activate a new row address after waiting for the used access to be completed, a relatively large waiting time occurs due to the activation of the row address in accessing the same bank. Specifically, this is a case where accesses to different row addresses in the same bank are continuous. As other conditions for waiting time, there are a case where writing is performed in the same bank after reading and a case where reading is performed from the same bank after writing.

  Therefore, these waiting times cause a decrease in effective throughput related to DRAM access. Therefore, in particular, in communication I / O devices, short frame data may be input continuously in bursts. In such a case, when frequently accessing different row addresses in the same bank The effective throughput may be extremely reduced.

  An object of the present invention is to provide a memory access control technique capable of suppressing such a decrease in effective throughput related to DRAM access.

  In order to achieve such an object, the communication input / output device according to the present invention adds queue designation information indicating a queue corresponding to an output system to which the communication data is to be output to communication data that is sequentially input. And the communication data transferred from the multiplexing device are temporarily stored in a write target queue designated by the queue designation information among a plurality of queues logically formed in a data memory. Multiplex that reads out the communication data from the queue to be read corresponding to the output system selected from the queue and the output system selected based on the priority control logic from the queue, converts it to the communication speed of the output port corresponding to the output system, and outputs it A communication input / output device comprising a separation device, wherein the recording device comprises a DRAM having a plurality of row addresses for each bank, and the queue and A write target row address corresponding to the write target queue in the bank when the communication data is written to the write target queue and the data memory storing the communication data of the queue with a corresponding individual row address Is selected as a write target bank, the communication data is written, and if there is no bank in which the write target row address is active, the write target row address is inactive. A first DRAM access unit for writing the communication data after selecting a bank in the activated state as a write target bank and activating the write target row address, and a DRAM having a plurality of row addresses for each bank Storing queue control information used for controlling writing / reading to / from the queue of the data memory Write control that instructs the first DRAM access unit to write the communication data transferred from the multiplexing device to the write target queue based on queue control memory and queue control information in the queue control memory And reading the communication data from the read target queue to the first DRAM access unit based on the queue control information in the queue control memory and transferring the read communication data to the demultiplexer When the queue control information of the queue is recorded by the control unit and the individual row address of the queue control memory corresponding to the queue and the communication data is written to the write target queue, the queue control memory Select the bank whose write target row address corresponding to the write target queue is activated as the write target bank. If the bank whose write target row address is in an activated state does not exist, the bank whose write target row address is in an inactive state is selected as the write target bank. And a second DRAM access unit for writing the queue control information after the write target row address is activated.

  Further, in the above configuration example of the input / output device for communication according to the present invention, when the recording device writes the communication data of the queue to the bank for each combination of the queue and the bank of the data memory. A first bank management memory for storing a write pointer value used as a column address, wherein the write control unit combines the write target row address and the write target bank when writing the communication data; Is obtained from the first bank management memory, and the communication data is written to the column address consisting of the write pointer value in the write target row address of the write target bank. It is a thing.

  Also, in one configuration example of the communication input / output device according to the present invention, the recording device writes the queue control information of the queue to the bank for each combination of the queue and the bank of the queue control memory. A second bank management memory for storing a write pointer value used as a column address when the write control unit writes the queue control information, the write target row address and the write target bank Is obtained from the second bank management memory, and the queue control is performed on the column address composed of the write pointer value among the write target row addresses of the write target bank. Information is written.

  Also, in one configuration example of the communication input / output device according to the present invention, when the write control unit writes the queue control information, the write target row address used for writing the communication data, The queue control information is written using the write target bank and the write pointer value as the write target row address, write target bank, and write target column address of the queue control information.

  Also, in one configuration example of the communication input / output device according to the present invention, the queue control memory stores a communication data storage bank subsequent to the communication data written in a virtual storage address used on the virtual data memory. For each of the queues, a bank in which the first and last communication data of the queue is written is stored, and the write control unit writes the communication data into the write target queue. The queue last bank of the queue and the storage bank of the data subsequent to the last data before writing are updated, respectively, and when the read control unit reads the communication data from the read target queue, the queue head bank of the read target queue Instructing the first DRAM access unit to read out the communication data for the read pointer value of It is those you chose to update the head bank.

  Also, in one configuration example of the communication input / output device according to the present invention, the recording device uses, for each queue, the number of virtual storage addresses on the virtual data memory used by the queue. Queue use address number memory for storing the number of addresses, and when writing the communication data to the write target queue, based on the data length of the communication data, the required address number indicating the number of virtual storage addresses required for writing Calculate the remaining address number indicating the number of virtual storage addresses that can be used for the writing based on the used address number of the write target queue acquired from the queue used address number memory, and calculate the required address number and the By comparing with the number of remaining addresses, it is determined whether or not the communication data can be written. Further comprising an access arbitration unit for instructing the writing of the communication data.

  According to the present invention, in a recording device for temporarily storing communication data transferred from a multiplexing device in a write target queue designated by queue designation information among a plurality of queues logically formed in a data memory, Even when the data memory is composed of a DRAM, the number of activations of the row address can be reduced. For this reason, it is possible to suppress a decrease in effective throughput related to DRAM access for data memory.

1 is a block diagram illustrating a configuration of a communication input / output device according to a first embodiment. FIG. It is a block diagram which shows the structure of the queue control memory concerning 1st Embodiment. 3 is a block diagram showing a configuration of a first DRAM access unit (for DM) according to the first embodiment; FIG. FIG. 3 is a block diagram showing a configuration of a second DRAM access unit (for QM) according to the first embodiment. It is a flowchart which shows the write-in operation | movement of the write-control part concerning 1st Embodiment. 3 is a flowchart showing a read operation of a read control unit according to the first embodiment. It is explanatory drawing which shows the queue control information (the 1) just before reading data P2-1. It is explanatory drawing which shows the queue control information (the 2) just before data P2-1 reading. It is explanatory drawing which shows the queue control information (the 3) just before reading data P2-1. It is explanatory drawing which shows the change (the 1) of the queue control information at the time of data P2-1 reading. It is explanatory drawing which shows the change (the 2) of queue control information at the time of data P2-1 reading. It is explanatory drawing which shows the change (the 3) of queue control information at the time of data P2-1 reading. It is explanatory drawing which shows the change (the 1) of the queue control information at the time of data P2-2 reading. It is explanatory drawing which shows the change (the 2) of queue control information at the time of data P2-2 reading. It is explanatory drawing which shows the change (the 3) of queue control information at the time of data P2-2 reading. It is explanatory drawing which shows the change (the 1) of the queue control information at the time of data P2-4 writing. It is explanatory drawing which shows the change (the 2) of the queue control information at the time of data P2-4 writing. It is explanatory drawing which shows the change (the 3) of the queue control information at the time of data P2-4 writing. It is a flowchart which shows DRAM write processing. It is a flowchart which shows DRAM read-out processing. It is a block diagram which shows the structure of the access arbitration part concerning 2nd Embodiment. It is an example of a structure of the address number information for determination. It is a flowchart which shows the writability determination processing concerning 2nd Embodiment. It is a block diagram which shows the structure of QM concerning 3rd Embodiment. It is a block diagram which shows the structure of QSA, QLA, QCN, and a W / R pointer concerning 3rd Embodiment. It is a flowchart which shows the write-in operation | movement of the write-control part concerning 3rd Embodiment. It is a flowchart which shows the read-out operation | movement of the read-out control part concerning 3rd Embodiment. It is a block diagram which shows the structure of the conventional input / output device for communication (built-in memory). It is explanatory drawing which shows a response | compatibility with a queue and an output port.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a communication input / output device 1 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of the communication input / output device according to the first embodiment.

  The communication input / output device 1 is a communication input / output device for inputting / outputting communication data such as Ethernet (registered trademark) frame data, which is used in Internet communication or the like. The communication data input from the port is separated for each output system to which the communication data is to be output, converted to the communication speed of the output port corresponding to the output system, and output.

  As shown in FIG. 1, the communication input / output device 1 includes a multiplexer (MUX) 10, a demultiplexer (DEMUX) 20 with a built-in memory access control function, and a recording device (MEM) with a built-in access control function. 30. In the following, a case where communication data input / output by the communication input / output device 1 is frame data will be described as an example. However, the present invention is not limited to this, and various types of communication data such as packets and ATM cells are converted into frame data. It is also possible to input / output in the same manner as in FIG.

The multiplexing device 10 has a function of multiplexing the frame data sequentially input from the outside by adding queue designation information corresponding to the output system to which the frame data is to be output.
The recording device 30 writes the frame data transferred from the multiplexing device 10 into a write target designated by the queue designation information added to the frame data among a plurality of queues logically formed in the data memory. It has a function to temporarily store in a queue.
The demultiplexer 20 reads the frame data temporarily stored in the read target queue from the read target queue corresponding to the output system selected based on the priority control among the queues in the recording device 30, and corresponds to the output system. It has a function of converting and outputting the communication speed of the output port.

  In the present embodiment, in the recording apparatus 30, the data memory 31 is composed of a DRAM having a plurality of row addresses for each bank, and the frame data of the queue is stored at the row address corresponding to each queue. When the DRAM access unit 32 writes frame data to the write target queue, the bank in which the write target row address corresponding to the write target queue is activated is selected as the write target bank. When the frame data is written and there is no bank in which the write target row address is activated, the bank in which the write target row address is inactivated is selected as the write target bank and The frame data is written after the target row address is activated.

  In addition to this, a queue control memory made up of a DRAM having a plurality of row addresses for each bank, which stores queue control information used when the recording device 30 controls writing / reading to / from the queue of the data memory, and A write control unit that instructs the first DRAM access unit to write the frame data transferred from the multiplexing device to the write target queue based on queue control information in the queue control memory; A read control unit that instructs the first DRAM access unit to read frame data from the read target queue based on queue control information and transfers the read communication data to the demultiplexing device; is there.

  Further, the recording device 30 records the queue control information of the queue at the individual row address of the queue control memory corresponding to the queue, and writes the frame data to the write target queue. The bank in which the write target row address corresponding to the write target queue is activated is selected as the write target bank, the queue control information is written, and the write target row address is in the activated state. If the write target row address is not activated, the second DRAM to which the queue control information is written after the write target row address is activated by selecting the bank in which the write target row address is inactivated as the write target bank And an access unit.

  In this embodiment, as shown in FIG. 1, a case where two input ports Pin0 and Pin1 are provided as the input port Pin and two output ports Pout0 and Pout1 are provided as the output port Pout will be described as an example. However, the number of input ports Pin and output ports Pout is not limited to this. Three or more of either or both of the input port Pin and the output port Pout can be provided, and the number of input ports and the number of output ports may be different. Note that the number of input ports may be one.

[Multiplexer]
Next, with reference to FIG. 1, the multiplexing apparatus 10 used in the communication input / output apparatus 1 according to the present embodiment will be described in detail.
The multiplexing apparatus 10 includes a queue designation information adding unit 11 and a multiplexing unit 12 as main circuit units.

  The queue designation information adding unit 11 is provided for each of the input ports Pin0 and Pin1, and for frame data input from the corresponding input port Pin, queue designation information corresponding to the output destination of the frame data, and the frame It has a function of adding data frame length information (Byte) and outputting it to the multiplexing unit 12. At this time, for example, when outputting frame data to the multiplexing unit 12, the frame length information may be added by counting the number of bytes from the beginning to the end of the frame data as the frame length.

Multiplexing unit 12 is provided in common with each queue designation information adding unit 11, multiplexes the frame data output from each queue designation information adding unit 11 in a time division manner, and outputs it to recording apparatus 30. It has a function.
In the multiplexer 10, the designation of the queue corresponding to the output destination of the frame data may be realized by a bridge function such as IEEE802.1D. Specifically, the output port search by MAC address learning and the VLAN-ID are used. The output port can be specified (see Patent Document 1).

[Demultiplexer]
Next, the demultiplexer 20 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG.
The demultiplexer 20 is provided with a reading unit 21, a distribution unit 22, and speed conversion units 23 and 24 as main circuit units.

The reading unit 21 refers to the accumulation status of each queue acquired from the recording device 30 and the reading stop instruction signal output from the speed conversion units 23 and 24, and the frame data based on the priority control logic for each of the output ports Pout0 and Pout1. A function for selecting an output system to be output with priority, a function for outputting a read request for reading frame data from a read target queue corresponding to the output system, and a transfer from the recording apparatus 30 in response thereto The frame data is output to the distribution unit 22.
For priority control logic, for example, if the capacity of each queue is the same, general priority control such as reading from the queue with the largest amount of communication data stored in the queue among readable queues. Logic may be used (see Patent Document 1).

In addition, when the reading unit 21 outputs a read request to the recording device 30, the reading unit 21 instructs the recording device 30 with read data amount information indicating the data amount of the read data in addition to the queue designation information that specifies the queue to be read. To do.
For the read data amount information, for example, when the data accumulation amount of the queue to be read is equal to or less than a preset threshold value, a value equal to the data accumulation amount is output as the read data amount information. May be output as read data amount information.

The distribution unit 22 has a function of distributing the frame data output from the reading unit 21 to the speed conversion units 23 and 24 of the corresponding output port based on the queue designation information added to the frame data. Yes.
The speed converters 23 and 24 are provided for each output port, and according to the function of converting the frame data distributed from the distribution unit 22 into the communication speed of the output port and outputting the same, and the output status of the frame data A function of outputting a reading stop instruction signal to the reading unit 21.
The queue designation information added to the frame data is deleted by the distribution unit 22 or the speed conversion units 23 and 24.

[Recording device]
Next, the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG.

  As shown in FIG. 1, the recording device 30 includes, as main circuit units, a data memory (DM) 31, a first DRAM access unit (for DM) 32, a queue control memory 33, a write control unit 34, a read A control unit 35, a queue use address number memory 36, an access arbitration unit 37, and a second DRAM access unit (for QM) 38 are provided.

  The data memory (DM) 31 includes a general DRAM (DRAM chip) having a plurality of row addresses for each bank, and stores the frame data of the queue at the row address corresponding to the queue. It has a function. Specifically, the data memory 31 may be configured by one or a plurality of DRAM chips and correspond to each output system queue. In addition to the configuration in which each output system has one queue, It is also possible to have a plurality of queues in one output system. In this embodiment, the queue corresponds to the row address, and one DRAM chip is shared by a plurality of queues.

  The data memory 31 is provided with a plurality of storage areas having unique storage addresses. Each queue is configured by arbitrarily connecting virtual storage areas of a virtual data memory having a virtual storage address equivalent to the storage address of the data memory 31 regardless of whether the virtual storage addresses are continuous or discontinuous. The virtual storage address is address information corresponding to an actual column address used for accessing the DRAM.

In FIG. 7 to be described later, as a storage example of the virtual data memory, each virtual storage area having a unique virtual storage address ADM (0 to N: N is an integer of 2 or more) is written from the write control unit 34. The image in the case where stored data is stored is shown.
At this time, if one frame is longer than the data size for one virtual address, one frame is divided into a plurality of data D in accordance with the data size for one virtual address, and written to a plurality of different virtual storage addresses.

  For example, in the case of FIG. 7, the data P1-1, P1-2, and P1-3 of the queue P1 are stored in the virtual storage addresses 0, 1, and 2 of the bank 0 row address = P1, and the bank 1 row address is stored. Data P2-1, P2-2, and P2-3 of the queue P2 are stored in the virtual storage addresses 0, 1, and 2 of the address = P2. The order relation of these data and the correspondence relation with the frame are managed by an address queue management memory described later. When one frame is shorter than the data size of the virtual storage area, the frame data is stored in one virtual storage area.

  The first DRAM access unit 32 has a function of writing frame data to a write target row address corresponding to a write target queue in the data memory 31 in accordance with a DRAM write instruction from the write control unit 34, and a read It has a function of reading frame data from a write target row address corresponding to a read target queue in the data memory 31 in accordance with a DRAM read instruction from the control unit 35.

  The first DRAM access unit 32 has a function of writing frame data to a designated virtual storage address (column address) when the write target row address of the designated bank is in an activated state when writing frame data. When the write target row address is not activated, the write target row address is activated and then the frame data is written.

  Further, when reading the frame data, the first DRAM access unit 32 reads the frame data from the read target row address of the read target bank if the read target row address is activated in the designated read target bank. When the read target row address is not activated in the read target bank, there is a function of reading the frame data after activating the read target row address of the read target bank.

  The queue control memory 33 is composed of a semiconductor memory such as an SRAM chip, for example, and stores various queue control information used for controlling the writing / reading of frame data to / from each queue formed on the data memory 31. have.

  FIG. 2 is a block diagram illustrating a configuration of the queue control memory according to the first embodiment. The queue control memory 33 includes a plurality of storage units including registers and memories. The main storage units include an address queue management memory (QM) 33A, a queue head bank register (QSA) 33B, and a queue last bank memory (QLA). ) 33C, an access history register (AAR) 33D, a first bank management memory (for DM) 33E, and a second bank management memory (for QM) 33F. In the following description, register names are sometimes used as variable names for easy understanding.

The address queue management memory (QM) 33A is composed of a general DRAM having a plurality of row addresses for each bank, and stores a communication data storage bank following the communication data written to the virtual storage address. (QNA) is stored.
As shown in FIGS. 7 and 8 to be described later, the QNA is a bank in which communication data following the communication data written in the virtual storage address is stored. Further, as shown in FIG. 8 to be described later, the head data bank (DSA) and the number of consecutive virtual storage addresses (DNU) when frame data is written to continuous virtual storage addresses of the data memory are also recorded.

The queue head bank register (QSA) 33B and the queue last bank memory (QLA) 33C store, for each queue, the bank (QSA) in which the queue top frame data is written and the bank (QLA) in which the queue last frame data is written. It has a function to do.
In the example of FIG. 7, QSA and QLA are stored for each queue ID (queue number) for identifying a queue.

  The access history register (AAR) 33D records the address (including bank information and row address) at which the last write instruction or read instruction is recorded as AAR_1, and AAR_n is stored in AAR_ (n−1) when AAR_1 is updated. Update to a value (n is an integer greater than or equal to 2). That is, the history of the latest n write instructions or read instructions is displayed.

  The first bank management memory (for DM) 33E is composed of a semiconductor memory such as an SRAM chip, for example, and communication data of the queue is combined for each combination of a queue ID (queue number) for identifying the queue and a bank of DM. For each combination of a function for storing a write pointer value used as a column address when writing the data to the bank and a queue ID (queue number) for identifying the queue and a bank of DM, the communication data of the queue is It has a function of storing a read pointer value used as a column address when reading from the bank.

  The second bank management memory (for QM) 33F is made of a semiconductor memory such as an SRAM chip, for example. For each combination of a queue ID (queue number) for identifying a queue and a bank of QMs, the second bank management memory (for QM) 33F For each combination of a function for storing a write pointer value used as a column address when writing queue control information to the bank, and a queue ID (queue number) for identifying the queue and a bank of QM, the queue of the queue It has a function of storing a read pointer value used as a column address when reading control information from the bank.

  In the example of FIG. 9 described later, for each combination of a queue ID (queue number) for identifying a queue and a bank number for identifying a bank, a write pointer value (write pointer or BL) and a read pointer value (Read pointer or BS) is stored. Note that the initial value of the write pointer value and the read pointer value are assumed to be the same value.

  For example, in the queue P2, in the bank # 1 of the data memory (DM), the write pointer value is 3, and when the bank # 1 of the DM is the write target bank, the queue P2 is set to the column address indicated by the write pointer. The new frame data is written. In the queue P2, in the DM bank # 1, the read pointer value is 0. When the DM bank # 1 is the read target bank, the frame data in the queue P2 is read from the column address indicated by the read pointer. become.

  Also, in the queue P2, when the write pointer (BL_1) is 2 in the bank # 1 of the QM and the bank # 1 of the QM is the write target bank, the queue control information of the queue P2 is stored in the column address indicated by the BL_1. Will be written. In the queue P2, when the read pointer value (BS_1) is 0 in the bank # 1 of the QM and the bank # 1 of the QM is the read target bank, the queue control information of the queue P2 is obtained from the column address indicated by the BS_1. Will be read.

  The write control unit 34 selects an optimal bank based on the access history register (AAR) 33D in response to a write instruction from the access arbitration unit 37, and a virtual storage address (bank, row address, and write pointer). Is designated, and a DRAM write instruction for instructing writing of frame data is output to the first DRAM access unit 32.

The bank is selected as follows, for example.
The write controller 34 uses AAR to manage which row address is activated in each bank.
Among the banks, the bank in which the row address corresponding to the queue to be written is activated is selected. However, if the write pointer of the corresponding bank is updated, the value will be the same as the read pointer (or if the read pointer is 0 and the write pointer is updated and the upper limit of the column address is exceeded, or the read pointer is If the non-zero write pointer value before update is smaller than the read pointer value and the updated write pointer value is larger than the read pointer value), the bank is not selected.

  For example, first, if the row address of AAR_1 is the same value as the row address corresponding to the queue to be written, that row address is activated, so that bank is selected. If they are different, if the row address of AAR_2 is the same value as the row address corresponding to the queue to be written, that row address is activated, so that bank is selected. However, when the bank number of AAR_2 is the same as the bank number of AAR_1, the row address is not activated, so that bank is not selected.

  If not selected in the comparison up to AAR_2, if the row address of AAR_3 is the same value as the row address corresponding to the queue to be written, the row address is activated, so that bank is selected. However, when the bank number of AAR_3 is the same as the bank number of AAR_1 or AAR_2, the row address is not activated, so that bank is not selected.

Similarly, comparison is made up to AAR_n, and if the row address has the same value as the row address corresponding to the queue to be written and can be selected, that bank is selected. When comparing with AAR_n, if the bank number of AAR_n is the same as any one of AAR_1 to AAR_ (n-1), the row address is not activated, so that bank is not selected.
If no corresponding row address is activated (and can be selected), for example, a bank that is not recorded in any AAR is selected, or a bank that is recorded in the AAR remains. Select the bank with the oldest history.

  Further, the write control unit 34 selects the optimum QM bank according to the write instruction from the access arbitration unit 37, the QCN and QLA of the queue to be written, and the DM bank selection result, and the virtual DRAM that instructs QM to read QM with storage address (bank, row address, and BL) and write DSA, DNU, QNA with virtual storage address (bank, row address, and BL) It has a function of outputting a read instruction and a DRAM write instruction to the second DRAM access unit (for QM).

In the selection of the QM bank, similar to the DM bank selection, the bank in which the row address corresponding to the queue to be written is activated is selected from the banks of the QM.
However, when the BL of the corresponding bank is updated, it becomes the same value as the BS (or when the BS is updated with BL being 0 and the upper limit of the column address is exceeded, or when the BS is not 0 and before the update) If the BL is smaller than BS and the updated BL is larger than BS), the bank is not selected.
When the QCN of the queue to be written is other than 0, it may be unnecessary to select a bank for QM. A specific example of QM bank selection will be described later.

  In response to a read instruction from the access arbitration unit 37, the read control unit 35 designates a read target queue (row address) and a virtual storage address (bank and read pointer) based on the queue control information in the queue control memory 33. A function of outputting a DRAM read instruction for instructing reading of head data from the read target queue to the first DRAM access unit 32 and a function of transferring the data to the demultiplexing device 20 together with the frame end flag and the queue designation information And have.

  Further, the read control unit 35, in response to a read instruction from the access arbitration unit 37, based on the queue control information in the queue control memory 33, DSA, DNU, which designates a virtual storage address (bank, row address, BS), Read the QNA and write the DSA, DNU, and QNA specifying the virtual storage address (bank, row address, BS) to the QM. The DRAM read instruction and the DRAM write instruction are sent to the second DRAM access unit (QM The function to output to

The queue use address number memory (QCN) 36 is composed of a semiconductor memory such as an SRAM chip, for example, and stores a virtual address number QCN used by frame data stored in the queue for each queue, and a multiplexing function. It has a function of outputting the number of virtual addresses QCN of the designated queue in response to requests from the separation device 20 and the access arbitration unit 37.
In the example of FIG. 7, the number of virtual addresses QCN of the queue is stored for each queue ID (queue number) QID (P1 to PM: M is an integer of 2 or more) for identifying the queue.

  The access arbitration unit 37 receives the frame data transferred from the multiplexing device 10 and divides the frame data into a plurality of data D with a data size of one virtual address based on the frame length information added to the frame data. The function of calculating the number of times of writing by this, and writing to the write target queue designated by the queue designation information added to the frame data for each data D by the number of times of writing is instructed. A function of outputting a write instruction to the write control unit 34, and a function of adding the number of virtual addresses increased by writing the frame data to the number of virtual addresses QCN of the write target queue in the queue use address number memory 36. Have.

  Further, in response to a read request from the demultiplexer 20, the access arbitration unit 37 divides the data amount specified by the read data amount information of the read request by the data size for one virtual address, thereby reducing the number of reads. A function for calculating, a function for outputting to the read control unit 35 a read instruction for instructing reading of frame data from the read target queue designated by the queue designation information of the read request, and the frame data Read out at a readable timing by arbitrating the conflict between the function of subtracting the number of virtual addresses decreased by reading from the virtual address number QCN of the write target queue in the queue use address number memory 36 and the writing of frame data. And a function of outputting instructions.

[First DRAM access unit (for DM)]
Next, the first DRAM access unit (for DM) 32 used in the recording apparatus 30 according to the present embodiment will be described with reference to FIG. FIG. 3 is a block diagram showing a configuration of the first DRAM access unit (for DM) according to the first embodiment.
The first DRAM access unit 32 includes a FIFO memory 32A, an activation processing unit 32B, an access type determination unit 32C, a DRAM writing unit 32D, and a DRAM reading unit 32E as main circuit units.

  The FIFO memory 32A is composed of a general FIFO memory. The FIFO memory 32A has a function of accumulating a DRAM write instruction from the write control unit 34 and a DRAM read instruction from the read control unit 35, and a row by the activation processing unit 32B. After the address activation is completed, it has a function of reading the stored DRAM write instruction or DRAM read instruction in the order of input and outputting it to the access type determination unit 32C. At this time, as information for determining the access type, information indicating whether it is a DRAM write instruction from the write control unit 34 or a DRAM read instruction from the read control unit 35 is combined with each instruction. The information may be written in the FIFO memory 32A and output to the access type determination unit 32C.

  When the access arbitration unit 37 shown in FIG. 21 is used, the DRAM write instruction from the write control unit 34 and the DRAM read instruction from the read control unit 35 should not be input at the same time. Are simultaneously input, the writing of the DRAM writing instruction to the FIFO memory 32A may be prioritized and the writing of the DRAM reading instruction to the FIFO memory 32A may be made to wait.

  The activation processing unit 32B activates the write target row address of the DM when the write target row address of the DM is not activated when the DRAM write instruction is accumulated in the FIFO memory 32A. It has a function.

  Further, the activation processing unit 32B, when the DRAM read instruction is stored in the FIFO memory 32A, when the read target row address specified by the DRAM read instruction in the read target bank of DM is not in the activated state, When a function for activating a read target row address in the read target bank of the DM and a row address different from the read target row address in the read target bank of the DM are in an activated state, It has a function of activating the read target row address of DM in response to the completion of access.

  The access type determination unit 32C distributes the DRAM write instruction output from the FIFO memory 32A to the DRAM write unit 32D and outputs the DRAM read instruction output from the FIFO memory 32A to the DRAM read unit 32E. It has a function to output.

  Based on the combination of the write target row address, the write target bank, and the write pointer in the input DRAM write instruction, the DRAM writing unit 32D is designated by the DRAM write instruction to the designated DM column address. Has the function of writing the frame data (data D).

At this time, if a plurality of column addresses are required for writing frame data (data D) for one storage address, the burst mode, which is a function of the DRAM, is used to write to consecutive column addresses. The writing time can be shortened.
In addition, when the EoF value (information indicating whether or not the data to be written at the storage address includes the final data of the frame data: the frame end flag) is also written to the data memory 31, it is performed simultaneously with the writing of the frame data. Just do it.

  Based on the combination of the read target row address, the read target bank, and the read pointer in the input DRAM read instruction, the DRAM read unit 32E starts the frame from the DM column address indicated in the read target row address of the read target bank. It has a function of reading data (data D) and outputting it to the read control unit 35 together with queue designation information.

At this time, when a plurality of column addresses are required for reading frame data (data D) for one virtual storage address, reading is performed from successive column addresses using the burst mode which is a function of the DRAM. The time required for reading can be shortened.
When the EoF value (frame end flag) is written in the data memory 31, the EoF value may be read simultaneously with the reading of the frame data.
The read EoF value may be output to the read control unit 35 together with the frame data and the queue designation information.

[Second DRAM access unit (for QM)]
Next, the second DRAM access unit (for QM) 38 used in the recording apparatus 30 according to the present embodiment will be described with reference to FIG. FIG. 4 is a block diagram showing a configuration of the second DRAM access unit (for QM) according to the first embodiment.

  As with the first DRAM access unit (for DM) 32, the second DRAM access unit 38 has a FIFO memory 38A, an activation processing unit 38B, an access type determination unit 38C, and a DRAM write as main circuit units. A unit 38D and a DRAM reading unit 38E are provided.

  The FIFO memory 38A is a general FIFO memory, and stores a DRAM read instruction and a DRAM write instruction from the write control unit 34, and a DRAM read instruction and a DRAM write instruction from the read control unit 35 in a mixed manner. And a function of reading the accumulated DRAM write instruction or DRAM read instruction in the order of input after the activation of the row address by the activation processing unit 38B and outputting it to the access type determination unit 38C.

  At this time, as information for determining the access type, information indicating whether it is a DRAM write instruction or a DRAM read instruction is written in the FIFO memory 38A together with the respective instructions, and the information is also determined as the access type determination. You may make it output to the part 38C. Also, information indicating whether the instruction is from the write control unit 34 or the instruction from the read control unit 35 is written in the FIFO memory 38A together with each instruction, and the information is also output to the access type determination unit 38C. You may make it do.

  When the access arbitration unit 37 shown in FIG. 21 described later is used, an instruction from the write control unit 34 and an instruction from the read control unit 35 should not be input at the same time. In such a case, the instruction from the write control unit 34 to the FIFO memory 38A may be prioritized and the instruction write from the read control unit 35 to the FIFO memory 38A may be waited. However, it is prohibited to interrupt the instruction from the write control unit 34 between the DRAM read instruction from the read control unit 35 and the DRAM write instruction to the same address from the read control unit 35 immediately after that.

  The activation processing unit 38B activates the write target row address of the QM when the DRAM write instruction is accumulated in the FIFO memory 38A and the write target row address of the QM is not activated. It has a function.

  Further, the activation processing unit 38B, when the DRAM read instruction is stored in the FIFO memory 38A, when the read target row address specified by the DRAM read instruction is not in the active state in the read target bank of the QM, When a function for activating a read target row address in the read target bank of QM and a row address different from the read target row address in the read target bank of QM are in an activated state, It has a function of activating the QM read target row address in response to the access completion.

  Similarly to the DM access type determination unit 32C, the access type determination unit 38C distributes the DRAM write instruction output from the FIFO memory 38A to the DRAM write unit 38D and outputs the DRAM write instruction from the FIFO memory 38A. The DRAM read instruction is distributed to the DRAM read unit 38E and output.

Based on the combination of the write target row address and the write target bank in the input DRAM write instruction, the DRAM writing unit 38D uses the data (in the designated QM column address specified by the DRAM write instruction) ( (DSA, DNU, QNA).
At this time, if a plurality of column addresses are required for writing data (DSA, DNU, QNA), the burst mode, which is a function of the DRAM, may be used to write to successive column addresses. Write time can be shortened.

Based on the combination of the read target row address and the read target bank in the input DRAM read instruction, the DRAM read unit 38E receives data (DSA, DNU, QNA) are read out and output to the write control unit 34 or the read control unit 35.
At this time, if a plurality of column addresses are required for reading data (DSA, DNU, QNA) at one time, reading is performed from successive column addresses using the burst mode which is a function of the DRAM. In addition, the time required for reading can be shortened.

[Operation of First Embodiment]
Next, the operation of the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described with reference to FIGS.
FIG. 5 is a flowchart illustrating a write operation of the write control unit according to the first embodiment. FIG. 6 is a flowchart showing a read operation of the read control unit according to the first embodiment.

[Write operation]
First, the writing operation in the writing control unit 34 of the recording device 30 will be described with reference to FIG.
The write control unit 34 performs the write operation of FIG. 5 in response to a write instruction from the access arbitration unit 37.

  When new data is written to the write target queue, the main changes in the queue control information are the queue last bank (QLA) related to the write target queue and the last before writing of the write target queue before and after writing. A data storage bank (QNA), a write target bank (DSA), a DNU, DM and QM write pointers, and an access history register (AAR) 33D change after the data. However, when writing to the same bank as the last data before writing in the write target queue, the write pointers (BL) of DSA, QNA, and QM are not updated, and the DNU changes. Note that in the case of the first writing to the write target queue, the queue head bank (QSA) related to the write target queue also changes.

  For this reason, in the write operation of FIG. 5, the write control unit 34 writes the specified data to the selected bank, row address, and write pointer (output of the write instruction), and the queue last bank (QLA for the write target queue). ), Update of storage bank (QNA) of data subsequent to final data before writing in write target queue, update of write target bank (DSA) and DNU, update of write pointers of DM and QM Do. However, when writing to the same bank as the last data before writing in the write target queue, the DNU is updated without updating the write pointers (BL) of DSA, QNA, and QM.

In the case of the first writing to the write target queue, the queue head bank (QSA) related to the write target queue is also updated. Details of these updates will be described later based on an operation example.
At this time, the write control unit 34 executes the steps shown in FIG. 5 by accessing the queue control memory 33. Note that the processing order in FIG. 5 takes into account processing efficiency, but other processing orders may be used.

The write operation shown in FIG. 5 will be specifically described.
First, the write control unit 34 checks whether or not the QCN of the write target queue is 0 (step 120). If the QCN is 0 (step 120: YES), the bank of DM and QM is selected ( Step 121), the bank number of the selected QM bank is written to QSA and QLA (step 122), and the write pointer of the selected bank is read (step 123).

Next, the write control unit 34 writes data to the DM using the DM write pointer as the column address (step 124), and writes the DSA and DNU of the QM using BL as the column address (step 125). At this time, DSA indicates a DM write destination bank, and DNU is 1.
Thereafter, the write control unit 34 updates the write pointer of the selected bank (step 126), adds 1 to the QCN of the write target queue (step 127), and ends the series of write operations.

In step 120, if the QCN is not 0 (step 120: NO), the write control unit 34 reads the QLA in the write target queue (step 130) and sets the BL of the bank recorded in the QLA. Reading (step 131), it is confirmed whether or not writing to the same bank of DM (step 132).
Here, in the case of writing to the same bank (step 132: YES), the write control unit 34 reads DSA and DNU from QM using BL as a column address (step 133), and sets the write pointer of the DSA bank. Read (step 134).

Next, the write control unit 34 writes data to the DM using the DM write pointer as the column address (step 135), and writes the DSA and DNU of the QM using BL as the column address (step 136). At this time, the DSA writes the read value as it is, and the DNU writes a value obtained by adding 1 to the read value.
Thereafter, the write control unit 34 updates the DM write pointer of the selected bank (step 137), adds 1 to the QCN of the write target queue (step 127), and then ends a series of write operations. .

  If it is not writing to the same bank in step 132 (step 132: NO), the write control unit 34 selects DM and QM banks (step 140), and the QM bank selected in QLA is selected. The bank number is written (step 141), the bank number of the selected QM is written to the QNA QNA with the BL of the bank before selection as the column address (step 142), and the write pointer of the selected bank is read (step 142). 143).

Next, the write controller 34 writes data to the DM using the DM write pointer of the selected bank as the column address (step 144), and writes the DSA and DNU of the QM using the BL of the selected bank as the column address. (Step 145). At this time, DSA indicates a DM write destination bank, and DNU is 1.
Thereafter, the write control unit 34 updates the BL and DM write pointers of the selected bank (step 146), adds 1 to the QCN of the write target queue (step 127), and then performs a series of write operations. Exit.

[Read operation]
Next, with reference to FIG. 6, the reading operation in the reading control unit 35 of the recording apparatus 30 will be described.
The read control unit 35 executes the read operation of FIG. 6 in response to a read instruction from the access arbitration unit 37.

  When new data is read from the read target queue, main changes in the queue control information include the queue head bank (QSA) related to the read target queue, the read pointers of DM and QM, and the access history register (before and after the read). AAR) 33D changes. However, if the DNU in the QM is 2 or more, the QSA and QM read pointers (BS) are not updated, and the DNU changes. When the QCN of the read target queue is 1 (in this case, DNU is always 1), the QSA is not updated, and the DM and QM read pointers and AAR change.

  Therefore, in the read operation of FIG. 6, the read control unit 35 updates the queue head bank (QSA) related to the read target queue, updates the DM and QM read pointers, and outputs a read instruction. However, if the DNU in the QM is 2 or more, the DNU is updated without updating the QSA and QM read pointers (BS). Further, when the QCN of the read target queue is 1 (in this case, DNU is always 1), the QSA is not updated, and the DM and QM read pointers and the AAR are updated. Details of these updates will be described later based on an operation example. At this time, the read control unit 35 accesses the queue control memory 33 to execute the steps shown in FIG. Note that the processing order in FIG. 6 takes into account processing efficiency, but other processing orders may be used.

The read operation shown in FIG. 6 will be specifically described.
First, the read control unit 35 reads the QSA of the read target queue (step 150), and reads the BS of the bank recorded in the QSA (step 151).
Next, the read control unit 35 reads DSA, DNU, and QNA from the QM using the read BS as a column address (step 152), and reads the DSA read pointer (step 153).
Thereafter, the read control unit 35 reads data from the DM using the DM read pointer as a column address (step 154), updates the DSA read pointer (step 155), and then checks whether DNU is 1 or not. (Step 156).

Here, when DNU is 1 (step 156: YES), the read control unit 35 updates the BS (step 157), writes the QNA value to the QSA (step 158), and then starts from the QCN of the write target queue. 1 is subtracted (step 159), and a series of reading operations are completed.
If DNU is not 1 (step 156: NO), the read control unit 35 writes DSA, DNU, and QNA using BS as the column address (step 160). At this time, DSA and QNA write the read value as it is, and DNU writes a value obtained by subtracting 1. Thereafter, the process proceeds to step 159, where 1 is subtracted from the QCN of the write target queue (step 159), and the series of read operations is terminated.

[Operation example]
Next, referring to FIG. 7 to FIG. 18, in the frame data writing operation and reading operation in recording device 30, queue P2 is set as a read / write target queue, and data P2-3 is written to this queue P2. An example will be described in which the data P2-1 and P2-2 are read and then the data P2-4 is written.

FIG. 7 is an explanatory diagram showing queue control information (part 1) immediately before reading data P2-1. FIG. 8 is an explanatory diagram showing the queue control information (part 2) immediately before the data P2-1 is read. 7, 8, and 9 are explanatory diagrams showing the queue control information (part 3) immediately before the data P2-1 is read.
Here, queue control information immediately before reading data P2-1, that is, immediately after writing data P2-3 is shown.

  In this state, the data P1-1, P1-2, and P1-3 of the queue P1 are written to the virtual storage addresses “0, 1, 2” of the row address P1 of the bank 0 in the data memory (DM) 31. The data P2-1, P2-2, and P2-3 of the queue P2 are written in the virtual storage addresses “0, 1, 2” of the row address P2 of the bank 1. Further, the bank, row address, and virtual storage address of DM other than the above are not used.

FIG. 7 shows an example of writing in the order of P1-1, P1-2, P2-1, P2-2, P1-3, and P2-3, but the DM bank was selected as follows. It is an example.
When P1-1 is written, it is the first write of the corresponding queue (P1), and there is no activated row address, so bank 0 is selected as the initial value (row address P1 of bank 0 is registered in AAR_1) .

When P1-2 is written, the row address corresponding to the corresponding queue (P1) is the same as that of AAR_1, so 0 that is the bank of AAR_1 is selected (the value of AAR_1 is registered in AAR_2, Register row address P1).
At the time of P2-1 writing, since it is the first writing of the corresponding queue (P2) and the activated row address is only the same row address (P1 of bank 0), select 1 which is a bank other than AAR_1 (After registering the values of AAR_2 and AAR_1 in AAR_3 and AAR_2, respectively, the row address P2 of bank 1 is registered in AAR_1).

  At the time of P2-2 writing, since the row address corresponding to the corresponding queue (P2) is the same as AAR_1, 1 is selected as the bank of AAR_1 (the values of AAR_3, AAR_2, and AAR_1 are set to AAR_4, AAR_3, and After registering in AAR_2, the row address P2 of bank 1 is registered again in AAR_1). At this time, the banks of AAR_4, AAR_3, AAR_2, and AAR_1 are “0”, “0”, “1”, and “1”, respectively.

When P1-3 is written, the row address corresponding to the corresponding queue (P1) is the same as AAR_3, so AAR_3 bank 0 is selected (the values of AAR_4, AAR_3, AAR_2, and AAR_1 are set to AAR_5, AAR_4, AAR_3, respectively) And, after registering in AAR_2, register the row address P1 of bank 0 in AAR_1). At this time, the banks of AAR_5, AAR_4, AAR_3, AAR_2, and AAR_1 are “0”, “0”, “1”, “1”, and “0”, respectively.
At the time of writing P2-3, the row address corresponding to the corresponding queue (P2) is the same as AAR_2, so 1 which is the bank of AAR_2 is selected.

FIG. 7, FIG. 8, and FIG. 9 are examples of selecting a QM bank as follows.
When P1-1 is written, it is the first write of the corresponding queue (P1) and there is no activated row address, so bank 0 is selected as the initial value.
At the time of P1-2 writing, since DM is written to the same bank, there is no bank selection (using bank 0 which is a QLA bank).
At the time of P2-1 writing, since it is the first writing of the corresponding queue (P2) and the activated row address is only P1 of bank 0, 1 which is a bank other than bank 0 is selected.

At the time of P2-2 writing, since DM is written to the same bank, there is no bank selection (using bank 1 which is a QLA bank).
When writing P1-3, the bank 0 is selected because the row address P1 of the bank 0 is activated.
At the time of writing P2-3, the bank 1 is selected because the row address P2 of the bank 1 is activated.

  Note that when writing to P1-3 and P2-3, as with writing to P1-2 and P2-2, QM is updated only for DNU (operation when writing to the same bank of DM in FIG. 5). However, here, assuming that P1-2 and P1-3 are data of different frames (and P2-2 and P2-3 are data of different frames), the DSA of QM, DNU and QNA are updated (the same operation as that in the case of not writing to the same bank of DM in FIG. 5).

  As a result, the first DSA, DNU, and QNA of the bank 0 of the QM in the queue P1 are 0, 2, and 0, respectively, and the second DSA and DNU are 0 and 1 respectively (see FIG. 8). In addition, the first DSA, DNU, and QNA of the bank 1 of the QM in the queue P2 are 1, 2, 1, respectively, and the second DSA, DNU are 1, 1, respectively (see FIG. 8). Also, the DM W / R pointer (assuming that the initial value is 0) in the first bank management memory 33E and the QM W / R pointer (the initial value is 0) in the second bank management memory 33F. 9 is assumed).

  The queue head bank (QSA) of the queue P1 indicates 0 which is the bank of the QM used for writing the data P1-1, and the queue last bank (QLA) is the QM used for writing the data P1-3. A bank 0 is shown. The queue head bank (QSA) of the queue P2 indicates 1 which is the bank of the QM used for writing the data P2-1, and the queue last bank (QLA) is the QM used for writing the data P2-3. A bank 1 is shown (see “QSA” and “QLA” in FIG. 7).

  When the data P2-1 of the queue P2 is read in the states shown in FIGS. 7, 8, and 9, the queue control information changes as shown in FIGS. 10, 11, and 12. FIG. 10 is an explanatory diagram showing a change (part 1) in queue control information at the time of reading data P2-1. FIG. 11 is an explanatory diagram showing the change (part 2) in the queue control information when reading data P2-1. FIG. 12 is an explanatory diagram showing a change (part 3) in the queue control information when reading data P2-1.

  First, as shown in FIGS. 10, 11, and 12, the DSA is read from the BS value of the bank 1 of the QM indicated by the queue head bank (QSA) relating to the queue P2, and the read pointer of the bank 0 of the DM indicated by the DSA Since the data P2-1 is read from the value, the data D of the read target virtual address “0” of the row address P2 of the DM bank 1 is in an empty state, and the data relating to the queue P2 is two of P2-2 and P2-3. (See “DM”, “QSA”, “QLA”, “QCN”, and “Read Pointer / Write Pointer” for DM in FIGS. 10, 11, and 12).

  As a result, as shown in FIGS. 10, 11, and 12 (“QSA”, “DSA”, and DM “read pointer”), P2-2 becomes the head data of the queue P2, and the queue head of the DM Although the position changes from the virtual storage address “0” to “1”, since the DNU read from the QM at the same time as the DSA is 2, the update of the QM is only the DNU (1 is subtracted).

  Since the data D of the read target virtual address “0” in the row address P2 of the DM bank 1 is in an empty state, the DM read pointer is updated (added 1) as shown in FIG. In this case, the QM BS is not updated.

Thus, immediately after the data P2-1 is read (immediately before the data P2-2 is read), the queue control information is in the state shown in FIG. 10, FIG. 11, and FIG.
When the data P2-2 of the queue P2 is read in the states shown in FIGS. 10, 11, and 12, the queue control information changes as shown in FIGS. 13, 14, and 15. FIG. 13 is an explanatory diagram showing a change (part 1) in the queue control information when reading data P2-2. FIG. 14 is an explanatory diagram showing the change (part 2) in the queue control information when reading data P2-2. FIG. 15 is an explanatory diagram showing a change (No. 3) in the queue control information at the time of reading data P2-2.

  First, as shown in FIGS. 13, 14, and 15, the DSA is read from the BS value of the bank 1 of the QM indicated by the queue head bank (QSA) relating to the queue P2, and the read pointer of the bank 0 of the DM indicated by the DSA is read. Since the data P2-2 is read from the value, the data D of the read target virtual address “1” of the row address P2 of the DM bank 1 becomes empty, and the data related to the queue P2 is one of P2-3 (FIG. 12). “DM”, “QSA”, “QLA”, “QCN”, and “Read Pointer / Write Pointer” for DM).

  Accordingly, as shown in FIGS. 13, 14, and 15 (“QSA”, “DSA”, and “read pointer” for DM), P2-3 becomes the head data of the queue P2, and the queue head position is Since the DNU read from the QM at the same time as the DSA changes from the virtual storage address “1” of the row address P2 of the bank 1 of the DM to 1 and the QM BS is updated, the queue head bank for the queue P2 is updated. (QSA) is updated from “1” to “bank indicated by QNA read simultaneously with DSA (1 in this example)”, and the BS of row address P2 in bank 1 of QM is updated (add 1).

  Further, since the data D of the read target virtual address “1” of the row address P2 of the bank 1 of the DM is in an empty state, the DM read pointer is updated (added 1) as shown in FIG.

Thus, immediately after the data P2-2 is read (immediately before the data P2-4 is written), the queue control information is in the state shown in FIG. 13, FIG. 14, and FIG.
In the state shown in FIGS. 13, 14, and 15, when the data P2-4 of the queue P2 is written, the queue control information changes as shown in FIGS. 16, 17, and 18. FIG. 16 is an explanatory diagram showing a change (No. 1) in queue control information when data P2-4 is written. FIG. 17 is an explanatory diagram showing a change (part 2) in the queue control information at the time of writing data P2-4. FIG. 18 is an explanatory diagram showing a change (No. 3) in the queue control information when the data P2-4 is written.

  First, a DM bank is selected. The row addresses recorded in the AAR are P2 in the bank 1 for AAR_1 to AAR_3 and P1 in the bank 0 for AAR_4. In this case, only the row address P1 in the bank 0 and the P2 in the bank 1 are activated. And the row address of the write target queue matches the row address of AAR_1. Therefore, writing may be performed by selecting 1 which is the bank of AAR_1, but another unused bank (bank 2) is selected here in consideration of the fact that the previous access is reading.

In this case, the reason why the bank 1 is not selected is that due to the specification of the DRAM, a waiting time occurs when writing to the same bank after reading, and the effective throughput is reduced.
Regarding the QM bank selection, since the row address P2 of the QM bank 1 is activated, the bank 1 is selected. In this case, since different banks are selected for DM and QM, QLA stores not the DM bank but the selected QM bank.

  As shown in FIGS. 16, 17, and 18, the data P <b> 2-4 is written to the write target virtual address “0” indicated by the write pointer of the row address P <b> 2 of the DM bank 2. , And FIG. 18 (“DM”, “QLA”, “DSA”, “BL”, and “write pointer” for DM)), P2-4 becomes the new final data of the queue P2, and the queue end Since the position changes from the virtual storage address “2” of the row address P2 of the bank 1 of the DM to the virtual storage address “0” of the row address P2 of the bank 2 of the DM, the queue last bank (QLA) of the queue P1 is “1”. To the QM bank used for writing P2-4 (in this case, “1”), and the write pointer of row address P2 in DM bank 2 is updated (added 1). ) By the.

Also, since P2-4 follows P2-3 which was the last queue data before writing, as shown in FIGS. 17 and 18, bank 1 of the QM used for writing P2-3 As the succeeding bank (QNA) of the address “1” of the row address P2 of the QM, “1” which is the bank of the QM used for the writing of P2-4 is set, and the third DSA of the row address P2 of the bank 1 of the QM Each DNU is set to 2 (the DM bank storing P2-4) and 1, and the BL of the row address P2 of the bank 1 of the QM is updated (added 1).
Thus, immediately after the data P2-4 is written, the queue control information is in the state shown in FIGS. 16, 17, and 18.

[DRAM write operation (for DM)]
Next, with reference to FIG. 3 and FIG. 19, the DRAM write operation to the data memory (DM) 31 in the first DRAM access unit 32 (for DM) according to the present embodiment will be described. FIG. 19 is a flowchart showing the DRAM writing process.
The first DRAM access unit 32 (for DM) executes DRAM write processing (for DM) based on FIG. 19 in response to a DRAM write instruction from the write control unit 34.

  First, the activation processing unit 32B confirms whether or not the write target row address of the DM designated by the DRAM write instruction stored in the FIFO memory 32A is in an activated state (step 100). If the target row address is not activated (step 100: NO), the write target row address is activated (step 101), and the activation process is completed. If the write target row address of DM is in an activated state (step 100: YES), the activation process is completed without doing anything.

After completing the activation processing in the activation processing unit 32B, the DRAM write instruction is output from the FIFO memory 32A and input to the DRAM writing unit 32D via the access type determination unit 32C.
In response to this, the DRAM writing unit 32D writes the frame data (data D) specified by the DRAM write instruction to the DM column address corresponding to the input DRAM write instruction (step 102). Then, a series of DRAM write processing is completed.

  In this embodiment, when writing frame data to the DRAM constituting the data memory 31, the write control unit 34 writes a bank whose write target row address is in an activated state from among the banks of the DRAM. Is preferentially selected as a bank to be included. This reduces the probability that writing to different row addresses in the same bank will occur. For this reason, the number of times of waiting for the activation of the row address at the time of writing the frame data and the completion of the access to the different row address is reduced, and the decrease in the effective throughput of the DRAM access is suppressed.

[DRAM read operation (for DM)]
Next, with reference to FIGS. 3 and 20, a DRAM read operation for the data memory (DM) 31 in the first DRAM access unit (for DM) 32 according to the present embodiment will be described. FIG. 20 is a flowchart showing the DRAM reading process.
First DRAM access unit 32 executes DRAM read processing (for DM) based on FIG. 20 in response to a DRAM read instruction from read control unit 35.

  First, the activation processing unit 32B confirms whether or not the read target row address of the DM is in an activated state in the read target bank of the DM specified by the DRAM read instruction stored in the FIFO memory 32A (step 110). When the read target row address of DM is in the activated state (step 110: YES), the activation process is completed without doing anything.

After completing the activation process in the activation processing unit 32B, a DRAM read instruction is output from the FIFO memory 32A and input to the DRAM read unit 32E via the access type determination unit 32C.
In response to this, the DRAM read unit 32E reads frame data (data D) from the designated column address of the DM among the read target row addresses in the DM read target bank corresponding to the input DRAM read instruction. After that (step 114), the DRAM reading process is terminated.

If the read target row address in the DM read target bank is not in the activated state (step 110: NO), the activation processing unit 32B confirms whether a different row address is in the activated state in the DM read target bank. (Step 111).
If a different row address is not in the activated state (step 111: NO), the activation processing unit 32B activates the read target row address of the DM read target bank (step 113) and completes the activation process. To do. As a result, the DRAM reading unit 32E performs reading from the activated read target row address.

  If a different row address is in an activated state (step 111: YES), the activation processing unit 32B waits until the access to the different row address is completed (step 112), and then proceeds to step 113. In the same manner as described above, activation of the read target row address of DM is performed.

  As described above, when reading frame data from the DRAM constituting the data memory (DM) 31, since the frame data to be read is written in a specific bank, the row address of DM is set as in writing. An activated bank cannot be selected. Therefore, a waiting time occurs when reading from different row addresses in the same bank or reading from the same bank after writing. For reading from different row addresses in the same bank, a processing interval may be provided so that, for example, writing is inserted between the two row addresses so that reading from different row addresses does not continue.

[DRAM write operation (for QM)]
Next, with reference to FIG. 4 and FIG. 19, the DRAM write operation to the address queue management memory (QM) 33A in the second DRAM access unit (for QM) 38 according to the present embodiment will be described.
Second DRAM access unit 38 executes DRAM write processing (for QM) based on FIG. 19 in response to DRAM write instructions from write control unit 34 and read control unit 35.

  First, the activation processing unit 38B confirms whether the write target row address of the QM specified by the DRAM write instruction stored in the FIFO memory 38A is in an activated state (step 100), and the QM write target When the row address is not activated (step 100: NO), the write target row address is activated (step 101), and the activation process is completed. If the QM write target row address is in the activated state (step 100: YES), the activation process is completed without doing anything.

After completing the activation processing in the activation processing unit 38B, a DRAM write instruction is output from the FIFO memory 38A, and, similar to the first DRAM access unit 32, the DRAM writing unit 38D is connected via the access type determination unit 38C. Is input.
In response to this, the DRAM writing unit 38D writes the data (DSA and DNU or QNA) specified by the DRAM write instruction to the column address of the QM corresponding to the input DRAM write instruction ( Step 102), a series of DRAM write processing is terminated.

  In the present embodiment, when writing frame data to the DRAM constituting the data memory 31, the write control unit 34 activates the write target row address from each bank of the DRAM (DM). A bank is preferentially selected as a write target bank.

  Here, as shown in FIG. 5 described above, when the frame data is written, if the QCN of the write target queue is 0 (step 120: YES), the writing to the QM is the writing to the selected bank. As a result of QM bank selection, writing to different row addresses in the same bank does not occur in QM.

  When the frame data is written, if reading from the QM is necessary (step 132: YES), the bank selection is not performed and access to the bank of the QM to be read (reading and writing) is performed. The throughput of reading from the QM varies depending on whether or not the target row address is in an activated state. Accordingly, whether or not the row address of the QM to be read is activated is added to the determination in step 132 of FIG. 5, and if it is not activated, “No” may be selected.

  If the determination in step 132 is “NO”, it is necessary to write twice to the QM. An optimal bank can be selected for writing to the selected bank (DSA, DNU). However, for writing to the “bank before selection” (QNA), whether or not the target row address is in an activated state. Write throughput changes. As a method for suppressing throughput deterioration in this case, the same bank as the “bank before selection” may be selected, and QNA writing and DSA / DNU writing may be performed by one writing. When the same bank is selected, as shown in the examples of FIGS. 8 and 9, QNA, DSA, and DNU are written at successive positions of the same row address, so that writing can be performed once.

  This reduces the probability of writing to different row addresses in the same bank not only in DM but also in QM. This reduces the number of times DM and QM row addresses are activated when frame data is written, and the number of waits for completion of access to different row addresses, resulting in a decrease in effective throughput of not only DM but also QM DRAM access. Is also suppressed.

[DRAM read operation (for QM)]
Next, with reference to FIGS. 4 and 20, a DRAM read operation for the address queue management memory (QM) 33A in the second DRAM access unit (for QM) 38 according to the present embodiment will be described.
Second DRAM access unit 38 executes DRAM read processing (for QM) based on FIG. 20 in response to DRAM read instructions from write control unit 34 and read control unit 35.

  First, the activation processing unit 38B confirms whether or not the read target row address of the QM is in an activated state in the read target bank of the QM specified by the DRAM read instruction stored in the FIFO memory 38A (step 110). If the read target row address of QM is in the activated state, the activation process is completed.

After completing the activation processing in the activation processing unit 38B, a DRAM read instruction is output from the FIFO memory 38A and is input to the DRAM read unit 38E via the access type determination unit 38C in the same manner as the first DRAM access unit 32. Is done.
In response to this, the DRAM reading unit 38E receives data (DSA, DNU, QNA) from the column address of the designated QM among the row addresses to be read in the read target bank of the QM corresponding to the input DRAM read instruction. (Step 114), the DRAM reading process is terminated.

When the read target row address of the QM read target bank is not in the activated state (step 110: NO), the activation processing unit 38B confirms whether a different row address is in the activated state in the QM read target bank. (Step 111).
If a different row address is not in the activated state (step 111: NO), the activation processing unit 38B activates the read target row address of the QM read target bank (step 113), and completes the activation process. To do. As a result, the DRAM reading unit 38E performs reading from the activated read target row address.

  When a different row address is in an activated state (step 111: YES), the activation processing unit 38B waits until access to the different row address is completed (step 112), and then proceeds to step 113. In the same manner as described above, the read target row address of the QM is activated.

In this way, when data (DSA, DNU, QNA) is read from the QM, the data (DSA, DNU, QNA) to be read is written in a specific bank. A bank whose row address is in an activated state cannot be selected. Therefore, a waiting time occurs when reading from different row addresses in the same bank or reading from the same bank after writing.
Note that when reading frame data, in addition to reading from the QM, writing to the QM may be necessary (when the DNU is 2 or more).

[Effect of the first embodiment]
As described above, according to the present embodiment, in the recording device 30, the data memory (DM) 31 is configured by a DRAM having a plurality of row addresses for each bank, and the frame data of the queue is stored at the row address corresponding to the queue. When the first DRAM access unit 32 stores the frame data in the write target queue, the bank in which the write target row address corresponding to the write target queue is activated is written out If the bank data is selected and the frame data is written and there is no bank in which the write target row address is in the activated state, the bank in which the write target row address is in the inactive state is set as the write target bank. The frame data is written after selecting and activating the write target row address.

  More specifically, the recording device 30 includes a DRAM having a plurality of banks. The queue control memory 33 stores queue control information used to control writing / reading to / from the queue of the data memory 31, and the queue control memory. Based on the queue control information 33, the write control unit 34 for instructing the first DRAM access unit 32 to write the communication data transferred from the multiplexing device 10 to the write target queue, and the queue control memory 33 queue Based on the control information, there is provided a read control unit 35 that instructs the first DRAM access unit 32 to read communication data from the read target queue and transfers the read communication data to the multiplexer / demultiplexer 20. .

  In addition to this, the recording device 30 includes the second DRAM access unit 38, records the queue control information of the queue at the individual row address of the queue control memory 33 corresponding to the queue, and transmits the communication data to the write target queue. When the write target row address corresponding to the write target queue is activated as the write target bank among the banks of the queue control memory 33, the queue control information is written. If there is no bank in which the target row address is activated, the bank in which the target row address is inactive is selected as the target bank and the target row address is activated. The queue control information is written later.

  In general, in a DRAM, when writing data to an arbitrary row address of an arbitrary bank, it is necessary to activate the row address in the bank. When accessing a different row address of the same bank, the row address is Since it is necessary to activate a new row address after waiting for the used access to be completed, a relatively large waiting time occurs due to the activation of the row address in accessing the same bank. Specifically, this is a case where accesses to different row addresses in the same bank are continuous. As other conditions for waiting time, there are a case where writing is performed in the same bank after reading and a case where reading is performed from the same bank after writing.

According to the present embodiment, when writing frame data to the DRAM constituting the data memory 31, the bank in which the write target row address is activated is preferentially set as the write target bank among the banks of the DRAM. Selected.
As a result, the probability of writing to different row addresses in the same bank of the DRAM constituting the data memory 31 can be reduced. Therefore, it is possible to reduce the number of times of waiting for the activation of the row address when writing frame data to the DRAM constituting the data memory 31 and the completion of access to the different row address, and the DRAM to the DRAM constituting the data memory 31. It is possible to suppress a decrease in effective throughput related to access.

  In particular, in the communication input / output device 1, short frame data may be input continuously in bursts. According to the present invention, individual row addresses are assigned to the queues of the respective output systems. Therefore, in such a case, writing to the same row address is repeatedly performed, and the number of times of activation due to the change of the row address can be reduced. Therefore, even in such a case, since it is possible to suppress a decrease in effective throughput related to DRAM access, it is possible to sufficiently follow the processing speed of frame data and to reduce deterioration in communication quality.

  Further, in the present embodiment, for each combination of the queue and the bank of the data memory 31, the first bank management memory that stores a write pointer value used as a column address when writing the communication data of the queue to the bank (DM W / R pointer) 33E is provided, and when writing communication data, the write pointer value corresponding to the combination of the write target row address and the write target bank is obtained from the first bank management memory 33E. The communication data may be written to a column address composed of the write pointer value in the write target row address of the write target bank.

  As a result, even when individual row addresses are assigned to the queues of each output system, a plurality of queues can share each bank of the data memory 31, and when writing frame data to an arbitrary queue, Regardless of which bank in which the address is activated is selected, the column address to be used in the bank can be specified very quickly, and the effective throughput of DRAM (DM) access can be improved.

  In the present embodiment, for each combination of the queue and the bank of the queue control memory 33, the recording device 30 stores a write pointer value used as a column address when writing the queue control information of the queue to the bank. The second bank management memory (QM W / R pointer) 33F is provided, and when writing the queue control information, the write pointer value corresponding to the combination of the write target row address and the write target bank is set to the second value. The queue control information is obtained from the bank management memory 33F and the queue control information is written to the column address consisting of the write pointer value among the write target row addresses of the write target bank.

  As a result, even when individual row addresses are assigned to the queues of each output system, a plurality of queues can share each bank of QM, and when writing queue control information to any queue, the row address Regardless of which bank is activated, the column address to be used in the bank can be specified very quickly, and the effective throughput of DRAM (QM) access can be improved.

  In the present embodiment, the recording device 30 stores a communication data storage bank (QNA) subsequent to the communication data written in the virtual storage address, and the first and last communication data of the queue for each queue. May be stored in the bank (QSA, QLA) in which is written.

  In addition, when the write control unit 34 writes communication data to the write target queue (performs a write instruction), the communication data is written to the write target virtual address composed of the write pointer of the selected bank. The instruction is updated, the queue last bank (QLA) of the write target queue, the data storage bank (QNA) and the write pointer subsequent to the final data before writing are updated, and the read control unit 35 updates the read target queue. When reading communication data from (reading out), the communication data is read from the read pointer value of the queue head bank of the read target queue, and the queue head bank (QSA) and the read pointer of the read target queue are respectively updated. You may do it.

  As a result, the frame data of each queue is sequentially written to the virtual storage address in the free state, and the virtual storage address from which the frame data has been read out is managed again as a free state. Further, the virtual storage address of the frame data is managed in the order of writing for each queue.

  According to the present embodiment, the queue control memory 33 that stores the queue control information can store the bank information selected when writing the communication data, and can use the information when reading the corresponding communication data. The communication data can be read efficiently.

  Even when the queue control memory 33 is constituted by a DRAM, the number of activations of the row address of the QM DRAM can be reduced by the bank selection described above. For this reason, it is possible to suppress a decrease in effective throughput related to QM DRAM access. If the effective throughput related to QM DRAM access decreases, the frame data write / read throughput may decrease. Therefore, the frame data write / read can be suppressed by suppressing the decrease in the effective throughput related to QM DRAM access. It is possible to suppress a decrease in throughput.

Further, the queue control memory 33 for storing the queue control information can store the information of the bank selected at the time of writing the communication data, and can use the information at the time of reading the corresponding communication data.
In addition, when data in the same queue is written to successive addresses, the number of addresses in the QM can be made smaller than the number of addresses in the data memory by updating the DNU in the QM.

  In addition, this embodiment has a feature that it is not necessary to set an initial value such as a DSA value in the QM. In the present embodiment, only the QCN, the W / R pointer, and the AAR need to set initial values when the communication input / output device is activated. Therefore, the scale of the circuit for performing the initial setting or the scale of the software for performing the initial setting is extremely small, and the time required for the initial setting is extremely small.

[Second Embodiment]
Next, a communication input / output device 1 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 21 is a block diagram illustrating a configuration of an access arbitration unit according to the second embodiment.

  In the communication input / output device 1 according to the first embodiment, for example, when a large amount of frame data related to a specific output system is input, the data memory (DM) 31 and the address queue management memory (QM) of a specific bank ) If you continue writing to 33A, you will not be able to write to that bank.

  The purpose of this embodiment is to determine whether data can be written for each queue and bank of DM and QM, and to prevent the data storage amount for each queue from exceeding the set maximum storage amount. In the recording device 30, when the access arbitration unit 37 writes frame data to the write target queue (instructs writing), the number of virtual storage addresses necessary for writing is indicated based on the data length of the frame data. The necessary address number is calculated, and based on the used virtual address number of the write target queue acquired from the queue used address number memory 36, the remaining address number indicating the number of virtual storage addresses that can be used for the write is calculated. By comparing the required number of addresses with the number of remaining addresses, it is determined whether or not the frame data can be written. It is obtained so as to direct the writing of the frame data to the write control unit 34 in accordance with the.

  As shown in FIG. 21, in this embodiment, the access arbitration unit 37 includes, as main circuit units, a write enable / disable determination unit 37A, a write FIFO 37B, a read acceptance unit 37C, a read FIFO 37D, and a priority control unit. 37E, a queue use address number updating unit 37F, and an instruction output unit 37G are provided.

  The write enable / disable determining unit 37A includes queue designation information and frame length information added to the frame data transferred from the multiplexing device 10, determination address number information set in advance for each queue, and information on each queue. Based on the number of used virtual addresses, the function determines whether or not writing is possible, and the frame data is stored in one of the storage areas provided in the data memory (DM) 31 according to the determination result of writing It has a function of writing a write instruction in which queue designation information is added to the data obtained by dividing the data size for the virtual address into the write FIFO 37B.

The determination address number information includes the maximum virtual address number NKmax that can be used in the write target queue designated by the queue designation information.
FIG. 22 is a configuration example of the determination address number information. Here, the maximum number of virtual addresses NKmax is set for each queue ID for identifying the queue. The determination address number information is stored in, for example, the queue use address number update unit 37F or the internal memory (not shown) of the access arbitration unit 37.

  Based on the read data amount information of the read request output from the demultiplexer 20, the read accepting unit 37C calculates the number of times of reading for the DM, and reads the queue designation information of the read request as a read instruction for the number of times of reading. It has a function of writing to the FIFO 37D. In this calculation, a value obtained by dividing the data amount indicated by the read data amount information by the data size per DM virtual address is used as the number of readings, and if there is a remainder, 1 may be added to the number of readings.

  The priority control unit 37E reads the write instruction or the read instruction from the write FIFO 37B or the read FIFO 37D and outputs it to the queue use address number update unit 37F, and both the write FIFO 37B and the read FIFO 37D In the case where there are a write instruction and a read instruction, it has a function of preferentially reading the write instruction from the write FIFO 37B.

  When a write instruction is input from the priority control unit 37E, the queue use address number update unit 37F in the queue use address number memory 36 uses the write target queue use virtual address corresponding to the queue designation information of the write instruction. 1 is added to the number, and when the read instruction is input from the priority control unit 37E, and the function of outputting the write instruction to the instruction output unit 37G, the queue designation of the read instruction in the queue use address number memory 36 It has a function of subtracting 1 from the number of virtual addresses used in the read target queue corresponding to the information and outputting the read instruction to the instruction output unit 37G.

  The instruction output unit 37G has a function of outputting the write instruction to the write control unit 34 when a write instruction is input from the queue use address number updating unit 37F, and a read instruction when the read instruction is input. Is output to the read control unit 35.

[Operation of Second Embodiment]
Next, with reference to FIG. 23, a write determination operation at the time of writing frame data will be described as the operation of the access arbitration unit 37 according to the present embodiment. FIG. 23 is a flowchart illustrating a write permission / inhibition determination process according to the second embodiment.
The access arbitration unit 37 of the recording device 30 determines whether or not writing is possible for each frame data transferred from the multiplexing device 10 based on the writeability determination processing of FIG.

  First, the access arbitration unit 37 acquires the used virtual address number QCN of the write target queue from the queue used address number memory 36 (step 200), and subtracts the QCN from the total virtual address number NA for each queue. The remaining virtual address number NR is calculated (step 201), and the necessary virtual address number NF required for writing the target frame data to be written is calculated (step 202).

  Thereafter, NF and NR are compared (step 203). Here, if NF> NR (step 203: YES), the access arbitration unit 37 determines that writing is not possible, discards the target frame data (step 208), and ends the write determination processing for the target frame data. To do.

On the other hand, when NF ≦ NR (step 203: NO), the access arbitration unit 37 acquires the maximum virtual address number NKmax of the designated write target queue from the queue use address number memory 36 or the like (step 204), The number of remaining addresses NR is calculated by subtracting QCN from NKmax (step 205), and NF and NR are compared (step 206).
Here, if NF> NR (step 206: YES), the access arbitration unit 37 determines that writing is not possible, discards the target frame data (step 208), and terminates the write determination process for the target frame data. To do.

On the other hand, if NF ≦ NR (step 206: NO), the access arbitration unit 37 determines that the target frame data can be written (step 207), and ends the write determination process for the target frame data.
Thereafter, the access arbitration unit 37 divides the target frame data into data sizes corresponding to one virtual address according to the determination of whether or not writing is possible, and issues a write instruction in which queue designation information is added to the obtained data. The data is written to the write FIFO 37B.
Further, the number of virtual addresses used for each DM bank is managed for each queue by the queue used address number memory 36 or the like, and for example, the write determination process is performed with the maximum number of remaining addresses for each bank as NR. It may be.

[Effect of the second embodiment]
As described above, according to the present embodiment, in the recording device 30, the queue use address number memory 36 stores the use address number indicating the number of virtual storage addresses used by the queue for each queue. When the unit 37 writes communication data to the write target queue (instructs writing), the unit 37 calculates the necessary number of addresses indicating the number of virtual storage addresses required for writing based on the data length of the communication data, Based on the used virtual address number of the write target queue acquired from the used address number memory 36, the remaining address number indicating the number of virtual storage addresses that can be used for the write is calculated, and the necessary address number and the remaining address are calculated. The communication data is written to determine whether or not the communication data can be written, and the write control unit 34 determines whether or not the communication data can be written. It is obtained so as to instruct the writing of signal data.

  In the present embodiment, when the access arbitration unit 37 having the configuration shown in FIG. 21 is used, it may be erroneously determined that writing is possible if the write instruction data exists in the write FIFO 37B. In order to prevent erroneous determination, whether to use a value obtained by adding the number of virtual addresses in the write FIFO 37B (the number of write instructions) to the information in the queue used address number memory 36 as the used virtual address number of each queue. , NA or NKmax may be a value obtained by subtracting the number of virtual addresses (the number of write instructions) in the write FIFO 37B.

  Note that the number of virtual addresses used for each bank of the data memory 31 is managed for each queue by the queue used address number memory 36 or the like, and for example, the write determination process is performed with the maximum number of remaining addresses for each bank as NR. Thus, for a frame that is not discarded, all the data of the frame can be written to consecutive addresses in the same bank.

[Third Embodiment]
Next, a communication input / output device 1 according to a third embodiment of the present invention will be described with reference to FIGS. FIG. 24 is a block diagram illustrating a configuration of a QM according to the third embodiment. FIG. 25 is a block diagram illustrating a configuration of QSA, QLA, QCN, and a W / R pointer according to the third embodiment. FIG. 26 is a flowchart illustrating the write operation of the write control unit according to the third embodiment. FIG. 27 is a flowchart illustrating the read operation of the read control unit according to the third embodiment.

  In this embodiment, as shown in FIGS. 24 and 25, the QM DNU in the first embodiment is limited to 1, and the W / R pointer is used as a data memory (DM) 31 and an address queue. This is shared with the management memory (QM) 33A.

Next, the write operation shown in FIG. 26 will be specifically described.
First, the write control unit 34 checks whether or not the QCN of the write target queue is 0 (step 120). If the QCN is 0 (step 300: YES), the bank of DM and QM is selected ( Step 301), the bank number of the selected QM bank is written to QSA and QLA (step 302), and the write pointer of the selected bank is read (step 303).

  Next, the write control unit 34 writes data to the DM using the DM write pointer as a column address (step 304), updates the write pointer of the selected bank (step 305), and writes the QCN of the write target queue. After adding 1 to (step 306), the series of writing operations is terminated.

If the QCN is not 0 in step 300 (step 300: NO), the write control unit 34 reads the QLA in the write target queue (step 310) and writes the write pointer of the bank recorded in the QLA. Is read (step 311).
Next, the write control unit 34 selects DM and QM banks (step 312), writes the bank number of the selected bank to the QLA (step 313), and uses the write pointer of the bank before selection as the column address. After the selected bank number is written in the QNA QNA (step 314), the process proceeds to step 303.

Next, the reading operation shown in FIG. 27 will be described.
First, the read control unit 35 reads the QSA of the read target queue (step 320), and reads the bank read pointer recorded in the QSA (step 321).
Next, the read control unit 35 checks whether or not the QCN is 2 or more (step 322). If the QCN is not 2 or more (step 322: NO), the read controller 35 reads the data from the DM using the read pointer as the column address. (Step 323), after updating the read pointer (Step 324), 1 is subtracted from the QCN of the write target queue (Step 325), and the series of reading operations is completed.

  On the other hand, when the QCN is 2 or more at step 322 (step 322: YES), the read control unit 35 reads the QNA from the QM using the read pointer as the column address (step 326), and writes the QNA value to the QSA. Later (step 327), the process proceeds to step 323.

[Effect of the third embodiment]
As described above, according to the present embodiment, the QM DNU is limited to 1 and the W / R pointer is used for both DM and QM, so the DM bank and the QM bank are independent. However, in the write operation shown in FIG. 26, as in the first embodiment, by selecting a DM bank, degradation of the DRAM (DM and QM) access throughput is suppressed. be able to.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

In each of the above embodiments, when the communication input / output device 1 processes a multicast frame, a multicast output system is provided as one of the output systems, and a plurality of multicast frames are provided in the distribution unit 22 in the demultiplexer 20. It is also possible to provide a means for outputting to the speed converter 23 and to allocate a part of the queues logically formed in the data memory 31 of the recording device 30 as a queue corresponding to this multicast output system.
As a result, the multicast frame input from the outside to the multiplexing device 10 is temporarily stored in a queue corresponding to the multicast output system in the data memory 31, and the multicast frame is read from the queue by the demultiplexing device 20. Output from multiple output ports.

  DESCRIPTION OF SYMBOLS 1 ... Communication input / output device, 10 ... Multiplexer, 11 ... Queue designation information addition part, 12 ... Multiplexing part, 20 ... Demultiplexing device, 21 ... Reading part, 22 ... Distribution part, 23, 24 ... Speed Conversion unit, 30 ... recording device, 31 ... data memory (DM), 32 ... first DRAM access unit, 32A ... FIFO memory, 32B ... activation processing unit, 32C ... access type determination unit, 32D ... DRAM writing unit 32E ... DRAM reading unit, 33 ... Queue control memory, 33A ... Address queue management memory (QM), 33B ... Queue head bank register, 33C ... Queue last bank memory, 33D ... Access history register, 33E ... First bank management Memory, 33F ... Second bank management memory, 34 ... Write control unit, 35 ... Read control unit, 36 ... Queue usage address number memory, 37 ... Access control , 37A, write enable / disable determination unit, 37B, write FIFO, 37C, read acceptance unit, 37D, read FIFO, 37E, priority control unit, 37F, queue use address number update unit, 37G, instruction output unit, 38: Second DRAM access section.

Claims (6)

A multiplexing device that multiplexes by adding queue designation information indicating a queue corresponding to an output system to which the communication data is to be output, and the communication data transferred from the multiplexing device. Corresponding to a recording device for temporarily storing in a queue to be written designated by the queue designation information among a plurality of queues logically formed in the data memory, and an output system selected based on the priority control logic among the queues A communication input / output device comprising: a demultiplexer that reads the communication data from the read target queue and converts the communication data into a communication speed of an output port corresponding to the output system;
The recording device includes:
The data memory, which comprises a DRAM having a plurality of row addresses for each bank, stores communication data of the queue at individual row addresses corresponding to the queue,
When writing the communication data to the write target queue, the bank in which the write target row address corresponding to the write target queue is activated among the banks is selected as the write target bank, and the communication data is selected. When there is no bank in which the write target row address is in the activated state, the bank in which the write target row address is in the inactive state is selected as the write target bank, and the write target row address is selected. A first DRAM access unit for writing the communication data after activating
A queue control memory comprising a DRAM having a plurality of row addresses for each bank, and storing queue control information used for controlling writing / reading to / from the queue of the data memory;
A write control unit that instructs the first DRAM access unit to write the communication data transferred from the multiplexing device to the write target queue based on queue control information in the queue control memory;
A read control unit that instructs the first DRAM access unit to read communication data from the read target queue based on queue control information in the queue control memory, and transfers the read communication data to the demultiplexer; ,
When the queue control information of the queue is recorded with the individual row address of the queue control memory corresponding to the queue and the communication data is written to the write target queue, the write target queue of the queue control memory bank If the bank whose write target row address corresponding to is selected as a write target bank and writes the queue control information, and there is no bank where the write target row address is active, A second DRAM access unit that writes the queue control information after selecting the bank in which the write target row address is inactivated as the write target bank and activating the write target row address. An input / output device for communication. The communication input / output device according to claim 1,
For each combination of the queue and the bank of the data memory, the recording device includes a first bank management memory for storing a write pointer value used as a column address when writing communication data of the queue to the bank. In addition,
When writing the communication data, the write control unit acquires a write pointer value corresponding to a combination of the write target row address and the write target bank from the first bank management memory, and A communication input / output device, wherein the communication data is written to a column address composed of the write pointer value among the write target row addresses of the bank to be inserted. The communication input / output device according to claim 1 or 2,
The recording apparatus stores, for each combination of the queue and the bank of the queue control memory, a write pointer value used as a column address when writing the queue control information of the queue into the bank. Further comprising memory,
The write control unit obtains a write pointer value corresponding to a combination of the write target row address and the write target bank from the second bank management memory when writing the queue control information, An input / output device for communication, wherein the queue control information is written to a column address composed of the write pointer value among the write target row addresses of the write target bank. The communication input / output device according to claim 2,
When writing the queue control information, the write control unit uses the write target row address, the write target bank, and the write pointer value used for writing the communication data in the queue control information. An input / output device for communication, wherein the queue control information is written as a write target row address, a write target bank, and a write target column address. In the communication input / output device according to any one of claims 1 to 4,
The queue control memory stores a storage bank of communication data subsequent to the communication data written in the virtual storage address used on the virtual data memory, and the first and last communication data of the queue is written for each queue. Remembers the bank
When writing the communication data to the write target queue, the write control unit updates a queue last bank of the write target queue, a storage bank of data subsequent to the final data before writing,
When reading the communication data from the read target queue, the read control unit instructs the first DRAM access unit to read the communication data with respect to the read pointer value of the queue head bank of the read target queue, and An input / output device for communication characterized by updating a queue head bank of a target queue. In the communication input / output device according to any one of claims 1 to 5,
The recording device includes:
A queue use address number memory for storing a use address number indicating the number of virtual storage addresses on the virtual data memory used by the queue for each queue;
When writing the communication data to the write target queue, the necessary address number indicating the number of virtual storage addresses required for writing is calculated based on the data length of the communication data, and obtained from the queue use address number memory Based on the number of addresses used in the write target queue, the remaining address number indicating the number of virtual storage addresses that can be used for the write is calculated, and the communication data is compared by comparing the required address number with the remaining address number. The communication input / output device further comprising: an access arbitration unit that determines whether or not writing is possible, and instructs the writing control unit to write the communication data in accordance with the determination of writing permission.

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