JP6570075B2 - Communication input / output device - Google Patents

Description

  The present invention relates to a data communication technique, and more particularly to a memory access control technique used in a communication input / output device that inputs and outputs communication data (frame data).

Conventionally, for example, a configuration as disclosed in Patent Document 1 has been proposed as a communication input / output device that is used in data communication such as the Internet to input / output communication data such as Ethernet (registered trademark) frame data. ing. FIG. 19 is a block diagram showing a configuration of a conventional communication input / output device (built-in memory).
This communication input / output device includes a multiplexing device MUX, a recording device MEM, and a demultiplexing device DEMUX.

The MUX adds the queue designation information corresponding to the output destination of the frame data to the input frame data by the queue designation information addition section provided for each input port, and then multiplexes it by the multiplexing section. Output.
The MEM receives the frame data output from the MUX by time division multiplexing by the write control unit, refers to the queue designation information and the queue map added to each frame data, and stores the frame data in the built-in data memory. Of the queues logically provided for each output destination, the frame data is written to the queue address corresponding to the queue designation information. Further, in response to a read instruction from the DEMUX, the MEM reads frame data from the corresponding queue by the read control unit and outputs the frame data to the DEMUX.

  The DEMUX reads out the frame data from the output destination queue corresponding to the priority output port in the MEM based on the priority control logic for each output port by the reading unit, and distributes the frame data to the corresponding output port by the distribution unit. The data is converted into the communication speed of the output port by a speed conversion unit provided for each output.

  FIG. 20 is an explanatory diagram showing the correspondence between queues and output ports, and shows the case where the number of output ports is three. In FIG. 20A, queues and output ports are associated one-to-one, but as illustrated in FIG. 20B, one frame data is associated with a plurality of output ports. Can be handled when Further, as shown in FIG. 20C, a queue corresponding to the read priority can be associated with each output port.

JP 2011-0101095 A

  In such a communication input / output device, the storage capacity required by the MEM increases as the output system increases, so a DRAM is used as a data memory. However, since DRAM access has a waiting time due to the activation of the row address in each bank, in some cases, the effective throughput of the DRAM access is extremely reduced to follow the processing speed of frame data. There is a problem that communication quality is deteriorated because communication cannot be performed.

  In general, in a DRAM, when writing data to an arbitrary row address of an arbitrary bank, it is necessary to activate the row address in the bank. When accessing a different row address of the same bank, the row address is Since it is necessary to activate a new row address after waiting for the used access to be completed, a relatively large waiting time occurs due to the activation of the row address in accessing the same bank. Specifically, this is a case where accesses to different row addresses in the same bank are continuous. As other conditions for waiting time, there are a case where writing is performed in the same bank after reading and a case where reading is performed from the same bank after writing.

  Therefore, these waiting times cause a decrease in effective throughput related to DRAM access. Therefore, in particular, in communication I / O devices, short frame data may be input continuously in bursts. In such a case, when frequently accessing different row addresses in the same bank The effective throughput may be extremely reduced.

  An object of the present invention is to provide a memory access control technique capable of suppressing such a decrease in effective throughput related to DRAM access.

  In order to achieve such an object, the communication input / output device according to the present invention adds queue designation information indicating a queue corresponding to an output system to which the communication data is to be output to communication data that is sequentially input. And the communication data transferred from the multiplexing device are temporarily stored in a write target queue designated by the queue designation information among a plurality of queues logically formed in a data memory. Multiplex that reads out the communication data from the queue to be read corresponding to the output system selected from the queue and the output system selected based on the priority control logic from the queue, converts it to the communication speed of the output port corresponding to the output system, and outputs it A communication input / output device comprising a separation device, wherein the recording device comprises a DRAM having a write pointer for each bank, and communication of the queue When writing the communication data to the data memory storing the data and the write target queue, the bank in which the write target row address corresponding to the write pointer is activated among the banks is set as the write target bank. When the communication data is selected and the bank to which the write target row address is activated does not exist, the bank to which the write target row address is inactivated is selected as the write target bank. And a DRAM access unit for writing the communication data after activating the write target row address.

  In addition, one configuration example of the communication input / output device according to the present invention includes: a queue control memory that stores queue control information used when the recording device controls writing / reading to / from the queue of the data memory; A write control unit that instructs the DRAM access unit to write the communication data transferred from the multiplexing device to the write target queue based on queue control information in the queue control memory; A read control unit for instructing the DRAM access unit to read communication data from the read target queue based on queue control information, and transferring the read communication data to the demultiplexing device; Is written to the virtual storage address for each virtual storage address used in the virtual data memory. A subsequent address indicating a virtual storage address of communication data subsequent to the communication data stored, and for each of the queues, a queue head address indicating the start and end of the virtual storage address in which the communication data of the queue is written, and A queue last address is stored, and a common write address indicating a virtual storage address to which communication data is to be written next is stored for each bank in common with each of the queues, and the write control unit stores the write target When writing the communication data to the queue, the DRAM access unit is instructed to write the communication data to the write target virtual address consisting of the next write address of the bank selected as the write target bank, and the write target queue Queue end address, subsequent address for queue end address before write, and write The next write address of the bank selected as the elephant bank is updated, and when the read control unit reads the communication data from the read target queue, the read control unit updates the corresponding write target virtual address including the queue start address of the read target queue. Instruct the DRAM access unit to read communication data, and update the queue head address of the read target queue, the next write address of the read target bank, and the subsequent address related to the next write address of the new read target bank, respectively. It is a thing.

  Also, in one configuration example of the communication input / output device according to the present invention, the recording device uses, for each queue, the number of virtual storage addresses on the virtual data memory used by the queue. Queue use address number memory for storing the number of addresses, and when writing the communication data to the write target queue, based on the data length of the communication data, the required address number indicating the number of virtual storage addresses required for writing Calculate the remaining number of addresses indicating the number of virtual storage addresses that can be used for the writing based on the number of used addresses of the write target queue or the queue acquired from the queue used address number memory and calculate the necessary address Is compared with the number of remaining addresses to determine whether the communication data is writable, and the write data is It is obtained so as to further include an access arbitration unit for instructing the writing of the communication data to the control unit.

According to the present invention, in a recording device for temporarily storing communication data transferred from a multiplexing device in a write target queue designated by queue designation information among a plurality of queues logically formed in a data memory, Even when the data memory is composed of a DRAM, the number of activations of the row address can be reduced. For this reason, it is possible to suppress a decrease in effective throughput related to DRAM access.
Further, the queue control memory for storing the queue control information can store the information of the bank selected at the time of writing the communication data, and can use the information at the time of reading the corresponding communication data.

1 is a block diagram illustrating a configuration of a communication input / output device according to a first embodiment. FIG. It is a storage example of a virtual data memory. It is a block diagram which shows the structure of a queue control memory. It is a storage example of an address queue management memory. It is a storage example of a queue head address register and a queue last address register. It is a storage example of a queue use address number memory. 1 is a block diagram showing a configuration of a DRAM access unit according to a first embodiment. FIG. It is explanatory drawing which shows the write-in operation | movement in a write-control part. It is explanatory drawing which shows the read-out operation | movement in a read-out control part. It is explanatory drawing which shows the queue control information immediately before data P2-1 reading (immediately after writing data P2-3). It is explanatory drawing which shows the change of the queue control information at the time of data P2-1 reading. It is explanatory drawing which shows the change of the queue control information at the time of data P2-2 reading. It is explanatory drawing which shows the change of the queue control information at the time of data P1-4 writing. It is a flowchart which shows DRAM write processing. It is a flowchart which shows DRAM read-out processing. It is a block diagram which shows the structure of the access arbitration part concerning 2nd Embodiment. It is an example of a structure of the address number information for determination. It is a flowchart which shows the writability determination processing concerning 2nd Embodiment. It is a block diagram which shows the structure of the conventional input / output device for communication (built-in memory). It is explanatory drawing which shows a response | compatibility with a queue and an output port.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a communication input / output device 1 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of the communication input / output device according to the first embodiment.

  The communication input / output device 1 is a communication input / output device for inputting / outputting communication data such as Ethernet (registered trademark) frame data, which is used in Internet communication or the like. The communication data input from the port is separated for each output system to which the communication data is to be output, converted to the communication speed of the output port corresponding to the output system, and output.

  As shown in FIG. 1, the communication input / output device 1 includes a multiplexer (MUX) 10, a demultiplexer (DEMUX) 20 with a built-in memory access control function, and a recording device (MEM) with a built-in access control function. 30. In the following, a case where communication data input / output by the communication input / output device 1 is frame data will be described as an example. However, the present invention is not limited to this, and various types of communication data such as packets and ATM cells are converted into frame data. It is also possible to input / output in the same manner as in FIG.

The multiplexing device 10 has a function of multiplexing the frame data sequentially input from the outside by adding queue designation information corresponding to the output system to which the frame data is to be output.
The recording device 30 writes the frame data transferred from the multiplexing device 10 into a write target designated by the queue designation information added to the frame data among a plurality of queues logically formed in the data memory. It has a function to temporarily store in a queue.
The demultiplexer 20 reads the frame data temporarily stored in the read target queue from the read target queue corresponding to the output system selected based on the priority control among the queues in the recording device 30, and corresponds to the output system. It has a function of converting and outputting the communication speed of the output port.

  In this embodiment, in the recording apparatus 30, the data memory 31 is composed of a DRAM having a write pointer for each bank, and when the DRAM access unit 32 writes frame data to the write target queue, the write pointer of the bank If the bank in which the write target row address corresponding to is selected as the write target bank is written into the frame data, and there is no bank in which the write target row address is in the active state, The bank data in which the write target row address is deactivated is selected as the write target bank, and the frame data is written after the write target row address is activated.

  In this embodiment, as shown in FIG. 1, a case where two input ports Pin0 and Pin1 are provided as the input port Pin and two output ports Pout0 and Pout1 are provided as the output port Pout will be described as an example. However, the number of input ports Pin and output ports Pout is not limited to this. Three or more of either or both of the input port Pin and the output port Pout can be provided, and the number of input ports and the number of output ports may be different. Note that the number of input ports may be one.

[Multiplexer]
Next, with reference to FIG. 1, the multiplexing apparatus 10 used in the communication input / output apparatus 1 according to the present embodiment will be described in detail.
As shown in FIG. 1, the multiplexing apparatus 10 is provided with a queue designation information adding unit 11 and a multiplexing unit 12 as main circuit units.

  The queue designation information adding unit 11 is provided for each of the input ports Pin0 and Pin1, and for frame data input from the corresponding input port Pin, queue designation information corresponding to the output destination of the frame data, and the frame It has a function of adding data frame length information (Byte) and outputting it to the multiplexing unit 12. At this time, for example, when outputting frame data to the multiplexing unit 12, the frame length information may be added by counting the number of bytes from the beginning to the end of the frame data as the frame length.

Multiplexing unit 12 is provided in common with each queue designation information adding unit 11, multiplexes the frame data output from each queue designation information adding unit 11 in a time division manner, and outputs it to recording apparatus 30. It has a function.
In the multiplexer 10, the designation of the queue corresponding to the output destination of the frame data may be realized by a bridge function such as IEEE802.1D. Specifically, the output port search by MAC address learning and the VLAN-ID are used. The output port can be specified (see Patent Document 1).

[Demultiplexer]
Next, the demultiplexer 20 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG.
As shown in FIG. 1, the demultiplexer 20 includes a reading unit 21, a distribution unit 22, and speed conversion units 23 and 24 as main circuit units.

The reading unit 21 refers to the accumulation status of each queue acquired from the recording device 30 and the reading stop instruction signal output from the speed conversion units 23 and 24, and the frame data based on the priority control logic for each of the output ports Pout0 and Pout1. A function for selecting an output system to be output with priority, a function for outputting a read request for reading frame data from a read target queue corresponding to the output system, and a transfer from the recording apparatus 30 in response thereto The frame data is output to the distribution unit 22.
For priority control logic, for example, if the capacity of each queue is the same, general priority control such as reading from the queue with the largest amount of communication data stored in the queue among readable queues. Logic may be used (see Patent Document 1).

In addition, when the reading unit 21 outputs a read request to the recording device 30, the reading unit 21 instructs the recording device 30 with read data amount information indicating the data amount of the read data in addition to the queue designation information that specifies the queue to be read. To do.
For the read data amount information, for example, when the data accumulation amount of the queue to be read is equal to or less than a preset threshold value, a value equal to the data accumulation amount is output as the read data amount information. May be output as read data amount information.

The distribution unit 22 has a function of distributing the frame data output from the reading unit 21 to the speed conversion units 23 and 24 of the corresponding output port based on the queue designation information added to the frame data. Yes.
The speed converters 23 and 24 are provided for each output port, and according to the function of converting the frame data distributed from the distribution unit 22 into the communication speed of the output port and outputting the same, and the output status of the frame data A function of outputting a reading stop instruction signal to the reading unit 21.
The queue designation information added to the frame data is deleted by the distribution unit 22 or the speed conversion units 23 and 24.

[Recording device]
Next, the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG.

  As shown in FIG. 1, the recording device 30 includes, as main circuit units, a data memory 31, a DRAM access unit 32, a queue control memory 33, a write control unit 34, a read control unit 35, and a queue use address number memory 36. , And an access arbitration unit 37 is provided.

  The data memory 31 comprises a general DRAM (DRAM chip) having a plurality of row addresses for each bank, and has a function of storing frame data using a write pointer for each bank. Yes. Specifically, the data memory 31 may be composed of one or a plurality of DRAM chips and correspond to the write pointer for each bank. In addition to the configuration of having one queue for each output system, It is also possible to have a plurality of queues in one output system. In this embodiment, one DRAM chip is shared by a plurality of queues.

The data memory 31 is provided with a plurality of storage areas having unique storage addresses. Each queue is configured by arbitrarily connecting virtual storage areas of a virtual data memory having a virtual storage address equivalent to the storage address of the data memory 31 regardless of whether the virtual storage addresses are continuous / discontinuous or in ascending / descending order. Yes. The virtual storage address is used for managing frame data independent of the actual row address, column address (Column Address), and bank number used for accessing the DRAM, and is used in a virtual memory space. Address information.
FIG. 2 is a storage example of the virtual data memory. Here, an image in a case where data written from the write control unit 34 is stored for each virtual storage area having a unique virtual storage address ADM (0 to N: N is an integer of 2 or more) is shown. ing.

  At this time, if one frame is longer than the data size for one virtual address, one frame is divided into a plurality of data D in accordance with the data size for one virtual address, and written to a plurality of different virtual storage addresses. For example, in the case of FIG. 2, the virtual storage addresses 0, 1, and 4 of the bank 0 store the data P1-1, P1-2, and P1-3 of the queue P1, and the virtual storage addresses 2 and 2 of the bank 0 are stored. 3 and 5 store data P2-1, P2-2, and P2-3 of the queue P2. The order relation of these data and the correspondence relation with the frame are managed by an address queue management memory described later. When one frame is shorter than the data size of the virtual storage area, the frame data is stored in one virtual storage area.

  The DRAM access unit 32 has a function of writing frame data to a corresponding address in the data memory 31 in response to a DRAM write instruction from the write control unit 34 and a DRAM read instruction from the read control unit 35. A function of reading frame data from a corresponding address in the data memory 31.

  The DRAM access unit 32 has a function of writing frame data to a designated virtual storage address (row address and column address) when the write target row address of the designated bank is in an activated state when writing frame data. When the write target row address is not activated, the write target row address is activated and then the frame data is written.

  When reading the frame data, the DRAM access unit 32 reads the frame data from the read target row address of the read target bank if the read target row address is in the activated state in the designated read target bank. When the read target row address is not activated in the read target bank, the read target row address of the read target bank is activated and then the frame data is read.

  The queue control memory 33 is composed of a semiconductor memory such as an SRAM chip, for example, and has a function of storing various queue control information used for controlling writing / reading of frame data to / from each queue formed on the data memory 31. Have.

  FIG. 3 is a block diagram showing the configuration of the queue control memory. The queue control memory 33 includes a plurality of storage units composed of registers and memories. As main storage units, a free address register (VAR, UAR) 33A, an address queue management memory (QM) 33B, a queue head address register ( SAR) 33C, queue final address register (LAR) 33D, access history register (AAR) 33E, and work address register (TMPV, TMPL) 33F. In the following description, register names are sometimes used as variable names for easy understanding.

  The empty address register (VAR, UAR) 33A has a function of storing the next write address VAR and the unwritten address UAR for each bank in common with each queue. Among them, VAR (Valid Address Register) is address information for each bank indicating a virtual storage address where the frame data to be written next when the frame data received from the multiplexing apparatus 10 is written next. UAR (Unused Address Register) is a storage address indicating the head (young number) of unused virtual storage addresses in the same bank in which data has not been written yet after initialization.

  In this embodiment, when writing frame data, it is basically used in order from the youngest virtual storage address in each bank, and the virtual storage address that has become free by reading frame data is unused. It shall be reused in preference to the virtual storage address. The order of the virtual storage addresses to be reused may be any order, for example, the virtual storage addresses that have recently become empty, and may be reused in order, and is not limited to the lowest number.

The address queue management memory (QM) 33B has a function of storing a subsequent virtual address ADD (ADDress) and a pointer PN (Pointer of QM) for each virtual storage address ADM.
FIG. 4 is a storage example of the address queue management memory. Among these, ADD is a virtual storage address (including bank information) in which communication data following the communication data written to the virtual storage address is stored. PN is information (frame end flag: EoF) indicating whether or not the data stored at the virtual storage address includes the final data of the frame data.

The queue head address register (SAR) 33C has a function of storing a queue head address SAR (Start Address register of PM) for each queue.
The queue last address register (LAR) 33D has a function of storing a queue last address LAR (Last Address register of PM) for each queue.

  FIG. 5 shows a storage example of the queue head address register and the queue last address register. Here, SAR and LAR are stored for each queue ID (queue number) for identifying the queue. Among these, SAR is address information (including bank information) indicating the head of the virtual storage address in which the frame data of the queue is written. LAR is address information (including bank information) indicating the end of the virtual storage address in which the frame data of the queue is written.

  The access history register (AAR) 33E records the virtual storage address (including bank information) at which the last write instruction or read instruction is recorded as AAR_1, and AAR_n is the value of AAR_ (n-1) when AAR_1 is updated. (N is an integer of 2 or more). That is, the history of the latest n write instructions or read instructions is displayed.

The work address register (TMPV, TMPL) 33F has a function of storing a work next write address TMPV (Temporary register for VAR) and a work queue final address TMPL (Temporary register for LAR) in common with each queue. Have.
Among these, TMPV is address information (including bank information) indicating the next write address VAR of the queue in which writing / reading was performed immediately before. TMPL is address information (including bank information) indicating a queue final address LAR immediately before (before update) the queue in which writing was last performed. These are used to temporarily hold address information because of the processing procedure of each data write / read operation, but may also be used for the next write / read operation.

  In response to a write instruction from the access arbitration unit 37, the write control unit 34 selects an optimal bank VAR based on the access history register (AAR) and VAR and UAR for each bank, and a virtual storage address (TMPV) A DRAM write instruction for designating frame data and designating frame data is output to the DRAM access unit 32.

The bank (VAR) is selected as follows, for example.
The write controller 34 uses AAR to manage which row address is activated in each bank.
Among the VAR row addresses of each bank, an activated one is selected. However, when both UAR and VAR of the corresponding bank correspond to the upper limit value of the memory capacity for each bank, the bank is not selected.

  For example, first, if there is a VAR in which both the bank number and the row address have the same value as AAR_1, the row address of that VAR is activated, so that VAR is selected. If both have a VAR having the same value as AAR_2, the row address of that VAR is activated, so that VAR is selected. However, if the bank number of AAR_2 is the same as the bank number of AAR_1, the row address of that VAR is not activated, so the VAR of that bank number is not selected.

  If not selected in the comparison up to AAR_2, if both the bank number and the row address have a VAR having the same value as AAR_3, the row address of that VAR is activated, so that VAR is selected. However, when the bank number of AAR_3 is the same as the bank number of AAR_1 or AAR_2, the row address of the VAR is not activated, so the VAR of that bank number is not selected.

Hereinafter, similarly, comparison is made up to AAR_n, and if there is a VAR having the same value in both the bank number and the row address, and that selection is possible, that VAR is selected. When comparing with AAR_n, if the bank number of AAR_n is the same as any one of AAR_1 to AAR_ (n-1), the row address of that VAR is not activated, so the VAR of that bank number is selected. do not do.
If the corresponding row address is activated and there is no selectable address, for example, a bank VAR not recorded in any AAR is selected, or a bank recorded in the AAR is selected. The VAR of the bank having the oldest remaining history is selected.

  In response to a read instruction from the access arbitration unit 37, the read control unit 35 reads out the head data from the read target queue that specifies the virtual storage address (SAR) based on the queue control information in the queue control memory 33. A function of outputting an instruction to read DRAM to the DRAM access unit 32 and a function of transferring data read from the read target queue via the DRAM access unit 32 to the demultiplexing device 20 together with a frame end flag and queue designation information. Have.

The queue use address number memory 36 is composed of, for example, a semiconductor memory such as an SRAM chip. For each queue, the queue use address number memory 36 stores a virtual address number NK used by the frame data stored in the queue, and the demultiplexer 20. And a function of outputting the number NK of virtual addresses in the designated queue in response to a request from the access arbitration unit 37.
FIG. 6 is a storage example of the queue use address number memory. Here, for each queue ID (queue number) for identifying a queue, the number NK of virtual addresses of the queue is stored.

  The access arbitration unit 37 receives the frame data transferred from the multiplexing device 10 and divides the frame data into a plurality of data D with a data size of one virtual address based on the frame length information added to the frame data. The function of calculating the number of times of writing by this, and writing to the write target queue designated by the queue designation information added to the frame data for each data D by the number of times of writing is instructed. A function of outputting a write instruction to the write control unit 34 and a function of adding the number of virtual addresses increased by writing the frame data to the number of virtual addresses NK of the write target queue in the queue use address number memory 36. Have.

  Further, in response to a read request from the demultiplexer 20, the access arbitration unit 37 divides the data amount specified by the read data amount information of the read request by the data size for one virtual address, thereby reducing the number of reads. A function for calculating, a function for outputting to the read control unit 35 a read instruction for instructing reading of frame data from the read target queue designated by the queue designation information of the read request, and the frame data Read out at a readable timing by arbitrating the conflict between the function of subtracting the number of virtual addresses decreased by reading from the number of virtual addresses NK of the write target queue in the queue use address number memory 36 and the writing of frame data. And a function of outputting instructions.

[DRAM access section]
Next, the DRAM access unit 32 used in the recording apparatus 30 according to the present embodiment will be described with reference to FIG. FIG. 7 is a block diagram showing the configuration of the DRAM access unit according to the first embodiment.
The DRAM access unit 32 includes a FIFO memory 32A, an activation processing unit 32B, an access type determination unit 32C, a DRAM writing unit 32D, and a DRAM reading unit 32E as main circuit units.

  The FIFO memory 32A is composed of a general FIFO memory. The FIFO memory 32A has a function of accumulating a DRAM write instruction from the write control unit 34 and a DRAM read instruction from the read control unit 35, and a row by the activation processing unit 32B. After the address activation is completed, it has a function of reading the stored DRAM write instruction or DRAM read instruction in the order of input and outputting it to the access type determination unit 32C. At this time, as information for determining the access type, information indicating whether it is a DRAM write instruction from the write control unit 34 or a DRAM read instruction from the read control unit 35 is combined with each instruction. The information may be written in the FIFO memory 32A and output to the access type determination unit 32C.

  When an access arbitration unit 37 shown in FIG. 16 to be described later is used, a DRAM write instruction from the write control unit 34 and a DRAM read instruction from the read control unit 35 should not be input at the same time. If these are input simultaneously, the writing of the DRAM write instruction to the FIFO memory 32A is prioritized and the writing of the DRAM read instruction to the FIFO memory 32A is made to wait.

  The activation processing unit 32B has a function of activating the write target row address when the write target row address is not activated when the DRAM write instruction is accumulated in the FIFO memory 32A. ing.

  Further, the activation processing unit 32B, when the DRAM read instruction is stored in the FIFO memory 32A, when the read target row address specified by the DRAM read instruction is not in the active state in the read target bank, When the read target row address is activated in the target bank and a row address different from the read target row address is active in the read target bank, the read target is activated in response to the completion of access to the row address. And a function of activating the row address.

  The access type determination unit 32C distributes the DRAM write instruction output from the FIFO memory 32A to the DRAM write unit 32D, and distributes the DRAM read instruction output from the FIFO memory 32A to the DRAM read unit 32E. It has a function to output.

  Based on the combination of the write target row address and the write target bank in the input DRAM write instruction, the DRAM writing unit 32D sends the frame data (data) specified by the DRAM write instruction to the specified column address. D) has a function of writing.

At this time, if a plurality of column addresses are required for writing frame data (data D) for one storage address, the burst mode, which is a function of the DRAM, is used to write to consecutive column addresses. The writing time can be shortened.
Further, when the EoF value (PN) is also written to the data memory 31, it may be performed simultaneously with the writing of the frame data.

  Based on the combination of the read target row address and the read target bank in the input DRAM read instruction, the DRAM read unit 32E generates frame data (data D) from the indicated column address among the read target row addresses of the read target bank. Is read out and output to the read control unit 35 together with the queue designation information.

At this time, when a plurality of column addresses are required for reading frame data (data D) for one virtual storage address, reading is performed from successive column addresses using the burst mode which is a function of the DRAM. The time required for reading can be shortened.
When the EoF value (PN) is written in the data memory 31, the EoF value may be read simultaneously with the reading of the frame data.

  The read EoF value may be output to the read control unit 35 together with the frame data and the queue designation information. When the EoF value is not written in the data memory 31, the EoF value is written in the address queue management memory (QM) 33B, and the read control unit 35 outputs this EoF value to the DRAM access unit 32 together with the queue designation information. The EoF value received via the access type determination unit 32C together with the frame data read from the data memory 31 by the DRAM reading unit 32E may be output to the read control unit 35.

[Operation of First Embodiment]
Next, the operation of the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described with reference to FIGS.
FIG. 8 is an explanatory diagram showing a write operation in the write control unit. FIG. 9 is an explanatory diagram showing a read operation in the read control unit.

[Write operation]
First, a writing operation in the writing control unit 34 of the recording device 30 will be described with reference to FIG.
The write control unit 34 executes the processing operation of FIG. 8 in response to a write instruction from the access arbitration unit 37. When new data is written to the write target queue, from the viewpoint of sharing the storage address of the data memory 31 by each queue, the main change in the queue control information is that the queue related to the write target queue before and after the write. The final address LAR, the subsequent virtual address ADD relating to the queue final address before writing, the next write address VAR (only in the selected bank VAR) common to each queue, and the access history register (AAR) change. . In the case of the first writing to the write target queue, the queue head address SAR regarding the write target queue also changes.

  For this reason, in the processing operation of FIG. 8, the write control unit 34 writes specified data to the next write address VAR of the selected bank (outputs a write instruction), and updates the queue final address LAR regarding the write target queue. The subsequent virtual address ADD related to the queue final address before writing is updated, and the next write address VAR (only in the selected bank) is updated for each queue. In the case of the first writing to the write target queue, the queue head address related to the write target queue is also updated. Details of these updates will be described later based on an operation example.

  At this time, the write control unit 34 accesses the queue control memory 33 to execute steps W1 to W7 shown in FIG. That is, in the order of LAR retention (W1), LAR, SAR update (W2), VAR retention (W3), ADD update (W4), VAR update (W5), PN update (W6), and data output (W7). Execute the process. Note that the processing order in FIG. 8 takes processing efficiency into consideration, but may be another processing order.

[Read operation]
Next, with reference to FIG. 9, the reading operation in the reading control unit 35 of the recording apparatus 30 will be described.
The read control unit 35 executes the processing operation of FIG. 9 in response to a read instruction from the access arbitration unit 37. When new data is read from the read target queue, from the viewpoint of sharing the storage address of the data memory 31 by each queue, the main change in the queue control information is the queue head address related to the read target queue before and after the read. SAR, the next write address VAR common to each queue (only the VAR of the read target bank), the subsequent virtual address ADD related to the new next write address VAR (only the VAR of the read target bank), and the access history register (AAR) ) And change.

  For this reason, in the processing operation of FIG. 9, the read control unit 35 reads the EoF (End of Frame: frame end flag) for the queue head address SAR related to the read target queue, updates the queue head address SAR related to the read target queue, The next write address VAR (only the VAR of the read target bank) common to the queue is updated, the subsequent virtual address ADD related to the read virtual storage address is updated, and a read instruction is output. Details of these updates will be described later based on an operation example.

  At this time, the read control unit 35 accesses the queue control memory 33 to execute steps R1 to R5 shown in FIG. That is, processing is executed in the order of EoF output (R1), VAR retention (R2), VAR update (R3), SAR update (R4), subsequent virtual address update (R5), and read instruction output. Note that the processing order in FIG. 9 takes processing efficiency into consideration, but other processing orders may be used.

[Operation example]
Next, referring to FIG. 10 to FIG. 13, for the frame data writing operation and reading operation in recording device 30, queue P2 is set as a read / write target queue, and data P2-3 is written to this queue P2. An example will be described in which the data P2-1 and P2-2 are read and the data P1-4 are written.

  FIG. 10 is an explanatory diagram showing queue control information immediately before reading data P2-1 (immediately after writing data P2-3). Here, queue control information immediately before reading data P2-1, that is, immediately after writing data P2-3 is shown. In this state, the data P1-1, P1-2, and P1-3 of the queue P1 are written in the virtual storage addresses “0, 1, 4” of the bank 0 in the virtual data memory, and the virtual storage of the bank 0 is performed. Data P2-1, P2-2, and P2-3 of the queue P2 are written at the address "2, 3, 5". Further, the virtual storage address “6 to N” of bank 0 and bank 1 are unused.

Therefore, the next write address VAR of bank 0 is “6”, and the unwritten address UAR of bank 0 is also “6”. Further, the subsequent virtual address ADD relating to the virtual storage address “0, 1” of the bank 0 becomes “1, 4” of the bank 0 according to the order of the data P1-1, P1-2, and P1-3 of the queue P1. In accordance with the order of the data P2-1, P2-2, and P2-3 in the queue P2, the subsequent virtual address ADD related to the virtual storage address “2, 3” in the bank 0 is “3, 5” in the bank 0. . Note that the pointer PN of the virtual storage address “0, 2” of the bank 0 is “0”, and it can be seen that the data P1-1 and P2-1 do not include the end of the frame.
Note that the next write address VAR and the unwritten address UAR of the bank 1 are both the initial value 0. Nothing is stored in the ADD and PN of the bank 1.

  Further, the queue head address SAR of the queue P1 indicates the virtual storage address “bank 0 0” of the data P1-1, and the queue end address LAR indicates the virtual storage address “bank 0 4” of the data P1-3. ing. Further, the queue head address SAR of the queue P2 indicates the virtual storage address “bank 0-2” of the data P2-1, and the queue end address LAR indicates the virtual storage address “bank 0 of 5” of the data P2-3. ing. In addition, “bank 0-5” and “bank 0-3” are stored in the work next write address TMPV and work queue final address TMPL, respectively.

  In the state shown in FIG. 10, when the data P2-1 of the queue P2 is read, the queue control information changes as shown in FIG. FIG. 11 is an explanatory diagram showing changes in queue control information when reading data P2-1.

  First, since the data P2-1 is read from the read target virtual address “bank 0-2” indicated by the queue head address SAR regarding the queue P2, the data D of the read target virtual address “bank 0-2” becomes empty, and the queue There are two data relating to P2, P2-2 and P2-3. As a result, P2-2 becomes the head data of the queue P2, and the queue head position changes from the virtual storage address “bank 0-2” to “bank 0-3”, so the queue head address SAR regarding the queue P2 is “bank 0”. No. 2 ”is updated to“ Bank 0 3 ”.

  Further, since the data D of the read target virtual address “bank 0-2” is in an empty state, the virtual storage address “bank 0-2” becomes the write position of the next data for bank 0. As a result, the next write address VAR for bank 0 is updated from “6” to “2”. Accordingly, in order to maintain the order relationship between the old write address VAR “6” (for bank 0) and the new write address VAR “2” (for bank 0), the virtual storage address “bank” The subsequent virtual address ADD of “2 of 0” is updated from “3 of bank 0” to “6 of bank 0”. As a result, “bank 0-6” and “bank 0-3” are stored in the work next write address TMPV and work queue final address TMPL, respectively.

  When the data P2-2 in the queue P2 is read in the state shown in FIG. 11, the queue control information changes as shown in FIG. FIG. 12 is an explanatory diagram showing changes in the queue control information when reading data P2-2.

  First, since the data P2-2 is read from the read target virtual address “bank 0-3” indicated by the queue head address SAR relating to the queue P2, the data D of the read target virtual address “bank 0 3” becomes empty, and the queue Data relating to P2 is one of P2-3. As a result, P2-3 becomes the head data of the queue P2, and the queue head position changes from the virtual storage address “bank 0-3” to “bank 0-5”, so the queue head address SAR regarding the queue P2 is “bank 0”. No. 3 ”is updated to“ Bank 0 5 ”.

  Further, since the data D of the read target virtual address “Bank 0-3” is in an empty state, the virtual storage address “Bank 0-3” becomes the write position of the next data for Bank 0. As a result, the next write address VAR for bank 0 is updated from “2” to “3”. Accordingly, in order to maintain the order relationship between the old write address VAR “2” (for bank 0) and the new write address VAR “3” (for bank 0), the virtual storage address “bank” The subsequent virtual address ADD of “3 of 0” is updated from “5 of bank 0” to “2 of bank 0”. As a result, “bank 0-2” and “bank 0-3” are stored in the work next write address TMPV and work queue final address TMPL, respectively.

  When the data P1-4 of the queue P1 is written in the state shown in FIG. 12, the queue control information changes as shown in FIG. FIG. 13 is an explanatory diagram showing a change in queue control information when data P1-4 is written.

First, select a bank. The virtual addresses recorded in the AAR are only 0 to 5 of the bank 0. In this case, the activated bank is only the bank 0, and the activated row address is the row of the VAR of the bank 0. Matches the address. Therefore, the bank 0 may be selected for writing, but another bank (bank 1) is selected here in consideration of the fact that the immediately preceding access is read.
In this case, the reason why the bank 0 is not selected is that due to the specifications of the DRAM, a waiting time occurs when writing to the same bank after reading, and the effective throughput is reduced.

  Since the data P1-4 is written to the write target virtual address “0” indicated by the next write address VAR of the bank 1, the P1-4 becomes the new final data of the queue P1, and the queue final position is the virtual storage address “bank Since the value changes from “4 of 0” to “0 of bank 1”, the queue final address LAR of the queue P1 is updated from “4 of bank 0” to “0 of bank 1”.

  Also, since P1-4 follows P1-3 that was the last queue data before writing, the virtual storage address of P2-4 is the subsequent virtual address of the virtual storage address “Bank 0-4” of P1-3. The storage address “0 of bank 1” is set. Further, since P1-4 is written to the next write address VAR (for bank 1) before writing, the next write address VAR of bank 1 is updated from “0” to “1”. Note that the UAR of the bank 1 is also updated from “0” to “1”, and the VAR and UAR of the bank 0 are not updated. Thus, “0 in bank 1” and “4 in bank 0” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

[DRAM write operation]
Next, a DRAM write operation in the DRAM access unit 32 according to the present embodiment will be described with reference to FIG. FIG. 14 is a flowchart showing the DRAM writing process.
The DRAM access unit 32 executes the DRAM write process of FIG. 14 in response to a DRAM write instruction from the write control unit 34.

  First, the activation processing unit 32B confirms whether or not the write target row address designated by the DRAM write instruction stored in the FIFO memory 32A is in an activated state (step 100), and the write target row address is activated. If not in the activated state (step 100: NO), the write target row address is activated (step 101), and the activation process is completed. If the write target row address is in the activated state (step 100: YES), the activation process is completed without doing anything.

After completing the activation processing in the activation processing unit 32B, the DRAM write instruction is output from the FIFO memory 32A and input to the DRAM writing unit 32D via the access type determination unit 32C.
In response to this, the DRAM writing unit 32D writes the frame data (data D) specified by the DRAM write instruction to the column address corresponding to the input DRAM write instruction (step 102), and then a series of The DRAM writing process is terminated.

  In this embodiment, when writing frame data to the DRAM constituting the data memory 31, the write control unit 34 writes a bank whose write target row address is in an activated state from among the banks of the DRAM. Is preferentially selected as a bank to be included. This reduces the probability that writing to different row addresses in the same bank will occur. For this reason, the number of times of waiting for the activation of the row address at the time of writing the frame data and the completion of the access to the different row address is reduced, and the decrease in the effective throughput of the DRAM access is suppressed.

[DRAM read operation]
Next, with reference to FIG. 15, a DRAM read operation in the DRAM access unit 32 according to the present embodiment will be described. FIG. 15 is a flowchart showing DRAM read processing.
The DRAM access unit 32 executes the DRAM read processing of FIG. 15 in response to a DRAM read instruction from the read control unit 35.

  First, the activation processing unit 32B confirms whether or not the read target row address is in an activated state in the read target bank specified by the DRAM read instruction stored in the FIFO memory 32A (step 110), and reads the read target row address. Is in the activated state (step 110: YES), the activation process is completed without doing anything.

After completing the activation process in the activation processing unit 32B, a DRAM read instruction is output from the FIFO memory 32A and input to the DRAM read unit 32E via the access type determination unit 32C.
In response, DRAM read unit 32E reads frame data (data D) from the designated column address among the read target row addresses of the read target bank corresponding to the input DRAM read instruction (step 114). ), The DRAM reading process is terminated.

When the read target row address of the read target bank is not in the activated state (step 110: NO), the activation processing unit 32B confirms whether a different row address is in the activated state in the read target bank (step 111). ).
Here, if a different row address is not in the activated state (step 111: NO), the activation processing unit 32B activates the read target row address of the read target bank (step 113) and completes the activation process. As a result, the DRAM reading unit 32E performs reading from the activated read target row address.

  If a different row address is in an activated state (step 111: YES), the activation processing unit 32B waits until the access to the different row address is completed (step 112), and then proceeds to step 113. The read target row address is activated as described above.

  As described above, when reading frame data from the DRAM constituting the data memory 31, since the frame data to be read is written in a specific bank, the row address is in an activated state as in writing. You cannot select a bank. Therefore, a waiting time occurs when reading from different row addresses in the same bank or reading from the same bank after writing. For reading from different row addresses in the same bank, a processing interval may be provided so that, for example, writing is inserted between the two row addresses so that reading from different row addresses does not continue.

[Effect of the first embodiment]
As described above, according to the present embodiment, in the recording apparatus 30, when the data memory 31 is composed of a DRAM having a write pointer for each bank and frame data is written to the write target queue, it corresponds to the write pointer in the bank. If the bank in which the write target row address to be activated is selected as the write target bank and the frame data is written, and there is no bank in which the write target row address is in the active state, the write The frame data is written after the bank in which the target row address is inactivated is selected as the write target bank and the write target row address is activated.

  In general, in a DRAM, when writing data to an arbitrary row address of an arbitrary bank, it is necessary to activate the row address in the bank. When accessing a different row address of the same bank, the row address is Since it is necessary to activate a new row address after waiting for the used access to be completed, a relatively large waiting time occurs due to the activation of the row address in accessing the same bank. Specifically, this is a case where accesses to different row addresses in the same bank are continuous. As other conditions for waiting time, there are a case where writing is performed in the same bank after reading and a case where reading is performed from the same bank after writing.

According to the present embodiment, when writing frame data to the DRAM constituting the data memory 31, the bank in which the write target row address is activated is preferentially set as the write target bank among the banks of the DRAM. Selected.
This can reduce the probability of writing to different row addresses in the same bank. Therefore, it is possible to reduce the number of times of waiting for the activation of the row address at the time of writing the frame data and the completion of the access to the different row address, and it is possible to suppress the decrease in the effective throughput related to the DRAM access.

  In the present embodiment, the recording device 30 stores, for each virtual storage address, a subsequent address indicating a virtual storage address of communication data subsequent to the communication data written to the virtual storage address, and for each queue, Stores the queue head address and queue end address indicating the beginning and end of the virtual storage address where the communication data of the queue is written, and the next indicates the virtual storage address where the communication data is to be written next in common for each queue. The write address may be stored for each bank.

  In addition to this, when the write control unit 34 writes communication data to the write target queue (performs a write instruction), the communication control unit 34 writes the communication data to the write target virtual address composed of the next write address of the selected bank. Write, the queue final address of the write target queue, the subsequent virtual address related to the queue final address before writing, and the next write address of the selected bank are updated, and the read control unit 35 communicates from the read target queue. When reading data (performing a read instruction), the communication data is read from a read target virtual address (including bank information) consisting of the queue start address of the read target queue, and the queue start address of the read target queue and the read target bank Next write address and subsequent virtual address related to new next write address (for read target bank) Vinegar may be updated, respectively.

  As a result, the frame data of each queue is sequentially written to the virtual storage address in the free state, and the virtual storage address from which the frame data has been read out is managed again as a free state. Further, the virtual storage address of the frame data is managed in the order of writing for each queue. A virtual storage address in an empty state can be shared by a plurality of queues, and the use efficiency of the memory can be improved as compared with a case where a fixed address range is secured in advance for each conventional queue. It becomes possible. For this reason, it is not necessary to increase the memory capacity, and as a result, an increase in circuit scale and cost can be suppressed.

In addition, this embodiment has a feature that it is not necessary to set an initial value such as an ADD value in the QM. In the present embodiment, only the VAR, UAR, and AAR need to set initial values when the communication input / output device is activated (see “Initialization” in FIG. 8). Therefore, the scale of the circuit for performing the initial setting or the scale of the software for performing the initial setting is extremely small, and the time required for the initial setting is extremely small.
8 and the like illustrate the case where the PN for storing the EoF value is mounted in the QM, but the PN can also be mounted in the DRAM.

[Second Embodiment]
Next, a communication input / output device 1 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 16 is a block diagram illustrating a configuration of an access arbitration unit according to the second embodiment.

  In the communication input / output device 1 according to the first embodiment, when the virtual storage address of the virtual data memory is shared by a plurality of queues, for example, a large amount of frame data related to a specific output system is input. In this case, the virtual storage address of the virtual data memory may be occupied by the queue of the output system. Such occupation of the storage address is not limited to the first embodiment, and can occur in any configuration as long as the storage address is shared by a plurality of queues. Therefore, when such a storage address occupancy occurs, the queues of other output systems cannot use a sufficient number of storage addresses, frame data is easily discarded, and communication quality deteriorates.

  The purpose of this embodiment is to avoid occupying a storage address by a specific queue when the storage address is shared by a plurality of queues. In the recording apparatus 30, the access arbitration unit 37 has a write target queue. When the frame data is written in (instructed to write), the necessary address number indicating the number of virtual storage addresses required for writing is calculated based on the data length of the frame data and obtained from the queue use address number memory 36 Based on the number of virtual addresses used in the write target queue or each queue, the number of remaining virtual addresses indicating the number of virtual storage addresses that can be used for the write is calculated, and the required number of addresses and the number of remaining virtual addresses are compared. To determine whether or not the frame data can be written, and in accordance with the determination of whether or not writing is possible, the write control unit It is obtained so as to direct the writing of the frame data to 4.

  As shown in FIG. 16, in this embodiment, the access arbitration unit 37 includes, as main circuit units, a write enable / disable determination unit 37A, a write FIFO 37B, a read reception unit 37C, a read FIFO 37D, and a priority control unit. 37E, a queue use address number updating unit 37F, and an instruction output unit 37G are provided.

  The write enable / disable determining unit 37A includes queue designation information and frame length information added to the frame data transferred from the multiplexing device 10, determination address number information set in advance for each queue, and information on each queue. Based on the number of used virtual addresses, the function determines whether or not writing is possible, and the frame data corresponding to one virtual address of the storage area provided in the data memory 31 according to the determination result of writing And a write instruction in which queue designation information is added to the obtained data, respectively, is written to the write FIFO 37B.

The determination address number information includes the maximum number of virtual addresses NKmax that can be used in the write target queue specified by the queue specification information, and the minimum guaranteed virtual address number that is guaranteed to be used for the write target queue. NKmin.
FIG. 17 is a configuration example of the determination address number information. Here, a maximum virtual address number NKmax and a minimum guaranteed virtual address number NKmin are set for each queue ID for identifying a queue. The determination address number information is stored in, for example, the queue use address number update unit 37F or the internal memory (not shown) of the access arbitration unit 37.

  The read accepting unit 37C calculates the number of reads to the data memory 31 based on the read data amount information of the read request output from the demultiplexer 20, and uses the queue designation information of the read request as a read instruction for the number of times of reading. It has a function of writing to the reading FIFO 37D. In this calculation, a value obtained by dividing the data amount indicated by the read data amount information by the data size per virtual address of the data memory 31 is used as the number of readings, and if there is a remainder, 1 may be added to the number of readings.

  The priority control unit 37E reads the write instruction or the read instruction from the write FIFO 37B or the read FIFO 37D and outputs it to the queue use address number update unit 37F, and both the write FIFO 37B and the read FIFO 37D In the case where there are a write instruction and a read instruction, it has a function of preferentially reading the write instruction from the write FIFO 37B.

  When a write instruction is input from the priority control unit 37E, the queue use address number update unit 37F in the queue use address number memory 36 uses the write target queue use virtual address corresponding to the queue designation information of the write instruction. 1 is added to the number, and when the read instruction is input from the priority control unit 37E, and the function of outputting the write instruction to the instruction output unit 37G, the queue designation of the read instruction in the queue use address number memory 36 It has a function of subtracting 1 from the number of virtual addresses used in the read target queue corresponding to the information and outputting the read instruction to the instruction output unit 37G.

  The instruction output unit 37G has a function of outputting the write instruction to the write control unit 34 when a write instruction is input from the queue use address number updating unit 37F, and a read instruction when the read instruction is input. Is output to the read control unit 35.

[Operation of Second Embodiment]
Next, with reference to FIG. 18, a write determination operation at the time of writing frame data will be described as an operation of the access arbitration unit 37 according to the present embodiment. FIG. 18 is a flowchart illustrating the write permission / inhibition determination process according to the second embodiment.
The access arbitration unit 37 of the recording device 30 determines whether or not writing is possible for each frame data transferred from the multiplexing device 10 based on the writeability determination processing of FIG.

  First, the access arbitration unit 37 acquires the used virtual address number NK for all the queues from the queue used address number memory 36 (Step 200), and calculates the total virtual address number NKA used by all the queues (Step 201). ) The required virtual address number NF required for writing the target frame data to be written is calculated (step 202).

Thereafter, by subtracting NKA from the total address number NA of the virtual storage addresses of the virtual data memory, the remaining virtual address number NR indicating the number of virtual storage addresses that can be used for writing the target frame data is calculated (step 203). ), NF and NR are compared (step 204).
Here, when NF> NR (step 204: YES), the access arbitration unit 37 determines that writing is not possible, discards the target frame data (step 213), and terminates the write determination processing for the target frame data. To do.

On the other hand, when NF ≦ NR (step 204: NO), the access arbitration unit 37 acquires the maximum virtual address number NKmax of the designated write target queue from the queue use address number memory 36 or the like (step 205), The number of remaining virtual addresses NR is calculated by subtracting NK from NKmax (step 206), and NF and NR are compared (step 207).
Here, when NF> NR (step 207: YES), the access arbitration unit 37 determines that writing is not possible, discards the target frame data (step 213), and finishes the write determination process for the target frame data. To do.

  On the other hand, when NF ≦ NR (step 207: NO), the access arbitration unit 37 acquires the minimum guaranteed virtual address number NKmin for all the queues from the queue use address number memory 36 (step 208), and collects all the queues at once. The total guaranteed virtual address number NAmin to be guaranteed at least is calculated (step 209). At this time, if the queue use virtual address number NK of an arbitrary queue is equal to or greater than the minimum guaranteed virtual address number, the queue use virtual address number NK is added as the guaranteed virtual address number of the queue, and the queue use virtual address number NK Is less than the minimum guaranteed virtual address number, the minimum guaranteed virtual address number NKmin is added as the guaranteed virtual address number of the queue.

Thereafter, the access arbitration unit 37 calculates the remaining virtual address number NR by subtracting NAmin from NA (step 210), and compares NF and NR (step 211).
Here, if NF> NR (step 211: YES), the access arbitration unit 37 determines that writing is not possible, discards the target frame data (step 213), and ends the write determination processing for the target frame data. To do.

On the other hand, if NF ≦ NR (step 211: NO), the access arbitration unit 37 determines that the target frame data can be written (step 212), and ends the write determination process for the target frame data.
Thereafter, the access arbitration unit 37 divides the target frame data into data sizes corresponding to one virtual address according to the determination of whether or not writing is possible, and issues a write instruction in which queue designation information is added to the obtained data. The data is written to the write FIFO 37B.

[Effect of the second embodiment]
As described above, according to the present embodiment, in the recording device 30, the queue use address number memory 36 stores the use address number indicating the number of virtual storage addresses used by the queue for each queue. When the unit 37 writes communication data to the write target queue (instructs writing), the unit 37 calculates the necessary number of addresses indicating the number of virtual storage addresses required for writing based on the data length of the communication data, Based on the number of virtual addresses used for the write target queue or each queue acquired from the used address number memory 36, the number of remaining virtual addresses indicating the number of virtual storage addresses that can be used for the write is calculated, and the required number of addresses Is compared with the number of remaining virtual addresses to determine whether or not the communication data can be written, and written according to the determination of whether or not writing is possible. It is obtained so as to direct the writing of the communication data to the control unit 34.

  Therefore, since the number of virtual storage addresses used by each queue is limited, occupation of the virtual storage address by a queue corresponding to an arbitrary output system can be suppressed. For this reason, even when a large amount of frame data related to a specific output system is input, it is possible for the queues of other output systems to use a sufficient number of virtual storage addresses. As a result, it becomes possible to suppress the discarding of frame data and the deterioration of communication quality due to this, and as a countermeasure, it is not necessary to increase the memory capacity, and as a result, the increase in circuit scale and cost is suppressed Is possible.

Note that NKA and NAmin in this embodiment can be calculated (added, subtracted, etc.) at the same time when the queue use address number memory 36 is updated.
In the present embodiment, when the access arbitration unit 37 having the configuration shown in FIG. 16 is used, there is a possibility that it is erroneously determined that writing is possible if write instruction data exists in the write FIFO 37B. In order to prevent erroneous determination, whether to use a value obtained by adding the number of virtual addresses in the write FIFO 37B (the number of write instructions) to the information in the queue used address number memory 36 as the used virtual address number of each queue. , NA or NKmax may be a value obtained by subtracting the number of virtual addresses (the number of write instructions) in the write FIFO 37B.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

In each of the above embodiments, when the communication input / output device 1 processes a multicast frame, a multicast output system is provided as one of the output systems, and a plurality of multicast frames are provided in the distribution unit 22 in the demultiplexer 20. It is also possible to provide a means for outputting to the speed converter 23 and to allocate a part of the queues logically formed in the data memory 31 of the recording device 30 as a queue corresponding to this multicast output system.
As a result, the multicast frame input from the outside to the multiplexing device 10 is temporarily stored in a queue corresponding to the multicast output system in the data memory 31, and the multicast frame is read from the queue by the demultiplexing device 20. Output from multiple output ports.

  DESCRIPTION OF SYMBOLS 1 ... Communication input / output device, 10 ... Multiplexer, 11 ... Queue designation information addition part, 12 ... Multiplexing part, 20 ... Demultiplexing device, 21 ... Reading part, 22 ... Distribution part, 23, 24 ... Speed Conversion unit, 30 ... recording device, 31 ... data memory, 32 ... DRAM access unit, 32A ... FIFO memory, 32B ... activation processing unit, 32C ... access type determination unit, 32D ... DRAM writing unit, 32E ... DRAM reading unit 33 ... Queue control memory, 34 ... Write control unit, 35 ... Read control unit, 36 ... Queue use address number memory, 37 ... Access arbitration unit, 37A ... Write enable / disable judgment unit, 37B ... Write FIFO, 37C ... Read accepting unit, 37D ... Reading FIFO, 37E ... Priority control unit, 37F ... Queue usage address number updating unit, 37G ... Instruction output unit.

Claims (3)

A multiplexing device that multiplexes by adding queue designation information indicating a queue corresponding to an output system to which the communication data is to be output, and the communication data transferred from the multiplexing device. Corresponding to a recording device for temporarily storing in a queue to be written designated by the queue designation information among a plurality of queues logically formed in the data memory, and an output system selected based on the priority control logic among the queues A communication input / output device comprising: a demultiplexer that reads the communication data from the read target queue and converts the communication data into a communication speed of an output port corresponding to the output system;
The recording device comprises:
The data memory, which comprises a DRAM having a write pointer for each bank, stores communication data of the queue,
When writing the communication data to the write target queue, the bank in which the write target row address corresponding to the write pointer is activated among the banks is selected as the write target bank, and the communication data is written. If there is no bank in which the write target row address is in the activated state, the bank in which the write target row address is in the inactive state is selected as the write target bank and the write target row address is activated. And a DRAM access unit for writing the communication data after the communication input / output device. The communication input / output device according to claim 1,
The recording device comprises:
A queue control memory for storing queue control information used when controlling writing / reading to / from the queue of the data memory;
A write control unit that instructs the DRAM access unit to write the communication data transferred from the multiplexing device to the write target queue based on queue control information in the queue control memory;
A read control unit that instructs the DRAM access unit to read communication data from the read target queue based on queue control information in the queue control memory, and transfers the read communication data to the demultiplexer; ,
The queue control memory stores a subsequent address indicating a virtual storage address of communication data subsequent to the communication data written to the virtual storage address for each virtual storage address used on the virtual data memory, and for each queue Storing a queue head address and a queue last address indicating the head and end of the virtual storage address in which the communication data of the queue is written, and storing the communication data next in common for each of the queues The next write address indicating the address is stored for each bank,
When the write control unit writes the communication data to the write target queue, the write control unit writes the communication data to the write target virtual address including the next write address of the bank selected as the write target bank. Instruct the access unit to update the queue final address of the write target queue, the subsequent address related to the queue final address before writing, and the next write address of the bank selected as the write target bank,
When reading the communication data from the read target queue, the read control unit instructs the DRAM access unit to read the communication data for the read target virtual address consisting of the queue head address of the read target queue, and And a subsequent address related to the next write address of the new bank to be read and the next write address of the bank to be read are updated respectively. The communication input / output device according to claim 2 ,
The recording device comprises:
A queue use address number memory for storing a use address number indicating the number of virtual storage addresses on the virtual data memory used by the queue for each queue;
When writing the communication data to the write target queue, the necessary address number indicating the number of virtual storage addresses required for writing is calculated based on the data length of the communication data, and obtained from the queue use address number memory By calculating the number of remaining addresses indicating the number of virtual storage addresses that can be used for the writing based on the number of addresses used in the writing target queue or the queue, and comparing the number of necessary addresses with the number of remaining addresses An access arbitration unit that determines whether or not the communication data can be written, and instructs the write control unit to write the communication data in response to the determination of whether or not the communication data can be written. Output device.

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