JP2016158024A - Communication input / output device - Google Patents

Abstract

An object of the present invention is to increase the use efficiency of a data memory by a plurality of queues. When write control unit 33 writes communication data to a write target queue, the write control unit 33 writes the communication data to a write target address consisting of a next write address, the queue final address of the write target queue, When the read control unit 34 reads the communication data from the read target queue, the subsequent address and the next write address related to the queue final address before loading are updated, respectively. The communication data is read, and the queue head address, the next write address, and the subsequent address relating to the new next write address of the read target queue are updated. [Selection] Figure 1

Description

  The present invention relates to a data communication technique, and more particularly to a memory access control technique used in a communication input / output device that inputs and outputs communication data (frame data).

Conventionally, for example, a configuration as disclosed in Patent Document 1 has been proposed as a communication input / output device that is used in data communication such as the Internet to input / output communication data such as Ethernet (registered trademark) frame data. ing. FIG. 19 is a block diagram showing a configuration of a conventional communication input / output device (built-in memory).
This communication input / output device includes a multiplexing device MUX, a recording device MEM, and a demultiplexing device DEMUX.

The MUX adds the queue designation information corresponding to the output destination of the frame data to the input frame data by the queue designation information addition section provided for each input port, and then multiplexes it by the multiplexing section. Output.
The MEM receives the frame data output from the MUX by time division multiplexing by the write control unit, refers to the queue designation information and the queue map added to each frame data, and stores in the built-in data memory (DRAM chip). Among the queues logically provided for each frame data output destination, the frame data is written to the queue address corresponding to the queue designation information. Further, in response to a read instruction from the DEMUX, the MEM reads frame data from the corresponding queue by the read control unit and outputs the frame data to the DEMUX.

  The DEMUX reads out the frame data from the output destination queue corresponding to the priority output port in the MEM based on the priority control logic for each output port by the reading unit, and distributes the frame data to the corresponding output port by the distribution unit. The data is converted into the communication speed of the output port by a speed conversion unit provided for each output.

  FIG. 20 is an explanatory diagram showing the correspondence between queues and output ports, and shows the case where the number of output ports is three. In FIG. 20A, queues and output ports are associated one-to-one, but as illustrated in FIG. 20B, one frame data is associated with a plurality of output ports. Can be handled when Further, as shown in FIG. 20C, a queue corresponding to the read priority can be associated with each output port.

JP 2011-0101095 A

However, such a conventional technique has individual queues corresponding to the respective output ports, and the address range of these queues is fixedly determined by dividing the address of the data memory. The address range is different, and multiple queues cannot share the address range.
Therefore, since the address range in the data memory cannot be shared by a plurality of queues, it is necessary to secure a fixed storage capacity for each queue, and the use efficiency of the data memory is low. There was a problem. In addition, even if an address can be shared by multiple queues, it is possible that any particular queue may occupy an address if it is simply shared. In this case, the efficiency of using data memory is reduced. was there.

  An object of the present invention is to solve such a problem, and an object of the present invention is to provide a memory access control technique capable of improving the use efficiency of a data memory by a plurality of queues.

  In order to achieve such an object, the communication input / output device according to the present invention adds queue designation information indicating a queue corresponding to an output system to which the communication data is to be output to communication data that is sequentially input. And the communication data transferred from the multiplexing device are temporarily stored in a write target queue designated by the queue designation information among a plurality of queues logically formed in a data memory. Multiplex that reads out the communication data from the queue to be read corresponding to the output system selected from the queue and the output system selected based on the priority control logic from the queue, converts it to the communication speed of the output port corresponding to the output system, and outputs it A communication input / output device comprising a separation device, wherein the recording device controls writing / reading to / from the queue of the data memory. A queue control memory that stores the queue control information, a write control unit that writes the communication data transferred from the multiplexing device to the write target queue based on the queue control information of the queue control memory, and A read control unit that reads communication data from the read target queue and transfers the communication data to the demultiplexing device based on the queue control information of the queue control memory, the queue control memory for each storage address of the data memory, A subsequent address indicating a storage address of communication data subsequent to the communication data written to the storage address is stored, and a queue indicating the start and end of the storage address where the communication data of the queue is written for each queue Stores the start address and queue end address, and then communicates in common with each queue. The write control unit stores a next write address indicating a storage address to which data is to be written, and when the write control unit writes the communication data to the write target queue, the write control unit Write communication data, update the queue final address of the write target queue, the subsequent address related to the queue final address before writing, and the next write address, respectively, and the read control unit reads the communication data from the read target queue Is read from the read target address consisting of the queue start address of the read target queue, and the subsequent address related to the queue start address, the next write address, and the new next write address of the read target queue, respectively. It is to be updated.

  Also, in one configuration example of the communication input / output device according to the present invention, for each of the queues, the recording device has a number of used addresses indicating the number of storage addresses on the data memory used by the queue. When writing the communication data to the queue use address number memory to be stored and the write target queue, the necessary address number indicating the number of storage addresses required for writing is calculated based on the data length of the communication data, Based on the number of used addresses of the target queue or each queue acquired from the queue used address number memory, the number of remaining addresses indicating the number of storage addresses that can be used for the writing is calculated, and the required number of addresses and the remaining number of addresses are calculated. By comparing the number of addresses, it is determined whether or not the communication data can be written, and the write control unit Further comprising an access arbitration unit for instructing the writing of the communication data.

  Further, another communication input / output device according to the present invention multiplexes by adding queue designation information indicating a queue corresponding to an output system to which the communication data is output to communication data that is sequentially input and multiplexing the communication data. A recording device that temporarily stores the communication data transferred from the multiplexing device in a write target queue designated by the queue designation information among a plurality of queues logically formed in a data memory; A communication device comprising: a demultiplexer that reads out the communication data from a read target queue corresponding to an output system selected based on a priority control logic in the queue, converts the communication data to a communication speed of an output port corresponding to the output system, and outputs the communication data For each queue, the recording device uses a usage address indicating the number of storage addresses on the data memory used by the queue. When the communication data is written to the write target queue and the queue use address number memory for storing the number of addresses, the necessary address number indicating the number of storage addresses required for writing is calculated based on the data length of the communication data. Then, based on the number of used addresses of the write target queue or each queue acquired from the queue used address number memory, the number of remaining addresses indicating the number of storage addresses that can be used for the write is calculated, and the required number of addresses An access arbitration unit that determines whether or not the communication data can be written by comparing the remaining address number with the number of remaining addresses, and instructs the write control unit to write the communication data according to the determination of whether or not writing is possible It has.

  Further, in the configuration example of the communication input / output device according to the present invention, the access arbitration unit subtracts the used address number of each queue from the total address number of the storage addresses included in the data memory. The number of remaining addresses is calculated.

  Further, in the configuration example of the communication input / output device according to the present invention, the access arbitration unit starts from a maximum number of addresses indicating the number of usable storage addresses allocated in advance to the write target queue. The number of remaining addresses is calculated by subtracting the number of used addresses of the write target queue.

  In addition, according to an example of the configuration of the communication input / output device according to the present invention, the access arbitration unit guarantees a minimum guarantee in advance for each queue from the total number of storage addresses of the data memory. The number of remaining addresses is calculated by subtracting the addresses.

  According to the present invention, in a recording device for temporarily storing communication data transferred from a multiplexing device in a write target queue designated by queue designation information among a plurality of queues logically formed in a data memory, The use efficiency of the data memory can be increased. For this reason, it is not necessary to increase the memory capacity, and as a result, an increase in circuit scale and cost can be suppressed.

1 is a block diagram illustrating a configuration of a communication input / output device according to a first embodiment. FIG. 1 is a block diagram illustrating a configuration of a recording apparatus according to a first embodiment. It is a storage example of a data memory. It is a storage example of an address queue management memory. This is a storage example of a queue head / end address memory. It is a storage example of a queue use address number memory. It is explanatory drawing which shows the write-in operation | movement in a write-control part. It is explanatory drawing which shows the read-out operation | movement in a read-out control part. It is explanatory drawing which shows the queue control information immediately before data P2-1 reading (immediately after writing data P2-3). It is explanatory drawing which shows the change of the queue control information at the time of data P2-1 reading. It is explanatory drawing which shows the queue control information immediately after reading data P2-1 (just before reading data P2-2). It is explanatory drawing which shows the change of the queue control information at the time of data P2-2 reading. It is explanatory drawing which shows the queue control information immediately after reading data P2-2 (just before writing data P2-4). It is explanatory drawing which shows the change of the queue control information at the time of data P2-4 writing. It is explanatory drawing which shows the queue control information immediately after data P2-4 writing. It is a block diagram which shows the structure of the access arbitration part concerning 2nd Embodiment. It is an example of a structure of the address number information for determination. It is a flowchart which shows the writability determination processing concerning 2nd Embodiment. It is a block diagram which shows the structure of the conventional input / output device for communication (built-in memory). It is explanatory drawing which shows a response | compatibility with a queue and an output port.

Next, embodiments of the present invention will be described with reference to the drawings.
[First Embodiment]
First, a communication input / output device 1 according to a first embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram illustrating a configuration of the communication input / output device according to the first embodiment.

  The communication input / output device 1 is a communication input / output device for inputting / outputting communication data such as Ethernet (registered trademark) frame data, which is used in Internet communication or the like. The communication data input from the port is separated for each output system to which the communication data is to be output, converted to the communication speed of the output port corresponding to the output system, and output.

  As shown in FIG. 1, the communication input / output device 1 includes a multiplexer (MUX) 10, a demultiplexer (DEMUX) 20 with a built-in memory access control function, and a recording device (MEM) with a built-in access control function. 30. In the following, a case where communication data input / output by the communication input / output device 1 is frame data will be described as an example. However, the present invention is not limited to this, and various types of communication data such as packets and ATM cells are converted into frame data. It is also possible to input / output in the same manner as in FIG.

The multiplexing device 10 has a function of multiplexing the frame data sequentially input from the outside by adding queue designation information corresponding to the output system to which the frame data is to be output.
The recording device 30 writes the frame data transferred from the multiplexing device 10 into a write target designated by the queue designation information added to the frame data among a plurality of queues logically formed in the data memory. It has a function to temporarily store in a queue.
The demultiplexer 20 reads the frame data temporarily stored in the read target queue from the read target queue corresponding to the output system selected based on the priority control among the queues in the recording device 30, and corresponds to the output system. It has a function of converting and outputting the communication speed of the output port.

  In the present embodiment, in the storage device 30, the queue control memory 32 stores a subsequent address indicating a storage address of communication data subsequent to the communication data written to the storage address for each storage address of the data memory 31. For each queue, the queue start address and queue end address indicating the start and end of the storage address where the communication data of the queue is written are stored, and the storage address where the communication data is to be written next is common to each queue. Is stored.

  Further, when the write control unit 33 writes communication data to the write target queue, the communication control unit 33 writes the communication data to the write target address consisting of the next write address, the queue final address of the write target queue, before writing When the read control unit 34 reads the communication data from the read target queue, the subsequent address and the next write address related to the queue final address are updated. Each storage address of the data memory 31 is shared by each queue by reading data and updating each of the queue start address, the next write address, and the subsequent address related to the new next write address. It is a thing.

  In this embodiment, as shown in FIG. 1, a case where two input ports Pin0 and Pin1 are provided as the input port Pin and two output ports Pout0 and Pout1 are provided as the output port Pout will be described as an example. However, the number of input ports Pin and output ports Pout is not limited to this. Three or more of either one or both of the input port Pin and the output port Pout can be provided, and the number of input ports and the number of output ports may be different. Note that the number of input ports may be one.

[Multiplexer]
Next, with reference to FIG. 1, the multiplexing apparatus 10 used in the communication input / output apparatus 1 according to the present embodiment will be described in detail.
The multiplexing apparatus 10 includes a queue designation information adding unit 11 and a multiplexing unit 12 as main circuit units.

  The queue designation information adding unit 11 is provided for each of the input ports Pin0 and Pin1, and for frame data input from the corresponding input port Pin, queue designation information corresponding to the output destination of the frame data, and the frame It has a function of adding data frame length information (Byte) and outputting it to the multiplexing unit 12. At this time, for example, when outputting frame data to the multiplexing unit 12, the frame length information may be added by counting the number of bytes from the beginning to the end of the frame data as the frame length.

Multiplexing unit 12 is provided in common with each queue designation information adding unit 11, multiplexes the frame data output from each queue designation information adding unit 11 in a time division manner, and outputs it to recording apparatus 30. It has a function.
In the multiplexer 10, the designation of the queue corresponding to the output destination of the frame data may be realized by a bridge function such as IEEE802.1D. Specifically, the output port search by MAC address learning and the VLAN-ID are used. The output port can be specified (see Patent Document 1).

[Demultiplexer]
Next, the demultiplexer 20 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG.
The demultiplexer 20 is provided with a reading unit 21, a distribution unit 22, and speed conversion units 23 and 24 as main circuit units.

The reading unit 21 refers to the accumulation status of each queue acquired from the recording device 30 and the reading stop instruction signal output from the speed conversion units 23 and 24, and the frame data based on the priority control logic for each of the output ports Pout0 and Pout1. A function for selecting an output system to be output with priority, a function for outputting a read request for reading frame data from a read target queue corresponding to the output system, and a transfer from the storage device 30 in response thereto The frame data is output to the distribution unit 22.
For priority control logic, for example, if the capacity of each queue is the same, general priority control such as reading from the queue with the largest amount of communication data stored in the queue among readable queues. Logic may be used (see Patent Document 1).

In addition, when the reading unit 21 outputs a read request to the recording device 30, the reading unit 21 instructs the recording device 30 with read data amount information indicating the data amount of the read data in addition to the queue designation information that specifies the queue to be read. To do.
For the read data amount information, for example, when the data accumulation amount of the queue to be read is equal to or less than a preset threshold value, a value equal to the data accumulation amount is output as the read data amount information. May be output as read data amount information.

The distribution unit 22 has a function of distributing the frame data output from the reading unit 21 to the speed conversion units 23 and 24 of the corresponding output port based on the queue designation information added to the frame data. Yes.
The speed converters 23 and 24 are provided for each output port, and according to the function of converting the frame data distributed from the distribution unit 22 into the communication speed of the output port and outputting the same, and the output status of the frame data A function of outputting a reading stop instruction signal to the reading unit 21.
The queue designation information added to the frame data is deleted by the distribution unit 22 or the speed conversion units 23 and 24.

[Recording device]
Next, the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described in detail with reference to FIG. FIG. 2 is a block diagram illustrating a configuration of the recording apparatus according to the first embodiment.

  As shown in FIG. 2, the recording device 30 includes, as main circuit units, a data memory 31, a queue control memory 32, a write control unit 33, a read control unit 34, a queue use address number memory 35, and an access arbitration unit. 36 is provided.

  The data memory 31 is composed of, for example, a semiconductor memory such as a DRAM chip, and has a plurality of logical queues formed for each output system, and has a function of storing frame data corresponding to the output system using these queues. Yes. Specifically, the data memory 31 may be composed of one or a plurality of DRAM chips and correspond to each queue corresponding to a plurality of output systems, and each output system has one queue. In addition to the configuration, one output system can have a plurality of queues.

The data memory 31 is provided with a plurality of storage areas each having a unique storage address, and each queue can arbitrarily connect these storage areas regardless of whether the storage addresses are continuous / discontinuous or in ascending / descending order. It is configured.
FIG. 3 shows a storage example of the data memory. Here, the data written from the write control unit 33 is stored for each storage area having a unique storage address ADM (0 to N: N is an integer of 2 or more).

  At this time, if one frame is longer than the data size for one address, one frame is divided into a plurality of data D in accordance with the data size for one address, and written to a plurality of different storage addresses. For example, in the case of FIG. 3, data P1-1, P1-2, and P1-3 of the queue P1 are stored at the storage addresses 0, 1, and 4, and the queue P2 is stored at the storage addresses 2, 3, and 5. Data P2-1, P2-2, and P2-3 are stored. The order relation of these data and the correspondence relation with the frame are managed by an address queue management memory described later. When one frame is shorter than the data size of the storage area, the frame data is stored in one storage area.

The queue control memory 32 is composed of a semiconductor memory such as an SRAM chip, for example, and has a function of storing various queue control information used for controlling writing / reading of frame data to / from each queue formed on the data memory 31. Have.
The queue control memory 32 includes a plurality of storage units composed of registers and memories. The main storage units include a free address register (VAR, UAR) 32A, an address queue management memory (QM) 32B, and a queue head / end address. A memory (SAR, LAR) 32C and a work address register (TMPV, TMPL) 32D are provided. In the following description, register names are sometimes used as variable names for easy understanding.

  The empty address register (VAR, UAR) 32A has a function of storing the next write address VAR and the unwritten address UAR in common to each queue. Among them, VAR (Valid Address Register) is address information indicating a storage address to which the frame data is to be written next when the frame data received from the multiplexing apparatus 10 is written next. UAR (Unused Address Register) is a storage address indicating the head (young number) of unused storage addresses to which no data has been written yet after initialization.

  In this embodiment, when writing frame data, it is basically used in order from the lowest storage address. For storage addresses that have become empty due to reading of frame data, priority is given to unused storage addresses. Shall be reused. Note that the order of storage addresses to be reused may be any order, for example, the storage addresses that have recently become empty, and are not limited to the lowest order.

The address queue management memory (QM) 32B has a function of storing a subsequent address ADD (ADDress) and a pointer PN (Pointer of QM) for each storage address ADM.
FIG. 4 is a storage example of the address queue management memory. Among these, ADD is a storage address in which communication data subsequent to the communication data written to the storage address is stored. PN is information (frame end flag) indicating whether or not the data stored at the storage address includes the final data of the frame data.

The queue head / last address memory (SAR, LAR) 32C has a function of storing a queue head address SAR (Start Address register of PM) and a queue last address LAR (Last Address register of PM) for each queue. .
FIG. 5 shows a storage example of the queue head / end address memory. Here, SAR and LAR are stored for each queue ID (queue number) for identifying the queue. Among these, SAR is address information indicating the head of the storage address where the frame data of the queue is written. LAR is address information indicating the final storage address in which frame data of the queue is written.

The work address register (TMPV, TMPL) 32D has a function of storing a work next write address TMPV (Temporary register for VAR) and a work queue final address TMPL (Temporary register for LAR) in common with each queue. Have.
Among these, TMPV is address information indicating the next write address VAR of the queue in which writing / reading was performed immediately before. TMPL is address information indicating the queue final address LAR immediately before (before update) the queue in which writing was last performed. These are used to temporarily hold address information because of the processing procedure of each data write / read operation, but may also be used for the next write / read operation.

  The write control unit 33 is designated among the queues of each output system formed on the data memory 31 based on the queue control information of the queue control memory 32 in response to a write instruction from the access arbitration unit 36. It has a function of writing the received frame data to the write target queue.

  Based on the queue control information in the queue control memory 32 in response to a read instruction from the access arbitration unit 36, the read control unit 34 selects the queue designation information from among the queues of each output system formed on the data memory 31. And a function of reading the head data from the read target queue specified in (2) and a function of transferring the data to the demultiplexing device 20 together with the frame end flag and the queue designation information.

For each queue, the queue use address number memory 35 stores a function for storing the number of addresses NK used by the frame data stored in the queue and a request from the demultiplexer 20 and the access arbitration unit 36. And a function of outputting the number of addresses NK of the designated queue.
FIG. 6 is a storage example of the queue use address number memory. Here, for each queue ID (queue number) for identifying a queue, the number of addresses NK of the queue is stored.

  The access arbitration unit 36 receives the frame data transferred from the multiplexing apparatus 10 and divides the frame data into a plurality of data D with a data size of one address based on the frame length information added to the frame data. A function for calculating the number of times of writing and writing for instructing writing to the write target queue designated by the queue designation information added to the frame data for each data D by the number of times of writing. A function of outputting an instruction to the write control unit 33, and a function of adding the number of addresses increased by writing the frame data to the number of addresses NK of the write target queue in the queue use address number memory 35. Yes.

  In response to a read request from the demultiplexer 20, the access arbitration unit 36 calculates the number of reads by dividing the data amount specified by the read data amount information of the read request by the data size for one address. A function for outputting to the read control unit 34 a read instruction for instructing reading of frame data from the read target queue designated by the queue designation information of the read request, and the number of times of reading, Arranges a conflict between the function of subtracting the address number decreased by reading from the address number NK of the write target queue in the queue use address number memory 35 and the writing of frame data, and outputs a read instruction at a readable timing. It has the function to do.

[Operation of First Embodiment]
Next, the operation of the recording device 30 used in the communication input / output device 1 according to the present embodiment will be described with reference to FIGS.
FIG. 7 is an explanatory diagram showing a write operation in the write control unit. FIG. 8 is an explanatory diagram showing a read operation in the read control unit.

[Write operation]
First, a writing operation in the writing control unit 33 of the recording device 30 will be described with reference to FIG.
The write control unit 33 executes the processing operation of FIG. 7 in response to a write instruction from the access arbitration unit 36. When new data is written to the write target queue, from the viewpoint of sharing the storage address of the data memory 31 by each queue, the main change in the queue control information is that the queue related to the write target queue before and after the write. The final address LAR, the subsequent address ADD relating to the queue final address before writing, and the next write address VAR common to each queue are changed. In the case of the first writing to the write target queue, the queue head address SAR regarding the write target queue also changes.

  Therefore, in the processing operation of FIG. 7, the write control unit 33 writes the specified data to the next write address VAR, updates the queue final address LAR regarding the write target queue, and the subsequent address regarding the queue final address before writing. The ADD is updated and the next write address VAR common to each queue is updated. In the case of the first writing to the write target queue, the queue head address related to the write target queue is also updated. Details of these updates will be described later based on an operation example.

  At this time, the write control unit 33 executes steps W1 to W7 shown in FIG. 7 by accessing the data memory 31 and the queue control memory 32. That is, processing is performed in the order of LAR retention (W1), LAR, SAR update (W2), VAR retention (W3), ADD update (W4), VAR update (W5), PN update (W6), and data storage (W7). Run. Note that the processing order of FIG. 7 is based on processing efficiency, but may be other processing orders.

[Read operation]
Next, with reference to FIG. 8, a reading operation in the reading control unit 34 of the recording apparatus 30 will be described.
The read control unit 34 executes the processing operation of FIG. 8 in response to a read instruction from the access arbitration unit 36. When new data is read from the read target queue, from the viewpoint of sharing the storage address of the data memory 31 by each queue, the main change in the queue control information is the queue head address related to the read target queue before and after the read. The SAR, the next write address VAR common to each queue, and the subsequent address ADD relating to the new next write address VAR change.

  For this reason, in the processing operation of FIG. 8, the read control unit 34 reads the data and the EoF (End of Frame: frame end flag) from the queue head address SAR related to the read target queue, and sets the queue head address SAR related to the read target queue. Update, update of the next write address VAR common to each queue, update of the subsequent address ADD related to the read storage address. Details of these updates will be described later based on an operation example.

  At this time, the read control unit 34 accesses the data memory 31 and the queue control memory 32 to execute steps R1 to R5 shown in FIG. That is, processing is executed in the order of data output, EoF output (R1), VAR retention (R2), VAR update (R3), SAR update (R4), and subsequent address update (R5). Note that the processing order in FIG. 8 takes processing efficiency into consideration, but may be another processing order.

[Operation example]
Next, referring to FIG. 9 to FIG. 15, in the frame data writing operation and reading operation in recording device 30, queue P2 is set as a read / write target queue, and data P2-3 is written to this queue P2. An example will be described in which the data P2-1 and P2-2 are read and then the data P2-4 is written.

  FIG. 9 is an explanatory diagram showing queue control information immediately before reading data P2-1 (immediately after writing data P2-3). Here, queue control information immediately before reading data P2-1, that is, immediately after writing data P2-3 is shown. In this state, the data P1-1, P1-2, and P1-3 of the queue P1 are written in the storage address “0, 1, 4” in the data memory 31, and the storage address “2, 3, 5” is stored. The data P2-1, P2-2, and P2-3 of the queue P2 are written in the. Further, the storage addresses “6 to N” are unused.

  Therefore, the next write address VAR is “6”, and the unwritten address UAR is also “6”. Further, the subsequent address ADD relating to the storage address “0, 1” becomes “1, 4” according to the order of the data P1-1, P1-2, and P1-3 in the queue P1, and the data P2-1 in the queue P2 In accordance with the order of P2-2 and P2-3, the subsequent address ADD for the storage address “2, 3” is “3, 5”. The pointer PN of the storage address “0, 2” is “0”, and it can be seen that the data P1-1 and P2-1 do not include the end of the frame.

  Further, the queue head address SAR of the queue P1 indicates the storage address “0” of the data P1-1, and the queue final address LAR indicates the storage address “4” of the data P1-3. Further, the queue head address SAR of the queue P2 indicates the storage address “2” of the data P2-1, and the queue final address LAR indicates the storage address “5” of the data P2-3. Note that “5” and “3” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

  In the state shown in FIG. 9, when the data P2-1 of the queue P2 is read, the queue control information changes as shown in FIG. FIG. 10 is an explanatory diagram showing changes in queue control information when reading data P2-1.

  First, as shown in FIG. 10A, the data P2-1 is read from the read target address “2” indicated by the queue head address SAR relating to the queue P2, so that the data D at the read target address “2” is in an empty state. The data relating to the queue P2 is two of P2-2 and P2-3. As a result, as shown in FIG. 10B, P2-2 becomes the head data of the queue P2, and the queue head position changes from the storage address “2” to “3”, so the queue head address SAR regarding the queue P2 is changed. It is updated from “2” to “3”.

  Further, since the data D at the read target address “2” is in an empty state, as shown in FIG. 10C, the storage address “2” becomes the writing position of the next data. As a result, the next write address VAR is updated from “6” to “2”. Accordingly, in order to maintain the order relationship between the old primary write address VAR “6” and the new primary write address VAR “2”, as shown in FIG. The subsequent address ADD is updated from “3” to “6”.

  As a result, the queue control information changes to the state shown in FIG. FIG. 11 is an explanatory diagram showing queue control information immediately after reading data P2-1 (just before reading data P2-2). Note that “6” and “3” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

  When the data P2-2 in the queue P2 is read in the state shown in FIG. 11, the queue control information changes as shown in FIG. FIG. 12 is an explanatory diagram showing changes in the queue control information when reading data P2-2.

  First, as shown in FIG. 12A, the data P2-2 is read from the read target address “3” indicated by the queue head address SAR relating to the queue P2, so that the data D at the read target address “3” is in an empty state. The data relating to the queue P2 is one of P2-3. As a result, as shown in FIG. 12B, P2-3 becomes the head data of the queue P2, and the queue head position changes from the storage address “3” to “5”, so the queue head address SAR regarding the queue P2 is changed. It is updated from “3” to “5”.

  Further, since the data D at the read target address “3” is in an empty state, as shown in FIG. 12C, the storage address “3” becomes the writing position of the next data. As a result, the next write address VAR is updated from “2” to “3”. Accordingly, in order to maintain the order relationship between the old primary write address VAR “2” and the new primary write address VAR “3”, as shown in FIG. The subsequent address ADD is updated from “5” to “2”.

  As a result, the queue control information changes to the state shown in FIG. FIG. 13 is an explanatory diagram showing queue control information immediately after reading data P2-2 (just before writing data P2-4). Note that “2” and “3” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

  In the state shown in FIG. 13, when the data P2-4 of the queue P2 is written, the queue control information changes as shown in FIG. FIG. 14 is an explanatory diagram showing a change in queue control information at the time of writing data P2-4.

  First, as shown in FIG. 14A, since the data P2-4 is written to the write target address “3” indicated by the next write address VAR, as shown in FIG. Since the queue P2 becomes new final data and the queue final position changes from the storage address “5” to “3”, the queue final address LAR of the queue P2 is updated from “5” to “3”.

Further, since P2-4 follows P2-3 which was the last queue data before writing, as shown in FIG. 14C, as a subsequent address of the storage address “5” of P2-3. The storage address “3” of P2-4 is set.
Since P2-4 is written to the next write address VAR before writing, as shown in FIG. 14D, the next write address VAR is changed from “3” to the subsequent address “3”. 2 ”.

  As a result, the queue control information changes to the state shown in FIG. FIG. 15 is an explanatory diagram showing the queue control information immediately after the data P2-4 is written. Note that “3” and “5” are stored in the work next write address TMPV and the work queue final address TMPL, respectively.

[Effect of the first embodiment]
As described above, according to the present embodiment, in the recording device 30, for each storage address of the data memory 31, a subsequent address indicating a storage address of communication data subsequent to the communication data written to the storage address is stored. For each queue, a queue head address and a queue last address indicating the beginning and end of the storage address where the communication data of the queue is written are stored, and the storage address where the communication data is to be written next is common to each queue. The next write address is stored.

  When the write control unit 33 writes the communication data to the write target queue, the write control unit 33 writes the communication data to the write target address including the next write address, the queue last address of the write target queue, When the read control unit 34 reads the communication data from the read target queue, the subsequent address and the next write address related to the queue final address are updated. Data is read, and the queue start address, the next write address, and the subsequent address relating to the new next write address of the read target queue are updated.

  As a result, the frame data of each queue is sequentially written in the storage address in the data memory 31 that is in an empty state, and the storage address from which the frame data is read is managed as an empty state again. In addition, the storage address of the frame data is managed in the order of writing for each queue. Therefore, a storage address in the data memory 31 that is in an empty state can be shared by a plurality of queues. Compared to a case where a fixed address range is secured in advance for each conventional queue, the storage address of the memory is reduced. It is possible to increase the usage efficiency. For this reason, it is not necessary to increase the memory capacity, and as a result, an increase in circuit scale and cost can be suppressed.

In addition, this embodiment has a feature that it is not necessary to set an initial value such as an ADD value in the QM. In the present embodiment, only the VAR and the UAR need to set initial values when the communication input / output device is activated (see “Initialization” in FIG. 7). Therefore, the scale of the circuit for performing the initial setting or the scale of the software for performing the initial setting is extremely small, and the time required for the initial setting is extremely small.
In FIG. 9 and the like, the case where the PN for storing the EoF value is mounted in the QM is illustrated, but it is also possible to mount the PN in the DM.

[Second Embodiment]
Next, a communication input / output device 1 according to a second embodiment of the present invention will be described with reference to FIG. FIG. 16 is a block diagram illustrating a configuration of an access arbitration unit according to the second embodiment.

  In the communication input / output device 1 according to the first embodiment, when the storage address in the data memory 31 is shared by a plurality of queues, for example, a large amount of frame data related to a specific output system is input. In this case, the storage address in the data memory 31 may be occupied by the queue of the output system. Such occupation of the storage address is not limited to the first embodiment, and can occur in any configuration as long as the storage address is shared by a plurality of queues. Therefore, when such storage address occupancy occurs, the queues of other output systems cannot use a sufficient number of storage addresses, frame data is likely to be discarded, and communication quality deteriorates.

  The purpose of this embodiment is to avoid occupying a storage address by a specific queue when such storage addresses are shared by a plurality of queues. In the recording apparatus 30, the access arbitration unit 36 has a write target queue. When the frame data is written in, the necessary address number indicating the number of storage addresses necessary for writing is calculated based on the data length of the frame data, and the write target queue acquired from the queue use address number memory 35 or each Based on the number of used addresses in the queue, the number of remaining addresses indicating the number of storage addresses that can be used for the writing is calculated, and whether or not the frame data can be written is determined by comparing the required number of addresses with the number of remaining addresses. The frame data is written to the write control unit 33 according to the determination as to whether writing is possible. It is obtained by the Shimesuru so.

  As shown in FIG. 16, in this embodiment, the access arbitration unit 36 includes, as main circuit units, a write enable / disable determination unit 41, a write FIFO 42, a read reception unit 43, a read FIFO 44, and a priority control unit. 45, a queue use address number updating unit 46, and an instruction output unit 47 are provided.

  The write enable / disable determining unit 41 includes queue designation information and frame length information added to the frame data transferred from the multiplexing device 10, determination address number information set in advance for each queue, A function for determining whether or not writing is possible based on the number of addresses used, and data corresponding to one address in a storage area provided in the data memory 31 in accordance with the determination result on whether or not writing is possible It has a function of writing a write instruction in which queue designation information is added to the obtained data and the queue designation information is written to the write FIFO 42.

The determination address number information includes the maximum number of addresses NKmax that can be used in the write target queue designated by the queue designation information, and the minimum guaranteed address number NKmin that is guaranteed to be used for the write target queue. It is included.
FIG. 17 is a configuration example of the determination address number information. Here, a maximum address number NKmax and a minimum guaranteed address number NKmin are set for each queue ID for identifying a queue. The determination address number information is stored in, for example, an internal memory (not shown) of the queue use address number update unit 46 or the access arbitration unit 36.

  The read reception unit 43 calculates the number of reads to the data memory 31 based on the read data amount information of the read request output from the multiplexer / demultiplexer 20, and uses the queue designation information of the read request as a read instruction for the number of reads. It has a function of writing to the read FIFO 44. In this calculation, a value obtained by dividing the data amount indicated by the read data amount information by the data size per address of the data memory 31 is used as the number of readings, and if there is a remainder, 1 may be added to the number of readings.

  The priority control unit 45 reads the write instruction or the read instruction from the write FIFO 42 or the read FIFO 44 and outputs it to the queue use address number memory update unit 46, and both the write FIFO 42 and the read FIFO 44. When there is a writing instruction and a reading instruction, the writing instruction from the writing FIFO 42 is read preferentially.

  When a write instruction is input from the priority control unit 45, the queue use address number update unit 46 uses the number of addresses used in the write target queue corresponding to the queue designation information of the write instruction in the queue use address number memory 35. 1 and the function of outputting the write instruction to the instruction output unit 47, and when the read instruction is input from the priority control unit 45, the queue designation information of the read instruction in the queue use address number memory 35 And 1 is subtracted from the number of used addresses of the read target queue, and the read instruction is output to the instruction output unit 47.

  The instruction output unit 47 outputs a write instruction to the write control unit 33 when a write instruction is input from the queue use address number update unit 46, and the read instruction when a read instruction is input. Is output to the reading control unit 34.

[Operation of Second Embodiment]
Next, with reference to FIG. 18, a write determination operation at the time of writing frame data will be described as the operation of the access arbitration unit 36 according to the present embodiment. FIG. 18 is a flowchart illustrating the write permission / inhibition determination process according to the second embodiment.
The access arbitration unit 36 of the recording device 30 determines whether or not writing is possible for each frame data transferred from the multiplexing device 10 based on the writeability determination processing in FIG.

  First, the access arbitration unit 36 acquires the used address number NK for all the queues from the queue used address number memory 35 (step 100), calculates the total address number NKA used by all the queues (step 101), The required number of addresses NF required for writing the target frame data to be written is calculated (step 102).

Thereafter, by subtracting NKA from the total address number NA of storage addresses of the data memory 31, a remaining address number NR indicating the number of storage addresses that can be used for writing the target frame data is calculated (step 103). NF and NR are compared (step 104).
Here, if NF> NR (step 104: YES), the access arbitration unit 36 determines that writing is not possible, discards the target frame data (step 113), and ends the write determination processing for the target frame data. To do.

On the other hand, when NF ≦ NR (step 104: NO), the access arbitration unit 36 acquires the maximum address number NKmax of the designated write target queue from the queue use address number memory 35 or the like (step 105), and NKmax. NK is subtracted from NR to calculate the remaining address number NR (step 106), and NF and NR are compared (step 107).
Here, when NF> NR (step 107: YES), the access arbitration unit 36 determines that writing is not possible, discards the target frame data (step 113), and ends the write determination processing for the target frame data. To do.

  On the other hand, when NF ≦ NR (step 107: NO), the access arbitration unit 36 acquires the minimum guaranteed address number NKmin for all the queues from the queue use address number memory 35 (step 108), and collects all the queues at the lowest. The total guaranteed address number NAmin to be limited guaranteed is calculated (step 109). At this time, if the queue use address number NK of an arbitrary queue is equal to or greater than the minimum guaranteed address number, the queue use address number NK is added as the guaranteed address number of the queue, and the queue use address number NK is the minimum guaranteed address number. If it is less than the number, the minimum guaranteed address number NKmin is added as the guaranteed address number of the queue.

Thereafter, the access arbitration unit 36 calculates the remaining address number NR by subtracting NAmin from NA (step 110), and compares NF and NR (step 111).
Here, when NF> NR (step 111: YES), the access arbitration unit 36 determines that writing is not possible, discards the target frame data (step 113), and finishes the write determination process for the target frame data. To do.

On the other hand, when NF ≦ NR (step 111: NO), the access arbitration unit 36 determines that the target frame data is writable (step 112), and ends the write determination process for the target frame data.
Thereafter, in response to this write permission determination, the access arbitration unit 36 divides the target frame data into data sizes corresponding to one address of the data memory 31, and writes the queue designation information to the obtained data. Are written in the write FIFO 42, respectively.

[Effect of the second embodiment]
As described above, in this embodiment, in the recording device 30, the queue use address number memory 35 stores the use address number indicating the number of storage addresses on the data memory 31 used by the queue for each queue. When the access arbitration unit 36 writes the communication data to the write target queue, the access arbitration unit 36 calculates the necessary number of addresses indicating the number of storage addresses necessary for writing based on the data length of the communication data, and the number of queue use addresses Based on the write target queue or the number of used addresses of each queue acquired from the memory 35, the remaining address number indicating the number of storage addresses that can be used for the write is calculated, and the required address number, the remaining address number, To determine whether or not the communication data can be written, and to the write control unit 33 according to the determination of whether or not the communication data can be written. It is obtained so as to direct the writing of over data.

  Therefore, since the number of storage addresses used by each queue is limited, the occupation of storage addresses by a queue corresponding to an arbitrary output system can be suppressed. For this reason, even when a large amount of frame data relating to a specific output system is input, the queues of other output systems can use a sufficient number of storage addresses. This makes it possible to avoid discarding frame data and the resulting deterioration in communication quality, and as a countermeasure, it is not necessary to increase the memory capacity, thereby suppressing an increase in circuit scale and cost. Is possible.

Note that NKA and NAmin in the present embodiment can be calculated (added, subtracted, etc.) simultaneously when updating the queue use address number memory.
In the present embodiment, when the access arbitration unit configured as shown in FIG. 16 is used, there is a possibility that it is erroneously determined that writing is possible if write instruction data exists in the write FIFO. In order to prevent erroneous determination, a value obtained by adding the number of addresses in the write FIFO (number of write instructions) to the information in the queue use address number memory is used as the number of use addresses of each queue, or NA or A value obtained by subtracting the number of addresses in the write FIFO (the number of write instructions) may be used as NKmax.

[Extended embodiment]
The present invention has been described above with reference to the embodiments, but the present invention is not limited to the above embodiments. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the present invention. In addition, each embodiment can be implemented in any combination within a consistent range.

In each of the above embodiments, when the communication input / output device 1 processes a multicast frame, a multicast output system is provided as one of the output systems, and a plurality of multicast frames are provided in the distribution unit 22 in the demultiplexer 20. It is also possible to provide a means for outputting to the speed converter 23 and to allocate a part of the queues logically formed in the data memory DM of the recording device 30 as a queue corresponding to this multicast output system.
Thus, the multicast frame input from the outside to the multiplexer 10 is temporarily stored in a queue corresponding to the multicast output system in the data memory DM, and the multicast frame is read from the queue by the demultiplexer 20. Output from multiple output ports.

  DESCRIPTION OF SYMBOLS 1 ... Communication input / output device, 10 ... Multiplexer, 11 ... Queue designation information addition part, 12 ... Multiplexing part, 20 ... Demultiplexing device, 21 ... Reading part, 22 ... Distribution part, 23, 24 ... Speed Conversion unit, 30 ... recording device, 31 ... data memory, 32 ... queue control memory, 33 ... write control unit, 34 ... reading control unit, 35 ... queue use address number memory, 36 ... access arbitration unit, 41 ... write Determinability determination unit, 42... FIFO for writing, 43... Reception accepting unit, 44... FIFO for reading, 45... Priority control unit, 46.

Claims (6)

A multiplexing device that multiplexes by adding queue designation information indicating a queue corresponding to an output system to which the communication data is to be output, and the communication data transferred from the multiplexing device. Corresponding to a recording device for temporarily storing in a queue to be written designated by the queue designation information among a plurality of queues logically formed in the data memory, and an output system selected based on the priority control logic among the queues A communication input / output device comprising: a demultiplexer that reads the communication data from the read target queue and converts the communication data into a communication speed of an output port corresponding to the output system;
The recording device comprises:
A queue control memory for storing queue control information used when controlling writing / reading to / from the queue of the data memory;
A write control unit that writes the communication data transferred from the multiplexing device to the write target queue based on queue control information in the queue control memory;
A read control unit that reads communication data from the read target queue based on queue control information of the queue control memory and transfers the communication data to the demultiplexing device;
The queue control memory stores, for each storage address of the data memory, a subsequent address indicating a storage address of communication data subsequent to the communication data written to the storage address, and for each queue, communication data of the queue Is stored, and a queue start address and a queue end address indicating the start and end of the storage address to which communication data is written are stored, and a next write address indicating a storage address to which communication data is to be written next is stored in common with each queue And
When writing the communication data to the write target queue, the write control unit writes the communication data to a write target address composed of the next write address, the queue final address of the write target queue, the write Update the subsequent address and the next write address for the previous queue last address,
When the reading control unit reads the communication data from the reading target queue, the reading control unit reads the communication data from a reading target address including a queue leading address of the reading target queue, An input / output device for communication, wherein an address and a subsequent address relating to a new next write address are respectively updated. The communication input / output device according to claim 1,
The recording device comprises:
A queue use address number memory that stores a use address number indicating the number of storage addresses on the data memory used by the queue for each queue;
When writing the communication data to the write target queue, based on the data length of the communication data, calculate the required number of addresses indicating the number of storage addresses required for writing, and obtain the number of addresses used from the queue use address number memory Based on the number of addresses used in the write target queue or each of the queues, the remaining address number indicating the number of storage addresses that can be used for the write is calculated, and the required address number is compared with the remaining address number. And an access arbitration unit that determines whether or not communication data can be written, and instructs the write control unit to write the communication data in accordance with the determination of whether or not writing is possible. apparatus. A multiplexing device that multiplexes by adding queue designation information indicating a queue corresponding to an output system to which the communication data is to be output, and the communication data transferred from the multiplexing device. Corresponding to a recording device for temporarily storing in a queue to be written designated by the queue designation information among a plurality of queues logically formed in the data memory, and an output system selected based on the priority control logic among the queues A communication input / output device comprising: a demultiplexer that reads the communication data from the read target queue and converts the communication data into a communication speed of an output port corresponding to the output system;
The recording device comprises:
A queue use address number memory that stores a use address number indicating the number of storage addresses on the data memory used by the queue for each queue;
When writing the communication data to the write target queue, based on the data length of the communication data, calculate the required number of addresses indicating the number of storage addresses required for writing, and obtain the number of addresses used from the queue use address number memory Based on the number of addresses used in the write target queue or each of the queues, the remaining address number indicating the number of storage addresses that can be used for the write is calculated, and the required address number is compared with the remaining address number. An input / output device for communication, comprising: an access arbitration unit that determines whether or not communication data can be written and instructs the write control unit to write the communication data in accordance with the determination of whether or not writing is possible . The communication input / output device according to claim 2 or 3,
The communication input / output device, wherein the access arbitration unit calculates the remaining address number by subtracting the used address number of each queue from the total address number of storage addresses of the data memory. The communication input / output device according to claim 2 or 3,
The access arbitration unit subtracts the number of used addresses of the write target queue from the maximum number of addresses indicating the number of usable storage addresses allocated in advance to the write target queue, thereby obtaining the remaining address. An input / output device for communication characterized by calculating a number. The communication input / output device according to claim 2 or 3,
The access arbitration unit calculates the number of remaining addresses by subtracting the lowest guaranteed address guaranteed in advance for each queue from the total number of addresses stored in the data memory. I / O device for communication.

Images