JP2019029766A - Semiconductor device, optical transmission device, and optical transmission system - Google Patents

Abstract

To provide a semiconductor device capable of improving signal quality.SOLUTION: In an embodiment, a level conversion device 11 includes transistors MN11 and MN12 receiving differential input signals, a constant current source CC 1 for supplying a constant current to each of the transistors MN11 and MN12, transistors MP11 and MP12 provided respectively corresponding to the transistors MN11 and MN12, a transistor MP 13 current-mirror connected to the transistor MP11, a transistor MP 16 current-mirror connected to the transistor MP12, a variable driving transistor MN13 provided on a current path of the transistor MP13 and configured so that the driving capability can be switched, and a transistor MN 16 current-mirror connected to the variable driving transistor MN 13, and an output signal having a voltage level corresponding to the resistance value of each of the transistors MP16 and MN16 is generated.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a semiconductor device, an optical transmission device, and an optical transmission system. For example, the present invention relates to a semiconductor device, an optical transmission device, and an optical transmission system suitable for improving signal quality without increasing power consumption.

  In recent years, in the field of silicon photonics, optical transmission devices have been increased in speed and size. Accordingly, the optical transmission device is required to have low power consumption.

  Conventionally, an optical transmission device uses a level conversion device composed of a bipolar transistor to convert a CML (Current Mode Logic) level electric signal of about 100 mV into a CMOS (complementary metal oxide) of about 1.0 V to 3.3 V. After amplifying the electrical signal to a semiconductor level, it was converted to an optical signal. However, although the bipolar transistor has the characteristics that the switching performance is high and the characteristic variation is small, there is a problem that the power consumption increases because a large current flows.

  A solution to such a problem is disclosed in Patent Document 1. The level conversion circuit disclosed in Patent Document 1 is configured by a MOS transistor without using a bipolar transistor. Thereby, this level conversion circuit can realize low power consumption and high integration.

JP 2006-287797 A

  However, since the configuration disclosed in Patent Document 1 is composed of MOS transistors, there is a problem that signal quality is deteriorated due to characteristic variations due to variations in process, temperature, and voltage. Other problems and novel features will become apparent from the description of the specification and the accompanying drawings.

  According to one embodiment, a semiconductor device includes: a first input transistor that receives one of a pair of differential input signals; a second input transistor that receives the other of a pair of the differential input signals; A constant current source for supplying a constant current to each of the second input transistors; first and second load transistors provided corresponding to each of the first and second input transistors; and A first mirror transistor that is connected in a current mirror and in which a first mirror current that is proportional to the current that flows in the first load transistor flows, and a current mirror that is configured in the second load transistor and that is proportional to the current that flows in the second load transistor. Provided on the first output transistor through which the first output current flows and the current path of the first mirror current, the driving capability is cut off. A first variable drive transistor configured to be capable of being connected, and a second output transistor connected to the first variable drive transistor in a current mirror and through which a second output current proportional to the first mirror current flows. A first output signal having a voltage level corresponding to the resistance value between the source and drain of each of the first and second output transistors is generated.

  According to the embodiment, it is possible to provide a semiconductor device, a transmission device, and a transmission system that can realize low power consumption without deteriorating signal quality.

1 is a block diagram illustrating a configuration example of an optical transmission system according to a first embodiment; FIG. 2 is a diagram illustrating a configuration example of a level conversion device provided in the optical transmission system according to the first exemplary embodiment; It is a figure which shows the relationship between the difference of the amplitude center voltage of an amplifier circuit and the threshold voltage of an inverter, and the output signal of an inverter. It is a figure for demonstrating the influence on the signal zone | band by the driving force adjustment of the level converter shown in FIG. FIG. 3 is a circuit diagram showing a configuration example of a variable drive transistor provided in the level conversion device shown in FIG. 2. It is a figure which shows the modification of the level converter shown in FIG. It is a figure which shows the connection relationship of the variable drive transistor, temperature detection circuit, and control circuit which were provided in the level converter shown in FIG. It is a circuit diagram which shows the specific structural example of a temperature detection circuit. It is a figure which shows the modification of the level converter shown in FIG. It is a figure which shows the structural example of the level conversion apparatus concerning Embodiment 2. FIG. FIG. 11 is a circuit diagram illustrating a configuration example of a variable drive transistor provided in the level conversion device illustrated in FIG. 10. It is a figure which shows the 1st modification of the level converter shown in FIG. It is a figure which shows the connection relation of the variable drive transistor and temperature detection circuit which were provided in the level converter shown in FIG. FIG. 6 is a diagram illustrating a configuration example of a level conversion apparatus according to a third embodiment. It is a figure which shows the specific structural example of a dummy circuit and a threshold voltage generation circuit. It is a figure which shows the structural example of the level conversion apparatus concerning Embodiment 4. FIG.

  Hereinafter, embodiments will be described with reference to the drawings. Since the drawings are simple, the technical scope of the embodiments should not be narrowly interpreted based on the description of the drawings. Moreover, the same code | symbol is attached | subjected to the same element and the overlapping description is abbreviate | omitted.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. Are partly or entirely modified, application examples, detailed explanations, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number.

  Further, in the following embodiments, the constituent elements (including operation steps and the like) are not necessarily essential except when clearly indicated and clearly considered essential in principle. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numbers and the like (including the number, numerical value, quantity, range, etc.).

<Embodiment 1>
FIG. 1 is a block diagram of a configuration example of the optical transmission system SYS1 according to the first embodiment. The optical transmission system SYS1 includes a transmission side LSI (Large Scale Integration) 2, an optical transmission device 1, and a reception side LSI 3. The optical transmission device 1 includes a level conversion device 11 and a photoelectric conversion device 12.

  The transmission-side LSI 2 outputs a CML level electrical signal (differential input signal IN) of, for example, about 100 mV. The optical transmission apparatus 1 converts the CML level electrical signal from the transmission-side LSI 2 into an optical signal and outputs it. More specifically, in the optical transmission device 1, the level conversion device 11 converts the level of the CML level electrical signal into a CMOS level electrical signal of about 3.3 V, for example, and the photoelectric conversion device 12 is level-converted. An electrical signal is converted into an optical signal and output. The optical signal from the optical transmission device 1 is received by the receiving-side LSI 3. The receiving-side LSI 3 performs predetermined processing after converting the received optical signal into an electrical signal.

  Here, the level conversion device 11 is required to have low power consumption as the speed and size are reduced. Therefore, the level conversion device 11 is constituted by a transistor that consumes less power than a bipolar transistor. This will be specifically described below.

(Configuration example of level converter 11)
FIG. 2 is a diagram illustrating a configuration example of the level conversion device 11.
As shown in FIG. 2, the level converter 11 includes an amplifier circuit PA1 and inverters INV1 and INV2.

  The amplifier circuit PA1 amplifies the CML level differential input signal IN transmitted from the transmission side LSI 2 and outputs a differential output signal OUT. The inverter INV1 logically inverts one of the pair of differential output signals OUT and outputs a CMOS level signal. The inverter INV2 logically inverts the other of the pair of differential output signals OUT and outputs a CMOS level signal.

  The amplifier circuit PA1 includes transistors MN11 to MN16, transistors MP11 to MP16, and a constant current source CC1. In the present embodiment, a case where the transistors MN11 to MN16 are N-channel MOS transistors and the transistors MP11 to MP16 are P-channel MOS transistors will be described as an example.

  The transistors MN11 and MN12 are input transistors that form an input differential pair. In the transistor MN11, the source is connected to the input terminal of the constant current source CC1, the drain is connected to the node N1, and the gate is connected to the input terminal INP of the amplifier circuit PA1. In the transistor MN12, the source is connected to the input terminal of the constant current source CC1, the drain is connected to the node N2, and the gate is connected to the input terminal INN of the amplifier circuit PA1. The output terminal of the constant current source CC1 is connected to the ground voltage terminal GND. Note that one of the pair of differential input signals IN is supplied to the input terminal INP, and the other of the pair of differential input signals IN is supplied to the input terminal INN.

  The transistors MP11 and MP12 are load transistors that constitute a load. In the transistor MP11, the source is connected to the power supply voltage terminal VDD, and the drain and gate are connected to the drain of the transistor MN11 via the node N1. In the transistor MP12, the source is connected to the power supply voltage terminal VDD, and the drain and gate are connected to the drain of the transistor MN12 via the node N2.

  The transistor MP13 is current mirror connected to the transistor MP11. Specifically, in the transistor MP13, the source is connected to the power supply voltage terminal VDD, the drain is connected to the node N3, and the gate is connected to the node N1.

  The transistor MN13 is a transistor having a variable driving capability (resistance value), and has a source connected to the ground voltage terminal GND, and a drain and a gate connected to the drain of the transistor MP13 via the node N3.

  The transistor MP14 is current-mirror connected to the transistor MP12. Specifically, in the transistor MP14, the source is connected to the power supply voltage terminal VDD, the drain is connected to the node N4, and the gate is connected to the node N2.

  The transistor MN14 is a transistor having a variable driving capability (resistance value), and has a source connected to the ground voltage terminal GND, and a drain and a gate connected to the drain of the transistor MP14 via the node N4.

  The transistors MP15 and MN15 are output transistors provided at one output stage of the amplifier circuit PA1. The transistor MP15 is current mirror connected to the transistor MP11. The transistor MN15 is current-mirror connected to the transistor MN14.

  Specifically, in the transistor MP15, the source is connected to the power supply voltage terminal VDD, the drain is connected to the output terminal OUTP of the amplifier circuit PA1, and the gate is connected to the node N1. In the transistor MN15, the source is connected to the ground voltage terminal GND, the drain is connected to the output terminal OUTP of the amplifier circuit PA1, and the gate is connected to the node N4. Note that one of the pair of differential output signals OUT is output from the output terminal OUTP to the outside.

  The transistors MP16 and MN16 are output transistors provided at the other output stage of the amplifier circuit PA1. The transistor MP16 is current mirror connected to the transistor MP12. The transistor MN16 is current mirror connected to the transistor MN13.

  Specifically, in the transistor MP16, the source is connected to the power supply voltage terminal VDD, the drain is connected to the output terminal OUTN of the amplifier circuit PA1, and the gate is connected to the node N2. In the transistor MN16, the source is connected to the ground voltage terminal GND, the drain is connected to the output terminal OUTN of the amplifier circuit PA1, and the gate is connected to the node N3. Note that the other of the pair of differential output signals OUT is output from the output terminal OUTN to the outside.

(Operation of the amplifier circuit PA1)
Next, the operation of the amplifier circuit PA1 will be described.

  For example, when one (INP) of the differential input signal IN is larger than the other (INN), the current I1 flowing through the transistor MN11 is larger than the current I2 flowing through the transistor MN12. At this time, since the current I51 proportional to the current I1 flows through the transistor MP15 and the current I52 proportional to the current I2 flows through the transistor MN15, the voltage value of one (OUTP) of the differential output signal OUT increases. . On the other hand, since a current I61 proportional to the current I2 flows through the transistor MP16 and a current I62 proportional to the current I1 flows through the transistor MN16, the voltage value of the other (OUTN) of the differential output signal OUT decreases. That is, when one (INP) of the differential input signal IN is larger than the other (INN), one (OUTP) of the differential output signal OUT is larger than the other (OUTN).

  On the other hand, when one (INP) of the differential input signal IN is smaller than the other (INN), the current I1 flowing through the transistor MN11 is smaller than the current I2 flowing through the transistor MN12. At this time, since the current I51 proportional to the current I1 flows through the transistor MP15 and the current I52 proportional to the current I2 flows through the transistor MN15, the voltage value of one (OUTP) of the differential output signal OUT becomes small. . On the other hand, since the current I61 proportional to the current I2 flows through the transistor MP16 and the current I62 proportional to the current I1 flows through the transistor MN16, the voltage value of the other (OUTN) of the differential output signal OUT increases. That is, when one (INP) of the differential input signal IN is smaller than the other (INN), one (OUTP) of the differential output signal OUT is smaller than the other (OUTN).

The operation of the amplifier circuit PA1 will be described more specifically.
When one of the differential input signals IN is applied to the gate of the transistor MN11 via the input terminal INP, a current I1 having a current value corresponding to one potential of the differential input signal IN flows through the transistor MN11. Thereby, the current I1 also flows through the transistor MP11. A current I3 proportional to the current I1 flowing through the transistor MP11 flows through the transistor MP13. In this example, the transistor MP13 is configured to have the same size as the transistor MP11. Therefore, a current I3 having the same current value as the current I1 flows through the transistor MP13. As a result, the current I3 also flows through the transistor MN13 having a variable driving capability.

  A current I62 proportional to the current I3 flowing through the transistor MN13 flows through the transistor MN16. In this example, the transistor MN16 is configured to have the same size as the transistor MN13. Therefore, a current I62 having the same current value as the current I3 (that is, the current I1) flows through the transistor MN16.

  When the other of the differential input signal IN is applied to the gate of the transistor MN12 via the input terminal INN, a current I2 having a current value corresponding to the other potential of the differential input signal IN flows through the transistor MN12. . As a result, the current I2 also flows through the transistor MP12. A current I61 proportional to the current I2 flowing through the transistor MP12 flows through the transistor MP16. In this example, the transistor MP16 is configured to have the same size as the transistor MP12. Therefore, a current I61 having the same current value as the current I2 flows through the transistor MP16.

  A voltage Vb2 having a value corresponding to the difference between the current I61 (corresponding to the current I2) and the current I62 (corresponding to the current I1) is generated at the output terminal OUTN of the amplifier circuit PA1. In other words, the output terminal OUTN of the amplifier circuit PA1 generates a voltage Vb2 obtained by dividing the power supply voltage VDD by the resistance (on-resistance) ratio between the source and drain of each of the transistors MP16 and MN16.

  The inverter INV2 logically inverts and outputs the voltage Vb2. Specifically, the inverter INV2 outputs an L level signal when the voltage Vb2 is equal to or higher than the threshold voltage Vth, and outputs an H level signal when the voltage Vb2 is lower than the threshold voltage Vth.

  Similarly, a current I4 proportional to the current I2 flowing through the transistor MP12 flows through the transistor MP14. In this example, the transistor MP14 is configured to have the same size as the transistor MP12. Therefore, the current I4 having the same current value as the current I2 flows through the transistor MP14. As a result, the current I4 also flows through the transistor MN14 having a variable driving capability.

  A current I52 proportional to the current I4 flowing through the transistor MN14 flows through the transistor MN15. In this example, the transistor MN15 is configured to have the same size as the transistor MN14. Therefore, the current I52 having the same current value as the current I4 (that is, the current I2) flows through the transistor MN15.

  A current I51 proportional to the current I1 flowing through the transistor MP11 flows through the transistor MP15. In this example, the transistor MP15 is configured to have the same size as the transistor MP11. Therefore, a current I51 having the same current value as the current I1 flows through the transistor MP15.

  A voltage Vb1 having a value corresponding to the difference between the current I51 (corresponding to the current I1) and the current I52 (corresponding to the current I2) is generated at the output terminal OUTP of the amplifier circuit PA1. In other words, the output terminal OUTP of the amplifier circuit PA1 generates a voltage Vb1 obtained by dividing the power supply voltage VDD by the resistance (on-resistance) ratio between the source and drain of each of the transistors MP15 and MN15.

  The inverter INV1 logically inverts and outputs the voltage Vb1. Specifically, the inverter INV1 outputs an L level signal when the voltage Vb1 is equal to or higher than the threshold voltage Vth, and outputs an H level signal when the voltage Vb1 is lower than the threshold voltage Vth.

  Here, it is desirable that the center voltage Vb2m having the amplitude of the voltage Vb2 of the output terminal OUTN and the threshold voltage Vth of the inverter INV2 are ideally the same. However, actually, an error exceeding the allowable range occurs between the amplitude center voltage Vb2m and the threshold voltage Vth due to characteristic variations due to process, temperature, and voltage variations, and variations in the constant current I12 flowing through the constant current source CC1. there is a possibility. In this case, since the duty ratio of the output signal of the inverter INV2 is lost, the signal quality is deteriorated.

  Similarly, it is desirable that the center voltage Vb1m having the amplitude of the voltage Vb1 of the output terminal OUTP and the threshold voltage Vth of the inverter INV1 are ideally the same. However, in practice, an error exceeding the allowable range occurs between the amplitude center voltage Vb1m and the threshold voltage Vth due to characteristic variations due to process, temperature, and voltage fluctuations and fluctuations in the constant current I12 flowing through the constant current source CC1. there is a possibility. In this case, since the duty ratio of the output signal of the inverter INV1 is destroyed, the signal quality is deteriorated.

  FIG. 3 is a diagram showing the relationship between the difference between the amplitude center voltages Vb1m and Vb2m and the threshold voltage Vth of the inverters INV1 and INV2 and the output signal of the inverter INV2.

  As shown in FIG. 3, when the amplitude center voltages Vb1m and Vb2m and the threshold voltages Vth of the inverters INV1 and INV2 have the same value (the waveform on the left side of the figure), the cross points of the output signals of the inverters INV1 and INV2 are , The center voltage of the power supply voltage VDD and the ground voltage GND.

  On the other hand, for example, when the amplitude center voltages Vb1m and Vb2m are lower than the threshold voltage Vth of the inverters INV1 and INV2 (the central waveform in the figure), the cross points of the output signals of the inverters INV1 and INV2 are the power supply voltage VDD and It becomes lower than the center voltage of the ground voltage GND. As a result, the duty ratios of the output signals of the inverters INV1 and INV2 are lost, so that the signal quality is deteriorated.

  Further, for example, when the amplitude center voltages Vb1m and Vb2m are higher than the threshold voltage Vth of the inverters INV1 and INV2 (the waveform on the right side of the figure), the cross points of the output signals of the inverters INV1 and INV2 are the power supply voltage VDD and the ground It becomes lower than the center voltage of the voltage GND. As a result, the duty ratios of the output signals of the inverters INV1 and INV2 are lost, so that the signal quality is deteriorated.

  In particular, in the optical transmission field, when a high-speed operation is performed at, for example, about 25 GHz, there is a possibility that a pulse loss or a data error may occur due to the duty ratio collapse.

  Therefore, in the present embodiment, by adjusting the driving capability of the transistor MN13 and adjusting the resistance (on-resistance) between the source and drain of the transistor MN16, the center voltage Vb2m having the amplitude of the voltage Vb2 of the output terminal OUTN The error from the threshold voltage Vth of the inverter INV2 is kept within an allowable range. Thereby, since the duty ratio collapse of the output signal of the inverter INV2 can be suppressed, the signal quality can be improved.

  Similarly, in the present embodiment, by adjusting the driving capability of the transistor MN14 and adjusting the resistance (on resistance) between the source and drain of the transistor MN15, the center voltage having the amplitude of the voltage Vb1 of the output terminal OUTP is adjusted. An error between Vb1m and the threshold voltage Vth of the inverter INV1 is suppressed within an allowable range. Thereby, since the duty ratio collapse of the output signal of the inverter INV1 can be suppressed, the signal quality can be improved.

  As described above, the level conversion device 11 according to the present embodiment uses the transistors MN13 and MN14 that are configured to have variable driving capabilities, thereby using the amplitude center voltages Vb1m and Vb2m of the differential output signal of the amplifier circuit PA1. An error between the inverters INV1 and INV2 and the threshold voltage Vth can be suppressed within an allowable range. Thereby, the level conversion apparatus 11 according to the present embodiment can suppress the duty ratio collapse of the level-converted output signal, so that the signal quality can be improved.

  Instead of adjusting the drive capability of the transistors MN13 and MN14, the amplitude center voltage of the voltages Vb1 and Vb2 is adjusted by adjusting the current I12 of the constant current source CC1 or adjusting the drive capability of the transistors MP13 and MP14. It is also possible to adjust Vb1m and Vb2m. However, as shown in FIG. 4, when the transistors MP13 and MP14 are adjusted, the differential pair output load is directly affected, so that the signal band of the amplifier circuit PA1 is greatly affected. In addition, when the constant current I12 of the constant current source CC1 is adjusted, there is a problem that the increase or decrease in the current consumption value of the amplifier circuit PA1 is large, which is not suitable for reducing power consumption. On the other hand, such a problem does not occur when the driving capabilities of the transistors MN13 and MN14 are adjusted.

(Specific configuration example of variable drive transistor MN13)
FIG. 5 is a diagram illustrating a specific configuration example of the variable drive transistor MN13.

  As shown in FIG. 5, the variable drive transistor MN13 includes a transistor MN131, n (n is a natural number) transistors Tr11 to Tr1n, and n switch elements SW11 to SW1n. In this embodiment, the case where the transistor MN131 and the transistors Tr11 to Tr1n are all N-channel MOS transistors will be described as an example.

  In the transistor MN131, the source is connected to the ground voltage terminal GND, and the drain and gate are connected to the node N3. In each of the transistors Tr11 to Tr1n, the source is connected to the ground voltage terminal GND, the drain is connected to the node N3, and the gate is connected to the first terminals of the switch elements SW11 to SW1n. In each of the switch elements SW11 to SW1n, the second terminal is connected to the node N3, the third terminal is connected to the ground voltage terminal GND, and the control signal S1 from the outside is supplied to the control terminal.

  For example, when the first terminal (the gate side terminal of each transistor Tr11 to Tr1n) of each switch element SW11 to SW1n is connected to the second terminal (the terminal on the node N3 side) by the control signal S1, each transistor Tr11 to Tr1n is Since the voltage of the node N3 is applied to the gate, the transistor is turned on. Thereby, the resistance value between the source (ground voltage terminal GND) and the drain (node N3) of the variable drive transistor MN13 is reduced. That is, the drive capability of the variable drive transistor MN13 is increased.

  On the other hand, when the first terminals of the switch elements SW11 to SW1n are connected to the third terminal (terminal on the ground voltage terminal GND side) by the control signal S1, the ground voltage GND is applied to the gates of the transistors Tr11 to Tr1n. To turn off. As a result, the resistance value between the source and drain of the variable drive transistor MN13 increases. That is, the drive capability of the variable drive transistor MN13 is reduced.

  In short, the drive capability of the variable drive transistor MN13 increases as the number of transistors turned on among the n transistors Tr11 to Tr1n increases, and the drive capability of the variable drive transistor MN13 decreases as the number of transistors turned on decreases.

  Therefore, for example, when the amplitude center voltage Vb2m is lower than the threshold voltage Vth of the inverter INV2, the drive capability of the variable drive transistor MN13 is increased by increasing the number of transistors that are turned on among the transistors Tr11 to Tr1n. As a result, the voltage at the node N3 decreases, and the on-resistance of the transistor MN16 increases. As a result, the amplitude center voltage Vb2m can be raised to approach the threshold voltage Vth. On the other hand, when the amplitude center voltage Vb2m is higher than the threshold voltage Vth of the inverter INV2, the drive capability of the variable drive transistor MN13 is reduced by reducing the number of transistors that are turned on among the transistors Tr11 to Tr1n. As a result, the voltage at the node N3 increases, and the on-resistance of the transistor MN16 decreases. As a result, the amplitude center voltage Vb2m can be lowered to approach the threshold voltage Vth.

  Since the variable drive transistor MN13 shown in FIG. 5 has a quick response performance, the influence on the direct signal band can be reduced even when the load capacity increases. Therefore, this configuration is suitable for a high bandwidth circuit.

  Since the configuration of the variable drive transistor MN14 is basically the same as that of the variable drive transistor MN13, the description thereof is omitted.

(Modification of level converter 11)
FIG. 6 is a diagram showing a modification of the level conversion device 11 as a level conversion device 11a.
FIG. 7 is a diagram illustrating a connection relationship among the variable drive transistor MN13, the temperature detection circuit 111, and the control circuit 112 provided in the level conversion device 11a.

  As shown in FIG. 6, the level conversion device 11a further includes a temperature detection circuit 111 and a control circuit 112 in addition to the amplifier circuit PA1 and the inverters INV1 and INV2.

  The temperature detection circuit 111 is a circuit that detects the temperature of the amplifier circuit PA1 or its peripheral region, and outputs a detection voltage Vdet whose voltage value linearly changes in accordance with the temperature change.

((Specific configuration example of temperature detection circuit 111))
FIG. 8 is a circuit diagram illustrating a specific configuration example of the temperature detection circuit 111.
As shown in FIG. 8, the temperature detection circuit 111 includes resistance elements R1 to R3, bipolar transistors Tr1 to Tr3, and an operational amplifier OP1.

  Resistance elements R1 to R3 are provided in series between power supply voltage terminal VDD and ground voltage terminal GND. The bipolar transistors Tr1 to Tr3 are connected between the base and the collector, and are provided in series between the power supply voltage terminal VDD and the ground voltage terminal GND together with the resistance elements R1 to R3. The voltage of the node N11 between the resistance elements R1 to R3 and the bipolar transistors Tr1 to Tr3 is supplied to the non-inverting input terminal of the operational amplifier OP1, and the output voltage of the operational amplifier OP1 ( Detection voltage) Vdet is fed back and supplied. Thereby, the operational amplifier OP1 outputs the voltage of the node N11 as the detection voltage Vdet.

  Note that the configuration of the temperature detection circuit 111 is not limited to the configuration illustrated in FIG. 8 and can be appropriately changed to another configuration having an equivalent function.

  The control circuit 112 is, for example, an AD converter, and converts the analog detection voltage Vdet into a digital control signal S1 and outputs it. As shown in FIG. 7, the drive capability of the variable drive transistor MN13 is controlled by the control signal S1. Although not shown in FIG. 7, the drive capability of the variable drive transistor MN14 is controlled by the control signal S2.

  Since the other configuration and operation of the level conversion device 11a are the same as those of the level conversion device 11, description thereof is omitted.

  The level conversion device 11 a can achieve the same effect as the level conversion device 11. Here, the level converter 11a changes the drive capability of the variable drive transistors MN13 and MN14 according to the temperature change, so that the amplitude center voltages Vbm1 and Vbm2 and the thresholds of the inverters INV1 and INV2 are changed even when the temperature changes. An error between the voltage Vth and the voltage Vth can be automatically suppressed within an allowable range. Thereby, the level conversion device 11a according to the present embodiment can suppress the duty ratio collapse of the level-converted output signal, so that the signal quality can be improved.

  In this embodiment, the case where the temperature detection circuit 111, the control circuit 112, the amplifier circuit PA1, and the inverters INV1 and INV2 are formed on the same semiconductor chip is described as an example. However, the present invention is not limited to this. The temperature detection circuit 111, the control circuit 112, the amplifier circuit PA1, and the inverters INV1 and INV2 may be formed on different semiconductor chips. Hereinafter, a brief description will be given with reference to FIG.

(Modification of level converter 11a)
FIG. 9 is a diagram showing a modification of the level conversion device 11a as a level conversion device 11b. As shown in FIG. 9, in the level converter 11b, the temperature detection circuit 111, the amplifier circuit PA1, and the inverters INV1 and INV2 are formed on the same semiconductor chip CHP1, and the control circuit 113 is provided outside the semiconductor chip CHP1. Yes. In this embodiment, a part of the function of the MCU (microcontroller) 113 is used as the control circuit 112.

  Since the other configuration and operation of the level conversion device 11b are the same as those of the level conversion device 11, description thereof is omitted.

  Like the level conversion device 11b shown in FIG. 9, some of the constituent elements may be provided outside the semiconductor chip CHP1.

<Embodiment 2>
FIG. 10 is a diagram of a configuration example of the level conversion device 21 according to the second embodiment. The level conversion device 21 corresponds to the level conversion device 11.

  As shown in FIG. 10, the level conversion device 21 includes an amplifier circuit PA2 and inverters INV1 and INV2. The amplifier circuit PA2 has variable drive transistors MN23 and MN24 instead of the variable drive transistors MN13 and MN14, as compared with the amplifier circuit PA1.

(Specific configuration example of variable drive transistor MN23)
FIG. 11 is a diagram illustrating a specific configuration example of the variable drive transistor MN23.

  As shown in FIG. 11, the variable drive transistor MN23 includes a transistor MN231. Here, the voltage from the variable voltage source 114 is supplied to the back gate of the transistor MN231.

  For example, when the voltage of the variable voltage source 114 is lowered, the driving capability of the transistor MN231, that is, the driving capability of the variable driving transistor MN13 is decreased. On the other hand, when the voltage of the variable voltage source 114 is increased, the driving capability of the transistor MN231, that is, the driving capability of the variable driving transistor MN13 is increased.

  Therefore, for example, when the amplitude center voltage Vb2m is lower than the threshold voltage Vth of the inverter INV2, the drive capability of the variable drive transistor MN13 is increased by increasing the back gate voltage of the transistor MN231. As a result, the voltage at the node N3 decreases, and the on-resistance of the transistor MN16 increases. As a result, the amplitude center voltage Vb2m can be raised to approach the threshold voltage Vth. On the other hand, when the amplitude center voltage Vb2m is higher than the threshold voltage Vth of the inverter INV2, the drive capability of the variable drive transistor MN13 is reduced by lowering the back gate voltage of the transistor MN231. As a result, the voltage at the node N3 increases, and the on-resistance of the transistor MN16 decreases. As a result, the amplitude center voltage Vb2m can be lowered to approach the threshold voltage Vth.

  Since the configuration of the variable drive transistor MN14 is basically the same as that of the variable drive transistor MN13, the description thereof is omitted.

  As described above, the level conversion device 21 according to the present embodiment uses the transistors MN23 and MN24 having variable driving capabilities, thereby allowing the amplitude center voltages Vb1m and Vb2m of the differential output signal of the amplifier circuit PA2 to be An error between the inverters INV1 and INV2 and the threshold voltage Vth can be suppressed within an allowable range. Thereby, the level conversion device 21 according to the present embodiment can suppress the duty ratio collapse of the level-converted output signal, so that the signal quality can be improved.

  Furthermore, since the level conversion device 21 according to the present embodiment can reduce the size of the variable drive transistor compared to the level conversion device 11, the circuit scale can be reduced. Thereby, the bandwidth can be effectively improved.

(First Modification of Level Conversion Device 21)
FIG. 12 is a diagram showing a first modification of the level conversion device 21 as a level conversion device 21a. FIG. 13 is a diagram illustrating a connection relationship between the variable drive transistor MN23 and the temperature detection circuit 111 provided in the level conversion device 21a.

  As shown in FIG. 12, the level conversion device 21a further includes a temperature detection circuit 111 in addition to the amplification circuit PA2 and the inverters INV1 and INV2, as compared with the level conversion device 21. The temperature detection circuit 111 is a circuit that detects the temperature of the amplifier circuit PA2 or its peripheral region, and outputs a detection voltage Vdet having a voltage value corresponding to the detected temperature. The specific configuration of the temperature detection circuit 111 is as already described.

  As shown in FIG. 13, the detection voltage Vdet of the temperature detection circuit 111 is supplied to the back gate of the transistor MN231 as a control signal. Thereby, the driving capability of the variable driving transistor MN23 is adjusted. Although not shown in FIG. 13, the detection voltage Vdet of the temperature detection circuit 111 is supplied as a control signal to the back gate of the transistor MN241 constituting the variable drive transistor MN24. Thereby, the driving capability of the variable driving transistor MN24 is adjusted.

  Other configurations and operations of the level conversion device 21a are the same as those of the level conversion device 21, and thus the description thereof is omitted.

  The level conversion device 21 a can achieve the same effect as the level conversion device 21. Here, the level conversion device 21a changes the drive capability of the variable drive transistors MN23 and MN24 according to the temperature change, so that the amplitude center voltages Vbm1 and Vbm2 and the thresholds of the inverters INV1 and INV2 are changed even when the temperature changes. An error between the voltage Vth and the voltage Vth can be automatically suppressed within an allowable range. As a result, the level conversion device 21a according to the present embodiment can suppress the duty ratio collapse of the level-converted output signal, thereby improving the signal quality.

  In this embodiment, the case where the temperature detection circuit 111, the amplifier circuit PA1, and the inverters INV1 and INV2 are formed on the same semiconductor chip is described as an example. However, the present invention is not limited to this. The temperature detection circuit 111, the amplifier circuit PA1, and the inverters INV1 and INV2 may be formed on different semiconductor chips.

<Embodiment 3>
FIG. 14 is a diagram of a configuration example of the level conversion device 31 according to the third embodiment. The level conversion device 31 corresponds to the level conversion device 11.

  As shown in FIG. 14, the level conversion device 31 further includes a dummy circuit 115, a threshold voltage generation circuit 116, and an operational amplifier 117 in addition to the amplification circuit PA2 and inverters INV1 and INV2, as compared with the level conversion device 21.

  The dummy circuit 115 is a dummy circuit of the amplifier circuit PA2, for example, and reproduces the amplitude center voltage Vb2m and outputs it as the voltage Vdmy. The threshold voltage generation circuit 116 is a dummy circuit of the inverter INV2, for example, and reproduces the threshold voltage Vth of the inverter INV2 and outputs it as the voltage Vthd.

  The operational amplifier 117 amplifies the difference between the voltage Vdmy output from the dummy circuit 115 and the voltage Vthd generated by the threshold voltage generation circuit 116 and outputs the amplified voltage as the detection voltage Vdet. This detection voltage Vdet is supplied as a control signal to the respective back gates of the transistors MN231 and MN241 constituting the variable drive transistors MN23 and MN24. Thereby, the driving capabilities of the variable driving transistors MN23 and MN24 are adjusted.

(Specific configuration examples of the dummy circuit 115 and the threshold voltage generation circuit 116)
FIG. 15 is a diagram illustrating a specific configuration example of the dummy circuit 115 and the threshold voltage generation circuit 116.

  First, a specific configuration example of the dummy circuit 115 will be described. The dummy circuit 115 includes transistors MP31 to MP33, MP36, transistors MN31 to MN33, MN36, and a constant current source CC3 as components necessary for reproducing the amplitude center voltage Vb2m.

  Regarding the structures and connection relationships of the transistors MP31 to MP33, MP36, MN31 to MN33, MN36 and the constant current source CC3 in the dummy circuit 115, the transistors MP11 to MP13, MP16, MN11 to MN13, MN16 and the constant current source CC1 in the amplifier circuit PA2 are described. This is basically the same as the structure and connection relationship. However, the same potential is supplied to the gates of the transistors MN31 and MN32. In this example, the gates of the transistors MN31 and MN32 are connected to each other. In the transistor MN33, the ground voltage GND is applied to the back gate.

  Thereby, the dummy circuit 115 can generate the voltage Vdmy showing substantially the same value as the amplitude center voltage Vb2m.

  Next, a specific configuration example of the threshold voltage generation circuit 116 will be described. The threshold voltage generation circuit 116 is a dummy circuit of the inverter INV2, for example, and includes a P-channel MOS transistor MP41 and an N-channel MOS transistor MN41. The transistors MP41 and MN41 are provided in series between the power supply voltage terminal VDD and the ground voltage terminal GND. The gates of the transistors MP41 and MN41 are connected to the input node NI, and the drains of the transistors MP41 and MN41 are connected to the output node NO. The output node NO and the input node NI are short-circuited.

  Thereby, the threshold voltage generation circuit 116 can generate a voltage Vthd having substantially the same value as the threshold voltage Vth of the inverter INV2 at the output node NO.

  Thus, the level conversion device 31 according to the present embodiment can achieve the same effects as the level conversion device 21. Further, the level conversion device 31 reproduces the amplitude center voltage Vb2m and the threshold voltage Vth of the inverter INV2 using the dummy circuit 115 and the threshold voltage generation circuit 116, and the variable drive transistors MN23 and MN24 have a small difference so that this difference becomes small. The driving ability is adjusted. Thereby, for example, even when characteristic variation due to process, temperature, voltage variation, variation in constant current I12, etc. occurs, between amplitude center voltage Vbm1, Vbm2 and threshold voltage Vth of inverters INV1, INV2 The error can be automatically suppressed within an allowable range. Thereby, the level conversion device 31 according to the present embodiment can suppress the duty ratio collapse of the level-converted output signal, and can improve the signal quality.

  In the present embodiment, the detection voltage Vdet generated according to the difference between the reproduction voltage of the amplitude center voltage Vb2m and the reproduction voltage of the threshold voltage Vth of the inverter INV2 is supplied to the variable drive transistors MN23 and MN24. However, the present invention is not limited to this. The variable drive transistor 24 may be supplied with a detection voltage Vdet2 generated separately from the detection voltage Vdet supplied to the variable drive transistor MN23. In this case, the separately provided dummy circuit reproduces the amplitude center voltage Vb1m, the separately provided threshold voltage generation circuit reproduces the threshold voltage Vth of the inverter INV1, and the separately provided operational amplifier has the amplitude center voltage Vb1m. , And a detection voltage Vdet2 corresponding to the difference between the inverter INV1 threshold voltage Vth.

<Embodiment 4>
FIG. 16 is a diagram of a configuration example of the level conversion device 41 according to the fourth embodiment. The level conversion device 41 corresponds to the level conversion device 11. The level converter 11 amplifies the differential input signal and outputs a differential output signal. On the other hand, the level converter 41 amplifies the differential input signal and outputs a single-ended signal.

  The level conversion device 41 includes an amplifier circuit PA3 and an inverter INV2. The amplifier circuit PA3 includes components necessary for outputting the voltage Vb2 from the output terminal OUTN among the components of the amplifier circuit PA1.

  Specifically, the amplifier circuit PA3 includes transistors MP11 to MP13 and MP16, transistors MN11 to MN13 and MN16, and a constant current source CC1. Since these structures and connection relationships are the same as those in the case of the amplifier circuit PA1, description thereof will be omitted.

  The amplifier circuit PA3 amplifies the CML level differential input signal IN of about 100 mV, and outputs a single end signal from the output terminal OUTN. The inverter INV2 logically inverts the single-end signal from the amplifier circuit PA3 and outputs a CMOS level signal of about 3.3V.

  As described above, the level conversion device 41 according to the present embodiment uses the transistor MN13 having a variable driving capability, and thereby the amplitude center voltage Vb2m of the single-ended signal output from the amplifier circuit PA3 and the inverter INV2 The error between the threshold voltage Vth and the threshold voltage Vth can be suppressed within an allowable range. As a result, the level conversion device 41 according to the present embodiment can suppress the duty ratio collapse of the level-converted output signal, thereby improving the signal quality.

  Although the case where the variable drive transistor MN13 is provided in the amplifier circuit PA3 has been described as an example in the present embodiment, the present invention is not limited to this. In the amplifier circuit PA3, a variable drive transistor MN23 whose back gate voltage is controlled may be provided instead of the variable drive transistor MN13.

  Similarly to the level conversion device 11a shown in FIG. 6, the level conversion device 41 may further include configurations of the temperature detection circuit 111 and the control circuit 112. Further, when the variable drive transistor MN23 is provided in place of the variable drive transistor MN13 in the amplifier circuit PA3, the configuration of the temperature detection circuit 111 may be further provided as in the level conversion device 21a shown in FIG. Alternatively, similarly to the level conversion device 31 shown in FIG. 14, the configurations of the dummy circuit 115, the threshold voltage generation circuit 116, and the operational amplifier 117 may be further provided.

  As described above, the level conversion apparatus according to the first to fourth embodiments and the optical transmission apparatus including the level conversion apparatus use, for example, the transistors MN13, MN23, and the like, which have a variable driving capability, for example, the amplifier circuit PA1. The error between the amplitude center voltage Vb2m of the output signal of PA4 and the threshold voltage Vth of the inverter INV2 can be suppressed within an allowable range. Accordingly, the level conversion device according to the first to fourth embodiments and the optical transmission device including the level conversion device can suppress the duty ratio collapse of the level-converted output signal, thereby improving the signal quality. it can.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the embodiments already described, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

  For example, the semiconductor device according to the above embodiment may have a configuration in which conductivity types (p-type or n-type) such as a semiconductor substrate, a semiconductor layer, and a diffusion layer (diffusion region) are inverted. Therefore, when one of n-type and p-type conductivity is the first conductivity type and the other conductivity type is the second conductivity type, the first conductivity type is p-type and the second conductivity type is The first conductivity type may be n-type and the second conductivity type may be p-type.

  A part or all of the above embodiment may be described as in the following supplementary notes, but is not limited thereto.

(Appendix 1)
A first input transistor for receiving one of a pair of differential input signals;
A second input transistor for receiving the other of the pair of differential input signals;
A constant current source for supplying a constant current to each of the first and second input transistors;
First and second load transistors provided corresponding to each of the first and second input transistors;
A first mirror transistor that is current-mirror connected to the first load transistor and through which a first mirror current proportional to a current flowing through the first load transistor flows;
A first output transistor that is configured as a current mirror in the second load transistor and through which a first output current proportional to a current flowing through the second load transistor flows;
A first variable drive transistor provided on the current path of the first mirror current and configured to be switchable in drive capability;
A second output transistor connected to the first variable drive transistor in a current mirror and through which a second output current proportional to the first mirror current flows;
A second mirror transistor that is current-mirror connected to the second load transistor and flows a second mirror current proportional to a current that flows through the second load transistor;
A third output transistor that is current-mirror connected to the first load transistor and through which a third output current proportional to the current flowing through the first load transistor flows;
A second variable driving transistor provided on the current path of the second mirror current and configured to be switchable in driving capability;
A fourth output transistor that is current-mirror connected to the second variable drive transistor and through which a fourth output current proportional to the second mirror current flows,
A first output signal having a voltage level corresponding to a resistance value between a source and a drain of each of the first and second output transistors is generated;
A second output signal having a voltage level corresponding to the resistance value between the source and drain of each of the third and fourth output transistors is generated;
Semiconductor device.

(Appendix 2)
The first variable drive transistor and the second variable drive transistor are:
In any case, the resistance value between the source and the drain can be changed.
The semiconductor device according to appendix 1.

(Appendix 3)
The first variable drive transistor includes:
A first MOS transistor provided on a current path of the first mirror current;
A plurality of second MOS transistors provided in parallel between the gate and the source of the first MOS transistor;
A plurality of first switch elements connecting the gates of the plurality of second MOS transistors to either the gate or the source of the first MOS transistor selected in accordance with a control signal;
The second variable drive transistor includes:
A third MOS transistor provided on a current path of the second mirror current;
A plurality of fourth MOS transistors provided in parallel between the gate and source of the third MOS transistor;
A plurality of second switch elements connecting the gates of the plurality of fourth MOS transistors to any one of the gate and drain of the third MOS transistor selected in accordance with the control signal;
The semiconductor device according to appendix 1.

(Appendix 4)
A temperature detection circuit for generating a detection voltage having a voltage value corresponding to the temperature of the semiconductor device;
A control circuit that generates the control signal in accordance with the detection voltage of the temperature detection circuit;
Further equipped with,
The semiconductor device according to attachment 3.

(Appendix 5)
The control circuit is an AD converter that converts the analog detection voltage into the digital control signal.
The semiconductor device according to appendix 4.

(Appendix 6)
The control circuit is a microcontroller including an AD converter that converts the analog detection voltage into the digital control signal.
The semiconductor device according to appendix 4.

(Appendix 7)
The first variable drive transistor and the second variable drive transistor are:
In any case, the resistance value between the source and the drain can be changed by an analog control signal applied to the back gate.
The semiconductor device according to appendix 1.

(Appendix 8)
A temperature detection circuit that outputs a detection voltage having a voltage value corresponding to the temperature of the semiconductor device as the control signal;
The semiconductor device according to appendix 7.

(Appendix 9)
A threshold voltage generation circuit for reproducing a threshold voltage of a subsequent circuit to which the first output signal of the semiconductor device is supplied;
A dummy circuit that reproduces the center voltage of the amplitude of the first output signal of the semiconductor device;
An operational amplifier that amplifies a potential difference between the threshold voltage reproduced by the threshold voltage generation circuit and the center voltage reproduced by the dummy circuit and outputs the amplified signal as the control signal;
Further equipped with,
The semiconductor device according to appendix 7.

(Appendix 10)
The semiconductor device according to appendix 1, which outputs the first and second output signals corresponding to the differential input signal as a pair of differential output signals;
A photoelectric conversion device for converting the differential output signal into an optical signal;
An optical transmission device comprising:

(Appendix 11)
A transmission circuit for outputting the differential input signal;
The optical transmission device according to appendix 10, which generates the optical signal based on the differential input signal;
A receiving circuit that executes predetermined processing based on the optical signal;
Optical transmission system equipped with.

1 Optical Transmission Device 2 Transmitting LSI
3 Receiving side LSI (receiving circuit)
11 level converter 11a, 11b level converter 12 photoelectric converter 21 level converter 21a level converter 31 level converter 41 level converter CC1 constant current source CC3 constant current source CHP1 semiconductor chip INP, INN input terminal INV1 inverter INV2 inverter MN11, MN12 transistors (input transistors)
MN13, MN14 transistors (variable drive transistors)
MN15, MN16 transistor (output transistor)
MN23, MN24 transistors (variable drive transistors)
MP11, MP12 transistor (load transistor)
MP13, MP14 transistor (mirror transistor)
MP15, MP16 transistor (output transistor)
MN31, MN32 transistors (input transistors)
MN33 transistor MN36 transistor (output transistor)
MP31, MP32 transistor (load transistor)
MP33 transistor (mirror transistor)
MP36 transistor (output transistor)
MN41 transistor MP41 transistor MN131 transistor MN231 transistor OP1 operational amplifier OUTP, OUTN output terminal PA1 amplifier circuit PA2 amplifier circuit PA3 amplifier circuit R1 to R3 resistance element SYS1 optical transmission system SW11 to SW1n switch element Tr1 to Tr3 bipolar transistor Tr11 to Tr1n transistor 111 Circuit 112 Control circuit 113 MCU (microcomputer)
114 variable voltage source 115 dummy circuit 116 threshold voltage generation circuit 117 operational amplifier

Claims (17)

A first input transistor for receiving one of a pair of differential input signals;
A second input transistor for receiving the other of the pair of differential input signals;
A constant current source for supplying a constant current to each of the first and second input transistors;
First and second load transistors provided corresponding to each of the first and second input transistors;
A first mirror transistor that is current-mirror connected to the first load transistor and through which a first mirror current proportional to a current flowing through the first load transistor flows;
A first output transistor that is configured as a current mirror in the second load transistor and through which a first output current proportional to a current flowing through the second load transistor flows;
A first variable drive transistor provided on the current path of the first mirror current and configured to be switchable in drive capability;
A second output transistor that is current-mirror connected to the first variable drive transistor and through which a second output current proportional to the first mirror current flows,
A first output signal having a voltage level corresponding to a resistance value between a source and a drain of each of the first and second output transistors is generated;
Semiconductor device. The first variable drive transistor includes:
The resistance value between the source and the drain is configured to be changeable,
The semiconductor device according to claim 1. The first variable drive transistor includes:
A first MOS transistor provided on a current path of the first mirror current;
A plurality of second MOS transistors provided in parallel between the gate and the source of the first MOS transistor;
A plurality of first switch elements connecting the gates of the plurality of second MOS transistors to any one of the gate and the source of the first MOS transistor selected in accordance with a control signal;
The semiconductor device according to claim 1. A temperature detection circuit for generating a detection voltage having a voltage value corresponding to the temperature of the semiconductor device;
A control circuit that generates the control signal in accordance with the detection voltage of the temperature detection circuit;
Further equipped with,
The semiconductor device according to claim 3. The control circuit is an AD converter that converts the analog detection voltage into the digital control signal.
The semiconductor device according to claim 4. The control circuit is a microcontroller including an AD converter that converts the analog detection voltage into the digital control signal.
The semiconductor device according to claim 4. The first variable drive transistor includes:
The resistance value between the source and the drain can be changed by an analog control signal applied to the back gate.
The semiconductor device according to claim 1. A temperature detection circuit that outputs a detection voltage having a voltage value corresponding to the temperature of the semiconductor device as the control signal;
The semiconductor device according to claim 7. A threshold voltage generation circuit for reproducing a threshold voltage of a subsequent circuit to which the first output signal of the semiconductor device is supplied;
A dummy circuit that reproduces the center voltage of the amplitude of the first output signal of the semiconductor device;
An operational amplifier that amplifies a potential difference between the threshold voltage reproduced by the threshold voltage generation circuit and the center voltage reproduced by the dummy circuit and outputs the amplified signal as the control signal;
Further equipped with,
The semiconductor device according to claim 7. A second mirror transistor that is current-mirror connected to the second load transistor and flows a second mirror current proportional to a current that flows through the second load transistor;
A third output transistor that is current-mirror connected to the first load transistor and through which a third output current proportional to the current flowing through the first load transistor flows;
A second variable driving transistor provided on the current path of the second mirror current and configured to be switchable in driving capability;
A fourth output transistor connected to the second variable drive transistor in a current mirror and through which a fourth output current proportional to the second mirror current flows;
Further comprising
A second output signal having a voltage level corresponding to the resistance value between the source and drain of each of the third and fourth output transistors is generated;
The semiconductor device according to claim 1. The first variable drive transistor and the second variable drive transistor are:
In any case, the resistance value between the source and the drain can be changed.
The semiconductor device according to claim 10. The first variable drive transistor includes:
A first MOS transistor provided on a current path of the first mirror current;
A plurality of second MOS transistors provided in parallel between the gate and the source of the first MOS transistor;
A plurality of first switch elements connecting the gates of the plurality of second MOS transistors to either the gate or the source of the first MOS transistor selected in accordance with a control signal;
The second variable drive transistor includes:
A third MOS transistor provided on a current path of the second mirror current;
A plurality of fourth MOS transistors provided in parallel between the gate and source of the third MOS transistor;
A plurality of second switch elements connecting the gates of the plurality of fourth MOS transistors to either the gate or the source of the third MOS transistor selected in accordance with the control signal;
The semiconductor device according to claim 10. The semiconductor device according to claim 1, wherein the first output signal corresponding to the differential input signal is output;
A photoelectric conversion device for converting the first output signal into an optical signal;
An optical transmission device comprising: A transmission circuit for outputting the differential input signal;
The optical transmission device according to claim 13, wherein the optical signal is generated based on the differential input signal;
A receiving circuit that executes predetermined processing based on the optical signal;
Optical transmission system equipped with. The semiconductor device according to claim 10, wherein the first and second output signals corresponding to the differential input signal are output as a pair of differential output signals;
A photoelectric conversion device for converting the differential output signal into an optical signal;
An optical transmission device comprising: A transmission circuit for outputting the differential input signal;
The optical transmission device according to claim 15, wherein the optical signal is generated based on the differential input signal;
A receiving circuit that executes predetermined processing based on the optical signal;
Optical transmission system equipped with. A first input transistor for receiving one of a pair of differential input signals;
A second input transistor for receiving the other of the pair of differential input signals;
A constant current source for supplying a constant current to each of the first and second input transistors;
First and second load transistors provided corresponding to each of the first and second input transistors;
A first mirror transistor that is current-mirror connected to the first load transistor and through which a first mirror current proportional to a current flowing through the first load transistor flows;
A first output transistor that is configured as a current mirror in the second load transistor and through which a first output current proportional to a current flowing through the second load transistor flows;
A first variable drive transistor provided on the current path of the first mirror current and configured to be switchable in drive capability;
A second output transistor connected to the first variable drive transistor in a current mirror and through which a second output current proportional to the first mirror current flows;
A second mirror transistor that is current-mirror connected to the second load transistor and flows a second mirror current proportional to a current that flows through the second load transistor;
A third output transistor that is current-mirror connected to the first load transistor and through which a third output current proportional to the current flowing through the first load transistor flows;
A second variable driving transistor provided on the current path of the second mirror current and configured to be switchable in driving capability;
A fourth output transistor that is current-mirror connected to the second variable drive transistor and through which a fourth output current proportional to the second mirror current flows,
A first output signal having a voltage level corresponding to a resistance value between a source and a drain of each of the first and second output transistors is generated;
A second output signal having a voltage level corresponding to the resistance value between the source and drain of each of the third and fourth output transistors is generated;
Semiconductor device.

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